drivers/i2c/busses/i2c-tegra.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * drivers/i2c/busses/i2c-tegra.c
   4  *
   5  * Copyright (C) 2010 Google, Inc.
   6  * Author: Colin Cross <ccross@android.com>
   7  */
   8
   9 #include <linux/bitfield.h>
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/dmaengine.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/err.h>
  15 #include <linux/i2c.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/iopoll.h>
  20 #include <linux/irq.h>
  21 #include <linux/kernel.h>
  22 #include <linux/ktime.h>
  23 #include <linux/module.h>
  24 #include <linux/of_device.h>
  25 #include <linux/pinctrl/consumer.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/reset.h>
  29
  30 #define BYTES_PER_FIFO_WORD 4
  31
  32 #define I2C_CNFG                                0x000
  33 #define I2C_CNFG_DEBOUNCE_CNT                   GENMASK(14, 12)
  34 #define I2C_CNFG_PACKET_MODE_EN                 BIT(10)
  35 #define I2C_CNFG_NEW_MASTER_FSM                 BIT(11)
  36 #define I2C_CNFG_MULTI_MASTER_MODE              BIT(17)
  37 #define I2C_STATUS                              0x01c
  38 #define I2C_SL_CNFG                             0x020
  39 #define I2C_SL_CNFG_NACK                        BIT(1)
  40 #define I2C_SL_CNFG_NEWSL                       BIT(2)
  41 #define I2C_SL_ADDR1                            0x02c
  42 #define I2C_SL_ADDR2                            0x030
  43 #define I2C_TLOW_SEXT                           0x034
  44 #define I2C_TX_FIFO                             0x050
  45 #define I2C_RX_FIFO                             0x054
  46 #define I2C_PACKET_TRANSFER_STATUS              0x058
  47 #define I2C_FIFO_CONTROL                        0x05c
  48 #define I2C_FIFO_CONTROL_TX_FLUSH               BIT(1)
  49 #define I2C_FIFO_CONTROL_RX_FLUSH               BIT(0)
  50 #define I2C_FIFO_CONTROL_TX_TRIG(x)             (((x) - 1) << 5)
  51 #define I2C_FIFO_CONTROL_RX_TRIG(x)             (((x) - 1) << 2)
  52 #define I2C_FIFO_STATUS                         0x060
  53 #define I2C_FIFO_STATUS_TX                      GENMASK(7, 4)
  54 #define I2C_FIFO_STATUS_RX                      GENMASK(3, 0)
  55 #define I2C_INT_MASK                            0x064
  56 #define I2C_INT_STATUS                          0x068
  57 #define I2C_INT_BUS_CLR_DONE                    BIT(11)
  58 #define I2C_INT_PACKET_XFER_COMPLETE            BIT(7)
  59 #define I2C_INT_NO_ACK                          BIT(3)
  60 #define I2C_INT_ARBITRATION_LOST                BIT(2)
  61 #define I2C_INT_TX_FIFO_DATA_REQ                BIT(1)
  62 #define I2C_INT_RX_FIFO_DATA_REQ                BIT(0)
  63 #define I2C_CLK_DIVISOR                         0x06c
  64 #define I2C_CLK_DIVISOR_STD_FAST_MODE           GENMASK(31, 16)
  65 #define I2C_CLK_DIVISOR_HSMODE                  GENMASK(15, 0)
  66
  67 #define DVC_CTRL_REG1                           0x000
  68 #define DVC_CTRL_REG1_INTR_EN                   BIT(10)
  69 #define DVC_CTRL_REG3                           0x008
  70 #define DVC_CTRL_REG3_SW_PROG                   BIT(26)
  71 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN          BIT(30)
  72 #define DVC_STATUS                              0x00c
  73 #define DVC_STATUS_I2C_DONE_INTR                BIT(30)
  74
  75 #define I2C_ERR_NONE                            0x00
  76 #define I2C_ERR_NO_ACK                          BIT(0)
  77 #define I2C_ERR_ARBITRATION_LOST                BIT(1)
  78 #define I2C_ERR_UNKNOWN_INTERRUPT               BIT(2)
  79 #define I2C_ERR_RX_BUFFER_OVERFLOW              BIT(3)
  80
  81 #define PACKET_HEADER0_HEADER_SIZE              GENMASK(29, 28)
  82 #define PACKET_HEADER0_PACKET_ID                GENMASK(23, 16)
  83 #define PACKET_HEADER0_CONT_ID                  GENMASK(15, 12)
  84 #define PACKET_HEADER0_PROTOCOL                 GENMASK(7, 4)
  85 #define PACKET_HEADER0_PROTOCOL_I2C             1
  86
  87 #define I2C_HEADER_CONT_ON_NAK                  BIT(21)
  88 #define I2C_HEADER_READ                         BIT(19)
  89 #define I2C_HEADER_10BIT_ADDR                   BIT(18)
  90 #define I2C_HEADER_IE_ENABLE                    BIT(17)
  91 #define I2C_HEADER_REPEAT_START                 BIT(16)
  92 #define I2C_HEADER_CONTINUE_XFER                BIT(15)
  93 #define I2C_HEADER_SLAVE_ADDR_SHIFT             1
  94
  95 #define I2C_BUS_CLEAR_CNFG                      0x084
  96 #define I2C_BC_SCLK_THRESHOLD                   GENMASK(23, 16)
  97 #define I2C_BC_STOP_COND                        BIT(2)
  98 #define I2C_BC_TERMINATE                        BIT(1)
  99 #define I2C_BC_ENABLE                           BIT(0)
 100 #define I2C_BUS_CLEAR_STATUS                    0x088
 101 #define I2C_BC_STATUS                           BIT(0)
 102
 103 #define I2C_CONFIG_LOAD                         0x08c
 104 #define I2C_MSTR_CONFIG_LOAD                    BIT(0)
 105
 106 #define I2C_CLKEN_OVERRIDE                      0x090
 107 #define I2C_MST_CORE_CLKEN_OVR                  BIT(0)
 108
 109 #define I2C_INTERFACE_TIMING_0                  0x094
 110 #define  I2C_INTERFACE_TIMING_THIGH             GENMASK(13, 8)
 111 #define  I2C_INTERFACE_TIMING_TLOW              GENMASK(5, 0)
 112 #define I2C_INTERFACE_TIMING_1                  0x098
 113 #define  I2C_INTERFACE_TIMING_TBUF              GENMASK(29, 24)
 114 #define  I2C_INTERFACE_TIMING_TSU_STO           GENMASK(21, 16)
 115 #define  I2C_INTERFACE_TIMING_THD_STA           GENMASK(13, 8)
 116 #define  I2C_INTERFACE_TIMING_TSU_STA           GENMASK(5, 0)
 117
 118 #define I2C_HS_INTERFACE_TIMING_0               0x09c
 119 #define  I2C_HS_INTERFACE_TIMING_THIGH          GENMASK(13, 8)
 120 #define  I2C_HS_INTERFACE_TIMING_TLOW           GENMASK(5, 0)
 121 #define I2C_HS_INTERFACE_TIMING_1               0x0a0
 122 #define  I2C_HS_INTERFACE_TIMING_TSU_STO        GENMASK(21, 16)
 123 #define  I2C_HS_INTERFACE_TIMING_THD_STA        GENMASK(13, 8)
 124 #define  I2C_HS_INTERFACE_TIMING_TSU_STA        GENMASK(5, 0)
 125
 126 #define I2C_MST_FIFO_CONTROL                    0x0b4
 127 #define I2C_MST_FIFO_CONTROL_RX_FLUSH           BIT(0)
 128 #define I2C_MST_FIFO_CONTROL_TX_FLUSH           BIT(1)
 129 #define I2C_MST_FIFO_CONTROL_RX_TRIG(x)         (((x) - 1) <<  4)
 130 #define I2C_MST_FIFO_CONTROL_TX_TRIG(x)         (((x) - 1) << 16)
 131
 132 #define I2C_MST_FIFO_STATUS                     0x0b8
 133 #define I2C_MST_FIFO_STATUS_TX                  GENMASK(23, 16)
 134 #define I2C_MST_FIFO_STATUS_RX                  GENMASK(7, 0)
 135
 136 /* configuration load timeout in microseconds */
 137 #define I2C_CONFIG_LOAD_TIMEOUT                 1000000
 138
 139 /* packet header size in bytes */
 140 #define I2C_PACKET_HEADER_SIZE                  12
 141
 142 /*
 143  * I2C Controller will use PIO mode for transfers up to 32 bytes in order to
 144  * avoid DMA overhead, otherwise external APB DMA controller will be used.
 145  * Note that the actual MAX PIO length is 20 bytes because 32 bytes include
 146  * I2C_PACKET_HEADER_SIZE.
 147  */
 148 #define I2C_PIO_MODE_PREFERRED_LEN              32
 149
 150 /*
 151  * msg_end_type: The bus control which needs to be sent at end of transfer.
 152  * @MSG_END_STOP: Send stop pulse.
 153  * @MSG_END_REPEAT_START: Send repeat-start.
 154  * @MSG_END_CONTINUE: Don't send stop or repeat-start.
 155  */
 156 enum msg_end_type {
 157         MSG_END_STOP,
 158         MSG_END_REPEAT_START,
 159         MSG_END_CONTINUE,
 160 };
 161
 162 /**
 163  * struct tegra_i2c_hw_feature : per hardware generation features
 164  * @has_continue_xfer_support: continue-transfer supported
 165  * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer
 166  *              completion interrupt on per packet basis.
 167  * @has_config_load_reg: Has the config load register to load the new
 168  *              configuration.
 169  * @clk_divisor_hs_mode: Clock divisor in HS mode.
 170  * @clk_divisor_std_mode: Clock divisor in standard mode. It is
 171  *              applicable if there is no fast clock source i.e. single clock
 172  *              source.
 173  * @clk_divisor_fast_mode: Clock divisor in fast mode. It is
 174  *              applicable if there is no fast clock source i.e. single clock
 175  *              source.
 176  * @clk_divisor_fast_plus_mode: Clock divisor in fast mode plus. It is
 177  *              applicable if there is no fast clock source (i.e. single
 178  *              clock source).
 179  * @has_multi_master_mode: The I2C controller supports running in single-master
 180  *              or multi-master mode.
 181  * @has_slcg_override_reg: The I2C controller supports a register that
 182  *              overrides the second level clock gating.
 183  * @has_mst_fifo: The I2C controller contains the new MST FIFO interface that
 184  *              provides additional features and allows for longer messages to
 185  *              be transferred in one go.
 186  * @quirks: I2C adapter quirks for limiting write/read transfer size and not
 187  *              allowing 0 length transfers.
 188  * @supports_bus_clear: Bus Clear support to recover from bus hang during
 189  *              SDA stuck low from device for some unknown reasons.
 190  * @has_apb_dma: Support of APBDMA on corresponding Tegra chip.
 191  * @tlow_std_mode: Low period of the clock in standard mode.
 192  * @thigh_std_mode: High period of the clock in standard mode.
 193  * @tlow_fast_fastplus_mode: Low period of the clock in fast/fast-plus modes.
 194  * @thigh_fast_fastplus_mode: High period of the clock in fast/fast-plus modes.
 195  * @setup_hold_time_std_mode: Setup and hold time for start and stop conditions
 196  *              in standard mode.
 197  * @setup_hold_time_fast_fast_plus_mode: Setup and hold time for start and stop
 198  *              conditions in fast/fast-plus modes.
 199  * @setup_hold_time_hs_mode: Setup and hold time for start and stop conditions
 200  *              in HS mode.
 201  * @has_interface_timing_reg: Has interface timing register to program the tuned
 202  *              timing settings.
 203  */
 204 struct tegra_i2c_hw_feature {
 205         bool has_continue_xfer_support;
 206         bool has_per_pkt_xfer_complete_irq;
 207         bool has_config_load_reg;
 208         u32 clk_divisor_hs_mode;
 209         u32 clk_divisor_std_mode;
 210         u32 clk_divisor_fast_mode;
 211         u32 clk_divisor_fast_plus_mode;
 212         bool has_multi_master_mode;
 213         bool has_slcg_override_reg;
 214         bool has_mst_fifo;
 215         const struct i2c_adapter_quirks *quirks;
 216         bool supports_bus_clear;
 217         bool has_apb_dma;
 218         u32 tlow_std_mode;
 219         u32 thigh_std_mode;
 220         u32 tlow_fast_fastplus_mode;
 221         u32 thigh_fast_fastplus_mode;
 222         u32 setup_hold_time_std_mode;
 223         u32 setup_hold_time_fast_fast_plus_mode;
 224         u32 setup_hold_time_hs_mode;
 225         bool has_interface_timing_reg;
 226 };
 227
 228 /**
 229  * struct tegra_i2c_dev - per device I2C context
 230  * @dev: device reference for power management
 231  * @hw: Tegra I2C HW feature
 232  * @adapter: core I2C layer adapter information
 233  * @div_clk: clock reference for div clock of I2C controller
 234  * @clocks: array of I2C controller clocks
 235  * @nclocks: number of clocks in the array
 236  * @rst: reset control for the I2C controller
 237  * @base: ioremapped registers cookie
 238  * @base_phys: physical base address of the I2C controller
 239  * @cont_id: I2C controller ID, used for packet header
 240  * @irq: IRQ number of transfer complete interrupt
 241  * @is_dvc: identifies the DVC I2C controller, has a different register layout
 242  * @is_vi: identifies the VI I2C controller, has a different register layout
 243  * @msg_complete: transfer completion notifier
 244  * @msg_err: error code for completed message
 245  * @msg_buf: pointer to current message data
 246  * @msg_buf_remaining: size of unsent data in the message buffer
 247  * @msg_read: indicates that the transfer is a read access
 248  * @bus_clk_rate: current I2C bus clock rate
 249  * @multimaster_mode: indicates that I2C controller is in multi-master mode
 250  * @tx_dma_chan: DMA transmit channel
 251  * @rx_dma_chan: DMA receive channel
 252  * @dma_phys: handle to DMA resources
 253  * @dma_buf: pointer to allocated DMA buffer
 254  * @dma_buf_size: DMA buffer size
 255  * @dma_mode: indicates active DMA transfer
 256  * @dma_complete: DMA completion notifier
 257  * @atomic_mode: indicates active atomic transfer
 258  */
 259 struct tegra_i2c_dev {
 260         struct device *dev;
 261         struct i2c_adapter adapter;
 262
 263         const struct tegra_i2c_hw_feature *hw;
 264         struct reset_control *rst;
 265         unsigned int cont_id;
 266         unsigned int irq;
 267
 268         phys_addr_t base_phys;
 269         void __iomem *base;
 270
 271         struct clk_bulk_data clocks[2];
 272         unsigned int nclocks;
 273
 274         struct clk *div_clk;
 275         u32 bus_clk_rate;
 276
 277         struct completion msg_complete;
 278         size_t msg_buf_remaining;
 279         int msg_err;
 280         u8 *msg_buf;
 281
 282         struct completion dma_complete;
 283         struct dma_chan *tx_dma_chan;
 284         struct dma_chan *rx_dma_chan;
 285         unsigned int dma_buf_size;
 286         dma_addr_t dma_phys;
 287         void *dma_buf;
 288
 289         bool multimaster_mode;
 290         bool atomic_mode;
 291         bool dma_mode;
 292         bool msg_read;
 293         bool is_dvc;
 294         bool is_vi;
 295 };
 296
 297 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
 298                        unsigned int reg)
 299 {
 300         writel_relaxed(val, i2c_dev->base + reg);
 301 }
 302
 303 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg)
 304 {
 305         return readl_relaxed(i2c_dev->base + reg);
 306 }
 307
 308 /*
 309  * If necessary, i2c_writel() and i2c_readl() will offset the register
 310  * in order to talk to the I2C block inside the DVC block.
 311  */
 312 static u32 tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, unsigned int reg)
 313 {
 314         if (i2c_dev->is_dvc)
 315                 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
 316         else if (i2c_dev->is_vi)
 317                 reg = 0xc00 + (reg << 2);
 318
 319         return reg;
 320 }
 321
 322 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned int reg)
 323 {
 324         writel_relaxed(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 325
 326         /* read back register to make sure that register writes completed */
 327         if (reg != I2C_TX_FIFO)
 328                 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 329 }
 330
 331 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg)
 332 {
 333         return readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 334 }
 335
 336 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
 337                         unsigned int reg, unsigned int len)
 338 {
 339         writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 340 }
 341
 342 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
 343                        unsigned int reg, unsigned int len)
 344 {
 345         readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 346 }
 347
 348 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 349 {
 350         u32 int_mask;
 351
 352         int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask;
 353         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 354 }
 355
 356 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 357 {
 358         u32 int_mask;
 359
 360         int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask;
 361         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 362 }
 363
 364 static void tegra_i2c_dma_complete(void *args)
 365 {
 366         struct tegra_i2c_dev *i2c_dev = args;
 367
 368         complete(&i2c_dev->dma_complete);
 369 }
 370
 371 static int tegra_i2c_dma_submit(struct tegra_i2c_dev *i2c_dev, size_t len)
 372 {
 373         struct dma_async_tx_descriptor *dma_desc;
 374         enum dma_transfer_direction dir;
 375         struct dma_chan *chan;
 376
 377         dev_dbg(i2c_dev->dev, "starting DMA for length: %zu\n", len);
 378
 379         reinit_completion(&i2c_dev->dma_complete);
 380
 381         dir = i2c_dev->msg_read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
 382         chan = i2c_dev->msg_read ? i2c_dev->rx_dma_chan : i2c_dev->tx_dma_chan;
 383
 384         dma_desc = dmaengine_prep_slave_single(chan, i2c_dev->dma_phys,
 385                                                len, dir, DMA_PREP_INTERRUPT |
 386                                                DMA_CTRL_ACK);
 387         if (!dma_desc) {
 388                 dev_err(i2c_dev->dev, "failed to get %s DMA descriptor\n",
 389                         i2c_dev->msg_read ? "RX" : "TX");
 390                 return -EINVAL;
 391         }
 392
 393         dma_desc->callback = tegra_i2c_dma_complete;
 394         dma_desc->callback_param = i2c_dev;
 395
 396         dmaengine_submit(dma_desc);
 397         dma_async_issue_pending(chan);
 398
 399         return 0;
 400 }
 401
 402 static void tegra_i2c_release_dma(struct tegra_i2c_dev *i2c_dev)
 403 {
 404         if (i2c_dev->dma_buf) {
 405                 dma_free_coherent(i2c_dev->dev, i2c_dev->dma_buf_size,
 406                                   i2c_dev->dma_buf, i2c_dev->dma_phys);
 407                 i2c_dev->dma_buf = NULL;
 408         }
 409
 410         if (i2c_dev->tx_dma_chan) {
 411                 dma_release_channel(i2c_dev->tx_dma_chan);
 412                 i2c_dev->tx_dma_chan = NULL;
 413         }
 414
 415         if (i2c_dev->rx_dma_chan) {
 416                 dma_release_channel(i2c_dev->rx_dma_chan);
 417                 i2c_dev->rx_dma_chan = NULL;
 418         }
 419 }
 420
 421 static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev)
 422 {
 423         struct dma_chan *chan;
 424         dma_addr_t dma_phys;
 425         u32 *dma_buf;
 426         int err;
 427
 428         if (!i2c_dev->hw->has_apb_dma || i2c_dev->is_vi)
 429                 return 0;
 430
 431         if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) {
 432                 dev_dbg(i2c_dev->dev, "DMA support not enabled\n");
 433                 return 0;
 434         }
 435
 436         chan = dma_request_chan(i2c_dev->dev, "rx");
 437         if (IS_ERR(chan)) {
 438                 err = PTR_ERR(chan);
 439                 goto err_out;
 440         }
 441
 442         i2c_dev->rx_dma_chan = chan;
 443
 444         chan = dma_request_chan(i2c_dev->dev, "tx");
 445         if (IS_ERR(chan)) {
 446                 err = PTR_ERR(chan);
 447                 goto err_out;
 448         }
 449
 450         i2c_dev->tx_dma_chan = chan;
 451
 452         i2c_dev->dma_buf_size = i2c_dev->hw->quirks->max_write_len +
 453                                 I2C_PACKET_HEADER_SIZE;
 454
 455         dma_buf = dma_alloc_coherent(i2c_dev->dev, i2c_dev->dma_buf_size,
 456                                      &dma_phys, GFP_KERNEL | __GFP_NOWARN);
 457         if (!dma_buf) {
 458                 dev_err(i2c_dev->dev, "failed to allocate DMA buffer\n");
 459                 err = -ENOMEM;
 460                 goto err_out;
 461         }
 462
 463         i2c_dev->dma_buf = dma_buf;
 464         i2c_dev->dma_phys = dma_phys;
 465
 466         return 0;
 467
 468 err_out:
 469         tegra_i2c_release_dma(i2c_dev);
 470         if (err != -EPROBE_DEFER) {
 471                 dev_err(i2c_dev->dev, "cannot use DMA: %d\n", err);
 472                 dev_err(i2c_dev->dev, "falling back to PIO\n");
 473                 return 0;
 474         }
 475
 476         return err;
 477 }
 478
 479 /*
 480  * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
 481  * block.  This block is identical to the rest of the I2C blocks, except that
 482  * it only supports master mode, it has registers moved around, and it needs
 483  * some extra init to get it into I2C mode.  The register moves are handled
 484  * by i2c_readl() and i2c_writel().
 485  */
 486 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
 487 {
 488         u32 val;
 489
 490         val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
 491         val |= DVC_CTRL_REG3_SW_PROG;
 492         val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
 493         dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
 494
 495         val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
 496         val |= DVC_CTRL_REG1_INTR_EN;
 497         dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
 498 }
 499
 500 static void tegra_i2c_vi_init(struct tegra_i2c_dev *i2c_dev)
 501 {
 502         u32 value;
 503
 504         value = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, 2) |
 505                 FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, 4);
 506         i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_0);
 507
 508         value = FIELD_PREP(I2C_INTERFACE_TIMING_TBUF, 4) |
 509                 FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STO, 7) |
 510                 FIELD_PREP(I2C_INTERFACE_TIMING_THD_STA, 4) |
 511                 FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STA, 4);
 512         i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_1);
 513
 514         value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, 3) |
 515                 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, 8);
 516         i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_0);
 517
 518         value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STO, 11) |
 519                 FIELD_PREP(I2C_HS_INTERFACE_TIMING_THD_STA, 11) |
 520                 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STA, 11);
 521         i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_1);
 522
 523         value = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND;
 524         i2c_writel(i2c_dev, value, I2C_BUS_CLEAR_CNFG);
 525
 526         i2c_writel(i2c_dev, 0x0, I2C_TLOW_SEXT);
 527 }
 528
 529 static int tegra_i2c_poll_register(struct tegra_i2c_dev *i2c_dev,
 530                                    u32 reg, u32 mask, u32 delay_us,
 531                                    u32 timeout_us)
 532 {
 533         void __iomem *addr = i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg);
 534         u32 val;
 535
 536         if (!i2c_dev->atomic_mode)
 537                 return readl_relaxed_poll_timeout(addr, val, !(val & mask),
 538                                                   delay_us, timeout_us);
 539
 540         return readl_relaxed_poll_timeout_atomic(addr, val, !(val & mask),
 541                                                  delay_us, timeout_us);
 542 }
 543
 544 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
 545 {
 546         u32 mask, val, offset;
 547         int err;
 548
 549         if (i2c_dev->hw->has_mst_fifo) {
 550                 mask = I2C_MST_FIFO_CONTROL_TX_FLUSH |
 551                        I2C_MST_FIFO_CONTROL_RX_FLUSH;
 552                 offset = I2C_MST_FIFO_CONTROL;
 553         } else {
 554                 mask = I2C_FIFO_CONTROL_TX_FLUSH |
 555                        I2C_FIFO_CONTROL_RX_FLUSH;
 556                 offset = I2C_FIFO_CONTROL;
 557         }
 558
 559         val = i2c_readl(i2c_dev, offset);
 560         val |= mask;
 561         i2c_writel(i2c_dev, val, offset);
 562
 563         err = tegra_i2c_poll_register(i2c_dev, offset, mask, 1000, 1000000);
 564         if (err) {
 565                 dev_err(i2c_dev->dev, "failed to flush FIFO\n");
 566                 return err;
 567         }
 568
 569         return 0;
 570 }
 571
 572 static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev)
 573 {
 574         int err;
 575
 576         if (!i2c_dev->hw->has_config_load_reg)
 577                 return 0;
 578
 579         i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD);
 580
 581         err = tegra_i2c_poll_register(i2c_dev, I2C_CONFIG_LOAD, 0xffffffff,
 582                                       1000, I2C_CONFIG_LOAD_TIMEOUT);
 583         if (err) {
 584                 dev_err(i2c_dev->dev, "failed to load config\n");
 585                 return err;
 586         }
 587
 588         return 0;
 589 }
 590
 591 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
 592 {
 593         u32 val, clk_divisor, clk_multiplier, tsu_thd, tlow, thigh, non_hs_mode;
 594         int err;
 595
 596         /*
 597          * The reset shouldn't ever fail in practice. The failure will be a
 598          * sign of a severe problem that needs to be resolved. Still we don't
 599          * want to fail the initialization completely because this may break
 600          * kernel boot up since voltage regulators use I2C. Hence, we will
 601          * emit a noisy warning on error, which won't stay unnoticed and
 602          * won't hose machine entirely.
 603          */
 604         err = reset_control_reset(i2c_dev->rst);
 605         WARN_ON_ONCE(err);
 606
 607         if (i2c_dev->is_dvc)
 608                 tegra_dvc_init(i2c_dev);
 609
 610         val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
 611               FIELD_PREP(I2C_CNFG_DEBOUNCE_CNT, 2);
 612
 613         if (i2c_dev->hw->has_multi_master_mode)
 614                 val |= I2C_CNFG_MULTI_MASTER_MODE;
 615
 616         i2c_writel(i2c_dev, val, I2C_CNFG);
 617         i2c_writel(i2c_dev, 0, I2C_INT_MASK);
 618
 619         if (i2c_dev->is_vi)
 620                 tegra_i2c_vi_init(i2c_dev);
 621
 622         switch (i2c_dev->bus_clk_rate) {
 623         case I2C_MAX_STANDARD_MODE_FREQ + 1 ... I2C_MAX_FAST_MODE_PLUS_FREQ:
 624         default:
 625                 tlow = i2c_dev->hw->tlow_fast_fastplus_mode;
 626                 thigh = i2c_dev->hw->thigh_fast_fastplus_mode;
 627                 tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode;
 628
 629                 if (i2c_dev->bus_clk_rate > I2C_MAX_FAST_MODE_FREQ)
 630                         non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode;
 631                 else
 632                         non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode;
 633                 break;
 634
 635         case 0 ... I2C_MAX_STANDARD_MODE_FREQ:
 636                 tlow = i2c_dev->hw->tlow_std_mode;
 637                 thigh = i2c_dev->hw->thigh_std_mode;
 638                 tsu_thd = i2c_dev->hw->setup_hold_time_std_mode;
 639                 non_hs_mode = i2c_dev->hw->clk_divisor_std_mode;
 640                 break;
 641         }
 642
 643         /* make sure clock divisor programmed correctly */
 644         clk_divisor = FIELD_PREP(I2C_CLK_DIVISOR_HSMODE,
 645                                  i2c_dev->hw->clk_divisor_hs_mode) |
 646                       FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE, non_hs_mode);
 647         i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
 648
 649         if (i2c_dev->hw->has_interface_timing_reg) {
 650                 val = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, thigh) |
 651                       FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, tlow);
 652                 i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0);
 653         }
 654
 655         /*
 656          * Configure setup and hold times only when tsu_thd is non-zero.
 657          * Otherwise, preserve the chip default values.
 658          */
 659         if (i2c_dev->hw->has_interface_timing_reg && tsu_thd)
 660                 i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1);
 661
 662         clk_multiplier = (tlow + thigh + 2) * (non_hs_mode + 1);
 663
 664         err = clk_set_rate(i2c_dev->div_clk,
 665                            i2c_dev->bus_clk_rate * clk_multiplier);
 666         if (err) {
 667                 dev_err(i2c_dev->dev, "failed to set div-clk rate: %d\n", err);
 668                 return err;
 669         }
 670
 671         if (!i2c_dev->is_dvc && !i2c_dev->is_vi) {
 672                 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
 673
 674                 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
 675                 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
 676                 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
 677                 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
 678         }
 679
 680         err = tegra_i2c_flush_fifos(i2c_dev);
 681         if (err)
 682                 return err;
 683
 684         if (i2c_dev->multimaster_mode && i2c_dev->hw->has_slcg_override_reg)
 685                 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE);
 686
 687         err = tegra_i2c_wait_for_config_load(i2c_dev);
 688         if (err)
 689                 return err;
 690
 691         return 0;
 692 }
 693
 694 static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev)
 695 {
 696         u32 cnfg;
 697
 698         /*
 699          * NACK interrupt is generated before the I2C controller generates
 700          * the STOP condition on the bus.  So, wait for 2 clock periods
 701          * before disabling the controller so that the STOP condition has
 702          * been delivered properly.
 703          */
 704         udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
 705
 706         cnfg = i2c_readl(i2c_dev, I2C_CNFG);
 707         if (cnfg & I2C_CNFG_PACKET_MODE_EN)
 708                 i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG);
 709
 710         return tegra_i2c_wait_for_config_load(i2c_dev);
 711 }
 712
 713 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
 714 {
 715         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 716         unsigned int words_to_transfer, rx_fifo_avail;
 717         u8 *buf = i2c_dev->msg_buf;
 718         u32 val;
 719
 720         /*
 721          * Catch overflow due to message fully sent before the check for
 722          * RX FIFO availability.
 723          */
 724         if (WARN_ON_ONCE(!(i2c_dev->msg_buf_remaining)))
 725                 return -EINVAL;
 726
 727         if (i2c_dev->hw->has_mst_fifo) {
 728                 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS);
 729                 rx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_RX, val);
 730         } else {
 731                 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 732                 rx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_RX, val);
 733         }
 734
 735         /* round down to exclude partial word at the end of buffer */
 736         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 737         if (words_to_transfer > rx_fifo_avail)
 738                 words_to_transfer = rx_fifo_avail;
 739
 740         i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
 741
 742         buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 743         buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 744         rx_fifo_avail -= words_to_transfer;
 745
 746         /*
 747          * If there is a partial word at the end of buffer, handle it
 748          * manually to prevent overwriting past the end of buffer.
 749          */
 750         if (rx_fifo_avail > 0 && buf_remaining > 0) {
 751                 /*
 752                  * buf_remaining > 3 check not needed as rx_fifo_avail == 0
 753                  * when (words_to_transfer was > rx_fifo_avail) earlier
 754                  * in this function.
 755                  */
 756                 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
 757                 val = cpu_to_le32(val);
 758                 memcpy(buf, &val, buf_remaining);
 759                 buf_remaining = 0;
 760                 rx_fifo_avail--;
 761         }
 762
 763         /* RX FIFO must be drained, otherwise it's an Overflow case. */
 764         if (WARN_ON_ONCE(rx_fifo_avail))
 765                 return -EINVAL;
 766
 767         i2c_dev->msg_buf_remaining = buf_remaining;
 768         i2c_dev->msg_buf = buf;
 769
 770         return 0;
 771 }
 772
 773 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
 774 {
 775         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 776         unsigned int words_to_transfer, tx_fifo_avail;
 777         u8 *buf = i2c_dev->msg_buf;
 778         u32 val;
 779
 780         if (i2c_dev->hw->has_mst_fifo) {
 781                 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS);
 782                 tx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_TX, val);
 783         } else {
 784                 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 785                 tx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_TX, val);
 786         }
 787
 788         /* round down to exclude partial word at the end of buffer */
 789         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 790
 791         /*
 792          * This hunk pushes 4 bytes at a time into the TX FIFO.
 793          *
 794          * It's very common to have < 4 bytes, hence there is no word
 795          * to push if we have less than 4 bytes to transfer.
 796          */
 797         if (words_to_transfer) {
 798                 if (words_to_transfer > tx_fifo_avail)
 799                         words_to_transfer = tx_fifo_avail;
 800
 801                 /*
 802                  * Update state before writing to FIFO.  Note that this may
 803                  * cause us to finish writing all bytes (AKA buf_remaining
 804                  * goes to 0), hence we have a potential for an interrupt
 805                  * (PACKET_XFER_COMPLETE is not maskable), but GIC interrupt
 806                  * is disabled at this point.
 807                  */
 808                 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 809                 tx_fifo_avail -= words_to_transfer;
 810
 811                 i2c_dev->msg_buf_remaining = buf_remaining;
 812                 i2c_dev->msg_buf = buf + words_to_transfer * BYTES_PER_FIFO_WORD;
 813
 814                 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
 815
 816                 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 817         }
 818
 819         /*
 820          * If there is a partial word at the end of buffer, handle it manually
 821          * to prevent reading past the end of buffer, which could cross a page
 822          * boundary and fault.
 823          */
 824         if (tx_fifo_avail > 0 && buf_remaining > 0) {
 825                 /*
 826                  * buf_remaining > 3 check not needed as tx_fifo_avail == 0
 827                  * when (words_to_transfer was > tx_fifo_avail) earlier
 828                  * in this function for non-zero words_to_transfer.
 829                  */
 830                 memcpy(&val, buf, buf_remaining);
 831                 val = le32_to_cpu(val);
 832
 833                 i2c_dev->msg_buf_remaining = 0;
 834                 i2c_dev->msg_buf = NULL;
 835
 836                 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
 837         }
 838
 839         return 0;
 840 }
 841
 842 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
 843 {
 844         const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
 845         struct tegra_i2c_dev *i2c_dev = dev_id;
 846         u32 status;
 847
 848         status = i2c_readl(i2c_dev, I2C_INT_STATUS);
 849
 850         if (status == 0) {
 851                 dev_warn(i2c_dev->dev, "IRQ status 0 %08x %08x %08x\n",
 852                          i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
 853                          i2c_readl(i2c_dev, I2C_STATUS),
 854                          i2c_readl(i2c_dev, I2C_CNFG));
 855                 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
 856                 goto err;
 857         }
 858
 859         if (status & status_err) {
 860                 tegra_i2c_disable_packet_mode(i2c_dev);
 861                 if (status & I2C_INT_NO_ACK)
 862                         i2c_dev->msg_err |= I2C_ERR_NO_ACK;
 863                 if (status & I2C_INT_ARBITRATION_LOST)
 864                         i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
 865                 goto err;
 866         }
 867
 868         /*
 869          * I2C transfer is terminated during the bus clear, so skip
 870          * processing the other interrupts.
 871          */
 872         if (i2c_dev->hw->supports_bus_clear && (status & I2C_INT_BUS_CLR_DONE))
 873                 goto err;
 874
 875         if (!i2c_dev->dma_mode) {
 876                 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
 877                         if (tegra_i2c_empty_rx_fifo(i2c_dev)) {
 878                                 /*
 879                                  * Overflow error condition: message fully sent,
 880                                  * with no XFER_COMPLETE interrupt but hardware
 881                                  * asks to transfer more.
 882                                  */
 883                                 i2c_dev->msg_err |= I2C_ERR_RX_BUFFER_OVERFLOW;
 884                                 goto err;
 885                         }
 886                 }
 887
 888                 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
 889                         if (i2c_dev->msg_buf_remaining)
 890                                 tegra_i2c_fill_tx_fifo(i2c_dev);
 891                         else
 892                                 tegra_i2c_mask_irq(i2c_dev,
 893                                                    I2C_INT_TX_FIFO_DATA_REQ);
 894                 }
 895         }
 896
 897         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 898         if (i2c_dev->is_dvc)
 899                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 900
 901         /*
 902          * During message read XFER_COMPLETE interrupt is triggered prior to
 903          * DMA completion and during message write XFER_COMPLETE interrupt is
 904          * triggered after DMA completion.
 905          *
 906          * PACKETS_XFER_COMPLETE indicates completion of all bytes of transfer,
 907          * so forcing msg_buf_remaining to 0 in DMA mode.
 908          */
 909         if (status & I2C_INT_PACKET_XFER_COMPLETE) {
 910                 if (i2c_dev->dma_mode)
 911                         i2c_dev->msg_buf_remaining = 0;
 912                 /*
 913                  * Underflow error condition: XFER_COMPLETE before message
 914                  * fully sent.
 915                  */
 916                 if (WARN_ON_ONCE(i2c_dev->msg_buf_remaining)) {
 917                         i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
 918                         goto err;
 919                 }
 920                 complete(&i2c_dev->msg_complete);
 921         }
 922         goto done;
 923 err:
 924         /* mask all interrupts on error */
 925         tegra_i2c_mask_irq(i2c_dev,
 926                            I2C_INT_NO_ACK |
 927                            I2C_INT_ARBITRATION_LOST |
 928                            I2C_INT_PACKET_XFER_COMPLETE |
 929                            I2C_INT_TX_FIFO_DATA_REQ |
 930                            I2C_INT_RX_FIFO_DATA_REQ);
 931
 932         if (i2c_dev->hw->supports_bus_clear)
 933                 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
 934
 935         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 936
 937         if (i2c_dev->is_dvc)
 938                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 939
 940         if (i2c_dev->dma_mode) {
 941                 if (i2c_dev->msg_read)
 942                         dmaengine_terminate_async(i2c_dev->rx_dma_chan);
 943                 else
 944                         dmaengine_terminate_async(i2c_dev->tx_dma_chan);
 945
 946                 complete(&i2c_dev->dma_complete);
 947         }
 948
 949         complete(&i2c_dev->msg_complete);
 950 done:
 951         return IRQ_HANDLED;
 952 }
 953
 954 static void tegra_i2c_config_fifo_trig(struct tegra_i2c_dev *i2c_dev,
 955                                        size_t len)
 956 {
 957         struct dma_slave_config slv_config = {0};
 958         u32 val, reg, dma_burst, reg_offset;
 959         struct dma_chan *chan;
 960         int err;
 961
 962         if (i2c_dev->hw->has_mst_fifo)
 963                 reg = I2C_MST_FIFO_CONTROL;
 964         else
 965                 reg = I2C_FIFO_CONTROL;
 966
 967         if (i2c_dev->dma_mode) {
 968                 if (len & 0xF)
 969                         dma_burst = 1;
 970                 else if (len & 0x10)
 971                         dma_burst = 4;
 972                 else
 973                         dma_burst = 8;
 974
 975                 if (i2c_dev->msg_read) {
 976                         chan = i2c_dev->rx_dma_chan;
 977                         reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_RX_FIFO);
 978
 979                         slv_config.src_addr = i2c_dev->base_phys + reg_offset;
 980                         slv_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 981                         slv_config.src_maxburst = dma_burst;
 982
 983                         if (i2c_dev->hw->has_mst_fifo)
 984                                 val = I2C_MST_FIFO_CONTROL_RX_TRIG(dma_burst);
 985                         else
 986                                 val = I2C_FIFO_CONTROL_RX_TRIG(dma_burst);
 987                 } else {
 988                         chan = i2c_dev->tx_dma_chan;
 989                         reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_TX_FIFO);
 990
 991                         slv_config.dst_addr = i2c_dev->base_phys + reg_offset;
 992                         slv_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 993                         slv_config.dst_maxburst = dma_burst;
 994
 995                         if (i2c_dev->hw->has_mst_fifo)
 996                                 val = I2C_MST_FIFO_CONTROL_TX_TRIG(dma_burst);
 997                         else
 998                                 val = I2C_FIFO_CONTROL_TX_TRIG(dma_burst);
 999                 }
1000
1001                 slv_config.device_fc = true;
1002                 err = dmaengine_slave_config(chan, &slv_config);
1003                 if (err) {
1004                         dev_err(i2c_dev->dev, "DMA config failed: %d\n", err);
1005                         dev_err(i2c_dev->dev, "falling back to PIO\n");
1006
1007                         tegra_i2c_release_dma(i2c_dev);
1008                         i2c_dev->dma_mode = false;
1009                 } else {
1010                         goto out;
1011                 }
1012         }
1013
1014         if (i2c_dev->hw->has_mst_fifo)
1015                 val = I2C_MST_FIFO_CONTROL_TX_TRIG(8) |
1016                       I2C_MST_FIFO_CONTROL_RX_TRIG(1);
1017         else
1018                 val = I2C_FIFO_CONTROL_TX_TRIG(8) |
1019                       I2C_FIFO_CONTROL_RX_TRIG(1);
1020 out:
1021         i2c_writel(i2c_dev, val, reg);
1022 }
1023
1024 static unsigned long tegra_i2c_poll_completion(struct tegra_i2c_dev *i2c_dev,
1025                                                struct completion *complete,
1026                                                unsigned int timeout_ms)
1027 {
1028         ktime_t ktime = ktime_get();
1029         ktime_t ktimeout = ktime_add_ms(ktime, timeout_ms);
1030
1031         do {
1032                 u32 status = i2c_readl(i2c_dev, I2C_INT_STATUS);
1033
1034                 if (status)
1035                         tegra_i2c_isr(i2c_dev->irq, i2c_dev);
1036
1037                 if (completion_done(complete)) {
1038                         s64 delta = ktime_ms_delta(ktimeout, ktime);
1039
1040                         return msecs_to_jiffies(delta) ?: 1;
1041                 }
1042
1043                 ktime = ktime_get();
1044
1045         } while (ktime_before(ktime, ktimeout));
1046
1047         return 0;
1048 }
1049
1050 static unsigned long tegra_i2c_wait_completion(struct tegra_i2c_dev *i2c_dev,
1051                                                struct completion *complete,
1052                                                unsigned int timeout_ms)
1053 {
1054         unsigned long ret;
1055
1056         if (i2c_dev->atomic_mode) {
1057                 ret = tegra_i2c_poll_completion(i2c_dev, complete, timeout_ms);
1058         } else {
1059                 enable_irq(i2c_dev->irq);
1060                 ret = wait_for_completion_timeout(complete,
1061                                                   msecs_to_jiffies(timeout_ms));
1062                 disable_irq(i2c_dev->irq);
1063
1064                 /*
1065                  * Under some rare circumstances (like running KASAN +
1066                  * NFS root) CPU, which handles interrupt, may stuck in
1067                  * uninterruptible state for a significant time.  In this
1068                  * case we will get timeout if I2C transfer is running on
1069                  * a sibling CPU, despite of IRQ being raised.
1070                  *
1071                  * In order to handle this rare condition, the IRQ status
1072                  * needs to be checked after timeout.
1073                  */
1074                 if (ret == 0)
1075                         ret = tegra_i2c_poll_completion(i2c_dev, complete, 0);
1076         }
1077
1078         return ret;
1079 }
1080
1081 static int tegra_i2c_issue_bus_clear(struct i2c_adapter *adap)
1082 {
1083         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1084         u32 val, time_left;
1085         int err;
1086
1087         reinit_completion(&i2c_dev->msg_complete);
1088
1089         val = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND |
1090               I2C_BC_TERMINATE;
1091         i2c_writel(i2c_dev, val, I2C_BUS_CLEAR_CNFG);
1092
1093         err = tegra_i2c_wait_for_config_load(i2c_dev);
1094         if (err)
1095                 return err;
1096
1097         val |= I2C_BC_ENABLE;
1098         i2c_writel(i2c_dev, val, I2C_BUS_CLEAR_CNFG);
1099         tegra_i2c_unmask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
1100
1101         time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete, 50);
1102         tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
1103
1104         if (time_left == 0) {
1105                 dev_err(i2c_dev->dev, "failed to clear bus\n");
1106                 return -ETIMEDOUT;
1107         }
1108
1109         val = i2c_readl(i2c_dev, I2C_BUS_CLEAR_STATUS);
1110         if (!(val & I2C_BC_STATUS)) {
1111                 dev_err(i2c_dev->dev, "un-recovered arbitration lost\n");
1112                 return -EIO;
1113         }
1114
1115         return -EAGAIN;
1116 }
1117
1118 static void tegra_i2c_push_packet_header(struct tegra_i2c_dev *i2c_dev,
1119                                          struct i2c_msg *msg,
1120                                          enum msg_end_type end_state)
1121 {
1122         u32 *dma_buf = i2c_dev->dma_buf;
1123         u32 packet_header;
1124
1125         packet_header = FIELD_PREP(PACKET_HEADER0_HEADER_SIZE, 0) |
1126                         FIELD_PREP(PACKET_HEADER0_PROTOCOL,
1127                                    PACKET_HEADER0_PROTOCOL_I2C) |
1128                         FIELD_PREP(PACKET_HEADER0_CONT_ID, i2c_dev->cont_id) |
1129                         FIELD_PREP(PACKET_HEADER0_PACKET_ID, 1);
1130
1131         if (i2c_dev->dma_mode && !i2c_dev->msg_read)
1132                 *dma_buf++ = packet_header;
1133         else
1134                 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1135
1136         packet_header = msg->len - 1;
1137
1138         if (i2c_dev->dma_mode && !i2c_dev->msg_read)
1139                 *dma_buf++ = packet_header;
1140         else
1141                 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1142
1143         packet_header = I2C_HEADER_IE_ENABLE;
1144
1145         if (end_state == MSG_END_CONTINUE)
1146                 packet_header |= I2C_HEADER_CONTINUE_XFER;
1147         else if (end_state == MSG_END_REPEAT_START)
1148                 packet_header |= I2C_HEADER_REPEAT_START;
1149
1150         if (msg->flags & I2C_M_TEN) {
1151                 packet_header |= msg->addr;
1152                 packet_header |= I2C_HEADER_10BIT_ADDR;
1153         } else {
1154                 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
1155         }
1156
1157         if (msg->flags & I2C_M_IGNORE_NAK)
1158                 packet_header |= I2C_HEADER_CONT_ON_NAK;
1159
1160         if (msg->flags & I2C_M_RD)
1161                 packet_header |= I2C_HEADER_READ;
1162
1163         if (i2c_dev->dma_mode && !i2c_dev->msg_read)
1164                 *dma_buf++ = packet_header;
1165         else
1166                 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1167 }
1168
1169 static int tegra_i2c_error_recover(struct tegra_i2c_dev *i2c_dev,
1170                                    struct i2c_msg *msg)
1171 {
1172         if (i2c_dev->msg_err == I2C_ERR_NONE)
1173                 return 0;
1174
1175         tegra_i2c_init(i2c_dev);
1176
1177         /* start recovery upon arbitration loss in single master mode */
1178         if (i2c_dev->msg_err == I2C_ERR_ARBITRATION_LOST) {
1179                 if (!i2c_dev->multimaster_mode)
1180                         return i2c_recover_bus(&i2c_dev->adapter);
1181
1182                 return -EAGAIN;
1183         }
1184
1185         if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
1186                 if (msg->flags & I2C_M_IGNORE_NAK)
1187                         return 0;
1188
1189                 return -EREMOTEIO;
1190         }
1191
1192         return -EIO;
1193 }
1194
1195 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
1196                               struct i2c_msg *msg,
1197                               enum msg_end_type end_state)
1198 {
1199         unsigned long time_left, xfer_time = 100;
1200         size_t xfer_size;
1201         u32 int_mask;
1202         int err;
1203
1204         err = tegra_i2c_flush_fifos(i2c_dev);
1205         if (err)
1206                 return err;
1207
1208         i2c_dev->msg_buf = msg->buf;
1209         i2c_dev->msg_buf_remaining = msg->len;
1210         i2c_dev->msg_err = I2C_ERR_NONE;
1211         i2c_dev->msg_read = !!(msg->flags & I2C_M_RD);
1212         reinit_completion(&i2c_dev->msg_complete);
1213
1214         if (i2c_dev->msg_read)
1215                 xfer_size = msg->len;
1216         else
1217                 xfer_size = msg->len + I2C_PACKET_HEADER_SIZE;
1218
1219         xfer_size = ALIGN(xfer_size, BYTES_PER_FIFO_WORD);
1220
1221         i2c_dev->dma_mode = xfer_size > I2C_PIO_MODE_PREFERRED_LEN &&
1222                             i2c_dev->dma_buf && !i2c_dev->atomic_mode;
1223
1224         tegra_i2c_config_fifo_trig(i2c_dev, xfer_size);
1225
1226         /*
1227          * Transfer time in mSec = Total bits / transfer rate
1228          * Total bits = 9 bits per byte (including ACK bit) + Start & stop bits
1229          */
1230         xfer_time += DIV_ROUND_CLOSEST(((xfer_size * 9) + 2) * MSEC_PER_SEC,
1231                                        i2c_dev->bus_clk_rate);
1232
1233         int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
1234         tegra_i2c_unmask_irq(i2c_dev, int_mask);
1235
1236         if (i2c_dev->dma_mode) {
1237                 if (i2c_dev->msg_read) {
1238                         dma_sync_single_for_device(i2c_dev->dev,
1239                                                    i2c_dev->dma_phys,
1240                                                    xfer_size, DMA_FROM_DEVICE);
1241
1242                         err = tegra_i2c_dma_submit(i2c_dev, xfer_size);
1243                         if (err)
1244                                 return err;
1245                 } else {
1246                         dma_sync_single_for_cpu(i2c_dev->dev,
1247                                                 i2c_dev->dma_phys,
1248                                                 xfer_size, DMA_TO_DEVICE);
1249                 }
1250         }
1251
1252         tegra_i2c_push_packet_header(i2c_dev, msg, end_state);
1253
1254         if (!i2c_dev->msg_read) {
1255                 if (i2c_dev->dma_mode) {
1256                         memcpy(i2c_dev->dma_buf + I2C_PACKET_HEADER_SIZE,
1257                                msg->buf, msg->len);
1258
1259                         dma_sync_single_for_device(i2c_dev->dev,
1260                                                    i2c_dev->dma_phys,
1261                                                    xfer_size, DMA_TO_DEVICE);
1262
1263                         err = tegra_i2c_dma_submit(i2c_dev, xfer_size);
1264                         if (err)
1265                                 return err;
1266                 } else {
1267                         tegra_i2c_fill_tx_fifo(i2c_dev);
1268                 }
1269         }
1270
1271         if (i2c_dev->hw->has_per_pkt_xfer_complete_irq)
1272                 int_mask |= I2C_INT_PACKET_XFER_COMPLETE;
1273
1274         if (!i2c_dev->dma_mode) {
1275                 if (msg->flags & I2C_M_RD)
1276                         int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
1277                 else if (i2c_dev->msg_buf_remaining)
1278                         int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
1279         }
1280
1281         tegra_i2c_unmask_irq(i2c_dev, int_mask);
1282         dev_dbg(i2c_dev->dev, "unmasked IRQ: %02x\n",
1283                 i2c_readl(i2c_dev, I2C_INT_MASK));
1284
1285         if (i2c_dev->dma_mode) {
1286                 time_left = tegra_i2c_wait_completion(i2c_dev,
1287                                                       &i2c_dev->dma_complete,
1288                                                       xfer_time);
1289
1290                 /*
1291                  * Synchronize DMA first, since dmaengine_terminate_sync()
1292                  * performs synchronization after the transfer's termination
1293                  * and we want to get a completion if transfer succeeded.
1294                  */
1295                 dmaengine_synchronize(i2c_dev->msg_read ?
1296                                       i2c_dev->rx_dma_chan :
1297                                       i2c_dev->tx_dma_chan);
1298
1299                 dmaengine_terminate_sync(i2c_dev->msg_read ?
1300                                          i2c_dev->rx_dma_chan :
1301                                          i2c_dev->tx_dma_chan);
1302
1303                 if (!time_left && !completion_done(&i2c_dev->dma_complete)) {
1304                         dev_err(i2c_dev->dev, "DMA transfer timed out\n");
1305                         tegra_i2c_init(i2c_dev);
1306                         return -ETIMEDOUT;
1307                 }
1308
1309                 if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE) {
1310                         dma_sync_single_for_cpu(i2c_dev->dev,
1311                                                 i2c_dev->dma_phys,
1312                                                 xfer_size, DMA_FROM_DEVICE);
1313
1314                         memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf, msg->len);
1315                 }
1316         }
1317
1318         time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete,
1319                                               xfer_time);
1320
1321         tegra_i2c_mask_irq(i2c_dev, int_mask);
1322
1323         if (time_left == 0) {
1324                 dev_err(i2c_dev->dev, "I2C transfer timed out\n");
1325                 tegra_i2c_init(i2c_dev);
1326                 return -ETIMEDOUT;
1327         }
1328
1329         dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n",
1330                 time_left, completion_done(&i2c_dev->msg_complete),
1331                 i2c_dev->msg_err);
1332
1333         i2c_dev->dma_mode = false;
1334
1335         err = tegra_i2c_error_recover(i2c_dev, msg);
1336         if (err)
1337                 return err;
1338
1339         return 0;
1340 }
1341
1342 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
1343                           int num)
1344 {
1345         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1346         int i, ret;
1347
1348         ret = pm_runtime_get_sync(i2c_dev->dev);
1349         if (ret < 0) {
1350                 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret);
1351                 pm_runtime_put_noidle(i2c_dev->dev);
1352                 return ret;
1353         }
1354
1355         for (i = 0; i < num; i++) {
1356                 enum msg_end_type end_type = MSG_END_STOP;
1357
1358                 if (i < (num - 1)) {
1359                         /* check whether follow up message is coming */
1360                         if (msgs[i + 1].flags & I2C_M_NOSTART)
1361                                 end_type = MSG_END_CONTINUE;
1362                         else
1363                                 end_type = MSG_END_REPEAT_START;
1364                 }
1365                 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
1366                 if (ret)
1367                         break;
1368         }
1369
1370         pm_runtime_put(i2c_dev->dev);
1371
1372         return ret ?: i;
1373 }
1374
1375 static int tegra_i2c_xfer_atomic(struct i2c_adapter *adap,
1376                                  struct i2c_msg msgs[], int num)
1377 {
1378         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1379         int ret;
1380
1381         i2c_dev->atomic_mode = true;
1382         ret = tegra_i2c_xfer(adap, msgs, num);
1383         i2c_dev->atomic_mode = false;
1384
1385         return ret;
1386 }
1387
1388 static u32 tegra_i2c_func(struct i2c_adapter *adap)
1389 {
1390         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1391         u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
1392                   I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING;
1393
1394         if (i2c_dev->hw->has_continue_xfer_support)
1395                 ret |= I2C_FUNC_NOSTART;
1396
1397         return ret;
1398 }
1399
1400 static const struct i2c_algorithm tegra_i2c_algo = {
1401         .master_xfer            = tegra_i2c_xfer,
1402         .master_xfer_atomic     = tegra_i2c_xfer_atomic,
1403         .functionality          = tegra_i2c_func,
1404 };
1405
1406 /* payload size is only 12 bit */
1407 static const struct i2c_adapter_quirks tegra_i2c_quirks = {
1408         .flags = I2C_AQ_NO_ZERO_LEN,
1409         .max_read_len = SZ_4K,
1410         .max_write_len = SZ_4K - I2C_PACKET_HEADER_SIZE,
1411 };
1412
1413 static const struct i2c_adapter_quirks tegra194_i2c_quirks = {
1414         .flags = I2C_AQ_NO_ZERO_LEN,
1415         .max_write_len = SZ_64K - I2C_PACKET_HEADER_SIZE,
1416 };
1417
1418 static struct i2c_bus_recovery_info tegra_i2c_recovery_info = {
1419         .recover_bus = tegra_i2c_issue_bus_clear,
1420 };
1421
1422 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
1423         .has_continue_xfer_support = false,
1424         .has_per_pkt_xfer_complete_irq = false,
1425         .clk_divisor_hs_mode = 3,
1426         .clk_divisor_std_mode = 0,
1427         .clk_divisor_fast_mode = 0,
1428         .clk_divisor_fast_plus_mode = 0,
1429         .has_config_load_reg = false,
1430         .has_multi_master_mode = false,
1431         .has_slcg_override_reg = false,
1432         .has_mst_fifo = false,
1433         .quirks = &tegra_i2c_quirks,
1434         .supports_bus_clear = false,
1435         .has_apb_dma = true,
1436         .tlow_std_mode = 0x4,
1437         .thigh_std_mode = 0x2,
1438         .tlow_fast_fastplus_mode = 0x4,
1439         .thigh_fast_fastplus_mode = 0x2,
1440         .setup_hold_time_std_mode = 0x0,
1441         .setup_hold_time_fast_fast_plus_mode = 0x0,
1442         .setup_hold_time_hs_mode = 0x0,
1443         .has_interface_timing_reg = false,
1444 };
1445
1446 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
1447         .has_continue_xfer_support = true,
1448         .has_per_pkt_xfer_complete_irq = false,
1449         .clk_divisor_hs_mode = 3,
1450         .clk_divisor_std_mode = 0,
1451         .clk_divisor_fast_mode = 0,
1452         .clk_divisor_fast_plus_mode = 0,
1453         .has_config_load_reg = false,
1454         .has_multi_master_mode = false,
1455         .has_slcg_override_reg = false,
1456         .has_mst_fifo = false,
1457         .quirks = &tegra_i2c_quirks,
1458         .supports_bus_clear = false,
1459         .has_apb_dma = true,
1460         .tlow_std_mode = 0x4,
1461         .thigh_std_mode = 0x2,
1462         .tlow_fast_fastplus_mode = 0x4,
1463         .thigh_fast_fastplus_mode = 0x2,
1464         .setup_hold_time_std_mode = 0x0,
1465         .setup_hold_time_fast_fast_plus_mode = 0x0,
1466         .setup_hold_time_hs_mode = 0x0,
1467         .has_interface_timing_reg = false,
1468 };
1469
1470 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
1471         .has_continue_xfer_support = true,
1472         .has_per_pkt_xfer_complete_irq = true,
1473         .clk_divisor_hs_mode = 1,
1474         .clk_divisor_std_mode = 0x19,
1475         .clk_divisor_fast_mode = 0x19,
1476         .clk_divisor_fast_plus_mode = 0x10,
1477         .has_config_load_reg = false,
1478         .has_multi_master_mode = false,
1479         .has_slcg_override_reg = false,
1480         .has_mst_fifo = false,
1481         .quirks = &tegra_i2c_quirks,
1482         .supports_bus_clear = true,
1483         .has_apb_dma = true,
1484         .tlow_std_mode = 0x4,
1485         .thigh_std_mode = 0x2,
1486         .tlow_fast_fastplus_mode = 0x4,
1487         .thigh_fast_fastplus_mode = 0x2,
1488         .setup_hold_time_std_mode = 0x0,
1489         .setup_hold_time_fast_fast_plus_mode = 0x0,
1490         .setup_hold_time_hs_mode = 0x0,
1491         .has_interface_timing_reg = false,
1492 };
1493
1494 static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
1495         .has_continue_xfer_support = true,
1496         .has_per_pkt_xfer_complete_irq = true,
1497         .clk_divisor_hs_mode = 1,
1498         .clk_divisor_std_mode = 0x19,
1499         .clk_divisor_fast_mode = 0x19,
1500         .clk_divisor_fast_plus_mode = 0x10,
1501         .has_config_load_reg = true,
1502         .has_multi_master_mode = false,
1503         .has_slcg_override_reg = true,
1504         .has_mst_fifo = false,
1505         .quirks = &tegra_i2c_quirks,
1506         .supports_bus_clear = true,
1507         .has_apb_dma = true,
1508         .tlow_std_mode = 0x4,
1509         .thigh_std_mode = 0x2,
1510         .tlow_fast_fastplus_mode = 0x4,
1511         .thigh_fast_fastplus_mode = 0x2,
1512         .setup_hold_time_std_mode = 0x0,
1513         .setup_hold_time_fast_fast_plus_mode = 0x0,
1514         .setup_hold_time_hs_mode = 0x0,
1515         .has_interface_timing_reg = true,
1516 };
1517
1518 static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
1519         .has_continue_xfer_support = true,
1520         .has_per_pkt_xfer_complete_irq = true,
1521         .clk_divisor_hs_mode = 1,
1522         .clk_divisor_std_mode = 0x19,
1523         .clk_divisor_fast_mode = 0x19,
1524         .clk_divisor_fast_plus_mode = 0x10,
1525         .has_config_load_reg = true,
1526         .has_multi_master_mode = false,
1527         .has_slcg_override_reg = true,
1528         .has_mst_fifo = false,
1529         .quirks = &tegra_i2c_quirks,
1530         .supports_bus_clear = true,
1531         .has_apb_dma = true,
1532         .tlow_std_mode = 0x4,
1533         .thigh_std_mode = 0x2,
1534         .tlow_fast_fastplus_mode = 0x4,
1535         .thigh_fast_fastplus_mode = 0x2,
1536         .setup_hold_time_std_mode = 0,
1537         .setup_hold_time_fast_fast_plus_mode = 0,
1538         .setup_hold_time_hs_mode = 0,
1539         .has_interface_timing_reg = true,
1540 };
1541
1542 static const struct tegra_i2c_hw_feature tegra186_i2c_hw = {
1543         .has_continue_xfer_support = true,
1544         .has_per_pkt_xfer_complete_irq = true,
1545         .clk_divisor_hs_mode = 1,
1546         .clk_divisor_std_mode = 0x16,
1547         .clk_divisor_fast_mode = 0x19,
1548         .clk_divisor_fast_plus_mode = 0x10,
1549         .has_config_load_reg = true,
1550         .has_multi_master_mode = false,
1551         .has_slcg_override_reg = true,
1552         .has_mst_fifo = false,
1553         .quirks = &tegra_i2c_quirks,
1554         .supports_bus_clear = true,
1555         .has_apb_dma = false,
1556         .tlow_std_mode = 0x4,
1557         .thigh_std_mode = 0x3,
1558         .tlow_fast_fastplus_mode = 0x4,
1559         .thigh_fast_fastplus_mode = 0x2,
1560         .setup_hold_time_std_mode = 0,
1561         .setup_hold_time_fast_fast_plus_mode = 0,
1562         .setup_hold_time_hs_mode = 0,
1563         .has_interface_timing_reg = true,
1564 };
1565
1566 static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
1567         .has_continue_xfer_support = true,
1568         .has_per_pkt_xfer_complete_irq = true,
1569         .clk_divisor_hs_mode = 1,
1570         .clk_divisor_std_mode = 0x4f,
1571         .clk_divisor_fast_mode = 0x3c,
1572         .clk_divisor_fast_plus_mode = 0x16,
1573         .has_config_load_reg = true,
1574         .has_multi_master_mode = true,
1575         .has_slcg_override_reg = true,
1576         .has_mst_fifo = true,
1577         .quirks = &tegra194_i2c_quirks,
1578         .supports_bus_clear = true,
1579         .has_apb_dma = false,
1580         .tlow_std_mode = 0x8,
1581         .thigh_std_mode = 0x7,
1582         .tlow_fast_fastplus_mode = 0x2,
1583         .thigh_fast_fastplus_mode = 0x2,
1584         .setup_hold_time_std_mode = 0x08080808,
1585         .setup_hold_time_fast_fast_plus_mode = 0x02020202,
1586         .setup_hold_time_hs_mode = 0x090909,
1587         .has_interface_timing_reg = true,
1588 };
1589
1590 static const struct of_device_id tegra_i2c_of_match[] = {
1591         { .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, },
1592         { .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, },
1593         { .compatible = "nvidia,tegra210-i2c-vi", .data = &tegra210_i2c_hw, },
1594         { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, },
1595         { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, },
1596         { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
1597         { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
1598         { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
1599         { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
1600         {},
1601 };
1602 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
1603
1604 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev)
1605 {
1606         struct device_node *np = i2c_dev->dev->of_node;
1607         bool multi_mode;
1608         int err;
1609
1610         err = of_property_read_u32(np, "clock-frequency",
1611                                    &i2c_dev->bus_clk_rate);
1612         if (err)
1613                 i2c_dev->bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ;
1614
1615         multi_mode = of_property_read_bool(np, "multi-master");
1616         i2c_dev->multimaster_mode = multi_mode;
1617
1618         if (of_device_is_compatible(np, "nvidia,tegra20-i2c-dvc"))
1619                 i2c_dev->is_dvc = true;
1620
1621         if (of_device_is_compatible(np, "nvidia,tegra210-i2c-vi"))
1622                 i2c_dev->is_vi = true;
1623 }
1624
1625 static int tegra_i2c_init_clocks(struct tegra_i2c_dev *i2c_dev)
1626 {
1627         int err;
1628
1629         i2c_dev->clocks[i2c_dev->nclocks++].id = "div-clk";
1630
1631         if (i2c_dev->hw == &tegra20_i2c_hw || i2c_dev->hw == &tegra30_i2c_hw)
1632                 i2c_dev->clocks[i2c_dev->nclocks++].id = "fast-clk";
1633
1634         if (i2c_dev->is_vi)
1635                 i2c_dev->clocks[i2c_dev->nclocks++].id = "slow";
1636
1637         err = devm_clk_bulk_get(i2c_dev->dev, i2c_dev->nclocks,
1638                                 i2c_dev->clocks);
1639         if (err)
1640                 return err;
1641
1642         err = clk_bulk_prepare(i2c_dev->nclocks, i2c_dev->clocks);
1643         if (err)
1644                 return err;
1645
1646         i2c_dev->div_clk = i2c_dev->clocks[0].clk;
1647
1648         if (!i2c_dev->multimaster_mode)
1649                 return 0;
1650
1651         err = clk_enable(i2c_dev->div_clk);
1652         if (err) {
1653                 dev_err(i2c_dev->dev, "failed to enable div-clk: %d\n", err);
1654                 goto unprepare_clocks;
1655         }
1656
1657         return 0;
1658
1659 unprepare_clocks:
1660         clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks);
1661
1662         return err;
1663 }
1664
1665 static void tegra_i2c_release_clocks(struct tegra_i2c_dev *i2c_dev)
1666 {
1667         if (i2c_dev->multimaster_mode)
1668                 clk_disable(i2c_dev->div_clk);
1669
1670         clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks);
1671 }
1672
1673 static int tegra_i2c_init_hardware(struct tegra_i2c_dev *i2c_dev)
1674 {
1675         int ret;
1676
1677         ret = pm_runtime_get_sync(i2c_dev->dev);
1678         if (ret < 0)
1679                 dev_err(i2c_dev->dev, "runtime resume failed: %d\n", ret);
1680         else
1681                 ret = tegra_i2c_init(i2c_dev);
1682
1683         pm_runtime_put(i2c_dev->dev);
1684
1685         return ret;
1686 }
1687
1688 static int tegra_i2c_probe(struct platform_device *pdev)
1689 {
1690         struct tegra_i2c_dev *i2c_dev;
1691         struct resource *res;
1692         int err;
1693
1694         i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
1695         if (!i2c_dev)
1696                 return -ENOMEM;
1697
1698         platform_set_drvdata(pdev, i2c_dev);
1699
1700         init_completion(&i2c_dev->msg_complete);
1701         init_completion(&i2c_dev->dma_complete);
1702
1703         i2c_dev->hw = of_device_get_match_data(&pdev->dev);
1704         i2c_dev->cont_id = pdev->id;
1705         i2c_dev->dev = &pdev->dev;
1706
1707         i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1708         if (IS_ERR(i2c_dev->base))
1709                 return PTR_ERR(i2c_dev->base);
1710
1711         i2c_dev->base_phys = res->start;
1712
1713         err = platform_get_irq(pdev, 0);
1714         if (err < 0)
1715                 return err;
1716
1717         i2c_dev->irq = err;
1718
1719         /* interrupt will be enabled during of transfer time */
1720         irq_set_status_flags(i2c_dev->irq, IRQ_NOAUTOEN);
1721
1722         err = devm_request_irq(i2c_dev->dev, i2c_dev->irq, tegra_i2c_isr,
1723                                IRQF_NO_SUSPEND, dev_name(i2c_dev->dev),
1724                                i2c_dev);
1725         if (err)
1726                 return err;
1727
1728         i2c_dev->rst = devm_reset_control_get_exclusive(i2c_dev->dev, "i2c");
1729         if (IS_ERR(i2c_dev->rst)) {
1730                 dev_err_probe(i2c_dev->dev, PTR_ERR(i2c_dev->rst),
1731                               "failed to get reset control\n");
1732                 return PTR_ERR(i2c_dev->rst);
1733         }
1734
1735         tegra_i2c_parse_dt(i2c_dev);
1736
1737         err = tegra_i2c_init_clocks(i2c_dev);
1738         if (err)
1739                 return err;
1740
1741         err = tegra_i2c_init_dma(i2c_dev);
1742         if (err)
1743                 goto release_clocks;
1744
1745         /*
1746          * VI I2C is in VE power domain which is not always ON and not
1747          * IRQ-safe.  Thus, IRQ-safe device shouldn't be attached to a
1748          * non IRQ-safe domain because this prevents powering off the power
1749          * domain.
1750          *
1751          * VI I2C device shouldn't be marked as IRQ-safe because VI I2C won't
1752          * be used for atomic transfers.
1753          */
1754         if (!i2c_dev->is_vi)
1755                 pm_runtime_irq_safe(i2c_dev->dev);
1756
1757         pm_runtime_enable(i2c_dev->dev);
1758
1759         err = tegra_i2c_init_hardware(i2c_dev);
1760         if (err)
1761                 goto release_rpm;
1762
1763         i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
1764         i2c_dev->adapter.dev.of_node = i2c_dev->dev->of_node;
1765         i2c_dev->adapter.dev.parent = i2c_dev->dev;
1766         i2c_dev->adapter.retries = 1;
1767         i2c_dev->adapter.timeout = 6 * HZ;
1768         i2c_dev->adapter.quirks = i2c_dev->hw->quirks;
1769         i2c_dev->adapter.owner = THIS_MODULE;
1770         i2c_dev->adapter.class = I2C_CLASS_DEPRECATED;
1771         i2c_dev->adapter.algo = &tegra_i2c_algo;
1772         i2c_dev->adapter.nr = pdev->id;
1773
1774         if (i2c_dev->hw->supports_bus_clear)
1775                 i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info;
1776
1777         strlcpy(i2c_dev->adapter.name, dev_name(i2c_dev->dev),
1778                 sizeof(i2c_dev->adapter.name));
1779
1780         err = i2c_add_numbered_adapter(&i2c_dev->adapter);
1781         if (err)
1782                 goto release_rpm;
1783
1784         return 0;
1785
1786 release_rpm:
1787         pm_runtime_disable(i2c_dev->dev);
1788
1789         tegra_i2c_release_dma(i2c_dev);
1790 release_clocks:
1791         tegra_i2c_release_clocks(i2c_dev);
1792
1793         return err;
1794 }
1795
1796 static int tegra_i2c_remove(struct platform_device *pdev)
1797 {
1798         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1799
1800         i2c_del_adapter(&i2c_dev->adapter);
1801         pm_runtime_disable(i2c_dev->dev);
1802
1803         tegra_i2c_release_dma(i2c_dev);
1804         tegra_i2c_release_clocks(i2c_dev);
1805
1806         return 0;
1807 }
1808
1809 static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev)
1810 {
1811         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1812         int err;
1813
1814         err = pinctrl_pm_select_default_state(dev);
1815         if (err)
1816                 return err;
1817
1818         err = clk_bulk_enable(i2c_dev->nclocks, i2c_dev->clocks);
1819         if (err)
1820                 return err;
1821
1822         /*
1823          * VI I2C device is attached to VE power domain which goes through
1824          * power ON/OFF during runtime PM resume/suspend, meaning that
1825          * controller needs to be re-initialized after power ON.
1826          */
1827         if (i2c_dev->is_vi) {
1828                 err = tegra_i2c_init(i2c_dev);
1829                 if (err)
1830                         goto disable_clocks;
1831         }
1832
1833         return 0;
1834
1835 disable_clocks:
1836         clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks);
1837
1838         return err;
1839 }
1840
1841 static int __maybe_unused tegra_i2c_runtime_suspend(struct device *dev)
1842 {
1843         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1844
1845         clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks);
1846
1847         return pinctrl_pm_select_idle_state(dev);
1848 }
1849
1850 static int __maybe_unused tegra_i2c_suspend(struct device *dev)
1851 {
1852         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1853         int err;
1854
1855         i2c_mark_adapter_suspended(&i2c_dev->adapter);
1856
1857         if (!pm_runtime_status_suspended(dev)) {
1858                 err = tegra_i2c_runtime_suspend(dev);
1859                 if (err)
1860                         return err;
1861         }
1862
1863         return 0;
1864 }
1865
1866 static int __maybe_unused tegra_i2c_resume(struct device *dev)
1867 {
1868         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1869         int err;
1870
1871         /*
1872          * We need to ensure that clocks are enabled so that registers can be
1873          * restored in tegra_i2c_init().
1874          */
1875         err = tegra_i2c_runtime_resume(dev);
1876         if (err)
1877                 return err;
1878
1879         err = tegra_i2c_init(i2c_dev);
1880         if (err)
1881                 return err;
1882
1883         /*
1884          * In case we are runtime suspended, disable clocks again so that we
1885          * don't unbalance the clock reference counts during the next runtime
1886          * resume transition.
1887          */
1888         if (pm_runtime_status_suspended(dev)) {
1889                 err = tegra_i2c_runtime_suspend(dev);
1890                 if (err)
1891                         return err;
1892         }
1893
1894         i2c_mark_adapter_resumed(&i2c_dev->adapter);
1895
1896         return 0;
1897 }
1898
1899 static const struct dev_pm_ops tegra_i2c_pm = {
1900         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_i2c_suspend, tegra_i2c_resume)
1901         SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume,
1902                            NULL)
1903 };
1904
1905 static struct platform_driver tegra_i2c_driver = {
1906         .probe = tegra_i2c_probe,
1907         .remove = tegra_i2c_remove,
1908         .driver = {
1909                 .name = "tegra-i2c",
1910                 .of_match_table = tegra_i2c_of_match,
1911                 .pm = &tegra_i2c_pm,
1912         },
1913 };
1914 module_platform_driver(tegra_i2c_driver);
1915
1916 MODULE_DESCRIPTION("NVIDIA Tegra I2C Bus Controller driver");
1917 MODULE_AUTHOR("Colin Cross");
1918 MODULE_LICENSE("GPL v2");