1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for STMicroelectronics STM32F7 I2C controller
5 * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc
7 * Please see below a link to the documentation:
8 * http://www.st.com/resource/en/reference_manual/dm00124865.pdf
10 * Copyright (C) M'boumba Cedric Madianga 2017
11 * Copyright (C) STMicroelectronics 2017
12 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
14 * This driver is based on i2c-stm32f4.c
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/i2c.h>
21 #include <linux/interrupt.h>
23 #include <linux/iopoll.h>
24 #include <linux/mfd/syscon.h>
25 #include <linux/module.h>
27 #include <linux/of_address.h>
28 #include <linux/of_platform.h>
29 #include <linux/platform_device.h>
30 #include <linux/pinctrl/consumer.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/pm_wakeirq.h>
33 #include <linux/regmap.h>
34 #include <linux/reset.h>
35 #include <linux/slab.h>
37 #include "i2c-stm32.h"
39 /* STM32F7 I2C registers */
40 #define STM32F7_I2C_CR1 0x00
41 #define STM32F7_I2C_CR2 0x04
42 #define STM32F7_I2C_OAR1 0x08
43 #define STM32F7_I2C_OAR2 0x0C
44 #define STM32F7_I2C_PECR 0x20
45 #define STM32F7_I2C_TIMINGR 0x10
46 #define STM32F7_I2C_ISR 0x18
47 #define STM32F7_I2C_ICR 0x1C
48 #define STM32F7_I2C_RXDR 0x24
49 #define STM32F7_I2C_TXDR 0x28
51 /* STM32F7 I2C control 1 */
52 #define STM32F7_I2C_CR1_PECEN BIT(23)
53 #define STM32F7_I2C_CR1_WUPEN BIT(18)
54 #define STM32F7_I2C_CR1_SBC BIT(16)
55 #define STM32F7_I2C_CR1_RXDMAEN BIT(15)
56 #define STM32F7_I2C_CR1_TXDMAEN BIT(14)
57 #define STM32F7_I2C_CR1_ANFOFF BIT(12)
58 #define STM32F7_I2C_CR1_ERRIE BIT(7)
59 #define STM32F7_I2C_CR1_TCIE BIT(6)
60 #define STM32F7_I2C_CR1_STOPIE BIT(5)
61 #define STM32F7_I2C_CR1_NACKIE BIT(4)
62 #define STM32F7_I2C_CR1_ADDRIE BIT(3)
63 #define STM32F7_I2C_CR1_RXIE BIT(2)
64 #define STM32F7_I2C_CR1_TXIE BIT(1)
65 #define STM32F7_I2C_CR1_PE BIT(0)
66 #define STM32F7_I2C_ALL_IRQ_MASK (STM32F7_I2C_CR1_ERRIE \
67 | STM32F7_I2C_CR1_TCIE \
68 | STM32F7_I2C_CR1_STOPIE \
69 | STM32F7_I2C_CR1_NACKIE \
70 | STM32F7_I2C_CR1_RXIE \
71 | STM32F7_I2C_CR1_TXIE)
72 #define STM32F7_I2C_XFER_IRQ_MASK (STM32F7_I2C_CR1_TCIE \
73 | STM32F7_I2C_CR1_STOPIE \
74 | STM32F7_I2C_CR1_NACKIE \
75 | STM32F7_I2C_CR1_RXIE \
76 | STM32F7_I2C_CR1_TXIE)
78 /* STM32F7 I2C control 2 */
79 #define STM32F7_I2C_CR2_PECBYTE BIT(26)
80 #define STM32F7_I2C_CR2_RELOAD BIT(24)
81 #define STM32F7_I2C_CR2_NBYTES_MASK GENMASK(23, 16)
82 #define STM32F7_I2C_CR2_NBYTES(n) (((n) & 0xff) << 16)
83 #define STM32F7_I2C_CR2_NACK BIT(15)
84 #define STM32F7_I2C_CR2_STOP BIT(14)
85 #define STM32F7_I2C_CR2_START BIT(13)
86 #define STM32F7_I2C_CR2_HEAD10R BIT(12)
87 #define STM32F7_I2C_CR2_ADD10 BIT(11)
88 #define STM32F7_I2C_CR2_RD_WRN BIT(10)
89 #define STM32F7_I2C_CR2_SADD10_MASK GENMASK(9, 0)
90 #define STM32F7_I2C_CR2_SADD10(n) (((n) & \
91 STM32F7_I2C_CR2_SADD10_MASK))
92 #define STM32F7_I2C_CR2_SADD7_MASK GENMASK(7, 1)
93 #define STM32F7_I2C_CR2_SADD7(n) (((n) & 0x7f) << 1)
95 /* STM32F7 I2C Own Address 1 */
96 #define STM32F7_I2C_OAR1_OA1EN BIT(15)
97 #define STM32F7_I2C_OAR1_OA1MODE BIT(10)
98 #define STM32F7_I2C_OAR1_OA1_10_MASK GENMASK(9, 0)
99 #define STM32F7_I2C_OAR1_OA1_10(n) (((n) & \
100 STM32F7_I2C_OAR1_OA1_10_MASK))
101 #define STM32F7_I2C_OAR1_OA1_7_MASK GENMASK(7, 1)
102 #define STM32F7_I2C_OAR1_OA1_7(n) (((n) & 0x7f) << 1)
103 #define STM32F7_I2C_OAR1_MASK (STM32F7_I2C_OAR1_OA1_7_MASK \
104 | STM32F7_I2C_OAR1_OA1_10_MASK \
105 | STM32F7_I2C_OAR1_OA1EN \
106 | STM32F7_I2C_OAR1_OA1MODE)
108 /* STM32F7 I2C Own Address 2 */
109 #define STM32F7_I2C_OAR2_OA2EN BIT(15)
110 #define STM32F7_I2C_OAR2_OA2MSK_MASK GENMASK(10, 8)
111 #define STM32F7_I2C_OAR2_OA2MSK(n) (((n) & 0x7) << 8)
112 #define STM32F7_I2C_OAR2_OA2_7_MASK GENMASK(7, 1)
113 #define STM32F7_I2C_OAR2_OA2_7(n) (((n) & 0x7f) << 1)
114 #define STM32F7_I2C_OAR2_MASK (STM32F7_I2C_OAR2_OA2MSK_MASK \
115 | STM32F7_I2C_OAR2_OA2_7_MASK \
116 | STM32F7_I2C_OAR2_OA2EN)
118 /* STM32F7 I2C Interrupt Status */
119 #define STM32F7_I2C_ISR_ADDCODE_MASK GENMASK(23, 17)
120 #define STM32F7_I2C_ISR_ADDCODE_GET(n) \
121 (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17)
122 #define STM32F7_I2C_ISR_DIR BIT(16)
123 #define STM32F7_I2C_ISR_BUSY BIT(15)
124 #define STM32F7_I2C_ISR_PECERR BIT(11)
125 #define STM32F7_I2C_ISR_ARLO BIT(9)
126 #define STM32F7_I2C_ISR_BERR BIT(8)
127 #define STM32F7_I2C_ISR_TCR BIT(7)
128 #define STM32F7_I2C_ISR_TC BIT(6)
129 #define STM32F7_I2C_ISR_STOPF BIT(5)
130 #define STM32F7_I2C_ISR_NACKF BIT(4)
131 #define STM32F7_I2C_ISR_ADDR BIT(3)
132 #define STM32F7_I2C_ISR_RXNE BIT(2)
133 #define STM32F7_I2C_ISR_TXIS BIT(1)
134 #define STM32F7_I2C_ISR_TXE BIT(0)
136 /* STM32F7 I2C Interrupt Clear */
137 #define STM32F7_I2C_ICR_PECCF BIT(11)
138 #define STM32F7_I2C_ICR_ARLOCF BIT(9)
139 #define STM32F7_I2C_ICR_BERRCF BIT(8)
140 #define STM32F7_I2C_ICR_STOPCF BIT(5)
141 #define STM32F7_I2C_ICR_NACKCF BIT(4)
142 #define STM32F7_I2C_ICR_ADDRCF BIT(3)
144 /* STM32F7 I2C Timing */
145 #define STM32F7_I2C_TIMINGR_PRESC(n) (((n) & 0xf) << 28)
146 #define STM32F7_I2C_TIMINGR_SCLDEL(n) (((n) & 0xf) << 20)
147 #define STM32F7_I2C_TIMINGR_SDADEL(n) (((n) & 0xf) << 16)
148 #define STM32F7_I2C_TIMINGR_SCLH(n) (((n) & 0xff) << 8)
149 #define STM32F7_I2C_TIMINGR_SCLL(n) ((n) & 0xff)
151 #define STM32F7_I2C_MAX_LEN 0xff
152 #define STM32F7_I2C_DMA_LEN_MIN 0x16
153 #define STM32F7_I2C_MAX_SLAVE 0x2
155 #define STM32F7_I2C_DNF_DEFAULT 0
156 #define STM32F7_I2C_DNF_MAX 16
158 #define STM32F7_I2C_ANALOG_FILTER_ENABLE 1
159 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */
160 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
162 #define STM32F7_I2C_RISE_TIME_DEFAULT 25 /* ns */
163 #define STM32F7_I2C_FALL_TIME_DEFAULT 10 /* ns */
165 #define STM32F7_PRESC_MAX BIT(4)
166 #define STM32F7_SCLDEL_MAX BIT(4)
167 #define STM32F7_SDADEL_MAX BIT(4)
168 #define STM32F7_SCLH_MAX BIT(8)
169 #define STM32F7_SCLL_MAX BIT(8)
171 #define STM32F7_AUTOSUSPEND_DELAY (HZ / 100)
174 * struct stm32f7_i2c_regs - i2c f7 registers backup
175 * @cr1: Control register 1
176 * @cr2: Control register 2
177 * @oar1: Own address 1 register
178 * @oar2: Own address 2 register
179 * @tmgr: Timing register
181 struct stm32f7_i2c_regs {
190 * struct stm32f7_i2c_spec - private i2c specification timing
191 * @rate: I2C bus speed (Hz)
192 * @rate_min: 80% of I2C bus speed (Hz)
193 * @rate_max: 100% of I2C bus speed (Hz)
194 * @fall_max: Max fall time of both SDA and SCL signals (ns)
195 * @rise_max: Max rise time of both SDA and SCL signals (ns)
196 * @hddat_min: Min data hold time (ns)
197 * @vddat_max: Max data valid time (ns)
198 * @sudat_min: Min data setup time (ns)
199 * @l_min: Min low period of the SCL clock (ns)
200 * @h_min: Min high period of the SCL clock (ns)
202 struct stm32f7_i2c_spec {
216 * struct stm32f7_i2c_setup - private I2C timing setup parameters
217 * @speed: I2C speed mode (standard, Fast Plus)
218 * @speed_freq: I2C speed frequency (Hz)
219 * @clock_src: I2C clock source frequency (Hz)
220 * @rise_time: Rise time (ns)
221 * @fall_time: Fall time (ns)
222 * @dnf: Digital filter coefficient (0-16)
223 * @analog_filter: Analog filter delay (On/Off)
224 * @fmp_clr_offset: Fast Mode Plus clear register offset from set register
226 struct stm32f7_i2c_setup {
227 enum stm32_i2c_speed speed;
238 * struct stm32f7_i2c_timings - private I2C output parameters
240 * @presc: Prescaler value
241 * @scldel: Data setup time
242 * @sdadel: Data hold time
243 * @sclh: SCL high period (master mode)
244 * @scll: SCL low period (master mode)
246 struct stm32f7_i2c_timings {
247 struct list_head node;
256 * struct stm32f7_i2c_msg - client specific data
257 * @addr: 8-bit or 10-bit slave addr, including r/w bit
258 * @count: number of bytes to be transferred
260 * @result: result of the transfer
261 * @stop: last I2C msg to be sent, i.e. STOP to be generated
262 * @smbus: boolean to know if the I2C IP is used in SMBus mode
263 * @size: type of SMBus protocol
264 * @read_write: direction of SMBus protocol
265 * SMBus block read and SMBus block write - block read process call protocols
266 * @smbus_buf: buffer to be used for SMBus protocol transfer. It will
267 * contain a maximum of 32 bytes of data + byte command + byte count + PEC
268 * This buffer has to be 32-bit aligned to be compliant with memory address
269 * register in DMA mode.
271 struct stm32f7_i2c_msg {
280 u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4);
284 * struct stm32f7_i2c_dev - private data of the controller
285 * @adap: I2C adapter for this controller
286 * @dev: device for this controller
287 * @base: virtual memory area
288 * @complete: completion of I2C message
290 * @speed: I2C clock frequency of the controller. Standard, Fast or Fast+
291 * @msg: Pointer to data to be written
292 * @msg_num: number of I2C messages to be executed
293 * @msg_id: message identifiant
294 * @f7_msg: customized i2c msg for driver usage
295 * @setup: I2C timing input setup
296 * @timing: I2C computed timings
297 * @slave: list of slave devices registered on the I2C bus
298 * @slave_running: slave device currently used
299 * @backup_regs: backup of i2c controller registers (for suspend/resume)
300 * @slave_dir: transfer direction for the current slave device
301 * @master_mode: boolean to know in which mode the I2C is running (master or
304 * @use_dma: boolean to know if dma is used in the current transfer
305 * @regmap: holds SYSCFG phandle for Fast Mode Plus bits
306 * @fmp_sreg: register address for setting Fast Mode Plus bits
307 * @fmp_creg: register address for clearing Fast Mode Plus bits
308 * @fmp_mask: mask for Fast Mode Plus bits in set register
309 * @wakeup_src: boolean to know if the device is a wakeup source
311 struct stm32f7_i2c_dev {
312 struct i2c_adapter adap;
315 struct completion complete;
319 unsigned int msg_num;
321 struct stm32f7_i2c_msg f7_msg;
322 struct stm32f7_i2c_setup setup;
323 struct stm32f7_i2c_timings timing;
324 struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE];
325 struct i2c_client *slave_running;
326 struct stm32f7_i2c_regs backup_regs;
329 struct stm32_i2c_dma *dma;
331 struct regmap *regmap;
339 * All these values are coming from I2C Specification, Version 6.0, 4th of
342 * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast,
343 * and Fast-mode Plus I2C-bus devices
345 static struct stm32f7_i2c_spec i2c_specs[] = {
346 [STM32_I2C_SPEED_STANDARD] = {
347 .rate = I2C_MAX_STANDARD_MODE_FREQ,
348 .rate_min = I2C_MAX_STANDARD_MODE_FREQ * 8 / 10, /* 80% */
349 .rate_max = I2C_MAX_STANDARD_MODE_FREQ,
358 [STM32_I2C_SPEED_FAST] = {
359 .rate = I2C_MAX_FAST_MODE_FREQ,
360 .rate_min = I2C_MAX_FAST_MODE_FREQ * 8 / 10, /* 80% */
361 .rate_max = I2C_MAX_FAST_MODE_FREQ,
370 [STM32_I2C_SPEED_FAST_PLUS] = {
371 .rate = I2C_MAX_FAST_MODE_PLUS_FREQ,
372 .rate_min = I2C_MAX_FAST_MODE_PLUS_FREQ * 8 / 10, /* 80% */
373 .rate_max = I2C_MAX_FAST_MODE_PLUS_FREQ,
384 static const struct stm32f7_i2c_setup stm32f7_setup = {
385 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
386 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
387 .dnf = STM32F7_I2C_DNF_DEFAULT,
388 .analog_filter = STM32F7_I2C_ANALOG_FILTER_ENABLE,
391 static const struct stm32f7_i2c_setup stm32mp15_setup = {
392 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
393 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
394 .dnf = STM32F7_I2C_DNF_DEFAULT,
395 .analog_filter = STM32F7_I2C_ANALOG_FILTER_ENABLE,
396 .fmp_clr_offset = 0x40,
399 static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask)
401 writel_relaxed(readl_relaxed(reg) | mask, reg);
404 static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask)
406 writel_relaxed(readl_relaxed(reg) & ~mask, reg);
409 static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)
411 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
414 static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev,
415 struct stm32f7_i2c_setup *setup,
416 struct stm32f7_i2c_timings *output)
418 u32 p_prev = STM32F7_PRESC_MAX;
419 u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
421 u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
423 u32 clk_error_prev = i2cbus;
425 u32 af_delay_min, af_delay_max;
427 u32 clk_min, clk_max;
428 int sdadel_min, sdadel_max;
430 struct stm32f7_i2c_timings *v, *_v, *s;
431 struct list_head solutions;
435 if (setup->speed >= STM32_I2C_SPEED_END) {
436 dev_err(i2c_dev->dev, "speed out of bound {%d/%d}\n",
437 setup->speed, STM32_I2C_SPEED_END - 1);
441 if ((setup->rise_time > i2c_specs[setup->speed].rise_max) ||
442 (setup->fall_time > i2c_specs[setup->speed].fall_max)) {
443 dev_err(i2c_dev->dev,
444 "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
445 setup->rise_time, i2c_specs[setup->speed].rise_max,
446 setup->fall_time, i2c_specs[setup->speed].fall_max);
450 if (setup->dnf > STM32F7_I2C_DNF_MAX) {
451 dev_err(i2c_dev->dev,
452 "DNF out of bound %d/%d\n",
453 setup->dnf, STM32F7_I2C_DNF_MAX);
457 if (setup->speed_freq > i2c_specs[setup->speed].rate) {
458 dev_err(i2c_dev->dev, "ERROR: Freq {%d/%d}\n",
459 setup->speed_freq, i2c_specs[setup->speed].rate);
463 /* Analog and Digital Filters */
465 (setup->analog_filter ?
466 STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0);
468 (setup->analog_filter ?
469 STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0);
470 dnf_delay = setup->dnf * i2cclk;
472 sdadel_min = i2c_specs[setup->speed].hddat_min + setup->fall_time -
473 af_delay_min - (setup->dnf + 3) * i2cclk;
475 sdadel_max = i2c_specs[setup->speed].vddat_max - setup->rise_time -
476 af_delay_max - (setup->dnf + 4) * i2cclk;
478 scldel_min = setup->rise_time + i2c_specs[setup->speed].sudat_min;
485 dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n",
486 sdadel_min, sdadel_max, scldel_min);
488 INIT_LIST_HEAD(&solutions);
489 /* Compute possible values for PRESC, SCLDEL and SDADEL */
490 for (p = 0; p < STM32F7_PRESC_MAX; p++) {
491 for (l = 0; l < STM32F7_SCLDEL_MAX; l++) {
492 u32 scldel = (l + 1) * (p + 1) * i2cclk;
494 if (scldel < scldel_min)
497 for (a = 0; a < STM32F7_SDADEL_MAX; a++) {
498 u32 sdadel = (a * (p + 1) + 1) * i2cclk;
500 if (((sdadel >= sdadel_min) &&
501 (sdadel <= sdadel_max)) &&
503 v = kmalloc(sizeof(*v), GFP_KERNEL);
514 list_add_tail(&v->node,
525 if (list_empty(&solutions)) {
526 dev_err(i2c_dev->dev, "no Prescaler solution\n");
531 tsync = af_delay_min + dnf_delay + (2 * i2cclk);
533 clk_max = NSEC_PER_SEC / i2c_specs[setup->speed].rate_min;
534 clk_min = NSEC_PER_SEC / i2c_specs[setup->speed].rate_max;
537 * Among Prescaler possibilities discovered above figures out SCL Low
538 * and High Period. Provided:
539 * - SCL Low Period has to be higher than SCL Clock Low Period
540 * defined by I2C Specification. I2C Clock has to be lower than
541 * (SCL Low Period - Analog/Digital filters) / 4.
542 * - SCL High Period has to be lower than SCL Clock High Period
543 * defined by I2C Specification
544 * - I2C Clock has to be lower than SCL High Period
546 list_for_each_entry(v, &solutions, node) {
547 u32 prescaler = (v->presc + 1) * i2cclk;
549 for (l = 0; l < STM32F7_SCLL_MAX; l++) {
550 u32 tscl_l = (l + 1) * prescaler + tsync;
552 if ((tscl_l < i2c_specs[setup->speed].l_min) ||
554 ((tscl_l - af_delay_min - dnf_delay) / 4))) {
558 for (h = 0; h < STM32F7_SCLH_MAX; h++) {
559 u32 tscl_h = (h + 1) * prescaler + tsync;
560 u32 tscl = tscl_l + tscl_h +
561 setup->rise_time + setup->fall_time;
563 if ((tscl >= clk_min) && (tscl <= clk_max) &&
564 (tscl_h >= i2c_specs[setup->speed].h_min) &&
566 int clk_error = tscl - i2cbus;
569 clk_error = -clk_error;
571 if (clk_error < clk_error_prev) {
572 clk_error_prev = clk_error;
583 dev_err(i2c_dev->dev, "no solution at all\n");
588 output->presc = s->presc;
589 output->scldel = s->scldel;
590 output->sdadel = s->sdadel;
591 output->scll = s->scll;
592 output->sclh = s->sclh;
594 dev_dbg(i2c_dev->dev,
595 "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
597 output->scldel, output->sdadel,
598 output->scll, output->sclh);
601 /* Release list and memory */
602 list_for_each_entry_safe(v, _v, &solutions, node) {
610 static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev,
611 struct stm32f7_i2c_setup *setup)
613 struct i2c_timings timings, *t = &timings;
616 t->bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
617 t->scl_rise_ns = i2c_dev->setup.rise_time;
618 t->scl_fall_ns = i2c_dev->setup.fall_time;
620 i2c_parse_fw_timings(i2c_dev->dev, t, false);
622 if (t->bus_freq_hz >= I2C_MAX_FAST_MODE_PLUS_FREQ)
623 i2c_dev->speed = STM32_I2C_SPEED_FAST_PLUS;
624 else if (t->bus_freq_hz >= I2C_MAX_FAST_MODE_FREQ)
625 i2c_dev->speed = STM32_I2C_SPEED_FAST;
627 i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
629 i2c_dev->setup.rise_time = t->scl_rise_ns;
630 i2c_dev->setup.fall_time = t->scl_fall_ns;
632 setup->speed = i2c_dev->speed;
633 setup->speed_freq = i2c_specs[setup->speed].rate;
634 setup->clock_src = clk_get_rate(i2c_dev->clk);
636 if (!setup->clock_src) {
637 dev_err(i2c_dev->dev, "clock rate is 0\n");
642 ret = stm32f7_i2c_compute_timing(i2c_dev, setup,
645 dev_err(i2c_dev->dev,
646 "failed to compute I2C timings.\n");
647 if (i2c_dev->speed > STM32_I2C_SPEED_STANDARD) {
649 setup->speed = i2c_dev->speed;
651 i2c_specs[setup->speed].rate;
652 dev_warn(i2c_dev->dev,
653 "downgrade I2C Speed Freq to (%i)\n",
654 i2c_specs[setup->speed].rate);
662 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n");
666 dev_dbg(i2c_dev->dev, "I2C Speed(%i), Freq(%i), Clk Source(%i)\n",
667 setup->speed, setup->speed_freq, setup->clock_src);
668 dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n",
669 setup->rise_time, setup->fall_time);
670 dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n",
671 (setup->analog_filter ? "On" : "Off"), setup->dnf);
676 static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev)
678 void __iomem *base = i2c_dev->base;
679 u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN;
681 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
684 static void stm32f7_i2c_dma_callback(void *arg)
686 struct stm32f7_i2c_dev *i2c_dev = (struct stm32f7_i2c_dev *)arg;
687 struct stm32_i2c_dma *dma = i2c_dev->dma;
688 struct device *dev = dma->chan_using->device->dev;
690 stm32f7_i2c_disable_dma_req(i2c_dev);
691 dma_unmap_single(dev, dma->dma_buf, dma->dma_len, dma->dma_data_dir);
692 complete(&dma->dma_complete);
695 static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev)
697 struct stm32f7_i2c_timings *t = &i2c_dev->timing;
700 /* Timing settings */
701 timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc);
702 timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel);
703 timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel);
704 timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh);
705 timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll);
706 writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR);
709 if (i2c_dev->setup.analog_filter)
710 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
711 STM32F7_I2C_CR1_ANFOFF);
713 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
714 STM32F7_I2C_CR1_ANFOFF);
715 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
719 static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev)
721 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
722 void __iomem *base = i2c_dev->base;
725 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR);
730 static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev)
732 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
733 void __iomem *base = i2c_dev->base;
736 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR);
739 /* Flush RX buffer has no data is expected */
740 readb_relaxed(base + STM32F7_I2C_RXDR);
744 static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev)
746 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
749 if (i2c_dev->use_dma)
750 f7_msg->count -= STM32F7_I2C_MAX_LEN;
752 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
754 cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK;
755 if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
756 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
758 cr2 &= ~STM32F7_I2C_CR2_RELOAD;
759 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
762 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
765 static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev)
767 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
772 * For I2C_SMBUS_BLOCK_DATA && I2C_SMBUS_BLOCK_PROC_CALL, the first
773 * data received inform us how many data will follow.
775 stm32f7_i2c_read_rx_data(i2c_dev);
778 * Update NBYTES with the value read to continue the transfer
780 val = f7_msg->buf - sizeof(u8);
781 f7_msg->count = *val;
782 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
783 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
784 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
785 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
788 static int stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap)
790 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
792 dev_info(i2c_dev->dev, "Trying to recover bus\n");
794 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
797 stm32f7_i2c_hw_config(i2c_dev);
802 static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev)
807 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR,
809 !(status & STM32F7_I2C_ISR_BUSY),
814 dev_info(i2c_dev->dev, "bus busy\n");
816 ret = stm32f7_i2c_release_bus(&i2c_dev->adap);
818 dev_err(i2c_dev->dev, "Failed to recover the bus (%d)\n", ret);
825 static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
828 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
829 void __iomem *base = i2c_dev->base;
833 f7_msg->addr = msg->addr;
834 f7_msg->buf = msg->buf;
835 f7_msg->count = msg->len;
837 f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1);
839 reinit_completion(&i2c_dev->complete);
841 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
842 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
844 /* Set transfer direction */
845 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
846 if (msg->flags & I2C_M_RD)
847 cr2 |= STM32F7_I2C_CR2_RD_WRN;
849 /* Set slave address */
850 cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10);
851 if (msg->flags & I2C_M_TEN) {
852 cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK;
853 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr);
854 cr2 |= STM32F7_I2C_CR2_ADD10;
856 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK;
857 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
860 /* Set nb bytes to transfer and reload if needed */
861 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
862 if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
863 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
864 cr2 |= STM32F7_I2C_CR2_RELOAD;
866 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
869 /* Enable NACK, STOP, error and transfer complete interrupts */
870 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
871 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
873 /* Clear DMA req and TX/RX interrupt */
874 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
875 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
877 /* Configure DMA or enable RX/TX interrupt */
878 i2c_dev->use_dma = false;
879 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
880 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
881 msg->flags & I2C_M_RD,
882 f7_msg->count, f7_msg->buf,
883 stm32f7_i2c_dma_callback,
886 i2c_dev->use_dma = true;
888 dev_warn(i2c_dev->dev, "can't use DMA\n");
891 if (!i2c_dev->use_dma) {
892 if (msg->flags & I2C_M_RD)
893 cr1 |= STM32F7_I2C_CR1_RXIE;
895 cr1 |= STM32F7_I2C_CR1_TXIE;
897 if (msg->flags & I2C_M_RD)
898 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
900 cr1 |= STM32F7_I2C_CR1_TXDMAEN;
903 /* Configure Start/Repeated Start */
904 cr2 |= STM32F7_I2C_CR2_START;
906 i2c_dev->master_mode = true;
908 /* Write configurations registers */
909 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
910 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
913 static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
914 unsigned short flags, u8 command,
915 union i2c_smbus_data *data)
917 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
918 struct device *dev = i2c_dev->dev;
919 void __iomem *base = i2c_dev->base;
924 reinit_completion(&i2c_dev->complete);
926 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
927 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
929 /* Set transfer direction */
930 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
931 if (f7_msg->read_write)
932 cr2 |= STM32F7_I2C_CR2_RD_WRN;
934 /* Set slave address */
935 cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK);
936 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
938 f7_msg->smbus_buf[0] = command;
939 switch (f7_msg->size) {
940 case I2C_SMBUS_QUICK:
948 case I2C_SMBUS_BYTE_DATA:
949 if (f7_msg->read_write) {
950 f7_msg->stop = false;
952 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
956 f7_msg->smbus_buf[1] = data->byte;
959 case I2C_SMBUS_WORD_DATA:
960 if (f7_msg->read_write) {
961 f7_msg->stop = false;
963 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
967 f7_msg->smbus_buf[1] = data->word & 0xff;
968 f7_msg->smbus_buf[2] = data->word >> 8;
971 case I2C_SMBUS_BLOCK_DATA:
972 if (f7_msg->read_write) {
973 f7_msg->stop = false;
975 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
978 if (data->block[0] > I2C_SMBUS_BLOCK_MAX ||
980 dev_err(dev, "Invalid block write size %d\n",
984 f7_msg->count = data->block[0] + 2;
985 for (i = 1; i < f7_msg->count; i++)
986 f7_msg->smbus_buf[i] = data->block[i - 1];
989 case I2C_SMBUS_PROC_CALL:
990 f7_msg->stop = false;
992 f7_msg->smbus_buf[1] = data->word & 0xff;
993 f7_msg->smbus_buf[2] = data->word >> 8;
994 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
995 f7_msg->read_write = I2C_SMBUS_READ;
997 case I2C_SMBUS_BLOCK_PROC_CALL:
998 f7_msg->stop = false;
999 if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) {
1000 dev_err(dev, "Invalid block write size %d\n",
1004 f7_msg->count = data->block[0] + 2;
1005 for (i = 1; i < f7_msg->count; i++)
1006 f7_msg->smbus_buf[i] = data->block[i - 1];
1007 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1008 f7_msg->read_write = I2C_SMBUS_READ;
1010 case I2C_SMBUS_I2C_BLOCK_DATA:
1011 /* Rely on emulated i2c transfer (through master_xfer) */
1014 dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size);
1018 f7_msg->buf = f7_msg->smbus_buf;
1021 if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) {
1022 cr1 |= STM32F7_I2C_CR1_PECEN;
1023 cr2 |= STM32F7_I2C_CR2_PECBYTE;
1024 if (!f7_msg->read_write)
1027 cr1 &= ~STM32F7_I2C_CR1_PECEN;
1028 cr2 &= ~STM32F7_I2C_CR2_PECBYTE;
1031 /* Set number of bytes to be transferred */
1032 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
1033 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1035 /* Enable NACK, STOP, error and transfer complete interrupts */
1036 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
1037 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
1039 /* Clear DMA req and TX/RX interrupt */
1040 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1041 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1043 /* Configure DMA or enable RX/TX interrupt */
1044 i2c_dev->use_dma = false;
1045 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
1046 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1047 cr2 & STM32F7_I2C_CR2_RD_WRN,
1048 f7_msg->count, f7_msg->buf,
1049 stm32f7_i2c_dma_callback,
1052 i2c_dev->use_dma = true;
1054 dev_warn(i2c_dev->dev, "can't use DMA\n");
1057 if (!i2c_dev->use_dma) {
1058 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1059 cr1 |= STM32F7_I2C_CR1_RXIE;
1061 cr1 |= STM32F7_I2C_CR1_TXIE;
1063 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1064 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1066 cr1 |= STM32F7_I2C_CR1_TXDMAEN;
1070 cr2 |= STM32F7_I2C_CR2_START;
1072 i2c_dev->master_mode = true;
1074 /* Write configurations registers */
1075 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1076 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1081 static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev)
1083 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1084 void __iomem *base = i2c_dev->base;
1088 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
1089 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
1091 /* Set transfer direction */
1092 cr2 |= STM32F7_I2C_CR2_RD_WRN;
1094 switch (f7_msg->size) {
1095 case I2C_SMBUS_BYTE_DATA:
1098 case I2C_SMBUS_WORD_DATA:
1099 case I2C_SMBUS_PROC_CALL:
1102 case I2C_SMBUS_BLOCK_DATA:
1103 case I2C_SMBUS_BLOCK_PROC_CALL:
1105 cr2 |= STM32F7_I2C_CR2_RELOAD;
1109 f7_msg->buf = f7_msg->smbus_buf;
1110 f7_msg->stop = true;
1112 /* Add one byte for PEC if needed */
1113 if (cr1 & STM32F7_I2C_CR1_PECEN)
1116 /* Set number of bytes to be transferred */
1117 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK);
1118 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1121 * Configure RX/TX interrupt:
1123 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE);
1124 cr1 |= STM32F7_I2C_CR1_RXIE;
1127 * Configure DMA or enable RX/TX interrupt:
1128 * For I2C_SMBUS_BLOCK_DATA and I2C_SMBUS_BLOCK_PROC_CALL we don't use
1129 * dma as we don't know in advance how many data will be received
1131 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1132 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1134 i2c_dev->use_dma = false;
1135 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN &&
1136 f7_msg->size != I2C_SMBUS_BLOCK_DATA &&
1137 f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) {
1138 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1139 cr2 & STM32F7_I2C_CR2_RD_WRN,
1140 f7_msg->count, f7_msg->buf,
1141 stm32f7_i2c_dma_callback,
1145 i2c_dev->use_dma = true;
1147 dev_warn(i2c_dev->dev, "can't use DMA\n");
1150 if (!i2c_dev->use_dma)
1151 cr1 |= STM32F7_I2C_CR1_RXIE;
1153 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1155 /* Configure Repeated Start */
1156 cr2 |= STM32F7_I2C_CR2_START;
1158 /* Write configurations registers */
1159 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1160 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1163 static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev)
1165 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1166 u8 count, internal_pec, received_pec;
1168 internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR);
1170 switch (f7_msg->size) {
1171 case I2C_SMBUS_BYTE:
1172 case I2C_SMBUS_BYTE_DATA:
1173 received_pec = f7_msg->smbus_buf[1];
1175 case I2C_SMBUS_WORD_DATA:
1176 case I2C_SMBUS_PROC_CALL:
1177 received_pec = f7_msg->smbus_buf[2];
1179 case I2C_SMBUS_BLOCK_DATA:
1180 case I2C_SMBUS_BLOCK_PROC_CALL:
1181 count = f7_msg->smbus_buf[0];
1182 received_pec = f7_msg->smbus_buf[count];
1185 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n");
1189 if (internal_pec != received_pec) {
1190 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n",
1191 internal_pec, received_pec);
1198 static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode)
1205 if (slave->flags & I2C_CLIENT_TEN) {
1207 * For 10-bit addr, addcode = 11110XY with
1208 * X = Bit 9 of slave address
1209 * Y = Bit 8 of slave address
1211 addr = slave->addr >> 8;
1213 if (addr == addcode)
1216 addr = slave->addr & 0x7f;
1217 if (addr == addcode)
1224 static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev)
1226 struct i2c_client *slave = i2c_dev->slave_running;
1227 void __iomem *base = i2c_dev->base;
1231 if (i2c_dev->slave_dir) {
1232 /* Notify i2c slave that new read transfer is starting */
1233 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
1236 * Disable slave TX config in case of I2C combined message
1237 * (I2C Write followed by I2C Read)
1239 mask = STM32F7_I2C_CR2_RELOAD;
1240 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask);
1241 mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1242 STM32F7_I2C_CR1_TCIE;
1243 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1245 /* Enable TX empty, STOP, NACK interrupts */
1246 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1247 STM32F7_I2C_CR1_TXIE;
1248 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1250 /* Write 1st data byte */
1251 writel_relaxed(value, base + STM32F7_I2C_TXDR);
1253 /* Notify i2c slave that new write transfer is starting */
1254 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
1256 /* Set reload mode to be able to ACK/NACK each received byte */
1257 mask = STM32F7_I2C_CR2_RELOAD;
1258 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1261 * Set STOP, NACK, RX empty and transfer complete interrupts.*
1262 * Set Slave Byte Control to be able to ACK/NACK each data
1265 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1266 STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1267 STM32F7_I2C_CR1_TCIE;
1268 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1272 static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev)
1274 void __iomem *base = i2c_dev->base;
1275 u32 isr, addcode, dir, mask;
1278 isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1279 addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr);
1280 dir = isr & STM32F7_I2C_ISR_DIR;
1282 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1283 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) {
1284 i2c_dev->slave_running = i2c_dev->slave[i];
1285 i2c_dev->slave_dir = dir;
1287 /* Start I2C slave processing */
1288 stm32f7_i2c_slave_start(i2c_dev);
1290 /* Clear ADDR flag */
1291 mask = STM32F7_I2C_ICR_ADDRCF;
1292 writel_relaxed(mask, base + STM32F7_I2C_ICR);
1298 static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1299 struct i2c_client *slave, int *id)
1303 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1304 if (i2c_dev->slave[i] == slave) {
1310 dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr);
1315 static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1316 struct i2c_client *slave, int *id)
1318 struct device *dev = i2c_dev->dev;
1322 * slave[0] supports 7-bit and 10-bit slave address
1323 * slave[1] supports 7-bit slave address only
1325 for (i = STM32F7_I2C_MAX_SLAVE - 1; i >= 0; i--) {
1326 if (i == 1 && (slave->flags & I2C_CLIENT_TEN))
1328 if (!i2c_dev->slave[i]) {
1334 dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr);
1339 static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev)
1343 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1344 if (i2c_dev->slave[i])
1351 static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev)
1356 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1357 if (i2c_dev->slave[i])
1364 static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev)
1366 void __iomem *base = i2c_dev->base;
1367 u32 cr2, status, mask;
1371 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1373 /* Slave transmitter mode */
1374 if (status & STM32F7_I2C_ISR_TXIS) {
1375 i2c_slave_event(i2c_dev->slave_running,
1376 I2C_SLAVE_READ_PROCESSED,
1379 /* Write data byte */
1380 writel_relaxed(val, base + STM32F7_I2C_TXDR);
1383 /* Transfer Complete Reload for Slave receiver mode */
1384 if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) {
1386 * Read data byte then set NBYTES to receive next byte or NACK
1387 * the current received byte
1389 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR);
1390 ret = i2c_slave_event(i2c_dev->slave_running,
1391 I2C_SLAVE_WRITE_RECEIVED,
1394 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
1395 cr2 |= STM32F7_I2C_CR2_NBYTES(1);
1396 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
1398 mask = STM32F7_I2C_CR2_NACK;
1399 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1404 if (status & STM32F7_I2C_ISR_NACKF) {
1405 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1406 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1410 if (status & STM32F7_I2C_ISR_STOPF) {
1411 /* Disable interrupts */
1412 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK);
1414 if (i2c_dev->slave_dir) {
1416 * Flush TX buffer in order to not used the byte in
1417 * TXDR for the next transfer
1419 mask = STM32F7_I2C_ISR_TXE;
1420 stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask);
1423 /* Clear STOP flag */
1424 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1426 /* Notify i2c slave that a STOP flag has been detected */
1427 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val);
1429 i2c_dev->slave_running = NULL;
1432 /* Address match received */
1433 if (status & STM32F7_I2C_ISR_ADDR)
1434 stm32f7_i2c_slave_addr(i2c_dev);
1439 static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
1441 struct stm32f7_i2c_dev *i2c_dev = data;
1442 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1443 void __iomem *base = i2c_dev->base;
1445 int ret = IRQ_HANDLED;
1447 /* Check if the interrupt if for a slave device */
1448 if (!i2c_dev->master_mode) {
1449 ret = stm32f7_i2c_slave_isr_event(i2c_dev);
1453 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1456 if (status & STM32F7_I2C_ISR_TXIS)
1457 stm32f7_i2c_write_tx_data(i2c_dev);
1460 if (status & STM32F7_I2C_ISR_RXNE)
1461 stm32f7_i2c_read_rx_data(i2c_dev);
1464 if (status & STM32F7_I2C_ISR_NACKF) {
1465 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1466 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1467 f7_msg->result = -ENXIO;
1470 /* STOP detection flag */
1471 if (status & STM32F7_I2C_ISR_STOPF) {
1472 /* Disable interrupts */
1473 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1474 mask = STM32F7_I2C_XFER_IRQ_MASK;
1476 mask = STM32F7_I2C_ALL_IRQ_MASK;
1477 stm32f7_i2c_disable_irq(i2c_dev, mask);
1479 /* Clear STOP flag */
1480 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1482 if (i2c_dev->use_dma) {
1483 ret = IRQ_WAKE_THREAD;
1485 i2c_dev->master_mode = false;
1486 complete(&i2c_dev->complete);
1490 /* Transfer complete */
1491 if (status & STM32F7_I2C_ISR_TC) {
1493 mask = STM32F7_I2C_CR2_STOP;
1494 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1495 } else if (i2c_dev->use_dma) {
1496 ret = IRQ_WAKE_THREAD;
1497 } else if (f7_msg->smbus) {
1498 stm32f7_i2c_smbus_rep_start(i2c_dev);
1502 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1506 if (status & STM32F7_I2C_ISR_TCR) {
1508 stm32f7_i2c_smbus_reload(i2c_dev);
1510 stm32f7_i2c_reload(i2c_dev);
1516 static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data)
1518 struct stm32f7_i2c_dev *i2c_dev = data;
1519 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1520 struct stm32_i2c_dma *dma = i2c_dev->dma;
1525 * Wait for dma transfer completion before sending next message or
1526 * notity the end of xfer to the client
1528 ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ);
1530 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__);
1531 stm32f7_i2c_disable_dma_req(i2c_dev);
1532 dmaengine_terminate_all(dma->chan_using);
1533 f7_msg->result = -ETIMEDOUT;
1536 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1538 if (status & STM32F7_I2C_ISR_TC) {
1539 if (f7_msg->smbus) {
1540 stm32f7_i2c_smbus_rep_start(i2c_dev);
1544 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1547 i2c_dev->master_mode = false;
1548 complete(&i2c_dev->complete);
1554 static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data)
1556 struct stm32f7_i2c_dev *i2c_dev = data;
1557 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1558 void __iomem *base = i2c_dev->base;
1559 struct device *dev = i2c_dev->dev;
1560 struct stm32_i2c_dma *dma = i2c_dev->dma;
1563 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1566 if (status & STM32F7_I2C_ISR_BERR) {
1567 dev_err(dev, "<%s>: Bus error\n", __func__);
1568 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR);
1569 stm32f7_i2c_release_bus(&i2c_dev->adap);
1570 f7_msg->result = -EIO;
1573 /* Arbitration loss */
1574 if (status & STM32F7_I2C_ISR_ARLO) {
1575 dev_dbg(dev, "<%s>: Arbitration loss\n", __func__);
1576 writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR);
1577 f7_msg->result = -EAGAIN;
1580 if (status & STM32F7_I2C_ISR_PECERR) {
1581 dev_err(dev, "<%s>: PEC error in reception\n", __func__);
1582 writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR);
1583 f7_msg->result = -EINVAL;
1586 if (!i2c_dev->slave_running) {
1588 /* Disable interrupts */
1589 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1590 mask = STM32F7_I2C_XFER_IRQ_MASK;
1592 mask = STM32F7_I2C_ALL_IRQ_MASK;
1593 stm32f7_i2c_disable_irq(i2c_dev, mask);
1597 if (i2c_dev->use_dma) {
1598 stm32f7_i2c_disable_dma_req(i2c_dev);
1599 dmaengine_terminate_all(dma->chan_using);
1602 i2c_dev->master_mode = false;
1603 complete(&i2c_dev->complete);
1608 static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap,
1609 struct i2c_msg msgs[], int num)
1611 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
1612 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1613 struct stm32_i2c_dma *dma = i2c_dev->dma;
1614 unsigned long time_left;
1617 i2c_dev->msg = msgs;
1618 i2c_dev->msg_num = num;
1619 i2c_dev->msg_id = 0;
1620 f7_msg->smbus = false;
1622 ret = pm_runtime_get_sync(i2c_dev->dev);
1626 ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1630 stm32f7_i2c_xfer_msg(i2c_dev, msgs);
1632 time_left = wait_for_completion_timeout(&i2c_dev->complete,
1633 i2c_dev->adap.timeout);
1634 ret = f7_msg->result;
1637 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n",
1638 i2c_dev->msg->addr);
1639 if (i2c_dev->use_dma)
1640 dmaengine_terminate_all(dma->chan_using);
1645 pm_runtime_mark_last_busy(i2c_dev->dev);
1646 pm_runtime_put_autosuspend(i2c_dev->dev);
1648 return (ret < 0) ? ret : num;
1651 static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
1652 unsigned short flags, char read_write,
1653 u8 command, int size,
1654 union i2c_smbus_data *data)
1656 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter);
1657 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1658 struct stm32_i2c_dma *dma = i2c_dev->dma;
1659 struct device *dev = i2c_dev->dev;
1660 unsigned long timeout;
1663 f7_msg->addr = addr;
1664 f7_msg->size = size;
1665 f7_msg->read_write = read_write;
1666 f7_msg->smbus = true;
1668 ret = pm_runtime_get_sync(dev);
1672 ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1676 ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data);
1680 timeout = wait_for_completion_timeout(&i2c_dev->complete,
1681 i2c_dev->adap.timeout);
1682 ret = f7_msg->result;
1687 dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr);
1688 if (i2c_dev->use_dma)
1689 dmaengine_terminate_all(dma->chan_using);
1695 if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) {
1696 ret = stm32f7_i2c_smbus_check_pec(i2c_dev);
1701 if (read_write && size != I2C_SMBUS_QUICK) {
1703 case I2C_SMBUS_BYTE:
1704 case I2C_SMBUS_BYTE_DATA:
1705 data->byte = f7_msg->smbus_buf[0];
1707 case I2C_SMBUS_WORD_DATA:
1708 case I2C_SMBUS_PROC_CALL:
1709 data->word = f7_msg->smbus_buf[0] |
1710 (f7_msg->smbus_buf[1] << 8);
1712 case I2C_SMBUS_BLOCK_DATA:
1713 case I2C_SMBUS_BLOCK_PROC_CALL:
1714 for (i = 0; i <= f7_msg->smbus_buf[0]; i++)
1715 data->block[i] = f7_msg->smbus_buf[i];
1718 dev_err(dev, "Unsupported smbus transaction\n");
1724 pm_runtime_mark_last_busy(dev);
1725 pm_runtime_put_autosuspend(dev);
1729 static void stm32f7_i2c_enable_wakeup(struct stm32f7_i2c_dev *i2c_dev,
1732 void __iomem *base = i2c_dev->base;
1733 u32 mask = STM32F7_I2C_CR1_WUPEN;
1735 if (!i2c_dev->wakeup_src)
1739 device_set_wakeup_enable(i2c_dev->dev, true);
1740 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1742 device_set_wakeup_enable(i2c_dev->dev, false);
1743 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1747 static int stm32f7_i2c_reg_slave(struct i2c_client *slave)
1749 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1750 void __iomem *base = i2c_dev->base;
1751 struct device *dev = i2c_dev->dev;
1752 u32 oar1, oar2, mask;
1755 if (slave->flags & I2C_CLIENT_PEC) {
1756 dev_err(dev, "SMBus PEC not supported in slave mode\n");
1760 if (stm32f7_i2c_is_slave_busy(i2c_dev)) {
1761 dev_err(dev, "Too much slave registered\n");
1765 ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id);
1769 ret = pm_runtime_get_sync(dev);
1773 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
1774 stm32f7_i2c_enable_wakeup(i2c_dev, true);
1777 /* Configure Own Address 1 */
1778 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
1779 oar1 &= ~STM32F7_I2C_OAR1_MASK;
1780 if (slave->flags & I2C_CLIENT_TEN) {
1781 oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr);
1782 oar1 |= STM32F7_I2C_OAR1_OA1MODE;
1784 oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr);
1786 oar1 |= STM32F7_I2C_OAR1_OA1EN;
1787 i2c_dev->slave[id] = slave;
1788 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1);
1789 } else if (id == 1) {
1790 /* Configure Own Address 2 */
1791 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
1792 oar2 &= ~STM32F7_I2C_OAR2_MASK;
1793 if (slave->flags & I2C_CLIENT_TEN) {
1798 oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr);
1799 oar2 |= STM32F7_I2C_OAR2_OA2EN;
1800 i2c_dev->slave[id] = slave;
1801 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2);
1808 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK);
1810 /* Enable Address match interrupt, error interrupt and enable I2C */
1811 mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE |
1813 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1817 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
1818 stm32f7_i2c_enable_wakeup(i2c_dev, false);
1820 pm_runtime_mark_last_busy(dev);
1821 pm_runtime_put_autosuspend(dev);
1826 static int stm32f7_i2c_unreg_slave(struct i2c_client *slave)
1828 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1829 void __iomem *base = i2c_dev->base;
1833 ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id);
1837 WARN_ON(!i2c_dev->slave[id]);
1839 ret = pm_runtime_get_sync(i2c_dev->dev);
1844 mask = STM32F7_I2C_OAR1_OA1EN;
1845 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask);
1847 mask = STM32F7_I2C_OAR2_OA2EN;
1848 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask);
1851 i2c_dev->slave[id] = NULL;
1853 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
1854 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
1855 stm32f7_i2c_enable_wakeup(i2c_dev, false);
1858 pm_runtime_mark_last_busy(i2c_dev->dev);
1859 pm_runtime_put_autosuspend(i2c_dev->dev);
1864 static int stm32f7_i2c_write_fm_plus_bits(struct stm32f7_i2c_dev *i2c_dev,
1869 if (i2c_dev->speed != STM32_I2C_SPEED_FAST_PLUS ||
1870 IS_ERR_OR_NULL(i2c_dev->regmap))
1874 if (i2c_dev->fmp_sreg == i2c_dev->fmp_creg)
1875 ret = regmap_update_bits(i2c_dev->regmap,
1878 enable ? i2c_dev->fmp_mask : 0);
1880 ret = regmap_write(i2c_dev->regmap,
1881 enable ? i2c_dev->fmp_sreg :
1888 static int stm32f7_i2c_setup_fm_plus_bits(struct platform_device *pdev,
1889 struct stm32f7_i2c_dev *i2c_dev)
1891 struct device_node *np = pdev->dev.of_node;
1894 i2c_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg-fmp");
1895 if (IS_ERR(i2c_dev->regmap))
1899 ret = of_property_read_u32_index(np, "st,syscfg-fmp", 1,
1900 &i2c_dev->fmp_sreg);
1904 i2c_dev->fmp_creg = i2c_dev->fmp_sreg +
1905 i2c_dev->setup.fmp_clr_offset;
1907 return of_property_read_u32_index(np, "st,syscfg-fmp", 2,
1908 &i2c_dev->fmp_mask);
1911 static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
1913 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE |
1914 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
1915 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
1916 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
1917 I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC |
1918 I2C_FUNC_SMBUS_I2C_BLOCK;
1921 static const struct i2c_algorithm stm32f7_i2c_algo = {
1922 .master_xfer = stm32f7_i2c_xfer,
1923 .smbus_xfer = stm32f7_i2c_smbus_xfer,
1924 .functionality = stm32f7_i2c_func,
1925 .reg_slave = stm32f7_i2c_reg_slave,
1926 .unreg_slave = stm32f7_i2c_unreg_slave,
1929 static int stm32f7_i2c_probe(struct platform_device *pdev)
1931 struct stm32f7_i2c_dev *i2c_dev;
1932 const struct stm32f7_i2c_setup *setup;
1933 struct resource *res;
1934 struct i2c_adapter *adap;
1935 struct reset_control *rst;
1936 dma_addr_t phy_addr;
1937 int irq_error, irq_event, ret;
1939 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
1943 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1944 i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
1945 if (IS_ERR(i2c_dev->base))
1946 return PTR_ERR(i2c_dev->base);
1947 phy_addr = (dma_addr_t)res->start;
1949 irq_event = platform_get_irq(pdev, 0);
1950 if (irq_event <= 0) {
1951 if (irq_event != -EPROBE_DEFER)
1952 dev_err(&pdev->dev, "Failed to get IRQ event: %d\n",
1954 return irq_event ? : -ENOENT;
1957 irq_error = platform_get_irq(pdev, 1);
1958 if (irq_error <= 0) {
1959 if (irq_error != -EPROBE_DEFER)
1960 dev_err(&pdev->dev, "Failed to get IRQ error: %d\n",
1962 return irq_error ? : -ENOENT;
1965 i2c_dev->wakeup_src = of_property_read_bool(pdev->dev.of_node,
1968 i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
1969 if (IS_ERR(i2c_dev->clk)) {
1970 dev_err(&pdev->dev, "Error: Missing controller clock\n");
1971 return PTR_ERR(i2c_dev->clk);
1974 ret = clk_prepare_enable(i2c_dev->clk);
1976 dev_err(&pdev->dev, "Failed to prepare_enable clock\n");
1980 rst = devm_reset_control_get(&pdev->dev, NULL);
1982 dev_err(&pdev->dev, "Error: Missing controller reset\n");
1986 reset_control_assert(rst);
1988 reset_control_deassert(rst);
1990 i2c_dev->dev = &pdev->dev;
1992 ret = devm_request_threaded_irq(&pdev->dev, irq_event,
1993 stm32f7_i2c_isr_event,
1994 stm32f7_i2c_isr_event_thread,
1996 pdev->name, i2c_dev);
1998 dev_err(&pdev->dev, "Failed to request irq event %i\n",
2003 ret = devm_request_irq(&pdev->dev, irq_error, stm32f7_i2c_isr_error, 0,
2004 pdev->name, i2c_dev);
2006 dev_err(&pdev->dev, "Failed to request irq error %i\n",
2011 setup = of_device_get_match_data(&pdev->dev);
2013 dev_err(&pdev->dev, "Can't get device data\n");
2017 i2c_dev->setup = *setup;
2019 ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup);
2023 if (i2c_dev->speed == STM32_I2C_SPEED_FAST_PLUS) {
2024 ret = stm32f7_i2c_setup_fm_plus_bits(pdev, i2c_dev);
2027 ret = stm32f7_i2c_write_fm_plus_bits(i2c_dev, true);
2032 adap = &i2c_dev->adap;
2033 i2c_set_adapdata(adap, i2c_dev);
2034 snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)",
2036 adap->owner = THIS_MODULE;
2037 adap->timeout = 2 * HZ;
2039 adap->algo = &stm32f7_i2c_algo;
2040 adap->dev.parent = &pdev->dev;
2041 adap->dev.of_node = pdev->dev.of_node;
2043 init_completion(&i2c_dev->complete);
2045 /* Init DMA config if supported */
2046 i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr,
2049 if (PTR_ERR(i2c_dev->dma) == -ENODEV)
2050 i2c_dev->dma = NULL;
2051 else if (IS_ERR(i2c_dev->dma)) {
2052 ret = PTR_ERR(i2c_dev->dma);
2053 if (ret != -EPROBE_DEFER)
2055 "Failed to request dma error %i\n", ret);
2059 if (i2c_dev->wakeup_src) {
2060 device_set_wakeup_capable(i2c_dev->dev, true);
2062 ret = dev_pm_set_wake_irq(i2c_dev->dev, irq_event);
2064 dev_err(i2c_dev->dev, "Failed to set wake up irq\n");
2065 goto clr_wakeup_capable;
2069 platform_set_drvdata(pdev, i2c_dev);
2071 pm_runtime_set_autosuspend_delay(i2c_dev->dev,
2072 STM32F7_AUTOSUSPEND_DELAY);
2073 pm_runtime_use_autosuspend(i2c_dev->dev);
2074 pm_runtime_set_active(i2c_dev->dev);
2075 pm_runtime_enable(i2c_dev->dev);
2077 pm_runtime_get_noresume(&pdev->dev);
2079 stm32f7_i2c_hw_config(i2c_dev);
2081 ret = i2c_add_adapter(adap);
2085 dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr);
2087 pm_runtime_mark_last_busy(i2c_dev->dev);
2088 pm_runtime_put_autosuspend(i2c_dev->dev);
2093 pm_runtime_put_noidle(i2c_dev->dev);
2094 pm_runtime_disable(i2c_dev->dev);
2095 pm_runtime_set_suspended(i2c_dev->dev);
2096 pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2098 if (i2c_dev->wakeup_src)
2099 dev_pm_clear_wake_irq(i2c_dev->dev);
2102 if (i2c_dev->wakeup_src)
2103 device_set_wakeup_capable(i2c_dev->dev, false);
2106 stm32_i2c_dma_free(i2c_dev->dma);
2107 i2c_dev->dma = NULL;
2111 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2114 clk_disable_unprepare(i2c_dev->clk);
2119 static int stm32f7_i2c_remove(struct platform_device *pdev)
2121 struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
2123 i2c_del_adapter(&i2c_dev->adap);
2124 pm_runtime_get_sync(i2c_dev->dev);
2126 if (i2c_dev->wakeup_src) {
2127 dev_pm_clear_wake_irq(i2c_dev->dev);
2129 * enforce that wakeup is disabled and that the device
2130 * is marked as non wakeup capable
2132 device_init_wakeup(i2c_dev->dev, false);
2135 pm_runtime_put_noidle(i2c_dev->dev);
2136 pm_runtime_disable(i2c_dev->dev);
2137 pm_runtime_set_suspended(i2c_dev->dev);
2138 pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2141 stm32_i2c_dma_free(i2c_dev->dma);
2142 i2c_dev->dma = NULL;
2145 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2147 clk_disable_unprepare(i2c_dev->clk);
2152 static int __maybe_unused stm32f7_i2c_runtime_suspend(struct device *dev)
2154 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2156 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
2157 clk_disable_unprepare(i2c_dev->clk);
2162 static int __maybe_unused stm32f7_i2c_runtime_resume(struct device *dev)
2164 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2167 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
2168 ret = clk_prepare_enable(i2c_dev->clk);
2170 dev_err(dev, "failed to prepare_enable clock\n");
2178 #ifdef CONFIG_PM_SLEEP
2179 static int stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev *i2c_dev)
2182 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2184 ret = pm_runtime_get_sync(i2c_dev->dev);
2188 backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2189 backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
2190 backup_regs->oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
2191 backup_regs->oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
2192 backup_regs->tmgr = readl_relaxed(i2c_dev->base + STM32F7_I2C_TIMINGR);
2193 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2195 pm_runtime_put_sync(i2c_dev->dev);
2200 static int stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev *i2c_dev)
2204 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2206 ret = pm_runtime_get_sync(i2c_dev->dev);
2210 cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2211 if (cr1 & STM32F7_I2C_CR1_PE)
2212 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
2213 STM32F7_I2C_CR1_PE);
2215 writel_relaxed(backup_regs->tmgr, i2c_dev->base + STM32F7_I2C_TIMINGR);
2216 writel_relaxed(backup_regs->cr1 & ~STM32F7_I2C_CR1_PE,
2217 i2c_dev->base + STM32F7_I2C_CR1);
2218 if (backup_regs->cr1 & STM32F7_I2C_CR1_PE)
2219 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
2220 STM32F7_I2C_CR1_PE);
2221 writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2);
2222 writel_relaxed(backup_regs->oar1, i2c_dev->base + STM32F7_I2C_OAR1);
2223 writel_relaxed(backup_regs->oar2, i2c_dev->base + STM32F7_I2C_OAR2);
2224 stm32f7_i2c_write_fm_plus_bits(i2c_dev, true);
2226 pm_runtime_put_sync(i2c_dev->dev);
2231 static int stm32f7_i2c_suspend(struct device *dev)
2233 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2236 i2c_mark_adapter_suspended(&i2c_dev->adap);
2238 if (!device_may_wakeup(dev) && !dev->power.wakeup_path) {
2239 ret = stm32f7_i2c_regs_backup(i2c_dev);
2241 i2c_mark_adapter_resumed(&i2c_dev->adap);
2245 pinctrl_pm_select_sleep_state(dev);
2246 pm_runtime_force_suspend(dev);
2252 static int stm32f7_i2c_resume(struct device *dev)
2254 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2257 if (!device_may_wakeup(dev) && !dev->power.wakeup_path) {
2258 ret = pm_runtime_force_resume(dev);
2261 pinctrl_pm_select_default_state(dev);
2263 ret = stm32f7_i2c_regs_restore(i2c_dev);
2268 i2c_mark_adapter_resumed(&i2c_dev->adap);
2274 static const struct dev_pm_ops stm32f7_i2c_pm_ops = {
2275 SET_RUNTIME_PM_OPS(stm32f7_i2c_runtime_suspend,
2276 stm32f7_i2c_runtime_resume, NULL)
2277 SET_SYSTEM_SLEEP_PM_OPS(stm32f7_i2c_suspend, stm32f7_i2c_resume)
2280 static const struct of_device_id stm32f7_i2c_match[] = {
2281 { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup},
2282 { .compatible = "st,stm32mp15-i2c", .data = &stm32mp15_setup},
2285 MODULE_DEVICE_TABLE(of, stm32f7_i2c_match);
2287 static struct platform_driver stm32f7_i2c_driver = {
2289 .name = "stm32f7-i2c",
2290 .of_match_table = stm32f7_i2c_match,
2291 .pm = &stm32f7_i2c_pm_ops,
2293 .probe = stm32f7_i2c_probe,
2294 .remove = stm32f7_i2c_remove,
2297 module_platform_driver(stm32f7_i2c_driver);
2299 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
2300 MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver");
2301 MODULE_LICENSE("GPL v2");