drivers/i2c/busses/i2c-stm32f7.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for STMicroelectronics STM32F7 I2C controller
   4  *
   5  * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc
   6  * reference manual.
   7  * Please see below a link to the documentation:
   8  * http://www.st.com/resource/en/reference_manual/dm00124865.pdf
   9  *
  10  * Copyright (C) M'boumba Cedric Madianga 2017
  11  * Copyright (C) STMicroelectronics 2017
  12  * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
  13  *
  14  * This driver is based on i2c-stm32f4.c
  15  *
  16  */
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/err.h>
  20 #include <linux/i2c.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/io.h>
  23 #include <linux/iopoll.h>
  24 #include <linux/mfd/syscon.h>
  25 #include <linux/module.h>
  26 #include <linux/of.h>
  27 #include <linux/of_address.h>
  28 #include <linux/of_platform.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/pinctrl/consumer.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/regmap.h>
  33 #include <linux/reset.h>
  34 #include <linux/slab.h>
  35
  36 #include "i2c-stm32.h"
  37
  38 /* STM32F7 I2C registers */
  39 #define STM32F7_I2C_CR1                         0x00
  40 #define STM32F7_I2C_CR2                         0x04
  41 #define STM32F7_I2C_OAR1                        0x08
  42 #define STM32F7_I2C_OAR2                        0x0C
  43 #define STM32F7_I2C_PECR                        0x20
  44 #define STM32F7_I2C_TIMINGR                     0x10
  45 #define STM32F7_I2C_ISR                         0x18
  46 #define STM32F7_I2C_ICR                         0x1C
  47 #define STM32F7_I2C_RXDR                        0x24
  48 #define STM32F7_I2C_TXDR                        0x28
  49
  50 /* STM32F7 I2C control 1 */
  51 #define STM32F7_I2C_CR1_PECEN                   BIT(23)
  52 #define STM32F7_I2C_CR1_SBC                     BIT(16)
  53 #define STM32F7_I2C_CR1_RXDMAEN                 BIT(15)
  54 #define STM32F7_I2C_CR1_TXDMAEN                 BIT(14)
  55 #define STM32F7_I2C_CR1_ANFOFF                  BIT(12)
  56 #define STM32F7_I2C_CR1_ERRIE                   BIT(7)
  57 #define STM32F7_I2C_CR1_TCIE                    BIT(6)
  58 #define STM32F7_I2C_CR1_STOPIE                  BIT(5)
  59 #define STM32F7_I2C_CR1_NACKIE                  BIT(4)
  60 #define STM32F7_I2C_CR1_ADDRIE                  BIT(3)
  61 #define STM32F7_I2C_CR1_RXIE                    BIT(2)
  62 #define STM32F7_I2C_CR1_TXIE                    BIT(1)
  63 #define STM32F7_I2C_CR1_PE                      BIT(0)
  64 #define STM32F7_I2C_ALL_IRQ_MASK                (STM32F7_I2C_CR1_ERRIE \
  65                                                 | STM32F7_I2C_CR1_TCIE \
  66                                                 | STM32F7_I2C_CR1_STOPIE \
  67                                                 | STM32F7_I2C_CR1_NACKIE \
  68                                                 | STM32F7_I2C_CR1_RXIE \
  69                                                 | STM32F7_I2C_CR1_TXIE)
  70 #define STM32F7_I2C_XFER_IRQ_MASK               (STM32F7_I2C_CR1_TCIE \
  71                                                 | STM32F7_I2C_CR1_STOPIE \
  72                                                 | STM32F7_I2C_CR1_NACKIE \
  73                                                 | STM32F7_I2C_CR1_RXIE \
  74                                                 | STM32F7_I2C_CR1_TXIE)
  75
  76 /* STM32F7 I2C control 2 */
  77 #define STM32F7_I2C_CR2_PECBYTE                 BIT(26)
  78 #define STM32F7_I2C_CR2_RELOAD                  BIT(24)
  79 #define STM32F7_I2C_CR2_NBYTES_MASK             GENMASK(23, 16)
  80 #define STM32F7_I2C_CR2_NBYTES(n)               (((n) & 0xff) << 16)
  81 #define STM32F7_I2C_CR2_NACK                    BIT(15)
  82 #define STM32F7_I2C_CR2_STOP                    BIT(14)
  83 #define STM32F7_I2C_CR2_START                   BIT(13)
  84 #define STM32F7_I2C_CR2_HEAD10R                 BIT(12)
  85 #define STM32F7_I2C_CR2_ADD10                   BIT(11)
  86 #define STM32F7_I2C_CR2_RD_WRN                  BIT(10)
  87 #define STM32F7_I2C_CR2_SADD10_MASK             GENMASK(9, 0)
  88 #define STM32F7_I2C_CR2_SADD10(n)               (((n) & \
  89                                                 STM32F7_I2C_CR2_SADD10_MASK))
  90 #define STM32F7_I2C_CR2_SADD7_MASK              GENMASK(7, 1)
  91 #define STM32F7_I2C_CR2_SADD7(n)                (((n) & 0x7f) << 1)
  92
  93 /* STM32F7 I2C Own Address 1 */
  94 #define STM32F7_I2C_OAR1_OA1EN                  BIT(15)
  95 #define STM32F7_I2C_OAR1_OA1MODE                BIT(10)
  96 #define STM32F7_I2C_OAR1_OA1_10_MASK            GENMASK(9, 0)
  97 #define STM32F7_I2C_OAR1_OA1_10(n)              (((n) & \
  98                                                 STM32F7_I2C_OAR1_OA1_10_MASK))
  99 #define STM32F7_I2C_OAR1_OA1_7_MASK             GENMASK(7, 1)
 100 #define STM32F7_I2C_OAR1_OA1_7(n)               (((n) & 0x7f) << 1)
 101 #define STM32F7_I2C_OAR1_MASK                   (STM32F7_I2C_OAR1_OA1_7_MASK \
 102                                                 | STM32F7_I2C_OAR1_OA1_10_MASK \
 103                                                 | STM32F7_I2C_OAR1_OA1EN \
 104                                                 | STM32F7_I2C_OAR1_OA1MODE)
 105
 106 /* STM32F7 I2C Own Address 2 */
 107 #define STM32F7_I2C_OAR2_OA2EN                  BIT(15)
 108 #define STM32F7_I2C_OAR2_OA2MSK_MASK            GENMASK(10, 8)
 109 #define STM32F7_I2C_OAR2_OA2MSK(n)              (((n) & 0x7) << 8)
 110 #define STM32F7_I2C_OAR2_OA2_7_MASK             GENMASK(7, 1)
 111 #define STM32F7_I2C_OAR2_OA2_7(n)               (((n) & 0x7f) << 1)
 112 #define STM32F7_I2C_OAR2_MASK                   (STM32F7_I2C_OAR2_OA2MSK_MASK \
 113                                                 | STM32F7_I2C_OAR2_OA2_7_MASK \
 114                                                 | STM32F7_I2C_OAR2_OA2EN)
 115
 116 /* STM32F7 I2C Interrupt Status */
 117 #define STM32F7_I2C_ISR_ADDCODE_MASK            GENMASK(23, 17)
 118 #define STM32F7_I2C_ISR_ADDCODE_GET(n) \
 119                                 (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17)
 120 #define STM32F7_I2C_ISR_DIR                     BIT(16)
 121 #define STM32F7_I2C_ISR_BUSY                    BIT(15)
 122 #define STM32F7_I2C_ISR_PECERR                  BIT(11)
 123 #define STM32F7_I2C_ISR_ARLO                    BIT(9)
 124 #define STM32F7_I2C_ISR_BERR                    BIT(8)
 125 #define STM32F7_I2C_ISR_TCR                     BIT(7)
 126 #define STM32F7_I2C_ISR_TC                      BIT(6)
 127 #define STM32F7_I2C_ISR_STOPF                   BIT(5)
 128 #define STM32F7_I2C_ISR_NACKF                   BIT(4)
 129 #define STM32F7_I2C_ISR_ADDR                    BIT(3)
 130 #define STM32F7_I2C_ISR_RXNE                    BIT(2)
 131 #define STM32F7_I2C_ISR_TXIS                    BIT(1)
 132 #define STM32F7_I2C_ISR_TXE                     BIT(0)
 133
 134 /* STM32F7 I2C Interrupt Clear */
 135 #define STM32F7_I2C_ICR_PECCF                   BIT(11)
 136 #define STM32F7_I2C_ICR_ARLOCF                  BIT(9)
 137 #define STM32F7_I2C_ICR_BERRCF                  BIT(8)
 138 #define STM32F7_I2C_ICR_STOPCF                  BIT(5)
 139 #define STM32F7_I2C_ICR_NACKCF                  BIT(4)
 140 #define STM32F7_I2C_ICR_ADDRCF                  BIT(3)
 141
 142 /* STM32F7 I2C Timing */
 143 #define STM32F7_I2C_TIMINGR_PRESC(n)            (((n) & 0xf) << 28)
 144 #define STM32F7_I2C_TIMINGR_SCLDEL(n)           (((n) & 0xf) << 20)
 145 #define STM32F7_I2C_TIMINGR_SDADEL(n)           (((n) & 0xf) << 16)
 146 #define STM32F7_I2C_TIMINGR_SCLH(n)             (((n) & 0xff) << 8)
 147 #define STM32F7_I2C_TIMINGR_SCLL(n)             ((n) & 0xff)
 148
 149 #define STM32F7_I2C_MAX_LEN                     0xff
 150 #define STM32F7_I2C_DMA_LEN_MIN                 0x16
 151 #define STM32F7_I2C_MAX_SLAVE                   0x2
 152
 153 #define STM32F7_I2C_DNF_DEFAULT                 0
 154 #define STM32F7_I2C_DNF_MAX                     16
 155
 156 #define STM32F7_I2C_ANALOG_FILTER_ENABLE        1
 157 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN     50      /* ns */
 158 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX     260     /* ns */
 159
 160 #define STM32F7_I2C_RISE_TIME_DEFAULT           25      /* ns */
 161 #define STM32F7_I2C_FALL_TIME_DEFAULT           10      /* ns */
 162
 163 #define STM32F7_PRESC_MAX                       BIT(4)
 164 #define STM32F7_SCLDEL_MAX                      BIT(4)
 165 #define STM32F7_SDADEL_MAX                      BIT(4)
 166 #define STM32F7_SCLH_MAX                        BIT(8)
 167 #define STM32F7_SCLL_MAX                        BIT(8)
 168
 169 #define STM32F7_AUTOSUSPEND_DELAY               (HZ / 100)
 170
 171 /**
 172  * struct stm32f7_i2c_regs - i2c f7 registers backup
 173  * @cr1: Control register 1
 174  * @cr2: Control register 2
 175  * @oar1: Own address 1 register
 176  * @oar2: Own address 2 register
 177  * @pecr: PEC register
 178  * @tmgr: Timing register
 179  */
 180 struct stm32f7_i2c_regs {
 181         u32 cr1;
 182         u32 cr2;
 183         u32 oar1;
 184         u32 oar2;
 185         u32 pecr;
 186         u32 tmgr;
 187 };
 188
 189 /**
 190  * struct stm32f7_i2c_spec - private i2c specification timing
 191  * @rate: I2C bus speed (Hz)
 192  * @rate_min: 80% of I2C bus speed (Hz)
 193  * @rate_max: 100% of I2C bus speed (Hz)
 194  * @fall_max: Max fall time of both SDA and SCL signals (ns)
 195  * @rise_max: Max rise time of both SDA and SCL signals (ns)
 196  * @hddat_min: Min data hold time (ns)
 197  * @vddat_max: Max data valid time (ns)
 198  * @sudat_min: Min data setup time (ns)
 199  * @l_min: Min low period of the SCL clock (ns)
 200  * @h_min: Min high period of the SCL clock (ns)
 201  */
 202 struct stm32f7_i2c_spec {
 203         u32 rate;
 204         u32 rate_min;
 205         u32 rate_max;
 206         u32 fall_max;
 207         u32 rise_max;
 208         u32 hddat_min;
 209         u32 vddat_max;
 210         u32 sudat_min;
 211         u32 l_min;
 212         u32 h_min;
 213 };
 214
 215 /**
 216  * struct stm32f7_i2c_setup - private I2C timing setup parameters
 217  * @speed: I2C speed mode (standard, Fast Plus)
 218  * @speed_freq: I2C speed frequency  (Hz)
 219  * @clock_src: I2C clock source frequency (Hz)
 220  * @rise_time: Rise time (ns)
 221  * @fall_time: Fall time (ns)
 222  * @dnf: Digital filter coefficient (0-16)
 223  * @analog_filter: Analog filter delay (On/Off)
 224  */
 225 struct stm32f7_i2c_setup {
 226         enum stm32_i2c_speed speed;
 227         u32 speed_freq;
 228         u32 clock_src;
 229         u32 rise_time;
 230         u32 fall_time;
 231         u8 dnf;
 232         bool analog_filter;
 233 };
 234
 235 /**
 236  * struct stm32f7_i2c_timings - private I2C output parameters
 237  * @node: List entry
 238  * @presc: Prescaler value
 239  * @scldel: Data setup time
 240  * @sdadel: Data hold time
 241  * @sclh: SCL high period (master mode)
 242  * @scll: SCL low period (master mode)
 243  */
 244 struct stm32f7_i2c_timings {
 245         struct list_head node;
 246         u8 presc;
 247         u8 scldel;
 248         u8 sdadel;
 249         u8 sclh;
 250         u8 scll;
 251 };
 252
 253 /**
 254  * struct stm32f7_i2c_msg - client specific data
 255  * @addr: 8-bit or 10-bit slave addr, including r/w bit
 256  * @count: number of bytes to be transferred
 257  * @buf: data buffer
 258  * @result: result of the transfer
 259  * @stop: last I2C msg to be sent, i.e. STOP to be generated
 260  * @smbus: boolean to know if the I2C IP is used in SMBus mode
 261  * @size: type of SMBus protocol
 262  * @read_write: direction of SMBus protocol
 263  * SMBus block read and SMBus block write - block read process call protocols
 264  * @smbus_buf: buffer to be used for SMBus protocol transfer. It will
 265  * contain a maximum of 32 bytes of data + byte command + byte count + PEC
 266  * This buffer has to be 32-bit aligned to be compliant with memory address
 267  * register in DMA mode.
 268  */
 269 struct stm32f7_i2c_msg {
 270         u16 addr;
 271         u32 count;
 272         u8 *buf;
 273         int result;
 274         bool stop;
 275         bool smbus;
 276         int size;
 277         char read_write;
 278         u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4);
 279 };
 280
 281 /**
 282  * struct stm32f7_i2c_dev - private data of the controller
 283  * @adap: I2C adapter for this controller
 284  * @dev: device for this controller
 285  * @base: virtual memory area
 286  * @complete: completion of I2C message
 287  * @clk: hw i2c clock
 288  * @speed: I2C clock frequency of the controller. Standard, Fast or Fast+
 289  * @msg: Pointer to data to be written
 290  * @msg_num: number of I2C messages to be executed
 291  * @msg_id: message identifiant
 292  * @f7_msg: customized i2c msg for driver usage
 293  * @setup: I2C timing input setup
 294  * @timing: I2C computed timings
 295  * @slave: list of slave devices registered on the I2C bus
 296  * @slave_running: slave device currently used
 297  * @backup_regs: backup of i2c controller registers (for suspend/resume)
 298  * @slave_dir: transfer direction for the current slave device
 299  * @master_mode: boolean to know in which mode the I2C is running (master or
 300  * slave)
 301  * @dma: dma data
 302  * @use_dma: boolean to know if dma is used in the current transfer
 303  * @regmap: holds SYSCFG phandle for Fast Mode Plus bits
 304  */
 305 struct stm32f7_i2c_dev {
 306         struct i2c_adapter adap;
 307         struct device *dev;
 308         void __iomem *base;
 309         struct completion complete;
 310         struct clk *clk;
 311         int speed;
 312         struct i2c_msg *msg;
 313         unsigned int msg_num;
 314         unsigned int msg_id;
 315         struct stm32f7_i2c_msg f7_msg;
 316         struct stm32f7_i2c_setup setup;
 317         struct stm32f7_i2c_timings timing;
 318         struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE];
 319         struct i2c_client *slave_running;
 320         struct stm32f7_i2c_regs backup_regs;
 321         u32 slave_dir;
 322         bool master_mode;
 323         struct stm32_i2c_dma *dma;
 324         bool use_dma;
 325         struct regmap *regmap;
 326 };
 327
 328 /*
 329  * All these values are coming from I2C Specification, Version 6.0, 4th of
 330  * April 2014.
 331  *
 332  * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast,
 333  * and Fast-mode Plus I2C-bus devices
 334  */
 335 static struct stm32f7_i2c_spec i2c_specs[] = {
 336         [STM32_I2C_SPEED_STANDARD] = {
 337                 .rate = 100000,
 338                 .rate_min = 80000,
 339                 .rate_max = 100000,
 340                 .fall_max = 300,
 341                 .rise_max = 1000,
 342                 .hddat_min = 0,
 343                 .vddat_max = 3450,
 344                 .sudat_min = 250,
 345                 .l_min = 4700,
 346                 .h_min = 4000,
 347         },
 348         [STM32_I2C_SPEED_FAST] = {
 349                 .rate = 400000,
 350                 .rate_min = 320000,
 351                 .rate_max = 400000,
 352                 .fall_max = 300,
 353                 .rise_max = 300,
 354                 .hddat_min = 0,
 355                 .vddat_max = 900,
 356                 .sudat_min = 100,
 357                 .l_min = 1300,
 358                 .h_min = 600,
 359         },
 360         [STM32_I2C_SPEED_FAST_PLUS] = {
 361                 .rate = 1000000,
 362                 .rate_min = 800000,
 363                 .rate_max = 1000000,
 364                 .fall_max = 100,
 365                 .rise_max = 120,
 366                 .hddat_min = 0,
 367                 .vddat_max = 450,
 368                 .sudat_min = 50,
 369                 .l_min = 500,
 370                 .h_min = 260,
 371         },
 372 };
 373
 374 static const struct stm32f7_i2c_setup stm32f7_setup = {
 375         .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
 376         .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
 377         .dnf = STM32F7_I2C_DNF_DEFAULT,
 378         .analog_filter = STM32F7_I2C_ANALOG_FILTER_ENABLE,
 379 };
 380
 381 static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask)
 382 {
 383         writel_relaxed(readl_relaxed(reg) | mask, reg);
 384 }
 385
 386 static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask)
 387 {
 388         writel_relaxed(readl_relaxed(reg) & ~mask, reg);
 389 }
 390
 391 static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)
 392 {
 393         stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
 394 }
 395
 396 static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev,
 397                                       struct stm32f7_i2c_setup *setup,
 398                                       struct stm32f7_i2c_timings *output)
 399 {
 400         u32 p_prev = STM32F7_PRESC_MAX;
 401         u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
 402                                        setup->clock_src);
 403         u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
 404                                        setup->speed_freq);
 405         u32 clk_error_prev = i2cbus;
 406         u32 tsync;
 407         u32 af_delay_min, af_delay_max;
 408         u32 dnf_delay;
 409         u32 clk_min, clk_max;
 410         int sdadel_min, sdadel_max;
 411         int scldel_min;
 412         struct stm32f7_i2c_timings *v, *_v, *s;
 413         struct list_head solutions;
 414         u16 p, l, a, h;
 415         int ret = 0;
 416
 417         if (setup->speed >= STM32_I2C_SPEED_END) {
 418                 dev_err(i2c_dev->dev, "speed out of bound {%d/%d}\n",
 419                         setup->speed, STM32_I2C_SPEED_END - 1);
 420                 return -EINVAL;
 421         }
 422
 423         if ((setup->rise_time > i2c_specs[setup->speed].rise_max) ||
 424             (setup->fall_time > i2c_specs[setup->speed].fall_max)) {
 425                 dev_err(i2c_dev->dev,
 426                         "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
 427                         setup->rise_time, i2c_specs[setup->speed].rise_max,
 428                         setup->fall_time, i2c_specs[setup->speed].fall_max);
 429                 return -EINVAL;
 430         }
 431
 432         if (setup->dnf > STM32F7_I2C_DNF_MAX) {
 433                 dev_err(i2c_dev->dev,
 434                         "DNF out of bound %d/%d\n",
 435                         setup->dnf, STM32F7_I2C_DNF_MAX);
 436                 return -EINVAL;
 437         }
 438
 439         if (setup->speed_freq > i2c_specs[setup->speed].rate) {
 440                 dev_err(i2c_dev->dev, "ERROR: Freq {%d/%d}\n",
 441                         setup->speed_freq, i2c_specs[setup->speed].rate);
 442                 return -EINVAL;
 443         }
 444
 445         /*  Analog and Digital Filters */
 446         af_delay_min =
 447                 (setup->analog_filter ?
 448                  STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0);
 449         af_delay_max =
 450                 (setup->analog_filter ?
 451                  STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0);
 452         dnf_delay = setup->dnf * i2cclk;
 453
 454         sdadel_min = i2c_specs[setup->speed].hddat_min + setup->fall_time -
 455                 af_delay_min - (setup->dnf + 3) * i2cclk;
 456
 457         sdadel_max = i2c_specs[setup->speed].vddat_max - setup->rise_time -
 458                 af_delay_max - (setup->dnf + 4) * i2cclk;
 459
 460         scldel_min = setup->rise_time + i2c_specs[setup->speed].sudat_min;
 461
 462         if (sdadel_min < 0)
 463                 sdadel_min = 0;
 464         if (sdadel_max < 0)
 465                 sdadel_max = 0;
 466
 467         dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n",
 468                 sdadel_min, sdadel_max, scldel_min);
 469
 470         INIT_LIST_HEAD(&solutions);
 471         /* Compute possible values for PRESC, SCLDEL and SDADEL */
 472         for (p = 0; p < STM32F7_PRESC_MAX; p++) {
 473                 for (l = 0; l < STM32F7_SCLDEL_MAX; l++) {
 474                         u32 scldel = (l + 1) * (p + 1) * i2cclk;
 475
 476                         if (scldel < scldel_min)
 477                                 continue;
 478
 479                         for (a = 0; a < STM32F7_SDADEL_MAX; a++) {
 480                                 u32 sdadel = (a * (p + 1) + 1) * i2cclk;
 481
 482                                 if (((sdadel >= sdadel_min) &&
 483                                      (sdadel <= sdadel_max)) &&
 484                                     (p != p_prev)) {
 485                                         v = kmalloc(sizeof(*v), GFP_KERNEL);
 486                                         if (!v) {
 487                                                 ret = -ENOMEM;
 488                                                 goto exit;
 489                                         }
 490
 491                                         v->presc = p;
 492                                         v->scldel = l;
 493                                         v->sdadel = a;
 494                                         p_prev = p;
 495
 496                                         list_add_tail(&v->node,
 497                                                       &solutions);
 498                                         break;
 499                                 }
 500                         }
 501
 502                         if (p_prev == p)
 503                                 break;
 504                 }
 505         }
 506
 507         if (list_empty(&solutions)) {
 508                 dev_err(i2c_dev->dev, "no Prescaler solution\n");
 509                 ret = -EPERM;
 510                 goto exit;
 511         }
 512
 513         tsync = af_delay_min + dnf_delay + (2 * i2cclk);
 514         s = NULL;
 515         clk_max = NSEC_PER_SEC / i2c_specs[setup->speed].rate_min;
 516         clk_min = NSEC_PER_SEC / i2c_specs[setup->speed].rate_max;
 517
 518         /*
 519          * Among Prescaler possibilities discovered above figures out SCL Low
 520          * and High Period. Provided:
 521          * - SCL Low Period has to be higher than SCL Clock Low Period
 522          *   defined by I2C Specification. I2C Clock has to be lower than
 523          *   (SCL Low Period - Analog/Digital filters) / 4.
 524          * - SCL High Period has to be lower than SCL Clock High Period
 525          *   defined by I2C Specification
 526          * - I2C Clock has to be lower than SCL High Period
 527          */
 528         list_for_each_entry(v, &solutions, node) {
 529                 u32 prescaler = (v->presc + 1) * i2cclk;
 530
 531                 for (l = 0; l < STM32F7_SCLL_MAX; l++) {
 532                         u32 tscl_l = (l + 1) * prescaler + tsync;
 533
 534                         if ((tscl_l < i2c_specs[setup->speed].l_min) ||
 535                             (i2cclk >=
 536                              ((tscl_l - af_delay_min - dnf_delay) / 4))) {
 537                                 continue;
 538                         }
 539
 540                         for (h = 0; h < STM32F7_SCLH_MAX; h++) {
 541                                 u32 tscl_h = (h + 1) * prescaler + tsync;
 542                                 u32 tscl = tscl_l + tscl_h +
 543                                         setup->rise_time + setup->fall_time;
 544
 545                                 if ((tscl >= clk_min) && (tscl <= clk_max) &&
 546                                     (tscl_h >= i2c_specs[setup->speed].h_min) &&
 547                                     (i2cclk < tscl_h)) {
 548                                         int clk_error = tscl - i2cbus;
 549
 550                                         if (clk_error < 0)
 551                                                 clk_error = -clk_error;
 552
 553                                         if (clk_error < clk_error_prev) {
 554                                                 clk_error_prev = clk_error;
 555                                                 v->scll = l;
 556                                                 v->sclh = h;
 557                                                 s = v;
 558                                         }
 559                                 }
 560                         }
 561                 }
 562         }
 563
 564         if (!s) {
 565                 dev_err(i2c_dev->dev, "no solution at all\n");
 566                 ret = -EPERM;
 567                 goto exit;
 568         }
 569
 570         output->presc = s->presc;
 571         output->scldel = s->scldel;
 572         output->sdadel = s->sdadel;
 573         output->scll = s->scll;
 574         output->sclh = s->sclh;
 575
 576         dev_dbg(i2c_dev->dev,
 577                 "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
 578                 output->presc,
 579                 output->scldel, output->sdadel,
 580                 output->scll, output->sclh);
 581
 582 exit:
 583         /* Release list and memory */
 584         list_for_each_entry_safe(v, _v, &solutions, node) {
 585                 list_del(&v->node);
 586                 kfree(v);
 587         }
 588
 589         return ret;
 590 }
 591
 592 static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev,
 593                                     struct stm32f7_i2c_setup *setup)
 594 {
 595         int ret = 0;
 596
 597         setup->speed = i2c_dev->speed;
 598         setup->speed_freq = i2c_specs[setup->speed].rate;
 599         setup->clock_src = clk_get_rate(i2c_dev->clk);
 600
 601         if (!setup->clock_src) {
 602                 dev_err(i2c_dev->dev, "clock rate is 0\n");
 603                 return -EINVAL;
 604         }
 605
 606         do {
 607                 ret = stm32f7_i2c_compute_timing(i2c_dev, setup,
 608                                                  &i2c_dev->timing);
 609                 if (ret) {
 610                         dev_err(i2c_dev->dev,
 611                                 "failed to compute I2C timings.\n");
 612                         if (i2c_dev->speed > STM32_I2C_SPEED_STANDARD) {
 613                                 i2c_dev->speed--;
 614                                 setup->speed = i2c_dev->speed;
 615                                 setup->speed_freq =
 616                                         i2c_specs[setup->speed].rate;
 617                                 dev_warn(i2c_dev->dev,
 618                                          "downgrade I2C Speed Freq to (%i)\n",
 619                                          i2c_specs[setup->speed].rate);
 620                         } else {
 621                                 break;
 622                         }
 623                 }
 624         } while (ret);
 625
 626         if (ret) {
 627                 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n");
 628                 return ret;
 629         }
 630
 631         dev_dbg(i2c_dev->dev, "I2C Speed(%i), Freq(%i), Clk Source(%i)\n",
 632                 setup->speed, setup->speed_freq, setup->clock_src);
 633         dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n",
 634                 setup->rise_time, setup->fall_time);
 635         dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n",
 636                 (setup->analog_filter ? "On" : "Off"), setup->dnf);
 637
 638         return 0;
 639 }
 640
 641 static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev)
 642 {
 643         void __iomem *base = i2c_dev->base;
 644         u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN;
 645
 646         stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
 647 }
 648
 649 static void stm32f7_i2c_dma_callback(void *arg)
 650 {
 651         struct stm32f7_i2c_dev *i2c_dev = (struct stm32f7_i2c_dev *)arg;
 652         struct stm32_i2c_dma *dma = i2c_dev->dma;
 653         struct device *dev = dma->chan_using->device->dev;
 654
 655         stm32f7_i2c_disable_dma_req(i2c_dev);
 656         dma_unmap_single(dev, dma->dma_buf, dma->dma_len, dma->dma_data_dir);
 657         complete(&dma->dma_complete);
 658 }
 659
 660 static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev)
 661 {
 662         struct stm32f7_i2c_timings *t = &i2c_dev->timing;
 663         u32 timing = 0;
 664
 665         /* Timing settings */
 666         timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc);
 667         timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel);
 668         timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel);
 669         timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh);
 670         timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll);
 671         writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR);
 672
 673         /* Enable I2C */
 674         if (i2c_dev->setup.analog_filter)
 675                 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
 676                                      STM32F7_I2C_CR1_ANFOFF);
 677         else
 678                 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
 679                                      STM32F7_I2C_CR1_ANFOFF);
 680         stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
 681                              STM32F7_I2C_CR1_PE);
 682 }
 683
 684 static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev)
 685 {
 686         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 687         void __iomem *base = i2c_dev->base;
 688
 689         if (f7_msg->count) {
 690                 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR);
 691                 f7_msg->count--;
 692         }
 693 }
 694
 695 static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev)
 696 {
 697         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 698         void __iomem *base = i2c_dev->base;
 699
 700         if (f7_msg->count) {
 701                 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR);
 702                 f7_msg->count--;
 703         } else {
 704                 /* Flush RX buffer has no data is expected */
 705                 readb_relaxed(base + STM32F7_I2C_RXDR);
 706         }
 707 }
 708
 709 static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev)
 710 {
 711         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 712         u32 cr2;
 713
 714         if (i2c_dev->use_dma)
 715                 f7_msg->count -= STM32F7_I2C_MAX_LEN;
 716
 717         cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
 718
 719         cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK;
 720         if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
 721                 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
 722         } else {
 723                 cr2 &= ~STM32F7_I2C_CR2_RELOAD;
 724                 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
 725         }
 726
 727         writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
 728 }
 729
 730 static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev)
 731 {
 732         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 733         u32 cr2;
 734         u8 *val;
 735
 736         /*
 737          * For I2C_SMBUS_BLOCK_DATA && I2C_SMBUS_BLOCK_PROC_CALL, the first
 738          * data received inform us how many data will follow.
 739          */
 740         stm32f7_i2c_read_rx_data(i2c_dev);
 741
 742         /*
 743          * Update NBYTES with the value read to continue the transfer
 744          */
 745         val = f7_msg->buf - sizeof(u8);
 746         f7_msg->count = *val;
 747         cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
 748         cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
 749         cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
 750         writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
 751 }
 752
 753 static int stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap)
 754 {
 755         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
 756
 757         dev_info(i2c_dev->dev, "Trying to recover bus\n");
 758
 759         stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
 760                              STM32F7_I2C_CR1_PE);
 761
 762         stm32f7_i2c_hw_config(i2c_dev);
 763
 764         return 0;
 765 }
 766
 767 static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev)
 768 {
 769         u32 status;
 770         int ret;
 771
 772         ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR,
 773                                          status,
 774                                          !(status & STM32F7_I2C_ISR_BUSY),
 775                                          10, 1000);
 776         if (!ret)
 777                 return 0;
 778
 779         dev_info(i2c_dev->dev, "bus busy\n");
 780
 781         ret = stm32f7_i2c_release_bus(&i2c_dev->adap);
 782         if (ret) {
 783                 dev_err(i2c_dev->dev, "Failed to recover the bus (%d)\n", ret);
 784                 return ret;
 785         }
 786
 787         return -EBUSY;
 788 }
 789
 790 static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
 791                                  struct i2c_msg *msg)
 792 {
 793         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 794         void __iomem *base = i2c_dev->base;
 795         u32 cr1, cr2;
 796         int ret;
 797
 798         f7_msg->addr = msg->addr;
 799         f7_msg->buf = msg->buf;
 800         f7_msg->count = msg->len;
 801         f7_msg->result = 0;
 802         f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1);
 803
 804         reinit_completion(&i2c_dev->complete);
 805
 806         cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
 807         cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
 808
 809         /* Set transfer direction */
 810         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 811         if (msg->flags & I2C_M_RD)
 812                 cr2 |= STM32F7_I2C_CR2_RD_WRN;
 813
 814         /* Set slave address */
 815         cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10);
 816         if (msg->flags & I2C_M_TEN) {
 817                 cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK;
 818                 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr);
 819                 cr2 |= STM32F7_I2C_CR2_ADD10;
 820         } else {
 821                 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK;
 822                 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
 823         }
 824
 825         /* Set nb bytes to transfer and reload if needed */
 826         cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
 827         if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
 828                 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
 829                 cr2 |= STM32F7_I2C_CR2_RELOAD;
 830         } else {
 831                 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
 832         }
 833
 834         /* Enable NACK, STOP, error and transfer complete interrupts */
 835         cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
 836                 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
 837
 838         /* Clear DMA req and TX/RX interrupt */
 839         cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
 840                         STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
 841
 842         /* Configure DMA or enable RX/TX interrupt */
 843         i2c_dev->use_dma = false;
 844         if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
 845                 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
 846                                               msg->flags & I2C_M_RD,
 847                                               f7_msg->count, f7_msg->buf,
 848                                               stm32f7_i2c_dma_callback,
 849                                               i2c_dev);
 850                 if (!ret)
 851                         i2c_dev->use_dma = true;
 852                 else
 853                         dev_warn(i2c_dev->dev, "can't use DMA\n");
 854         }
 855
 856         if (!i2c_dev->use_dma) {
 857                 if (msg->flags & I2C_M_RD)
 858                         cr1 |= STM32F7_I2C_CR1_RXIE;
 859                 else
 860                         cr1 |= STM32F7_I2C_CR1_TXIE;
 861         } else {
 862                 if (msg->flags & I2C_M_RD)
 863                         cr1 |= STM32F7_I2C_CR1_RXDMAEN;
 864                 else
 865                         cr1 |= STM32F7_I2C_CR1_TXDMAEN;
 866         }
 867
 868         /* Configure Start/Repeated Start */
 869         cr2 |= STM32F7_I2C_CR2_START;
 870
 871         i2c_dev->master_mode = true;
 872
 873         /* Write configurations registers */
 874         writel_relaxed(cr1, base + STM32F7_I2C_CR1);
 875         writel_relaxed(cr2, base + STM32F7_I2C_CR2);
 876 }
 877
 878 static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
 879                                       unsigned short flags, u8 command,
 880                                       union i2c_smbus_data *data)
 881 {
 882         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 883         struct device *dev = i2c_dev->dev;
 884         void __iomem *base = i2c_dev->base;
 885         u32 cr1, cr2;
 886         int i, ret;
 887
 888         f7_msg->result = 0;
 889         reinit_completion(&i2c_dev->complete);
 890
 891         cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
 892         cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
 893
 894         /* Set transfer direction */
 895         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 896         if (f7_msg->read_write)
 897                 cr2 |= STM32F7_I2C_CR2_RD_WRN;
 898
 899         /* Set slave address */
 900         cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK);
 901         cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
 902
 903         f7_msg->smbus_buf[0] = command;
 904         switch (f7_msg->size) {
 905         case I2C_SMBUS_QUICK:
 906                 f7_msg->stop = true;
 907                 f7_msg->count = 0;
 908                 break;
 909         case I2C_SMBUS_BYTE:
 910                 f7_msg->stop = true;
 911                 f7_msg->count = 1;
 912                 break;
 913         case I2C_SMBUS_BYTE_DATA:
 914                 if (f7_msg->read_write) {
 915                         f7_msg->stop = false;
 916                         f7_msg->count = 1;
 917                         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 918                 } else {
 919                         f7_msg->stop = true;
 920                         f7_msg->count = 2;
 921                         f7_msg->smbus_buf[1] = data->byte;
 922                 }
 923                 break;
 924         case I2C_SMBUS_WORD_DATA:
 925                 if (f7_msg->read_write) {
 926                         f7_msg->stop = false;
 927                         f7_msg->count = 1;
 928                         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 929                 } else {
 930                         f7_msg->stop = true;
 931                         f7_msg->count = 3;
 932                         f7_msg->smbus_buf[1] = data->word & 0xff;
 933                         f7_msg->smbus_buf[2] = data->word >> 8;
 934                 }
 935                 break;
 936         case I2C_SMBUS_BLOCK_DATA:
 937                 if (f7_msg->read_write) {
 938                         f7_msg->stop = false;
 939                         f7_msg->count = 1;
 940                         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 941                 } else {
 942                         f7_msg->stop = true;
 943                         if (data->block[0] > I2C_SMBUS_BLOCK_MAX ||
 944                             !data->block[0]) {
 945                                 dev_err(dev, "Invalid block write size %d\n",
 946                                         data->block[0]);
 947                                 return -EINVAL;
 948                         }
 949                         f7_msg->count = data->block[0] + 2;
 950                         for (i = 1; i < f7_msg->count; i++)
 951                                 f7_msg->smbus_buf[i] = data->block[i - 1];
 952                 }
 953                 break;
 954         case I2C_SMBUS_PROC_CALL:
 955                 f7_msg->stop = false;
 956                 f7_msg->count = 3;
 957                 f7_msg->smbus_buf[1] = data->word & 0xff;
 958                 f7_msg->smbus_buf[2] = data->word >> 8;
 959                 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 960                 f7_msg->read_write = I2C_SMBUS_READ;
 961                 break;
 962         case I2C_SMBUS_BLOCK_PROC_CALL:
 963                 f7_msg->stop = false;
 964                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) {
 965                         dev_err(dev, "Invalid block write size %d\n",
 966                                 data->block[0]);
 967                         return -EINVAL;
 968                 }
 969                 f7_msg->count = data->block[0] + 2;
 970                 for (i = 1; i < f7_msg->count; i++)
 971                         f7_msg->smbus_buf[i] = data->block[i - 1];
 972                 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 973                 f7_msg->read_write = I2C_SMBUS_READ;
 974                 break;
 975         case I2C_SMBUS_I2C_BLOCK_DATA:
 976                 /* Rely on emulated i2c transfer (through master_xfer) */
 977                 return -EOPNOTSUPP;
 978         default:
 979                 dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size);
 980                 return -EOPNOTSUPP;
 981         }
 982
 983         f7_msg->buf = f7_msg->smbus_buf;
 984
 985         /* Configure PEC */
 986         if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) {
 987                 cr1 |= STM32F7_I2C_CR1_PECEN;
 988                 cr2 |= STM32F7_I2C_CR2_PECBYTE;
 989                 if (!f7_msg->read_write)
 990                         f7_msg->count++;
 991         } else {
 992                 cr1 &= ~STM32F7_I2C_CR1_PECEN;
 993                 cr2 &= ~STM32F7_I2C_CR2_PECBYTE;
 994         }
 995
 996         /* Set number of bytes to be transferred */
 997         cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
 998         cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
 999
1000         /* Enable NACK, STOP, error and transfer complete interrupts */
1001         cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
1002                 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
1003
1004         /* Clear DMA req and TX/RX interrupt */
1005         cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1006                         STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1007
1008         /* Configure DMA or enable RX/TX interrupt */
1009         i2c_dev->use_dma = false;
1010         if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
1011                 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1012                                               cr2 & STM32F7_I2C_CR2_RD_WRN,
1013                                               f7_msg->count, f7_msg->buf,
1014                                               stm32f7_i2c_dma_callback,
1015                                               i2c_dev);
1016                 if (!ret)
1017                         i2c_dev->use_dma = true;
1018                 else
1019                         dev_warn(i2c_dev->dev, "can't use DMA\n");
1020         }
1021
1022         if (!i2c_dev->use_dma) {
1023                 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1024                         cr1 |= STM32F7_I2C_CR1_RXIE;
1025                 else
1026                         cr1 |= STM32F7_I2C_CR1_TXIE;
1027         } else {
1028                 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1029                         cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1030                 else
1031                         cr1 |= STM32F7_I2C_CR1_TXDMAEN;
1032         }
1033
1034         /* Set Start bit */
1035         cr2 |= STM32F7_I2C_CR2_START;
1036
1037         i2c_dev->master_mode = true;
1038
1039         /* Write configurations registers */
1040         writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1041         writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1042
1043         return 0;
1044 }
1045
1046 static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev)
1047 {
1048         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1049         void __iomem *base = i2c_dev->base;
1050         u32 cr1, cr2;
1051         int ret;
1052
1053         cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
1054         cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
1055
1056         /* Set transfer direction */
1057         cr2 |= STM32F7_I2C_CR2_RD_WRN;
1058
1059         switch (f7_msg->size) {
1060         case I2C_SMBUS_BYTE_DATA:
1061                 f7_msg->count = 1;
1062                 break;
1063         case I2C_SMBUS_WORD_DATA:
1064         case I2C_SMBUS_PROC_CALL:
1065                 f7_msg->count = 2;
1066                 break;
1067         case I2C_SMBUS_BLOCK_DATA:
1068         case I2C_SMBUS_BLOCK_PROC_CALL:
1069                 f7_msg->count = 1;
1070                 cr2 |= STM32F7_I2C_CR2_RELOAD;
1071                 break;
1072         }
1073
1074         f7_msg->buf = f7_msg->smbus_buf;
1075         f7_msg->stop = true;
1076
1077         /* Add one byte for PEC if needed */
1078         if (cr1 & STM32F7_I2C_CR1_PECEN)
1079                 f7_msg->count++;
1080
1081         /* Set number of bytes to be transferred */
1082         cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK);
1083         cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1084
1085         /*
1086          * Configure RX/TX interrupt:
1087          */
1088         cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE);
1089         cr1 |= STM32F7_I2C_CR1_RXIE;
1090
1091         /*
1092          * Configure DMA or enable RX/TX interrupt:
1093          * For I2C_SMBUS_BLOCK_DATA and I2C_SMBUS_BLOCK_PROC_CALL we don't use
1094          * dma as we don't know in advance how many data will be received
1095          */
1096         cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1097                  STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1098
1099         i2c_dev->use_dma = false;
1100         if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN &&
1101             f7_msg->size != I2C_SMBUS_BLOCK_DATA &&
1102             f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) {
1103                 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1104                                               cr2 & STM32F7_I2C_CR2_RD_WRN,
1105                                               f7_msg->count, f7_msg->buf,
1106                                               stm32f7_i2c_dma_callback,
1107                                               i2c_dev);
1108
1109                 if (!ret)
1110                         i2c_dev->use_dma = true;
1111                 else
1112                         dev_warn(i2c_dev->dev, "can't use DMA\n");
1113         }
1114
1115         if (!i2c_dev->use_dma)
1116                 cr1 |= STM32F7_I2C_CR1_RXIE;
1117         else
1118                 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1119
1120         /* Configure Repeated Start */
1121         cr2 |= STM32F7_I2C_CR2_START;
1122
1123         /* Write configurations registers */
1124         writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1125         writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1126 }
1127
1128 static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev)
1129 {
1130         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1131         u8 count, internal_pec, received_pec;
1132
1133         internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR);
1134
1135         switch (f7_msg->size) {
1136         case I2C_SMBUS_BYTE:
1137         case I2C_SMBUS_BYTE_DATA:
1138                 received_pec = f7_msg->smbus_buf[1];
1139                 break;
1140         case I2C_SMBUS_WORD_DATA:
1141         case I2C_SMBUS_PROC_CALL:
1142                 received_pec = f7_msg->smbus_buf[2];
1143                 break;
1144         case I2C_SMBUS_BLOCK_DATA:
1145         case I2C_SMBUS_BLOCK_PROC_CALL:
1146                 count = f7_msg->smbus_buf[0];
1147                 received_pec = f7_msg->smbus_buf[count];
1148                 break;
1149         default:
1150                 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n");
1151                 return -EINVAL;
1152         }
1153
1154         if (internal_pec != received_pec) {
1155                 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n",
1156                         internal_pec, received_pec);
1157                 return -EBADMSG;
1158         }
1159
1160         return 0;
1161 }
1162
1163 static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode)
1164 {
1165         u32 addr;
1166
1167         if (!slave)
1168                 return false;
1169
1170         if (slave->flags & I2C_CLIENT_TEN) {
1171                 /*
1172                  * For 10-bit addr, addcode = 11110XY with
1173                  * X = Bit 9 of slave address
1174                  * Y = Bit 8 of slave address
1175                  */
1176                 addr = slave->addr >> 8;
1177                 addr |= 0x78;
1178                 if (addr == addcode)
1179                         return true;
1180         } else {
1181                 addr = slave->addr & 0x7f;
1182                 if (addr == addcode)
1183                         return true;
1184         }
1185
1186         return false;
1187 }
1188
1189 static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev)
1190 {
1191         struct i2c_client *slave = i2c_dev->slave_running;
1192         void __iomem *base = i2c_dev->base;
1193         u32 mask;
1194         u8 value = 0;
1195
1196         if (i2c_dev->slave_dir) {
1197                 /* Notify i2c slave that new read transfer is starting */
1198                 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
1199
1200                 /*
1201                  * Disable slave TX config in case of I2C combined message
1202                  * (I2C Write followed by I2C Read)
1203                  */
1204                 mask = STM32F7_I2C_CR2_RELOAD;
1205                 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask);
1206                 mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1207                        STM32F7_I2C_CR1_TCIE;
1208                 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1209
1210                 /* Enable TX empty, STOP, NACK interrupts */
1211                 mask =  STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1212                         STM32F7_I2C_CR1_TXIE;
1213                 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1214
1215                 /* Write 1st data byte */
1216                 writel_relaxed(value, base + STM32F7_I2C_TXDR);
1217         } else {
1218                 /* Notify i2c slave that new write transfer is starting */
1219                 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
1220
1221                 /* Set reload mode to be able to ACK/NACK each received byte */
1222                 mask = STM32F7_I2C_CR2_RELOAD;
1223                 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1224
1225                 /*
1226                  * Set STOP, NACK, RX empty and transfer complete interrupts.*
1227                  * Set Slave Byte Control to be able to ACK/NACK each data
1228                  * byte received
1229                  */
1230                 mask =  STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1231                         STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1232                         STM32F7_I2C_CR1_TCIE;
1233                 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1234         }
1235 }
1236
1237 static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev)
1238 {
1239         void __iomem *base = i2c_dev->base;
1240         u32 isr, addcode, dir, mask;
1241         int i;
1242
1243         isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1244         addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr);
1245         dir = isr & STM32F7_I2C_ISR_DIR;
1246
1247         for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1248                 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) {
1249                         i2c_dev->slave_running = i2c_dev->slave[i];
1250                         i2c_dev->slave_dir = dir;
1251
1252                         /* Start I2C slave processing */
1253                         stm32f7_i2c_slave_start(i2c_dev);
1254
1255                         /* Clear ADDR flag */
1256                         mask = STM32F7_I2C_ICR_ADDRCF;
1257                         writel_relaxed(mask, base + STM32F7_I2C_ICR);
1258                         break;
1259                 }
1260         }
1261 }
1262
1263 static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1264                                     struct i2c_client *slave, int *id)
1265 {
1266         int i;
1267
1268         for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1269                 if (i2c_dev->slave[i] == slave) {
1270                         *id = i;
1271                         return 0;
1272                 }
1273         }
1274
1275         dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr);
1276
1277         return -ENODEV;
1278 }
1279
1280 static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1281                                          struct i2c_client *slave, int *id)
1282 {
1283         struct device *dev = i2c_dev->dev;
1284         int i;
1285
1286         /*
1287          * slave[0] supports 7-bit and 10-bit slave address
1288          * slave[1] supports 7-bit slave address only
1289          */
1290         for (i = STM32F7_I2C_MAX_SLAVE - 1; i >= 0; i--) {
1291                 if (i == 1 && (slave->flags & I2C_CLIENT_TEN))
1292                         continue;
1293                 if (!i2c_dev->slave[i]) {
1294                         *id = i;
1295                         return 0;
1296                 }
1297         }
1298
1299         dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr);
1300
1301         return -EINVAL;
1302 }
1303
1304 static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev)
1305 {
1306         int i;
1307
1308         for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1309                 if (i2c_dev->slave[i])
1310                         return true;
1311         }
1312
1313         return false;
1314 }
1315
1316 static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev)
1317 {
1318         int i, busy;
1319
1320         busy = 0;
1321         for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1322                 if (i2c_dev->slave[i])
1323                         busy++;
1324         }
1325
1326         return i == busy;
1327 }
1328
1329 static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev)
1330 {
1331         void __iomem *base = i2c_dev->base;
1332         u32 cr2, status, mask;
1333         u8 val;
1334         int ret;
1335
1336         status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1337
1338         /* Slave transmitter mode */
1339         if (status & STM32F7_I2C_ISR_TXIS) {
1340                 i2c_slave_event(i2c_dev->slave_running,
1341                                 I2C_SLAVE_READ_PROCESSED,
1342                                 &val);
1343
1344                 /* Write data byte */
1345                 writel_relaxed(val, base + STM32F7_I2C_TXDR);
1346         }
1347
1348         /* Transfer Complete Reload for Slave receiver mode */
1349         if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) {
1350                 /*
1351                  * Read data byte then set NBYTES to receive next byte or NACK
1352                  * the current received byte
1353                  */
1354                 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR);
1355                 ret = i2c_slave_event(i2c_dev->slave_running,
1356                                       I2C_SLAVE_WRITE_RECEIVED,
1357                                       &val);
1358                 if (!ret) {
1359                         cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
1360                         cr2 |= STM32F7_I2C_CR2_NBYTES(1);
1361                         writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
1362                 } else {
1363                         mask = STM32F7_I2C_CR2_NACK;
1364                         stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1365                 }
1366         }
1367
1368         /* NACK received */
1369         if (status & STM32F7_I2C_ISR_NACKF) {
1370                 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1371                 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1372         }
1373
1374         /* STOP received */
1375         if (status & STM32F7_I2C_ISR_STOPF) {
1376                 /* Disable interrupts */
1377                 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK);
1378
1379                 if (i2c_dev->slave_dir) {
1380                         /*
1381                          * Flush TX buffer in order to not used the byte in
1382                          * TXDR for the next transfer
1383                          */
1384                         mask = STM32F7_I2C_ISR_TXE;
1385                         stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask);
1386                 }
1387
1388                 /* Clear STOP flag */
1389                 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1390
1391                 /* Notify i2c slave that a STOP flag has been detected */
1392                 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val);
1393
1394                 i2c_dev->slave_running = NULL;
1395         }
1396
1397         /* Address match received */
1398         if (status & STM32F7_I2C_ISR_ADDR)
1399                 stm32f7_i2c_slave_addr(i2c_dev);
1400
1401         return IRQ_HANDLED;
1402 }
1403
1404 static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
1405 {
1406         struct stm32f7_i2c_dev *i2c_dev = data;
1407         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1408         void __iomem *base = i2c_dev->base;
1409         u32 status, mask;
1410         int ret = IRQ_HANDLED;
1411
1412         /* Check if the interrupt if for a slave device */
1413         if (!i2c_dev->master_mode) {
1414                 ret = stm32f7_i2c_slave_isr_event(i2c_dev);
1415                 return ret;
1416         }
1417
1418         status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1419
1420         /* Tx empty */
1421         if (status & STM32F7_I2C_ISR_TXIS)
1422                 stm32f7_i2c_write_tx_data(i2c_dev);
1423
1424         /* RX not empty */
1425         if (status & STM32F7_I2C_ISR_RXNE)
1426                 stm32f7_i2c_read_rx_data(i2c_dev);
1427
1428         /* NACK received */
1429         if (status & STM32F7_I2C_ISR_NACKF) {
1430                 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1431                 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1432                 f7_msg->result = -ENXIO;
1433         }
1434
1435         /* STOP detection flag */
1436         if (status & STM32F7_I2C_ISR_STOPF) {
1437                 /* Disable interrupts */
1438                 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1439                         mask = STM32F7_I2C_XFER_IRQ_MASK;
1440                 else
1441                         mask = STM32F7_I2C_ALL_IRQ_MASK;
1442                 stm32f7_i2c_disable_irq(i2c_dev, mask);
1443
1444                 /* Clear STOP flag */
1445                 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1446
1447                 if (i2c_dev->use_dma) {
1448                         ret = IRQ_WAKE_THREAD;
1449                 } else {
1450                         i2c_dev->master_mode = false;
1451                         complete(&i2c_dev->complete);
1452                 }
1453         }
1454
1455         /* Transfer complete */
1456         if (status & STM32F7_I2C_ISR_TC) {
1457                 if (f7_msg->stop) {
1458                         mask = STM32F7_I2C_CR2_STOP;
1459                         stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1460                 } else if (i2c_dev->use_dma) {
1461                         ret = IRQ_WAKE_THREAD;
1462                 } else if (f7_msg->smbus) {
1463                         stm32f7_i2c_smbus_rep_start(i2c_dev);
1464                 } else {
1465                         i2c_dev->msg_id++;
1466                         i2c_dev->msg++;
1467                         stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1468                 }
1469         }
1470
1471         if (status & STM32F7_I2C_ISR_TCR) {
1472                 if (f7_msg->smbus)
1473                         stm32f7_i2c_smbus_reload(i2c_dev);
1474                 else
1475                         stm32f7_i2c_reload(i2c_dev);
1476         }
1477
1478         return ret;
1479 }
1480
1481 static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data)
1482 {
1483         struct stm32f7_i2c_dev *i2c_dev = data;
1484         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1485         struct stm32_i2c_dma *dma = i2c_dev->dma;
1486         u32 status;
1487         int ret;
1488
1489         /*
1490          * Wait for dma transfer completion before sending next message or
1491          * notity the end of xfer to the client
1492          */
1493         ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ);
1494         if (!ret) {
1495                 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__);
1496                 stm32f7_i2c_disable_dma_req(i2c_dev);
1497                 dmaengine_terminate_all(dma->chan_using);
1498                 f7_msg->result = -ETIMEDOUT;
1499         }
1500
1501         status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1502
1503         if (status & STM32F7_I2C_ISR_TC) {
1504                 if (f7_msg->smbus) {
1505                         stm32f7_i2c_smbus_rep_start(i2c_dev);
1506                 } else {
1507                         i2c_dev->msg_id++;
1508                         i2c_dev->msg++;
1509                         stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1510                 }
1511         } else {
1512                 i2c_dev->master_mode = false;
1513                 complete(&i2c_dev->complete);
1514         }
1515
1516         return IRQ_HANDLED;
1517 }
1518
1519 static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data)
1520 {
1521         struct stm32f7_i2c_dev *i2c_dev = data;
1522         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1523         void __iomem *base = i2c_dev->base;
1524         struct device *dev = i2c_dev->dev;
1525         struct stm32_i2c_dma *dma = i2c_dev->dma;
1526         u32 status;
1527
1528         status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1529
1530         /* Bus error */
1531         if (status & STM32F7_I2C_ISR_BERR) {
1532                 dev_err(dev, "<%s>: Bus error\n", __func__);
1533                 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR);
1534                 stm32f7_i2c_release_bus(&i2c_dev->adap);
1535                 f7_msg->result = -EIO;
1536         }
1537
1538         /* Arbitration loss */
1539         if (status & STM32F7_I2C_ISR_ARLO) {
1540                 dev_dbg(dev, "<%s>: Arbitration loss\n", __func__);
1541                 writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR);
1542                 f7_msg->result = -EAGAIN;
1543         }
1544
1545         if (status & STM32F7_I2C_ISR_PECERR) {
1546                 dev_err(dev, "<%s>: PEC error in reception\n", __func__);
1547                 writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR);
1548                 f7_msg->result = -EINVAL;
1549         }
1550
1551         if (!i2c_dev->slave_running) {
1552                 u32 mask;
1553                 /* Disable interrupts */
1554                 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1555                         mask = STM32F7_I2C_XFER_IRQ_MASK;
1556                 else
1557                         mask = STM32F7_I2C_ALL_IRQ_MASK;
1558                 stm32f7_i2c_disable_irq(i2c_dev, mask);
1559         }
1560
1561         /* Disable dma */
1562         if (i2c_dev->use_dma) {
1563                 stm32f7_i2c_disable_dma_req(i2c_dev);
1564                 dmaengine_terminate_all(dma->chan_using);
1565         }
1566
1567         i2c_dev->master_mode = false;
1568         complete(&i2c_dev->complete);
1569
1570         return IRQ_HANDLED;
1571 }
1572
1573 static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap,
1574                             struct i2c_msg msgs[], int num)
1575 {
1576         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
1577         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1578         struct stm32_i2c_dma *dma = i2c_dev->dma;
1579         unsigned long time_left;
1580         int ret;
1581
1582         i2c_dev->msg = msgs;
1583         i2c_dev->msg_num = num;
1584         i2c_dev->msg_id = 0;
1585         f7_msg->smbus = false;
1586
1587         ret = pm_runtime_get_sync(i2c_dev->dev);
1588         if (ret < 0)
1589                 return ret;
1590
1591         ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1592         if (ret)
1593                 goto pm_free;
1594
1595         stm32f7_i2c_xfer_msg(i2c_dev, msgs);
1596
1597         time_left = wait_for_completion_timeout(&i2c_dev->complete,
1598                                                 i2c_dev->adap.timeout);
1599         ret = f7_msg->result;
1600
1601         if (!time_left) {
1602                 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n",
1603                         i2c_dev->msg->addr);
1604                 if (i2c_dev->use_dma)
1605                         dmaengine_terminate_all(dma->chan_using);
1606                 ret = -ETIMEDOUT;
1607         }
1608
1609 pm_free:
1610         pm_runtime_mark_last_busy(i2c_dev->dev);
1611         pm_runtime_put_autosuspend(i2c_dev->dev);
1612
1613         return (ret < 0) ? ret : num;
1614 }
1615
1616 static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
1617                                   unsigned short flags, char read_write,
1618                                   u8 command, int size,
1619                                   union i2c_smbus_data *data)
1620 {
1621         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter);
1622         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1623         struct stm32_i2c_dma *dma = i2c_dev->dma;
1624         struct device *dev = i2c_dev->dev;
1625         unsigned long timeout;
1626         int i, ret;
1627
1628         f7_msg->addr = addr;
1629         f7_msg->size = size;
1630         f7_msg->read_write = read_write;
1631         f7_msg->smbus = true;
1632
1633         ret = pm_runtime_get_sync(dev);
1634         if (ret < 0)
1635                 return ret;
1636
1637         ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1638         if (ret)
1639                 goto pm_free;
1640
1641         ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data);
1642         if (ret)
1643                 goto pm_free;
1644
1645         timeout = wait_for_completion_timeout(&i2c_dev->complete,
1646                                               i2c_dev->adap.timeout);
1647         ret = f7_msg->result;
1648         if (ret)
1649                 goto pm_free;
1650
1651         if (!timeout) {
1652                 dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr);
1653                 if (i2c_dev->use_dma)
1654                         dmaengine_terminate_all(dma->chan_using);
1655                 ret = -ETIMEDOUT;
1656                 goto pm_free;
1657         }
1658
1659         /* Check PEC */
1660         if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) {
1661                 ret = stm32f7_i2c_smbus_check_pec(i2c_dev);
1662                 if (ret)
1663                         goto pm_free;
1664         }
1665
1666         if (read_write && size != I2C_SMBUS_QUICK) {
1667                 switch (size) {
1668                 case I2C_SMBUS_BYTE:
1669                 case I2C_SMBUS_BYTE_DATA:
1670                         data->byte = f7_msg->smbus_buf[0];
1671                 break;
1672                 case I2C_SMBUS_WORD_DATA:
1673                 case I2C_SMBUS_PROC_CALL:
1674                         data->word = f7_msg->smbus_buf[0] |
1675                                 (f7_msg->smbus_buf[1] << 8);
1676                 break;
1677                 case I2C_SMBUS_BLOCK_DATA:
1678                 case I2C_SMBUS_BLOCK_PROC_CALL:
1679                 for (i = 0; i <= f7_msg->smbus_buf[0]; i++)
1680                         data->block[i] = f7_msg->smbus_buf[i];
1681                 break;
1682                 default:
1683                         dev_err(dev, "Unsupported smbus transaction\n");
1684                         ret = -EINVAL;
1685                 }
1686         }
1687
1688 pm_free:
1689         pm_runtime_mark_last_busy(dev);
1690         pm_runtime_put_autosuspend(dev);
1691         return ret;
1692 }
1693
1694 static int stm32f7_i2c_reg_slave(struct i2c_client *slave)
1695 {
1696         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1697         void __iomem *base = i2c_dev->base;
1698         struct device *dev = i2c_dev->dev;
1699         u32 oar1, oar2, mask;
1700         int id, ret;
1701
1702         if (slave->flags & I2C_CLIENT_PEC) {
1703                 dev_err(dev, "SMBus PEC not supported in slave mode\n");
1704                 return -EINVAL;
1705         }
1706
1707         if (stm32f7_i2c_is_slave_busy(i2c_dev)) {
1708                 dev_err(dev, "Too much slave registered\n");
1709                 return -EBUSY;
1710         }
1711
1712         ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id);
1713         if (ret)
1714                 return ret;
1715
1716         ret = pm_runtime_get_sync(dev);
1717         if (ret < 0)
1718                 return ret;
1719
1720         if (id == 0) {
1721                 /* Configure Own Address 1 */
1722                 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
1723                 oar1 &= ~STM32F7_I2C_OAR1_MASK;
1724                 if (slave->flags & I2C_CLIENT_TEN) {
1725                         oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr);
1726                         oar1 |= STM32F7_I2C_OAR1_OA1MODE;
1727                 } else {
1728                         oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr);
1729                 }
1730                 oar1 |= STM32F7_I2C_OAR1_OA1EN;
1731                 i2c_dev->slave[id] = slave;
1732                 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1);
1733         } else if (id == 1) {
1734                 /* Configure Own Address 2 */
1735                 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
1736                 oar2 &= ~STM32F7_I2C_OAR2_MASK;
1737                 if (slave->flags & I2C_CLIENT_TEN) {
1738                         ret = -EOPNOTSUPP;
1739                         goto pm_free;
1740                 }
1741
1742                 oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr);
1743                 oar2 |= STM32F7_I2C_OAR2_OA2EN;
1744                 i2c_dev->slave[id] = slave;
1745                 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2);
1746         } else {
1747                 ret = -ENODEV;
1748                 goto pm_free;
1749         }
1750
1751         /* Enable ACK */
1752         stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK);
1753
1754         /* Enable Address match interrupt, error interrupt and enable I2C  */
1755         mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE |
1756                 STM32F7_I2C_CR1_PE;
1757         stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1758
1759         ret = 0;
1760 pm_free:
1761         pm_runtime_mark_last_busy(dev);
1762         pm_runtime_put_autosuspend(dev);
1763
1764         return ret;
1765 }
1766
1767 static int stm32f7_i2c_unreg_slave(struct i2c_client *slave)
1768 {
1769         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1770         void __iomem *base = i2c_dev->base;
1771         u32 mask;
1772         int id, ret;
1773
1774         ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id);
1775         if (ret)
1776                 return ret;
1777
1778         WARN_ON(!i2c_dev->slave[id]);
1779
1780         ret = pm_runtime_get_sync(i2c_dev->dev);
1781         if (ret < 0)
1782                 return ret;
1783
1784         if (id == 0) {
1785                 mask = STM32F7_I2C_OAR1_OA1EN;
1786                 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask);
1787         } else {
1788                 mask = STM32F7_I2C_OAR2_OA2EN;
1789                 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask);
1790         }
1791
1792         i2c_dev->slave[id] = NULL;
1793
1794         if (!(stm32f7_i2c_is_slave_registered(i2c_dev)))
1795                 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
1796
1797         pm_runtime_mark_last_busy(i2c_dev->dev);
1798         pm_runtime_put_autosuspend(i2c_dev->dev);
1799
1800         return 0;
1801 }
1802
1803 static int stm32f7_i2c_setup_fm_plus_bits(struct platform_device *pdev,
1804                                           struct stm32f7_i2c_dev *i2c_dev)
1805 {
1806         struct device_node *np = pdev->dev.of_node;
1807         int ret;
1808         u32 reg, mask;
1809
1810         i2c_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg-fmp");
1811         if (IS_ERR(i2c_dev->regmap)) {
1812                 /* Optional */
1813                 return 0;
1814         }
1815
1816         ret = of_property_read_u32_index(np, "st,syscfg-fmp", 1, &reg);
1817         if (ret)
1818                 return ret;
1819
1820         ret = of_property_read_u32_index(np, "st,syscfg-fmp", 2, &mask);
1821         if (ret)
1822                 return ret;
1823
1824         return regmap_update_bits(i2c_dev->regmap, reg, mask, mask);
1825 }
1826
1827 static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
1828 {
1829         return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE |
1830                 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
1831                 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
1832                 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
1833                 I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC |
1834                 I2C_FUNC_SMBUS_I2C_BLOCK;
1835 }
1836
1837 static const struct i2c_algorithm stm32f7_i2c_algo = {
1838         .master_xfer = stm32f7_i2c_xfer,
1839         .smbus_xfer = stm32f7_i2c_smbus_xfer,
1840         .functionality = stm32f7_i2c_func,
1841         .reg_slave = stm32f7_i2c_reg_slave,
1842         .unreg_slave = stm32f7_i2c_unreg_slave,
1843 };
1844
1845 static int stm32f7_i2c_probe(struct platform_device *pdev)
1846 {
1847         struct stm32f7_i2c_dev *i2c_dev;
1848         const struct stm32f7_i2c_setup *setup;
1849         struct resource *res;
1850         u32 clk_rate, rise_time, fall_time;
1851         struct i2c_adapter *adap;
1852         struct reset_control *rst;
1853         dma_addr_t phy_addr;
1854         int irq_error, irq_event, ret;
1855
1856         i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
1857         if (!i2c_dev)
1858                 return -ENOMEM;
1859
1860         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1861         i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
1862         if (IS_ERR(i2c_dev->base))
1863                 return PTR_ERR(i2c_dev->base);
1864         phy_addr = (dma_addr_t)res->start;
1865
1866         irq_event = platform_get_irq(pdev, 0);
1867         if (irq_event <= 0) {
1868                 if (irq_event != -EPROBE_DEFER)
1869                         dev_err(&pdev->dev, "Failed to get IRQ event: %d\n",
1870                                 irq_event);
1871                 return irq_event ? : -ENOENT;
1872         }
1873
1874         irq_error = platform_get_irq(pdev, 1);
1875         if (irq_error <= 0) {
1876                 if (irq_error != -EPROBE_DEFER)
1877                         dev_err(&pdev->dev, "Failed to get IRQ error: %d\n",
1878                                 irq_error);
1879                 return irq_error ? : -ENOENT;
1880         }
1881
1882         i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
1883         if (IS_ERR(i2c_dev->clk)) {
1884                 dev_err(&pdev->dev, "Error: Missing controller clock\n");
1885                 return PTR_ERR(i2c_dev->clk);
1886         }
1887
1888         ret = clk_prepare_enable(i2c_dev->clk);
1889         if (ret) {
1890                 dev_err(&pdev->dev, "Failed to prepare_enable clock\n");
1891                 return ret;
1892         }
1893
1894         i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
1895         ret = device_property_read_u32(&pdev->dev, "clock-frequency",
1896                                        &clk_rate);
1897         if (!ret && clk_rate >= 1000000) {
1898                 i2c_dev->speed = STM32_I2C_SPEED_FAST_PLUS;
1899                 ret = stm32f7_i2c_setup_fm_plus_bits(pdev, i2c_dev);
1900                 if (ret)
1901                         goto clk_free;
1902         } else if (!ret && clk_rate >= 400000) {
1903                 i2c_dev->speed = STM32_I2C_SPEED_FAST;
1904         } else if (!ret && clk_rate >= 100000) {
1905                 i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
1906         }
1907
1908         rst = devm_reset_control_get(&pdev->dev, NULL);
1909         if (IS_ERR(rst)) {
1910                 dev_err(&pdev->dev, "Error: Missing controller reset\n");
1911                 ret = PTR_ERR(rst);
1912                 goto clk_free;
1913         }
1914         reset_control_assert(rst);
1915         udelay(2);
1916         reset_control_deassert(rst);
1917
1918         i2c_dev->dev = &pdev->dev;
1919
1920         ret = devm_request_threaded_irq(&pdev->dev, irq_event,
1921                                         stm32f7_i2c_isr_event,
1922                                         stm32f7_i2c_isr_event_thread,
1923                                         IRQF_ONESHOT,
1924                                         pdev->name, i2c_dev);
1925         if (ret) {
1926                 dev_err(&pdev->dev, "Failed to request irq event %i\n",
1927                         irq_event);
1928                 goto clk_free;
1929         }
1930
1931         ret = devm_request_irq(&pdev->dev, irq_error, stm32f7_i2c_isr_error, 0,
1932                                pdev->name, i2c_dev);
1933         if (ret) {
1934                 dev_err(&pdev->dev, "Failed to request irq error %i\n",
1935                         irq_error);
1936                 goto clk_free;
1937         }
1938
1939         setup = of_device_get_match_data(&pdev->dev);
1940         if (!setup) {
1941                 dev_err(&pdev->dev, "Can't get device data\n");
1942                 ret = -ENODEV;
1943                 goto clk_free;
1944         }
1945         i2c_dev->setup = *setup;
1946
1947         ret = device_property_read_u32(i2c_dev->dev, "i2c-scl-rising-time-ns",
1948                                        &rise_time);
1949         if (!ret)
1950                 i2c_dev->setup.rise_time = rise_time;
1951
1952         ret = device_property_read_u32(i2c_dev->dev, "i2c-scl-falling-time-ns",
1953                                        &fall_time);
1954         if (!ret)
1955                 i2c_dev->setup.fall_time = fall_time;
1956
1957         ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup);
1958         if (ret)
1959                 goto clk_free;
1960
1961         adap = &i2c_dev->adap;
1962         i2c_set_adapdata(adap, i2c_dev);
1963         snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)",
1964                  &res->start);
1965         adap->owner = THIS_MODULE;
1966         adap->timeout = 2 * HZ;
1967         adap->retries = 3;
1968         adap->algo = &stm32f7_i2c_algo;
1969         adap->dev.parent = &pdev->dev;
1970         adap->dev.of_node = pdev->dev.of_node;
1971
1972         init_completion(&i2c_dev->complete);
1973
1974         /* Init DMA config if supported */
1975         i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr,
1976                                              STM32F7_I2C_TXDR,
1977                                              STM32F7_I2C_RXDR);
1978         if (PTR_ERR(i2c_dev->dma) == -ENODEV)
1979                 i2c_dev->dma = NULL;
1980         else if (IS_ERR(i2c_dev->dma)) {
1981                 ret = PTR_ERR(i2c_dev->dma);
1982                 if (ret != -EPROBE_DEFER)
1983                         dev_err(&pdev->dev,
1984                                 "Failed to request dma error %i\n", ret);
1985                 goto clk_free;
1986         }
1987
1988         platform_set_drvdata(pdev, i2c_dev);
1989
1990         pm_runtime_set_autosuspend_delay(i2c_dev->dev,
1991                                          STM32F7_AUTOSUSPEND_DELAY);
1992         pm_runtime_use_autosuspend(i2c_dev->dev);
1993         pm_runtime_set_active(i2c_dev->dev);
1994         pm_runtime_enable(i2c_dev->dev);
1995
1996         pm_runtime_get_noresume(&pdev->dev);
1997
1998         stm32f7_i2c_hw_config(i2c_dev);
1999
2000         ret = i2c_add_adapter(adap);
2001         if (ret)
2002                 goto pm_disable;
2003
2004         dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr);
2005
2006         pm_runtime_mark_last_busy(i2c_dev->dev);
2007         pm_runtime_put_autosuspend(i2c_dev->dev);
2008
2009         return 0;
2010
2011 pm_disable:
2012         pm_runtime_put_noidle(i2c_dev->dev);
2013         pm_runtime_disable(i2c_dev->dev);
2014         pm_runtime_set_suspended(i2c_dev->dev);
2015         pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2016
2017         if (i2c_dev->dma) {
2018                 stm32_i2c_dma_free(i2c_dev->dma);
2019                 i2c_dev->dma = NULL;
2020         }
2021
2022 clk_free:
2023         clk_disable_unprepare(i2c_dev->clk);
2024
2025         return ret;
2026 }
2027
2028 static int stm32f7_i2c_remove(struct platform_device *pdev)
2029 {
2030         struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
2031
2032         i2c_del_adapter(&i2c_dev->adap);
2033         pm_runtime_get_sync(i2c_dev->dev);
2034
2035         pm_runtime_put_noidle(i2c_dev->dev);
2036         pm_runtime_disable(i2c_dev->dev);
2037         pm_runtime_set_suspended(i2c_dev->dev);
2038         pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2039
2040         if (i2c_dev->dma) {
2041                 stm32_i2c_dma_free(i2c_dev->dma);
2042                 i2c_dev->dma = NULL;
2043         }
2044
2045         clk_disable_unprepare(i2c_dev->clk);
2046
2047         return 0;
2048 }
2049
2050 static int __maybe_unused stm32f7_i2c_runtime_suspend(struct device *dev)
2051 {
2052         struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2053
2054         if (!stm32f7_i2c_is_slave_registered(i2c_dev))
2055                 clk_disable_unprepare(i2c_dev->clk);
2056
2057         return 0;
2058 }
2059
2060 static int __maybe_unused stm32f7_i2c_runtime_resume(struct device *dev)
2061 {
2062         struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2063         int ret;
2064
2065         if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
2066                 ret = clk_prepare_enable(i2c_dev->clk);
2067                 if (ret) {
2068                         dev_err(dev, "failed to prepare_enable clock\n");
2069                         return ret;
2070                 }
2071         }
2072
2073         return 0;
2074 }
2075
2076 static int __maybe_unused
2077 stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev *i2c_dev)
2078 {
2079         int ret;
2080         struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2081
2082         ret = pm_runtime_get_sync(i2c_dev->dev);
2083         if (ret < 0)
2084                 return ret;
2085
2086         backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2087         backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
2088         backup_regs->oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
2089         backup_regs->oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
2090         backup_regs->pecr = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR);
2091         backup_regs->tmgr = readl_relaxed(i2c_dev->base + STM32F7_I2C_TIMINGR);
2092
2093         pm_runtime_put_sync(i2c_dev->dev);
2094
2095         return ret;
2096 }
2097
2098 static int __maybe_unused
2099 stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev *i2c_dev)
2100 {
2101         u32 cr1;
2102         int ret;
2103         struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2104
2105         ret = pm_runtime_get_sync(i2c_dev->dev);
2106         if (ret < 0)
2107                 return ret;
2108
2109         cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2110         if (cr1 & STM32F7_I2C_CR1_PE)
2111                 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
2112                                      STM32F7_I2C_CR1_PE);
2113
2114         writel_relaxed(backup_regs->tmgr, i2c_dev->base + STM32F7_I2C_TIMINGR);
2115         writel_relaxed(backup_regs->cr1 & ~STM32F7_I2C_CR1_PE,
2116                        i2c_dev->base + STM32F7_I2C_CR1);
2117         if (backup_regs->cr1 & STM32F7_I2C_CR1_PE)
2118                 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
2119                                      STM32F7_I2C_CR1_PE);
2120         writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2);
2121         writel_relaxed(backup_regs->oar1, i2c_dev->base + STM32F7_I2C_OAR1);
2122         writel_relaxed(backup_regs->oar2, i2c_dev->base + STM32F7_I2C_OAR2);
2123         writel_relaxed(backup_regs->pecr, i2c_dev->base + STM32F7_I2C_PECR);
2124
2125         pm_runtime_put_sync(i2c_dev->dev);
2126
2127         return ret;
2128 }
2129
2130 static int __maybe_unused stm32f7_i2c_suspend(struct device *dev)
2131 {
2132         struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2133         int ret;
2134
2135         i2c_mark_adapter_suspended(&i2c_dev->adap);
2136         ret = stm32f7_i2c_regs_backup(i2c_dev);
2137         if (ret < 0) {
2138                 i2c_mark_adapter_resumed(&i2c_dev->adap);
2139                 return ret;
2140         }
2141
2142         pinctrl_pm_select_sleep_state(dev);
2143         pm_runtime_force_suspend(dev);
2144
2145         return 0;
2146 }
2147
2148 static int __maybe_unused stm32f7_i2c_resume(struct device *dev)
2149 {
2150         struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2151         int ret;
2152
2153         ret = pm_runtime_force_resume(dev);
2154         if (ret < 0)
2155                 return ret;
2156         pinctrl_pm_select_default_state(dev);
2157
2158         ret = stm32f7_i2c_regs_restore(i2c_dev);
2159         if (ret < 0)
2160                 return ret;
2161         i2c_mark_adapter_resumed(&i2c_dev->adap);
2162
2163         return 0;
2164 }
2165
2166 static const struct dev_pm_ops stm32f7_i2c_pm_ops = {
2167         SET_RUNTIME_PM_OPS(stm32f7_i2c_runtime_suspend,
2168                            stm32f7_i2c_runtime_resume, NULL)
2169         SET_SYSTEM_SLEEP_PM_OPS(stm32f7_i2c_suspend, stm32f7_i2c_resume)
2170 };
2171
2172 static const struct of_device_id stm32f7_i2c_match[] = {
2173         { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup},
2174         {},
2175 };
2176 MODULE_DEVICE_TABLE(of, stm32f7_i2c_match);
2177
2178 static struct platform_driver stm32f7_i2c_driver = {
2179         .driver = {
2180                 .name = "stm32f7-i2c",
2181                 .of_match_table = stm32f7_i2c_match,
2182                 .pm = &stm32f7_i2c_pm_ops,
2183         },
2184         .probe = stm32f7_i2c_probe,
2185         .remove = stm32f7_i2c_remove,
2186 };
2187
2188 module_platform_driver(stm32f7_i2c_driver);
2189
2190 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
2191 MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver");
2192 MODULE_LICENSE("GPL v2");