1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for STMicroelectronics STM32F7 I2C controller
5 * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc
7 * Please see below a link to the documentation:
8 * http://www.st.com/resource/en/reference_manual/dm00124865.pdf
10 * Copyright (C) M'boumba Cedric Madianga 2017
11 * Copyright (C) STMicroelectronics 2017
12 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
14 * This driver is based on i2c-stm32f4.c
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/i2c.h>
21 #include <linux/i2c-smbus.h>
22 #include <linux/interrupt.h>
24 #include <linux/iopoll.h>
25 #include <linux/mfd/syscon.h>
26 #include <linux/module.h>
28 #include <linux/of_address.h>
29 #include <linux/of_platform.h>
30 #include <linux/platform_device.h>
31 #include <linux/pinctrl/consumer.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/pm_wakeirq.h>
34 #include <linux/regmap.h>
35 #include <linux/reset.h>
36 #include <linux/slab.h>
38 #include "i2c-stm32.h"
40 /* STM32F7 I2C registers */
41 #define STM32F7_I2C_CR1 0x00
42 #define STM32F7_I2C_CR2 0x04
43 #define STM32F7_I2C_OAR1 0x08
44 #define STM32F7_I2C_OAR2 0x0C
45 #define STM32F7_I2C_PECR 0x20
46 #define STM32F7_I2C_TIMINGR 0x10
47 #define STM32F7_I2C_ISR 0x18
48 #define STM32F7_I2C_ICR 0x1C
49 #define STM32F7_I2C_RXDR 0x24
50 #define STM32F7_I2C_TXDR 0x28
52 /* STM32F7 I2C control 1 */
53 #define STM32F7_I2C_CR1_PECEN BIT(23)
54 #define STM32F7_I2C_CR1_ALERTEN BIT(22)
55 #define STM32F7_I2C_CR1_SMBHEN BIT(20)
56 #define STM32F7_I2C_CR1_WUPEN BIT(18)
57 #define STM32F7_I2C_CR1_SBC BIT(16)
58 #define STM32F7_I2C_CR1_RXDMAEN BIT(15)
59 #define STM32F7_I2C_CR1_TXDMAEN BIT(14)
60 #define STM32F7_I2C_CR1_ANFOFF BIT(12)
61 #define STM32F7_I2C_CR1_DNF_MASK GENMASK(11, 8)
62 #define STM32F7_I2C_CR1_DNF(n) (((n) & 0xf) << 8)
63 #define STM32F7_I2C_CR1_ERRIE BIT(7)
64 #define STM32F7_I2C_CR1_TCIE BIT(6)
65 #define STM32F7_I2C_CR1_STOPIE BIT(5)
66 #define STM32F7_I2C_CR1_NACKIE BIT(4)
67 #define STM32F7_I2C_CR1_ADDRIE BIT(3)
68 #define STM32F7_I2C_CR1_RXIE BIT(2)
69 #define STM32F7_I2C_CR1_TXIE BIT(1)
70 #define STM32F7_I2C_CR1_PE BIT(0)
71 #define STM32F7_I2C_ALL_IRQ_MASK (STM32F7_I2C_CR1_ERRIE \
72 | STM32F7_I2C_CR1_TCIE \
73 | STM32F7_I2C_CR1_STOPIE \
74 | STM32F7_I2C_CR1_NACKIE \
75 | STM32F7_I2C_CR1_RXIE \
76 | STM32F7_I2C_CR1_TXIE)
77 #define STM32F7_I2C_XFER_IRQ_MASK (STM32F7_I2C_CR1_TCIE \
78 | STM32F7_I2C_CR1_STOPIE \
79 | STM32F7_I2C_CR1_NACKIE \
80 | STM32F7_I2C_CR1_RXIE \
81 | STM32F7_I2C_CR1_TXIE)
83 /* STM32F7 I2C control 2 */
84 #define STM32F7_I2C_CR2_PECBYTE BIT(26)
85 #define STM32F7_I2C_CR2_RELOAD BIT(24)
86 #define STM32F7_I2C_CR2_NBYTES_MASK GENMASK(23, 16)
87 #define STM32F7_I2C_CR2_NBYTES(n) (((n) & 0xff) << 16)
88 #define STM32F7_I2C_CR2_NACK BIT(15)
89 #define STM32F7_I2C_CR2_STOP BIT(14)
90 #define STM32F7_I2C_CR2_START BIT(13)
91 #define STM32F7_I2C_CR2_HEAD10R BIT(12)
92 #define STM32F7_I2C_CR2_ADD10 BIT(11)
93 #define STM32F7_I2C_CR2_RD_WRN BIT(10)
94 #define STM32F7_I2C_CR2_SADD10_MASK GENMASK(9, 0)
95 #define STM32F7_I2C_CR2_SADD10(n) (((n) & \
96 STM32F7_I2C_CR2_SADD10_MASK))
97 #define STM32F7_I2C_CR2_SADD7_MASK GENMASK(7, 1)
98 #define STM32F7_I2C_CR2_SADD7(n) (((n) & 0x7f) << 1)
100 /* STM32F7 I2C Own Address 1 */
101 #define STM32F7_I2C_OAR1_OA1EN BIT(15)
102 #define STM32F7_I2C_OAR1_OA1MODE BIT(10)
103 #define STM32F7_I2C_OAR1_OA1_10_MASK GENMASK(9, 0)
104 #define STM32F7_I2C_OAR1_OA1_10(n) (((n) & \
105 STM32F7_I2C_OAR1_OA1_10_MASK))
106 #define STM32F7_I2C_OAR1_OA1_7_MASK GENMASK(7, 1)
107 #define STM32F7_I2C_OAR1_OA1_7(n) (((n) & 0x7f) << 1)
108 #define STM32F7_I2C_OAR1_MASK (STM32F7_I2C_OAR1_OA1_7_MASK \
109 | STM32F7_I2C_OAR1_OA1_10_MASK \
110 | STM32F7_I2C_OAR1_OA1EN \
111 | STM32F7_I2C_OAR1_OA1MODE)
113 /* STM32F7 I2C Own Address 2 */
114 #define STM32F7_I2C_OAR2_OA2EN BIT(15)
115 #define STM32F7_I2C_OAR2_OA2MSK_MASK GENMASK(10, 8)
116 #define STM32F7_I2C_OAR2_OA2MSK(n) (((n) & 0x7) << 8)
117 #define STM32F7_I2C_OAR2_OA2_7_MASK GENMASK(7, 1)
118 #define STM32F7_I2C_OAR2_OA2_7(n) (((n) & 0x7f) << 1)
119 #define STM32F7_I2C_OAR2_MASK (STM32F7_I2C_OAR2_OA2MSK_MASK \
120 | STM32F7_I2C_OAR2_OA2_7_MASK \
121 | STM32F7_I2C_OAR2_OA2EN)
123 /* STM32F7 I2C Interrupt Status */
124 #define STM32F7_I2C_ISR_ADDCODE_MASK GENMASK(23, 17)
125 #define STM32F7_I2C_ISR_ADDCODE_GET(n) \
126 (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17)
127 #define STM32F7_I2C_ISR_DIR BIT(16)
128 #define STM32F7_I2C_ISR_BUSY BIT(15)
129 #define STM32F7_I2C_ISR_ALERT BIT(13)
130 #define STM32F7_I2C_ISR_PECERR BIT(11)
131 #define STM32F7_I2C_ISR_ARLO BIT(9)
132 #define STM32F7_I2C_ISR_BERR BIT(8)
133 #define STM32F7_I2C_ISR_TCR BIT(7)
134 #define STM32F7_I2C_ISR_TC BIT(6)
135 #define STM32F7_I2C_ISR_STOPF BIT(5)
136 #define STM32F7_I2C_ISR_NACKF BIT(4)
137 #define STM32F7_I2C_ISR_ADDR BIT(3)
138 #define STM32F7_I2C_ISR_RXNE BIT(2)
139 #define STM32F7_I2C_ISR_TXIS BIT(1)
140 #define STM32F7_I2C_ISR_TXE BIT(0)
142 /* STM32F7 I2C Interrupt Clear */
143 #define STM32F7_I2C_ICR_ALERTCF BIT(13)
144 #define STM32F7_I2C_ICR_PECCF BIT(11)
145 #define STM32F7_I2C_ICR_ARLOCF BIT(9)
146 #define STM32F7_I2C_ICR_BERRCF BIT(8)
147 #define STM32F7_I2C_ICR_STOPCF BIT(5)
148 #define STM32F7_I2C_ICR_NACKCF BIT(4)
149 #define STM32F7_I2C_ICR_ADDRCF BIT(3)
151 /* STM32F7 I2C Timing */
152 #define STM32F7_I2C_TIMINGR_PRESC(n) (((n) & 0xf) << 28)
153 #define STM32F7_I2C_TIMINGR_SCLDEL(n) (((n) & 0xf) << 20)
154 #define STM32F7_I2C_TIMINGR_SDADEL(n) (((n) & 0xf) << 16)
155 #define STM32F7_I2C_TIMINGR_SCLH(n) (((n) & 0xff) << 8)
156 #define STM32F7_I2C_TIMINGR_SCLL(n) ((n) & 0xff)
158 #define STM32F7_I2C_MAX_LEN 0xff
159 #define STM32F7_I2C_DMA_LEN_MIN 0x16
161 STM32F7_SLAVE_HOSTNOTIFY,
162 STM32F7_SLAVE_7_10_BITS_ADDR,
163 STM32F7_SLAVE_7_BITS_ADDR,
164 STM32F7_I2C_MAX_SLAVE
167 #define STM32F7_I2C_DNF_DEFAULT 0
168 #define STM32F7_I2C_DNF_MAX 15
170 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */
171 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
173 #define STM32F7_I2C_RISE_TIME_DEFAULT 25 /* ns */
174 #define STM32F7_I2C_FALL_TIME_DEFAULT 10 /* ns */
176 #define STM32F7_PRESC_MAX BIT(4)
177 #define STM32F7_SCLDEL_MAX BIT(4)
178 #define STM32F7_SDADEL_MAX BIT(4)
179 #define STM32F7_SCLH_MAX BIT(8)
180 #define STM32F7_SCLL_MAX BIT(8)
182 #define STM32F7_AUTOSUSPEND_DELAY (HZ / 100)
185 * struct stm32f7_i2c_regs - i2c f7 registers backup
186 * @cr1: Control register 1
187 * @cr2: Control register 2
188 * @oar1: Own address 1 register
189 * @oar2: Own address 2 register
190 * @tmgr: Timing register
192 struct stm32f7_i2c_regs {
201 * struct stm32f7_i2c_spec - private i2c specification timing
202 * @rate: I2C bus speed (Hz)
203 * @fall_max: Max fall time of both SDA and SCL signals (ns)
204 * @rise_max: Max rise time of both SDA and SCL signals (ns)
205 * @hddat_min: Min data hold time (ns)
206 * @vddat_max: Max data valid time (ns)
207 * @sudat_min: Min data setup time (ns)
208 * @l_min: Min low period of the SCL clock (ns)
209 * @h_min: Min high period of the SCL clock (ns)
211 struct stm32f7_i2c_spec {
223 * struct stm32f7_i2c_setup - private I2C timing setup parameters
224 * @speed_freq: I2C speed frequency (Hz)
225 * @clock_src: I2C clock source frequency (Hz)
226 * @rise_time: Rise time (ns)
227 * @fall_time: Fall time (ns)
228 * @fmp_clr_offset: Fast Mode Plus clear register offset from set register
230 struct stm32f7_i2c_setup {
239 * struct stm32f7_i2c_timings - private I2C output parameters
241 * @presc: Prescaler value
242 * @scldel: Data setup time
243 * @sdadel: Data hold time
244 * @sclh: SCL high period (master mode)
245 * @scll: SCL low period (master mode)
247 struct stm32f7_i2c_timings {
248 struct list_head node;
257 * struct stm32f7_i2c_msg - client specific data
258 * @addr: 8-bit or 10-bit slave addr, including r/w bit
259 * @count: number of bytes to be transferred
261 * @result: result of the transfer
262 * @stop: last I2C msg to be sent, i.e. STOP to be generated
263 * @smbus: boolean to know if the I2C IP is used in SMBus mode
264 * @size: type of SMBus protocol
265 * @read_write: direction of SMBus protocol
266 * SMBus block read and SMBus block write - block read process call protocols
267 * @smbus_buf: buffer to be used for SMBus protocol transfer. It will
268 * contain a maximum of 32 bytes of data + byte command + byte count + PEC
269 * This buffer has to be 32-bit aligned to be compliant with memory address
270 * register in DMA mode.
272 struct stm32f7_i2c_msg {
281 u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4);
285 * struct stm32f7_i2c_alert - SMBus alert specific data
286 * @setup: platform data for the smbus_alert i2c client
287 * @ara: I2C slave device used to respond to the SMBus Alert with Alert
290 struct stm32f7_i2c_alert {
291 struct i2c_smbus_alert_setup setup;
292 struct i2c_client *ara;
296 * struct stm32f7_i2c_dev - private data of the controller
297 * @adap: I2C adapter for this controller
298 * @dev: device for this controller
299 * @base: virtual memory area
300 * @complete: completion of I2C message
302 * @bus_rate: I2C clock frequency of the controller
303 * @msg: Pointer to data to be written
304 * @msg_num: number of I2C messages to be executed
305 * @msg_id: message identifiant
306 * @f7_msg: customized i2c msg for driver usage
307 * @setup: I2C timing input setup
308 * @timing: I2C computed timings
309 * @slave: list of slave devices registered on the I2C bus
310 * @slave_running: slave device currently used
311 * @backup_regs: backup of i2c controller registers (for suspend/resume)
312 * @slave_dir: transfer direction for the current slave device
313 * @master_mode: boolean to know in which mode the I2C is running (master or
316 * @use_dma: boolean to know if dma is used in the current transfer
317 * @regmap: holds SYSCFG phandle for Fast Mode Plus bits
318 * @fmp_sreg: register address for setting Fast Mode Plus bits
319 * @fmp_creg: register address for clearing Fast Mode Plus bits
320 * @fmp_mask: mask for Fast Mode Plus bits in set register
321 * @wakeup_src: boolean to know if the device is a wakeup source
322 * @smbus_mode: states that the controller is configured in SMBus mode
323 * @host_notify_client: SMBus host-notify client
324 * @analog_filter: boolean to indicate enabling of the analog filter
325 * @dnf_dt: value of digital filter requested via dt
326 * @dnf: value of digital filter to apply
327 * @alert: SMBus alert specific data
329 struct stm32f7_i2c_dev {
330 struct i2c_adapter adap;
333 struct completion complete;
335 unsigned int bus_rate;
337 unsigned int msg_num;
339 struct stm32f7_i2c_msg f7_msg;
340 struct stm32f7_i2c_setup setup;
341 struct stm32f7_i2c_timings timing;
342 struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE];
343 struct i2c_client *slave_running;
344 struct stm32f7_i2c_regs backup_regs;
347 struct stm32_i2c_dma *dma;
349 struct regmap *regmap;
355 struct i2c_client *host_notify_client;
359 struct stm32f7_i2c_alert *alert;
363 * All these values are coming from I2C Specification, Version 6.0, 4th of
366 * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast,
367 * and Fast-mode Plus I2C-bus devices
369 static struct stm32f7_i2c_spec stm32f7_i2c_specs[] = {
371 .rate = I2C_MAX_STANDARD_MODE_FREQ,
381 .rate = I2C_MAX_FAST_MODE_FREQ,
391 .rate = I2C_MAX_FAST_MODE_PLUS_FREQ,
402 static const struct stm32f7_i2c_setup stm32f7_setup = {
403 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
404 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
407 static const struct stm32f7_i2c_setup stm32mp15_setup = {
408 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
409 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
410 .fmp_clr_offset = 0x40,
413 static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask)
415 writel_relaxed(readl_relaxed(reg) | mask, reg);
418 static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask)
420 writel_relaxed(readl_relaxed(reg) & ~mask, reg);
423 static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)
425 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
428 static struct stm32f7_i2c_spec *stm32f7_get_specs(u32 rate)
432 for (i = 0; i < ARRAY_SIZE(stm32f7_i2c_specs); i++)
433 if (rate <= stm32f7_i2c_specs[i].rate)
434 return &stm32f7_i2c_specs[i];
436 return ERR_PTR(-EINVAL);
439 #define RATE_MIN(rate) ((rate) * 8 / 10)
440 static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev,
441 struct stm32f7_i2c_setup *setup,
442 struct stm32f7_i2c_timings *output)
444 struct stm32f7_i2c_spec *specs;
445 u32 p_prev = STM32F7_PRESC_MAX;
446 u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
448 u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
450 u32 clk_error_prev = i2cbus;
452 u32 af_delay_min, af_delay_max;
454 u32 clk_min, clk_max;
455 int sdadel_min, sdadel_max;
457 struct stm32f7_i2c_timings *v, *_v, *s;
458 struct list_head solutions;
462 specs = stm32f7_get_specs(setup->speed_freq);
463 if (specs == ERR_PTR(-EINVAL)) {
464 dev_err(i2c_dev->dev, "speed out of bound {%d}\n",
469 if ((setup->rise_time > specs->rise_max) ||
470 (setup->fall_time > specs->fall_max)) {
471 dev_err(i2c_dev->dev,
472 "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
473 setup->rise_time, specs->rise_max,
474 setup->fall_time, specs->fall_max);
478 i2c_dev->dnf = DIV_ROUND_CLOSEST(i2c_dev->dnf_dt, i2cclk);
479 if (i2c_dev->dnf > STM32F7_I2C_DNF_MAX) {
480 dev_err(i2c_dev->dev,
481 "DNF out of bound %d/%d\n",
482 i2c_dev->dnf * i2cclk, STM32F7_I2C_DNF_MAX * i2cclk);
486 /* Analog and Digital Filters */
488 (i2c_dev->analog_filter ?
489 STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0);
491 (i2c_dev->analog_filter ?
492 STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0);
493 dnf_delay = i2c_dev->dnf * i2cclk;
495 sdadel_min = specs->hddat_min + setup->fall_time -
496 af_delay_min - (i2c_dev->dnf + 3) * i2cclk;
498 sdadel_max = specs->vddat_max - setup->rise_time -
499 af_delay_max - (i2c_dev->dnf + 4) * i2cclk;
501 scldel_min = setup->rise_time + specs->sudat_min;
508 dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n",
509 sdadel_min, sdadel_max, scldel_min);
511 INIT_LIST_HEAD(&solutions);
512 /* Compute possible values for PRESC, SCLDEL and SDADEL */
513 for (p = 0; p < STM32F7_PRESC_MAX; p++) {
514 for (l = 0; l < STM32F7_SCLDEL_MAX; l++) {
515 u32 scldel = (l + 1) * (p + 1) * i2cclk;
517 if (scldel < scldel_min)
520 for (a = 0; a < STM32F7_SDADEL_MAX; a++) {
521 u32 sdadel = (a * (p + 1) + 1) * i2cclk;
523 if (((sdadel >= sdadel_min) &&
524 (sdadel <= sdadel_max)) &&
526 v = kmalloc(sizeof(*v), GFP_KERNEL);
537 list_add_tail(&v->node,
548 if (list_empty(&solutions)) {
549 dev_err(i2c_dev->dev, "no Prescaler solution\n");
554 tsync = af_delay_min + dnf_delay + (2 * i2cclk);
556 clk_max = NSEC_PER_SEC / RATE_MIN(setup->speed_freq);
557 clk_min = NSEC_PER_SEC / setup->speed_freq;
560 * Among Prescaler possibilities discovered above figures out SCL Low
561 * and High Period. Provided:
562 * - SCL Low Period has to be higher than SCL Clock Low Period
563 * defined by I2C Specification. I2C Clock has to be lower than
564 * (SCL Low Period - Analog/Digital filters) / 4.
565 * - SCL High Period has to be lower than SCL Clock High Period
566 * defined by I2C Specification
567 * - I2C Clock has to be lower than SCL High Period
569 list_for_each_entry(v, &solutions, node) {
570 u32 prescaler = (v->presc + 1) * i2cclk;
572 for (l = 0; l < STM32F7_SCLL_MAX; l++) {
573 u32 tscl_l = (l + 1) * prescaler + tsync;
575 if ((tscl_l < specs->l_min) ||
577 ((tscl_l - af_delay_min - dnf_delay) / 4))) {
581 for (h = 0; h < STM32F7_SCLH_MAX; h++) {
582 u32 tscl_h = (h + 1) * prescaler + tsync;
583 u32 tscl = tscl_l + tscl_h +
584 setup->rise_time + setup->fall_time;
586 if ((tscl >= clk_min) && (tscl <= clk_max) &&
587 (tscl_h >= specs->h_min) &&
589 int clk_error = tscl - i2cbus;
592 clk_error = -clk_error;
594 if (clk_error < clk_error_prev) {
595 clk_error_prev = clk_error;
606 dev_err(i2c_dev->dev, "no solution at all\n");
611 output->presc = s->presc;
612 output->scldel = s->scldel;
613 output->sdadel = s->sdadel;
614 output->scll = s->scll;
615 output->sclh = s->sclh;
617 dev_dbg(i2c_dev->dev,
618 "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
620 output->scldel, output->sdadel,
621 output->scll, output->sclh);
624 /* Release list and memory */
625 list_for_each_entry_safe(v, _v, &solutions, node) {
633 static u32 stm32f7_get_lower_rate(u32 rate)
635 int i = ARRAY_SIZE(stm32f7_i2c_specs);
638 if (stm32f7_i2c_specs[i].rate < rate)
641 return stm32f7_i2c_specs[i].rate;
644 static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev,
645 struct stm32f7_i2c_setup *setup)
647 struct i2c_timings timings, *t = &timings;
650 t->bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
651 t->scl_rise_ns = i2c_dev->setup.rise_time;
652 t->scl_fall_ns = i2c_dev->setup.fall_time;
654 i2c_parse_fw_timings(i2c_dev->dev, t, false);
656 if (t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) {
657 dev_err(i2c_dev->dev, "Invalid bus speed (%i>%i)\n",
658 t->bus_freq_hz, I2C_MAX_FAST_MODE_PLUS_FREQ);
662 setup->speed_freq = t->bus_freq_hz;
663 i2c_dev->setup.rise_time = t->scl_rise_ns;
664 i2c_dev->setup.fall_time = t->scl_fall_ns;
665 i2c_dev->dnf_dt = t->digital_filter_width_ns;
666 setup->clock_src = clk_get_rate(i2c_dev->clk);
668 if (!setup->clock_src) {
669 dev_err(i2c_dev->dev, "clock rate is 0\n");
673 if (!of_property_read_bool(i2c_dev->dev->of_node, "i2c-digital-filter"))
674 i2c_dev->dnf_dt = STM32F7_I2C_DNF_DEFAULT;
677 ret = stm32f7_i2c_compute_timing(i2c_dev, setup,
680 dev_err(i2c_dev->dev,
681 "failed to compute I2C timings.\n");
682 if (setup->speed_freq <= I2C_MAX_STANDARD_MODE_FREQ)
685 stm32f7_get_lower_rate(setup->speed_freq);
686 dev_warn(i2c_dev->dev,
687 "downgrade I2C Speed Freq to (%i)\n",
693 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n");
697 i2c_dev->analog_filter = of_property_read_bool(i2c_dev->dev->of_node,
698 "i2c-analog-filter");
700 dev_dbg(i2c_dev->dev, "I2C Speed(%i), Clk Source(%i)\n",
701 setup->speed_freq, setup->clock_src);
702 dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n",
703 setup->rise_time, setup->fall_time);
704 dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n",
705 (i2c_dev->analog_filter ? "On" : "Off"), i2c_dev->dnf);
707 i2c_dev->bus_rate = setup->speed_freq;
712 static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev)
714 void __iomem *base = i2c_dev->base;
715 u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN;
717 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
720 static void stm32f7_i2c_dma_callback(void *arg)
722 struct stm32f7_i2c_dev *i2c_dev = (struct stm32f7_i2c_dev *)arg;
723 struct stm32_i2c_dma *dma = i2c_dev->dma;
724 struct device *dev = dma->chan_using->device->dev;
726 stm32f7_i2c_disable_dma_req(i2c_dev);
727 dma_unmap_single(dev, dma->dma_buf, dma->dma_len, dma->dma_data_dir);
728 complete(&dma->dma_complete);
731 static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev)
733 struct stm32f7_i2c_timings *t = &i2c_dev->timing;
736 /* Timing settings */
737 timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc);
738 timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel);
739 timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel);
740 timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh);
741 timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll);
742 writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR);
744 /* Configure the Analog Filter */
745 if (i2c_dev->analog_filter)
746 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
747 STM32F7_I2C_CR1_ANFOFF);
749 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
750 STM32F7_I2C_CR1_ANFOFF);
752 /* Program the Digital Filter */
753 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
754 STM32F7_I2C_CR1_DNF_MASK);
755 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
756 STM32F7_I2C_CR1_DNF(i2c_dev->dnf));
758 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
762 static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev)
764 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
765 void __iomem *base = i2c_dev->base;
768 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR);
773 static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev)
775 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
776 void __iomem *base = i2c_dev->base;
779 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR);
782 /* Flush RX buffer has no data is expected */
783 readb_relaxed(base + STM32F7_I2C_RXDR);
787 static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev)
789 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
792 if (i2c_dev->use_dma)
793 f7_msg->count -= STM32F7_I2C_MAX_LEN;
795 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
797 cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK;
798 if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
799 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
801 cr2 &= ~STM32F7_I2C_CR2_RELOAD;
802 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
805 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
808 static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev)
810 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
815 * For I2C_SMBUS_BLOCK_DATA && I2C_SMBUS_BLOCK_PROC_CALL, the first
816 * data received inform us how many data will follow.
818 stm32f7_i2c_read_rx_data(i2c_dev);
821 * Update NBYTES with the value read to continue the transfer
823 val = f7_msg->buf - sizeof(u8);
824 f7_msg->count = *val;
825 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
826 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
827 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
828 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
831 static int stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap)
833 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
835 dev_info(i2c_dev->dev, "Trying to recover bus\n");
837 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
840 stm32f7_i2c_hw_config(i2c_dev);
845 static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev)
850 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR,
852 !(status & STM32F7_I2C_ISR_BUSY),
857 dev_info(i2c_dev->dev, "bus busy\n");
859 ret = stm32f7_i2c_release_bus(&i2c_dev->adap);
861 dev_err(i2c_dev->dev, "Failed to recover the bus (%d)\n", ret);
868 static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
871 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
872 void __iomem *base = i2c_dev->base;
876 f7_msg->addr = msg->addr;
877 f7_msg->buf = msg->buf;
878 f7_msg->count = msg->len;
880 f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1);
882 reinit_completion(&i2c_dev->complete);
884 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
885 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
887 /* Set transfer direction */
888 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
889 if (msg->flags & I2C_M_RD)
890 cr2 |= STM32F7_I2C_CR2_RD_WRN;
892 /* Set slave address */
893 cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10);
894 if (msg->flags & I2C_M_TEN) {
895 cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK;
896 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr);
897 cr2 |= STM32F7_I2C_CR2_ADD10;
899 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK;
900 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
903 /* Set nb bytes to transfer and reload if needed */
904 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
905 if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
906 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
907 cr2 |= STM32F7_I2C_CR2_RELOAD;
909 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
912 /* Enable NACK, STOP, error and transfer complete interrupts */
913 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
914 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
916 /* Clear DMA req and TX/RX interrupt */
917 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
918 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
920 /* Configure DMA or enable RX/TX interrupt */
921 i2c_dev->use_dma = false;
922 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
923 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
924 msg->flags & I2C_M_RD,
925 f7_msg->count, f7_msg->buf,
926 stm32f7_i2c_dma_callback,
929 i2c_dev->use_dma = true;
931 dev_warn(i2c_dev->dev, "can't use DMA\n");
934 if (!i2c_dev->use_dma) {
935 if (msg->flags & I2C_M_RD)
936 cr1 |= STM32F7_I2C_CR1_RXIE;
938 cr1 |= STM32F7_I2C_CR1_TXIE;
940 if (msg->flags & I2C_M_RD)
941 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
943 cr1 |= STM32F7_I2C_CR1_TXDMAEN;
946 /* Configure Start/Repeated Start */
947 cr2 |= STM32F7_I2C_CR2_START;
949 i2c_dev->master_mode = true;
951 /* Write configurations registers */
952 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
953 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
956 static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
957 unsigned short flags, u8 command,
958 union i2c_smbus_data *data)
960 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
961 struct device *dev = i2c_dev->dev;
962 void __iomem *base = i2c_dev->base;
967 reinit_completion(&i2c_dev->complete);
969 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
970 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
972 /* Set transfer direction */
973 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
974 if (f7_msg->read_write)
975 cr2 |= STM32F7_I2C_CR2_RD_WRN;
977 /* Set slave address */
978 cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK);
979 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
981 f7_msg->smbus_buf[0] = command;
982 switch (f7_msg->size) {
983 case I2C_SMBUS_QUICK:
991 case I2C_SMBUS_BYTE_DATA:
992 if (f7_msg->read_write) {
993 f7_msg->stop = false;
995 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
999 f7_msg->smbus_buf[1] = data->byte;
1002 case I2C_SMBUS_WORD_DATA:
1003 if (f7_msg->read_write) {
1004 f7_msg->stop = false;
1006 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1008 f7_msg->stop = true;
1010 f7_msg->smbus_buf[1] = data->word & 0xff;
1011 f7_msg->smbus_buf[2] = data->word >> 8;
1014 case I2C_SMBUS_BLOCK_DATA:
1015 if (f7_msg->read_write) {
1016 f7_msg->stop = false;
1018 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1020 f7_msg->stop = true;
1021 if (data->block[0] > I2C_SMBUS_BLOCK_MAX ||
1023 dev_err(dev, "Invalid block write size %d\n",
1027 f7_msg->count = data->block[0] + 2;
1028 for (i = 1; i < f7_msg->count; i++)
1029 f7_msg->smbus_buf[i] = data->block[i - 1];
1032 case I2C_SMBUS_PROC_CALL:
1033 f7_msg->stop = false;
1035 f7_msg->smbus_buf[1] = data->word & 0xff;
1036 f7_msg->smbus_buf[2] = data->word >> 8;
1037 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1038 f7_msg->read_write = I2C_SMBUS_READ;
1040 case I2C_SMBUS_BLOCK_PROC_CALL:
1041 f7_msg->stop = false;
1042 if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) {
1043 dev_err(dev, "Invalid block write size %d\n",
1047 f7_msg->count = data->block[0] + 2;
1048 for (i = 1; i < f7_msg->count; i++)
1049 f7_msg->smbus_buf[i] = data->block[i - 1];
1050 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1051 f7_msg->read_write = I2C_SMBUS_READ;
1053 case I2C_SMBUS_I2C_BLOCK_DATA:
1054 /* Rely on emulated i2c transfer (through master_xfer) */
1057 dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size);
1061 f7_msg->buf = f7_msg->smbus_buf;
1064 if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) {
1065 cr1 |= STM32F7_I2C_CR1_PECEN;
1066 cr2 |= STM32F7_I2C_CR2_PECBYTE;
1067 if (!f7_msg->read_write)
1070 cr1 &= ~STM32F7_I2C_CR1_PECEN;
1071 cr2 &= ~STM32F7_I2C_CR2_PECBYTE;
1074 /* Set number of bytes to be transferred */
1075 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
1076 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1078 /* Enable NACK, STOP, error and transfer complete interrupts */
1079 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
1080 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
1082 /* Clear DMA req and TX/RX interrupt */
1083 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1084 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1086 /* Configure DMA or enable RX/TX interrupt */
1087 i2c_dev->use_dma = false;
1088 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
1089 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1090 cr2 & STM32F7_I2C_CR2_RD_WRN,
1091 f7_msg->count, f7_msg->buf,
1092 stm32f7_i2c_dma_callback,
1095 i2c_dev->use_dma = true;
1097 dev_warn(i2c_dev->dev, "can't use DMA\n");
1100 if (!i2c_dev->use_dma) {
1101 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1102 cr1 |= STM32F7_I2C_CR1_RXIE;
1104 cr1 |= STM32F7_I2C_CR1_TXIE;
1106 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1107 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1109 cr1 |= STM32F7_I2C_CR1_TXDMAEN;
1113 cr2 |= STM32F7_I2C_CR2_START;
1115 i2c_dev->master_mode = true;
1117 /* Write configurations registers */
1118 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1119 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1124 static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev)
1126 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1127 void __iomem *base = i2c_dev->base;
1131 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
1132 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
1134 /* Set transfer direction */
1135 cr2 |= STM32F7_I2C_CR2_RD_WRN;
1137 switch (f7_msg->size) {
1138 case I2C_SMBUS_BYTE_DATA:
1141 case I2C_SMBUS_WORD_DATA:
1142 case I2C_SMBUS_PROC_CALL:
1145 case I2C_SMBUS_BLOCK_DATA:
1146 case I2C_SMBUS_BLOCK_PROC_CALL:
1148 cr2 |= STM32F7_I2C_CR2_RELOAD;
1152 f7_msg->buf = f7_msg->smbus_buf;
1153 f7_msg->stop = true;
1155 /* Add one byte for PEC if needed */
1156 if (cr1 & STM32F7_I2C_CR1_PECEN)
1159 /* Set number of bytes to be transferred */
1160 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK);
1161 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1164 * Configure RX/TX interrupt:
1166 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE);
1167 cr1 |= STM32F7_I2C_CR1_RXIE;
1170 * Configure DMA or enable RX/TX interrupt:
1171 * For I2C_SMBUS_BLOCK_DATA and I2C_SMBUS_BLOCK_PROC_CALL we don't use
1172 * dma as we don't know in advance how many data will be received
1174 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1175 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1177 i2c_dev->use_dma = false;
1178 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN &&
1179 f7_msg->size != I2C_SMBUS_BLOCK_DATA &&
1180 f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) {
1181 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1182 cr2 & STM32F7_I2C_CR2_RD_WRN,
1183 f7_msg->count, f7_msg->buf,
1184 stm32f7_i2c_dma_callback,
1188 i2c_dev->use_dma = true;
1190 dev_warn(i2c_dev->dev, "can't use DMA\n");
1193 if (!i2c_dev->use_dma)
1194 cr1 |= STM32F7_I2C_CR1_RXIE;
1196 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1198 /* Configure Repeated Start */
1199 cr2 |= STM32F7_I2C_CR2_START;
1201 /* Write configurations registers */
1202 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1203 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1206 static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev)
1208 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1209 u8 count, internal_pec, received_pec;
1211 internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR);
1213 switch (f7_msg->size) {
1214 case I2C_SMBUS_BYTE:
1215 case I2C_SMBUS_BYTE_DATA:
1216 received_pec = f7_msg->smbus_buf[1];
1218 case I2C_SMBUS_WORD_DATA:
1219 case I2C_SMBUS_PROC_CALL:
1220 received_pec = f7_msg->smbus_buf[2];
1222 case I2C_SMBUS_BLOCK_DATA:
1223 case I2C_SMBUS_BLOCK_PROC_CALL:
1224 count = f7_msg->smbus_buf[0];
1225 received_pec = f7_msg->smbus_buf[count];
1228 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n");
1232 if (internal_pec != received_pec) {
1233 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n",
1234 internal_pec, received_pec);
1241 static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode)
1248 if (slave->flags & I2C_CLIENT_TEN) {
1250 * For 10-bit addr, addcode = 11110XY with
1251 * X = Bit 9 of slave address
1252 * Y = Bit 8 of slave address
1254 addr = slave->addr >> 8;
1256 if (addr == addcode)
1259 addr = slave->addr & 0x7f;
1260 if (addr == addcode)
1267 static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev)
1269 struct i2c_client *slave = i2c_dev->slave_running;
1270 void __iomem *base = i2c_dev->base;
1274 if (i2c_dev->slave_dir) {
1275 /* Notify i2c slave that new read transfer is starting */
1276 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
1279 * Disable slave TX config in case of I2C combined message
1280 * (I2C Write followed by I2C Read)
1282 mask = STM32F7_I2C_CR2_RELOAD;
1283 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask);
1284 mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1285 STM32F7_I2C_CR1_TCIE;
1286 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1288 /* Enable TX empty, STOP, NACK interrupts */
1289 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1290 STM32F7_I2C_CR1_TXIE;
1291 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1293 /* Write 1st data byte */
1294 writel_relaxed(value, base + STM32F7_I2C_TXDR);
1296 /* Notify i2c slave that new write transfer is starting */
1297 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
1299 /* Set reload mode to be able to ACK/NACK each received byte */
1300 mask = STM32F7_I2C_CR2_RELOAD;
1301 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1304 * Set STOP, NACK, RX empty and transfer complete interrupts.*
1305 * Set Slave Byte Control to be able to ACK/NACK each data
1308 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1309 STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1310 STM32F7_I2C_CR1_TCIE;
1311 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1315 static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev)
1317 void __iomem *base = i2c_dev->base;
1318 u32 isr, addcode, dir, mask;
1321 isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1322 addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr);
1323 dir = isr & STM32F7_I2C_ISR_DIR;
1325 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1326 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) {
1327 i2c_dev->slave_running = i2c_dev->slave[i];
1328 i2c_dev->slave_dir = dir;
1330 /* Start I2C slave processing */
1331 stm32f7_i2c_slave_start(i2c_dev);
1333 /* Clear ADDR flag */
1334 mask = STM32F7_I2C_ICR_ADDRCF;
1335 writel_relaxed(mask, base + STM32F7_I2C_ICR);
1341 static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1342 struct i2c_client *slave, int *id)
1346 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1347 if (i2c_dev->slave[i] == slave) {
1353 dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr);
1358 static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1359 struct i2c_client *slave, int *id)
1361 struct device *dev = i2c_dev->dev;
1365 * slave[STM32F7_SLAVE_HOSTNOTIFY] support only SMBus Host address (0x8)
1366 * slave[STM32F7_SLAVE_7_10_BITS_ADDR] supports 7-bit and 10-bit slave address
1367 * slave[STM32F7_SLAVE_7_BITS_ADDR] supports 7-bit slave address only
1369 if (i2c_dev->smbus_mode && (slave->addr == 0x08)) {
1370 if (i2c_dev->slave[STM32F7_SLAVE_HOSTNOTIFY])
1372 *id = STM32F7_SLAVE_HOSTNOTIFY;
1376 for (i = STM32F7_I2C_MAX_SLAVE - 1; i > STM32F7_SLAVE_HOSTNOTIFY; i--) {
1377 if ((i == STM32F7_SLAVE_7_BITS_ADDR) &&
1378 (slave->flags & I2C_CLIENT_TEN))
1380 if (!i2c_dev->slave[i]) {
1387 dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr);
1392 static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev)
1396 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1397 if (i2c_dev->slave[i])
1404 static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev)
1409 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1410 if (i2c_dev->slave[i])
1417 static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev)
1419 void __iomem *base = i2c_dev->base;
1420 u32 cr2, status, mask;
1424 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1426 /* Slave transmitter mode */
1427 if (status & STM32F7_I2C_ISR_TXIS) {
1428 i2c_slave_event(i2c_dev->slave_running,
1429 I2C_SLAVE_READ_PROCESSED,
1432 /* Write data byte */
1433 writel_relaxed(val, base + STM32F7_I2C_TXDR);
1436 /* Transfer Complete Reload for Slave receiver mode */
1437 if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) {
1439 * Read data byte then set NBYTES to receive next byte or NACK
1440 * the current received byte
1442 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR);
1443 ret = i2c_slave_event(i2c_dev->slave_running,
1444 I2C_SLAVE_WRITE_RECEIVED,
1447 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
1448 cr2 |= STM32F7_I2C_CR2_NBYTES(1);
1449 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
1451 mask = STM32F7_I2C_CR2_NACK;
1452 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1457 if (status & STM32F7_I2C_ISR_NACKF) {
1458 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1459 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1463 if (status & STM32F7_I2C_ISR_STOPF) {
1464 /* Disable interrupts */
1465 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK);
1467 if (i2c_dev->slave_dir) {
1469 * Flush TX buffer in order to not used the byte in
1470 * TXDR for the next transfer
1472 mask = STM32F7_I2C_ISR_TXE;
1473 stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask);
1476 /* Clear STOP flag */
1477 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1479 /* Notify i2c slave that a STOP flag has been detected */
1480 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val);
1482 i2c_dev->slave_running = NULL;
1485 /* Address match received */
1486 if (status & STM32F7_I2C_ISR_ADDR)
1487 stm32f7_i2c_slave_addr(i2c_dev);
1492 static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
1494 struct stm32f7_i2c_dev *i2c_dev = data;
1495 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1496 struct stm32_i2c_dma *dma = i2c_dev->dma;
1497 void __iomem *base = i2c_dev->base;
1499 int ret = IRQ_HANDLED;
1501 /* Check if the interrupt if for a slave device */
1502 if (!i2c_dev->master_mode) {
1503 ret = stm32f7_i2c_slave_isr_event(i2c_dev);
1507 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1510 if (status & STM32F7_I2C_ISR_TXIS)
1511 stm32f7_i2c_write_tx_data(i2c_dev);
1514 if (status & STM32F7_I2C_ISR_RXNE)
1515 stm32f7_i2c_read_rx_data(i2c_dev);
1518 if (status & STM32F7_I2C_ISR_NACKF) {
1519 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK (addr %x)\n",
1520 __func__, f7_msg->addr);
1521 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1522 if (i2c_dev->use_dma) {
1523 stm32f7_i2c_disable_dma_req(i2c_dev);
1524 dmaengine_terminate_async(dma->chan_using);
1526 f7_msg->result = -ENXIO;
1529 /* STOP detection flag */
1530 if (status & STM32F7_I2C_ISR_STOPF) {
1531 /* Disable interrupts */
1532 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1533 mask = STM32F7_I2C_XFER_IRQ_MASK;
1535 mask = STM32F7_I2C_ALL_IRQ_MASK;
1536 stm32f7_i2c_disable_irq(i2c_dev, mask);
1538 /* Clear STOP flag */
1539 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1541 if (i2c_dev->use_dma && !f7_msg->result) {
1542 ret = IRQ_WAKE_THREAD;
1544 i2c_dev->master_mode = false;
1545 complete(&i2c_dev->complete);
1549 /* Transfer complete */
1550 if (status & STM32F7_I2C_ISR_TC) {
1552 mask = STM32F7_I2C_CR2_STOP;
1553 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1554 } else if (i2c_dev->use_dma && !f7_msg->result) {
1555 ret = IRQ_WAKE_THREAD;
1556 } else if (f7_msg->smbus) {
1557 stm32f7_i2c_smbus_rep_start(i2c_dev);
1561 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1565 if (status & STM32F7_I2C_ISR_TCR) {
1567 stm32f7_i2c_smbus_reload(i2c_dev);
1569 stm32f7_i2c_reload(i2c_dev);
1575 static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data)
1577 struct stm32f7_i2c_dev *i2c_dev = data;
1578 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1579 struct stm32_i2c_dma *dma = i2c_dev->dma;
1584 * Wait for dma transfer completion before sending next message or
1585 * notity the end of xfer to the client
1587 ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ);
1589 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__);
1590 stm32f7_i2c_disable_dma_req(i2c_dev);
1591 dmaengine_terminate_async(dma->chan_using);
1592 f7_msg->result = -ETIMEDOUT;
1595 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1597 if (status & STM32F7_I2C_ISR_TC) {
1598 if (f7_msg->smbus) {
1599 stm32f7_i2c_smbus_rep_start(i2c_dev);
1603 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1606 i2c_dev->master_mode = false;
1607 complete(&i2c_dev->complete);
1613 static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data)
1615 struct stm32f7_i2c_dev *i2c_dev = data;
1616 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1617 void __iomem *base = i2c_dev->base;
1618 struct device *dev = i2c_dev->dev;
1619 struct stm32_i2c_dma *dma = i2c_dev->dma;
1622 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1625 if (status & STM32F7_I2C_ISR_BERR) {
1626 dev_err(dev, "<%s>: Bus error accessing addr 0x%x\n",
1627 __func__, f7_msg->addr);
1628 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR);
1629 stm32f7_i2c_release_bus(&i2c_dev->adap);
1630 f7_msg->result = -EIO;
1633 /* Arbitration loss */
1634 if (status & STM32F7_I2C_ISR_ARLO) {
1635 dev_dbg(dev, "<%s>: Arbitration loss accessing addr 0x%x\n",
1636 __func__, f7_msg->addr);
1637 writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR);
1638 f7_msg->result = -EAGAIN;
1641 if (status & STM32F7_I2C_ISR_PECERR) {
1642 dev_err(dev, "<%s>: PEC error in reception accessing addr 0x%x\n",
1643 __func__, f7_msg->addr);
1644 writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR);
1645 f7_msg->result = -EINVAL;
1648 if (status & STM32F7_I2C_ISR_ALERT) {
1649 dev_dbg(dev, "<%s>: SMBus alert received\n", __func__);
1650 writel_relaxed(STM32F7_I2C_ICR_ALERTCF, base + STM32F7_I2C_ICR);
1651 i2c_handle_smbus_alert(i2c_dev->alert->ara);
1655 if (!i2c_dev->slave_running) {
1657 /* Disable interrupts */
1658 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1659 mask = STM32F7_I2C_XFER_IRQ_MASK;
1661 mask = STM32F7_I2C_ALL_IRQ_MASK;
1662 stm32f7_i2c_disable_irq(i2c_dev, mask);
1666 if (i2c_dev->use_dma) {
1667 stm32f7_i2c_disable_dma_req(i2c_dev);
1668 dmaengine_terminate_async(dma->chan_using);
1671 i2c_dev->master_mode = false;
1672 complete(&i2c_dev->complete);
1677 static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap,
1678 struct i2c_msg msgs[], int num)
1680 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
1681 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1682 struct stm32_i2c_dma *dma = i2c_dev->dma;
1683 unsigned long time_left;
1686 i2c_dev->msg = msgs;
1687 i2c_dev->msg_num = num;
1688 i2c_dev->msg_id = 0;
1689 f7_msg->smbus = false;
1691 ret = pm_runtime_resume_and_get(i2c_dev->dev);
1695 ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1699 stm32f7_i2c_xfer_msg(i2c_dev, msgs);
1701 time_left = wait_for_completion_timeout(&i2c_dev->complete,
1702 i2c_dev->adap.timeout);
1703 ret = f7_msg->result;
1705 if (i2c_dev->use_dma)
1706 dmaengine_synchronize(dma->chan_using);
1709 * It is possible that some unsent data have already been
1710 * written into TXDR. To avoid sending old data in a
1711 * further transfer, flush TXDR in case of any error
1713 writel_relaxed(STM32F7_I2C_ISR_TXE,
1714 i2c_dev->base + STM32F7_I2C_ISR);
1719 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n",
1720 i2c_dev->msg->addr);
1721 if (i2c_dev->use_dma)
1722 dmaengine_terminate_sync(dma->chan_using);
1723 stm32f7_i2c_wait_free_bus(i2c_dev);
1728 pm_runtime_mark_last_busy(i2c_dev->dev);
1729 pm_runtime_put_autosuspend(i2c_dev->dev);
1731 return (ret < 0) ? ret : num;
1734 static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
1735 unsigned short flags, char read_write,
1736 u8 command, int size,
1737 union i2c_smbus_data *data)
1739 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter);
1740 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1741 struct stm32_i2c_dma *dma = i2c_dev->dma;
1742 struct device *dev = i2c_dev->dev;
1743 unsigned long timeout;
1746 f7_msg->addr = addr;
1747 f7_msg->size = size;
1748 f7_msg->read_write = read_write;
1749 f7_msg->smbus = true;
1751 ret = pm_runtime_resume_and_get(dev);
1755 ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1759 ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data);
1763 timeout = wait_for_completion_timeout(&i2c_dev->complete,
1764 i2c_dev->adap.timeout);
1765 ret = f7_msg->result;
1767 if (i2c_dev->use_dma)
1768 dmaengine_synchronize(dma->chan_using);
1771 * It is possible that some unsent data have already been
1772 * written into TXDR. To avoid sending old data in a
1773 * further transfer, flush TXDR in case of any error
1775 writel_relaxed(STM32F7_I2C_ISR_TXE,
1776 i2c_dev->base + STM32F7_I2C_ISR);
1781 dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr);
1782 if (i2c_dev->use_dma)
1783 dmaengine_terminate_sync(dma->chan_using);
1784 stm32f7_i2c_wait_free_bus(i2c_dev);
1790 if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) {
1791 ret = stm32f7_i2c_smbus_check_pec(i2c_dev);
1796 if (read_write && size != I2C_SMBUS_QUICK) {
1798 case I2C_SMBUS_BYTE:
1799 case I2C_SMBUS_BYTE_DATA:
1800 data->byte = f7_msg->smbus_buf[0];
1802 case I2C_SMBUS_WORD_DATA:
1803 case I2C_SMBUS_PROC_CALL:
1804 data->word = f7_msg->smbus_buf[0] |
1805 (f7_msg->smbus_buf[1] << 8);
1807 case I2C_SMBUS_BLOCK_DATA:
1808 case I2C_SMBUS_BLOCK_PROC_CALL:
1809 for (i = 0; i <= f7_msg->smbus_buf[0]; i++)
1810 data->block[i] = f7_msg->smbus_buf[i];
1813 dev_err(dev, "Unsupported smbus transaction\n");
1819 pm_runtime_mark_last_busy(dev);
1820 pm_runtime_put_autosuspend(dev);
1824 static void stm32f7_i2c_enable_wakeup(struct stm32f7_i2c_dev *i2c_dev,
1827 void __iomem *base = i2c_dev->base;
1828 u32 mask = STM32F7_I2C_CR1_WUPEN;
1830 if (!i2c_dev->wakeup_src)
1834 device_set_wakeup_enable(i2c_dev->dev, true);
1835 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1837 device_set_wakeup_enable(i2c_dev->dev, false);
1838 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1842 static int stm32f7_i2c_reg_slave(struct i2c_client *slave)
1844 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1845 void __iomem *base = i2c_dev->base;
1846 struct device *dev = i2c_dev->dev;
1847 u32 oar1, oar2, mask;
1850 if (slave->flags & I2C_CLIENT_PEC) {
1851 dev_err(dev, "SMBus PEC not supported in slave mode\n");
1855 if (stm32f7_i2c_is_slave_busy(i2c_dev)) {
1856 dev_err(dev, "Too much slave registered\n");
1860 ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id);
1864 ret = pm_runtime_resume_and_get(dev);
1868 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
1869 stm32f7_i2c_enable_wakeup(i2c_dev, true);
1873 /* Slave SMBus Host */
1874 i2c_dev->slave[id] = slave;
1878 /* Configure Own Address 1 */
1879 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
1880 oar1 &= ~STM32F7_I2C_OAR1_MASK;
1881 if (slave->flags & I2C_CLIENT_TEN) {
1882 oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr);
1883 oar1 |= STM32F7_I2C_OAR1_OA1MODE;
1885 oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr);
1887 oar1 |= STM32F7_I2C_OAR1_OA1EN;
1888 i2c_dev->slave[id] = slave;
1889 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1);
1893 /* Configure Own Address 2 */
1894 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
1895 oar2 &= ~STM32F7_I2C_OAR2_MASK;
1896 if (slave->flags & I2C_CLIENT_TEN) {
1901 oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr);
1902 oar2 |= STM32F7_I2C_OAR2_OA2EN;
1903 i2c_dev->slave[id] = slave;
1904 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2);
1908 dev_err(dev, "I2C slave id not supported\n");
1914 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK);
1916 /* Enable Address match interrupt, error interrupt and enable I2C */
1917 mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE |
1919 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1923 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
1924 stm32f7_i2c_enable_wakeup(i2c_dev, false);
1926 pm_runtime_mark_last_busy(dev);
1927 pm_runtime_put_autosuspend(dev);
1932 static int stm32f7_i2c_unreg_slave(struct i2c_client *slave)
1934 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1935 void __iomem *base = i2c_dev->base;
1939 ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id);
1943 WARN_ON(!i2c_dev->slave[id]);
1945 ret = pm_runtime_resume_and_get(i2c_dev->dev);
1950 mask = STM32F7_I2C_OAR1_OA1EN;
1951 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask);
1952 } else if (id == 2) {
1953 mask = STM32F7_I2C_OAR2_OA2EN;
1954 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask);
1957 i2c_dev->slave[id] = NULL;
1959 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
1960 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
1961 stm32f7_i2c_enable_wakeup(i2c_dev, false);
1964 pm_runtime_mark_last_busy(i2c_dev->dev);
1965 pm_runtime_put_autosuspend(i2c_dev->dev);
1970 static int stm32f7_i2c_write_fm_plus_bits(struct stm32f7_i2c_dev *i2c_dev,
1975 if (i2c_dev->bus_rate <= I2C_MAX_FAST_MODE_FREQ ||
1976 IS_ERR_OR_NULL(i2c_dev->regmap))
1980 if (i2c_dev->fmp_sreg == i2c_dev->fmp_creg)
1981 ret = regmap_update_bits(i2c_dev->regmap,
1984 enable ? i2c_dev->fmp_mask : 0);
1986 ret = regmap_write(i2c_dev->regmap,
1987 enable ? i2c_dev->fmp_sreg :
1994 static int stm32f7_i2c_setup_fm_plus_bits(struct platform_device *pdev,
1995 struct stm32f7_i2c_dev *i2c_dev)
1997 struct device_node *np = pdev->dev.of_node;
2000 i2c_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg-fmp");
2001 if (IS_ERR(i2c_dev->regmap))
2005 ret = of_property_read_u32_index(np, "st,syscfg-fmp", 1,
2006 &i2c_dev->fmp_sreg);
2010 i2c_dev->fmp_creg = i2c_dev->fmp_sreg +
2011 i2c_dev->setup.fmp_clr_offset;
2013 return of_property_read_u32_index(np, "st,syscfg-fmp", 2,
2014 &i2c_dev->fmp_mask);
2017 static int stm32f7_i2c_enable_smbus_host(struct stm32f7_i2c_dev *i2c_dev)
2019 struct i2c_adapter *adap = &i2c_dev->adap;
2020 void __iomem *base = i2c_dev->base;
2021 struct i2c_client *client;
2023 client = i2c_new_slave_host_notify_device(adap);
2025 return PTR_ERR(client);
2027 i2c_dev->host_notify_client = client;
2029 /* Enable SMBus Host address */
2030 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_SMBHEN);
2035 static void stm32f7_i2c_disable_smbus_host(struct stm32f7_i2c_dev *i2c_dev)
2037 void __iomem *base = i2c_dev->base;
2039 if (i2c_dev->host_notify_client) {
2040 /* Disable SMBus Host address */
2041 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1,
2042 STM32F7_I2C_CR1_SMBHEN);
2043 i2c_free_slave_host_notify_device(i2c_dev->host_notify_client);
2047 static int stm32f7_i2c_enable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev)
2049 struct stm32f7_i2c_alert *alert;
2050 struct i2c_adapter *adap = &i2c_dev->adap;
2051 struct device *dev = i2c_dev->dev;
2052 void __iomem *base = i2c_dev->base;
2054 alert = devm_kzalloc(dev, sizeof(*alert), GFP_KERNEL);
2058 alert->ara = i2c_new_smbus_alert_device(adap, &alert->setup);
2059 if (IS_ERR(alert->ara))
2060 return PTR_ERR(alert->ara);
2062 i2c_dev->alert = alert;
2064 /* Enable SMBus Alert */
2065 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_ALERTEN);
2070 static void stm32f7_i2c_disable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev)
2072 struct stm32f7_i2c_alert *alert = i2c_dev->alert;
2073 void __iomem *base = i2c_dev->base;
2076 /* Disable SMBus Alert */
2077 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1,
2078 STM32F7_I2C_CR1_ALERTEN);
2079 i2c_unregister_device(alert->ara);
2083 static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
2085 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
2087 u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE |
2088 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
2089 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
2090 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
2091 I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC |
2092 I2C_FUNC_SMBUS_I2C_BLOCK;
2094 if (i2c_dev->smbus_mode)
2095 func |= I2C_FUNC_SMBUS_HOST_NOTIFY;
2100 static const struct i2c_algorithm stm32f7_i2c_algo = {
2101 .master_xfer = stm32f7_i2c_xfer,
2102 .smbus_xfer = stm32f7_i2c_smbus_xfer,
2103 .functionality = stm32f7_i2c_func,
2104 .reg_slave = stm32f7_i2c_reg_slave,
2105 .unreg_slave = stm32f7_i2c_unreg_slave,
2108 static int stm32f7_i2c_probe(struct platform_device *pdev)
2110 struct stm32f7_i2c_dev *i2c_dev;
2111 const struct stm32f7_i2c_setup *setup;
2112 struct resource *res;
2113 struct i2c_adapter *adap;
2114 struct reset_control *rst;
2115 dma_addr_t phy_addr;
2116 int irq_error, irq_event, ret;
2118 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
2122 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2123 if (IS_ERR(i2c_dev->base))
2124 return PTR_ERR(i2c_dev->base);
2125 phy_addr = (dma_addr_t)res->start;
2127 irq_event = platform_get_irq(pdev, 0);
2129 return irq_event ? : -ENOENT;
2131 irq_error = platform_get_irq(pdev, 1);
2133 return irq_error ? : -ENOENT;
2135 i2c_dev->wakeup_src = of_property_read_bool(pdev->dev.of_node,
2138 i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
2139 if (IS_ERR(i2c_dev->clk))
2140 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_dev->clk),
2141 "Failed to get controller clock\n");
2143 ret = clk_prepare_enable(i2c_dev->clk);
2145 dev_err(&pdev->dev, "Failed to prepare_enable clock\n");
2149 rst = devm_reset_control_get(&pdev->dev, NULL);
2151 ret = dev_err_probe(&pdev->dev, PTR_ERR(rst),
2152 "Error: Missing reset ctrl\n");
2155 reset_control_assert(rst);
2157 reset_control_deassert(rst);
2159 i2c_dev->dev = &pdev->dev;
2161 ret = devm_request_threaded_irq(&pdev->dev, irq_event,
2162 stm32f7_i2c_isr_event,
2163 stm32f7_i2c_isr_event_thread,
2165 pdev->name, i2c_dev);
2167 dev_err(&pdev->dev, "Failed to request irq event %i\n",
2172 ret = devm_request_irq(&pdev->dev, irq_error, stm32f7_i2c_isr_error, 0,
2173 pdev->name, i2c_dev);
2175 dev_err(&pdev->dev, "Failed to request irq error %i\n",
2180 setup = of_device_get_match_data(&pdev->dev);
2182 dev_err(&pdev->dev, "Can't get device data\n");
2186 i2c_dev->setup = *setup;
2188 ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup);
2192 /* Setup Fast mode plus if necessary */
2193 if (i2c_dev->bus_rate > I2C_MAX_FAST_MODE_FREQ) {
2194 ret = stm32f7_i2c_setup_fm_plus_bits(pdev, i2c_dev);
2197 ret = stm32f7_i2c_write_fm_plus_bits(i2c_dev, true);
2202 adap = &i2c_dev->adap;
2203 i2c_set_adapdata(adap, i2c_dev);
2204 snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)",
2206 adap->owner = THIS_MODULE;
2207 adap->timeout = 2 * HZ;
2209 adap->algo = &stm32f7_i2c_algo;
2210 adap->dev.parent = &pdev->dev;
2211 adap->dev.of_node = pdev->dev.of_node;
2213 init_completion(&i2c_dev->complete);
2215 /* Init DMA config if supported */
2216 i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr,
2219 if (IS_ERR(i2c_dev->dma)) {
2220 ret = PTR_ERR(i2c_dev->dma);
2221 /* DMA support is optional, only report other errors */
2224 dev_dbg(i2c_dev->dev, "No DMA option: fallback using interrupts\n");
2225 i2c_dev->dma = NULL;
2228 if (i2c_dev->wakeup_src) {
2229 device_set_wakeup_capable(i2c_dev->dev, true);
2231 ret = dev_pm_set_wake_irq(i2c_dev->dev, irq_event);
2233 dev_err(i2c_dev->dev, "Failed to set wake up irq\n");
2234 goto clr_wakeup_capable;
2238 platform_set_drvdata(pdev, i2c_dev);
2240 pm_runtime_set_autosuspend_delay(i2c_dev->dev,
2241 STM32F7_AUTOSUSPEND_DELAY);
2242 pm_runtime_use_autosuspend(i2c_dev->dev);
2243 pm_runtime_set_active(i2c_dev->dev);
2244 pm_runtime_enable(i2c_dev->dev);
2246 pm_runtime_get_noresume(&pdev->dev);
2248 stm32f7_i2c_hw_config(i2c_dev);
2250 i2c_dev->smbus_mode = of_property_read_bool(pdev->dev.of_node, "smbus");
2252 ret = i2c_add_adapter(adap);
2256 if (i2c_dev->smbus_mode) {
2257 ret = stm32f7_i2c_enable_smbus_host(i2c_dev);
2259 dev_err(i2c_dev->dev,
2260 "failed to enable SMBus Host-Notify protocol (%d)\n",
2262 goto i2c_adapter_remove;
2266 if (of_property_read_bool(pdev->dev.of_node, "smbus-alert")) {
2267 ret = stm32f7_i2c_enable_smbus_alert(i2c_dev);
2269 dev_err(i2c_dev->dev,
2270 "failed to enable SMBus alert protocol (%d)\n",
2272 goto i2c_disable_smbus_host;
2276 dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr);
2278 pm_runtime_mark_last_busy(i2c_dev->dev);
2279 pm_runtime_put_autosuspend(i2c_dev->dev);
2283 i2c_disable_smbus_host:
2284 stm32f7_i2c_disable_smbus_host(i2c_dev);
2287 i2c_del_adapter(adap);
2290 pm_runtime_put_noidle(i2c_dev->dev);
2291 pm_runtime_disable(i2c_dev->dev);
2292 pm_runtime_set_suspended(i2c_dev->dev);
2293 pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2295 if (i2c_dev->wakeup_src)
2296 dev_pm_clear_wake_irq(i2c_dev->dev);
2299 if (i2c_dev->wakeup_src)
2300 device_set_wakeup_capable(i2c_dev->dev, false);
2303 stm32_i2c_dma_free(i2c_dev->dma);
2304 i2c_dev->dma = NULL;
2308 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2311 clk_disable_unprepare(i2c_dev->clk);
2316 static int stm32f7_i2c_remove(struct platform_device *pdev)
2318 struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
2320 stm32f7_i2c_disable_smbus_alert(i2c_dev);
2321 stm32f7_i2c_disable_smbus_host(i2c_dev);
2323 i2c_del_adapter(&i2c_dev->adap);
2324 pm_runtime_get_sync(i2c_dev->dev);
2326 if (i2c_dev->wakeup_src) {
2327 dev_pm_clear_wake_irq(i2c_dev->dev);
2329 * enforce that wakeup is disabled and that the device
2330 * is marked as non wakeup capable
2332 device_init_wakeup(i2c_dev->dev, false);
2335 pm_runtime_put_noidle(i2c_dev->dev);
2336 pm_runtime_disable(i2c_dev->dev);
2337 pm_runtime_set_suspended(i2c_dev->dev);
2338 pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2341 stm32_i2c_dma_free(i2c_dev->dma);
2342 i2c_dev->dma = NULL;
2345 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2347 clk_disable_unprepare(i2c_dev->clk);
2352 static int __maybe_unused stm32f7_i2c_runtime_suspend(struct device *dev)
2354 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2356 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
2357 clk_disable_unprepare(i2c_dev->clk);
2362 static int __maybe_unused stm32f7_i2c_runtime_resume(struct device *dev)
2364 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2367 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
2368 ret = clk_prepare_enable(i2c_dev->clk);
2370 dev_err(dev, "failed to prepare_enable clock\n");
2378 static int __maybe_unused stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev *i2c_dev)
2381 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2383 ret = pm_runtime_resume_and_get(i2c_dev->dev);
2387 backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2388 backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
2389 backup_regs->oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
2390 backup_regs->oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
2391 backup_regs->tmgr = readl_relaxed(i2c_dev->base + STM32F7_I2C_TIMINGR);
2392 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2394 pm_runtime_put_sync(i2c_dev->dev);
2399 static int __maybe_unused stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev *i2c_dev)
2403 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2405 ret = pm_runtime_resume_and_get(i2c_dev->dev);
2409 cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2410 if (cr1 & STM32F7_I2C_CR1_PE)
2411 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
2412 STM32F7_I2C_CR1_PE);
2414 writel_relaxed(backup_regs->tmgr, i2c_dev->base + STM32F7_I2C_TIMINGR);
2415 writel_relaxed(backup_regs->cr1 & ~STM32F7_I2C_CR1_PE,
2416 i2c_dev->base + STM32F7_I2C_CR1);
2417 if (backup_regs->cr1 & STM32F7_I2C_CR1_PE)
2418 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
2419 STM32F7_I2C_CR1_PE);
2420 writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2);
2421 writel_relaxed(backup_regs->oar1, i2c_dev->base + STM32F7_I2C_OAR1);
2422 writel_relaxed(backup_regs->oar2, i2c_dev->base + STM32F7_I2C_OAR2);
2423 stm32f7_i2c_write_fm_plus_bits(i2c_dev, true);
2425 pm_runtime_put_sync(i2c_dev->dev);
2430 static int __maybe_unused stm32f7_i2c_suspend(struct device *dev)
2432 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2435 i2c_mark_adapter_suspended(&i2c_dev->adap);
2437 if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) {
2438 ret = stm32f7_i2c_regs_backup(i2c_dev);
2440 i2c_mark_adapter_resumed(&i2c_dev->adap);
2444 pinctrl_pm_select_sleep_state(dev);
2445 pm_runtime_force_suspend(dev);
2451 static int __maybe_unused stm32f7_i2c_resume(struct device *dev)
2453 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2456 if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) {
2457 ret = pm_runtime_force_resume(dev);
2460 pinctrl_pm_select_default_state(dev);
2462 ret = stm32f7_i2c_regs_restore(i2c_dev);
2467 i2c_mark_adapter_resumed(&i2c_dev->adap);
2472 static const struct dev_pm_ops stm32f7_i2c_pm_ops = {
2473 SET_RUNTIME_PM_OPS(stm32f7_i2c_runtime_suspend,
2474 stm32f7_i2c_runtime_resume, NULL)
2475 SET_SYSTEM_SLEEP_PM_OPS(stm32f7_i2c_suspend, stm32f7_i2c_resume)
2478 static const struct of_device_id stm32f7_i2c_match[] = {
2479 { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup},
2480 { .compatible = "st,stm32mp15-i2c", .data = &stm32mp15_setup},
2483 MODULE_DEVICE_TABLE(of, stm32f7_i2c_match);
2485 static struct platform_driver stm32f7_i2c_driver = {
2487 .name = "stm32f7-i2c",
2488 .of_match_table = stm32f7_i2c_match,
2489 .pm = &stm32f7_i2c_pm_ops,
2491 .probe = stm32f7_i2c_probe,
2492 .remove = stm32f7_i2c_remove,
2495 module_platform_driver(stm32f7_i2c_driver);
2497 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
2498 MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver");
2499 MODULE_LICENSE("GPL v2");