1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for STMicroelectronics STM32F7 I2C controller
5 * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc
7 * Please see below a link to the documentation:
8 * http://www.st.com/resource/en/reference_manual/dm00124865.pdf
10 * Copyright (C) M'boumba Cedric Madianga 2017
11 * Copyright (C) STMicroelectronics 2017
12 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
14 * This driver is based on i2c-stm32f4.c
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/i2c.h>
21 #include <linux/interrupt.h>
23 #include <linux/iopoll.h>
24 #include <linux/mfd/syscon.h>
25 #include <linux/module.h>
27 #include <linux/of_address.h>
28 #include <linux/of_platform.h>
29 #include <linux/platform_device.h>
30 #include <linux/pinctrl/consumer.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/regmap.h>
33 #include <linux/reset.h>
34 #include <linux/slab.h>
36 #include "i2c-stm32.h"
38 /* STM32F7 I2C registers */
39 #define STM32F7_I2C_CR1 0x00
40 #define STM32F7_I2C_CR2 0x04
41 #define STM32F7_I2C_OAR1 0x08
42 #define STM32F7_I2C_OAR2 0x0C
43 #define STM32F7_I2C_PECR 0x20
44 #define STM32F7_I2C_TIMINGR 0x10
45 #define STM32F7_I2C_ISR 0x18
46 #define STM32F7_I2C_ICR 0x1C
47 #define STM32F7_I2C_RXDR 0x24
48 #define STM32F7_I2C_TXDR 0x28
50 /* STM32F7 I2C control 1 */
51 #define STM32F7_I2C_CR1_PECEN BIT(23)
52 #define STM32F7_I2C_CR1_SBC BIT(16)
53 #define STM32F7_I2C_CR1_RXDMAEN BIT(15)
54 #define STM32F7_I2C_CR1_TXDMAEN BIT(14)
55 #define STM32F7_I2C_CR1_ANFOFF BIT(12)
56 #define STM32F7_I2C_CR1_ERRIE BIT(7)
57 #define STM32F7_I2C_CR1_TCIE BIT(6)
58 #define STM32F7_I2C_CR1_STOPIE BIT(5)
59 #define STM32F7_I2C_CR1_NACKIE BIT(4)
60 #define STM32F7_I2C_CR1_ADDRIE BIT(3)
61 #define STM32F7_I2C_CR1_RXIE BIT(2)
62 #define STM32F7_I2C_CR1_TXIE BIT(1)
63 #define STM32F7_I2C_CR1_PE BIT(0)
64 #define STM32F7_I2C_ALL_IRQ_MASK (STM32F7_I2C_CR1_ERRIE \
65 | STM32F7_I2C_CR1_TCIE \
66 | STM32F7_I2C_CR1_STOPIE \
67 | STM32F7_I2C_CR1_NACKIE \
68 | STM32F7_I2C_CR1_RXIE \
69 | STM32F7_I2C_CR1_TXIE)
70 #define STM32F7_I2C_XFER_IRQ_MASK (STM32F7_I2C_CR1_TCIE \
71 | STM32F7_I2C_CR1_STOPIE \
72 | STM32F7_I2C_CR1_NACKIE \
73 | STM32F7_I2C_CR1_RXIE \
74 | STM32F7_I2C_CR1_TXIE)
76 /* STM32F7 I2C control 2 */
77 #define STM32F7_I2C_CR2_PECBYTE BIT(26)
78 #define STM32F7_I2C_CR2_RELOAD BIT(24)
79 #define STM32F7_I2C_CR2_NBYTES_MASK GENMASK(23, 16)
80 #define STM32F7_I2C_CR2_NBYTES(n) (((n) & 0xff) << 16)
81 #define STM32F7_I2C_CR2_NACK BIT(15)
82 #define STM32F7_I2C_CR2_STOP BIT(14)
83 #define STM32F7_I2C_CR2_START BIT(13)
84 #define STM32F7_I2C_CR2_HEAD10R BIT(12)
85 #define STM32F7_I2C_CR2_ADD10 BIT(11)
86 #define STM32F7_I2C_CR2_RD_WRN BIT(10)
87 #define STM32F7_I2C_CR2_SADD10_MASK GENMASK(9, 0)
88 #define STM32F7_I2C_CR2_SADD10(n) (((n) & \
89 STM32F7_I2C_CR2_SADD10_MASK))
90 #define STM32F7_I2C_CR2_SADD7_MASK GENMASK(7, 1)
91 #define STM32F7_I2C_CR2_SADD7(n) (((n) & 0x7f) << 1)
93 /* STM32F7 I2C Own Address 1 */
94 #define STM32F7_I2C_OAR1_OA1EN BIT(15)
95 #define STM32F7_I2C_OAR1_OA1MODE BIT(10)
96 #define STM32F7_I2C_OAR1_OA1_10_MASK GENMASK(9, 0)
97 #define STM32F7_I2C_OAR1_OA1_10(n) (((n) & \
98 STM32F7_I2C_OAR1_OA1_10_MASK))
99 #define STM32F7_I2C_OAR1_OA1_7_MASK GENMASK(7, 1)
100 #define STM32F7_I2C_OAR1_OA1_7(n) (((n) & 0x7f) << 1)
101 #define STM32F7_I2C_OAR1_MASK (STM32F7_I2C_OAR1_OA1_7_MASK \
102 | STM32F7_I2C_OAR1_OA1_10_MASK \
103 | STM32F7_I2C_OAR1_OA1EN \
104 | STM32F7_I2C_OAR1_OA1MODE)
106 /* STM32F7 I2C Own Address 2 */
107 #define STM32F7_I2C_OAR2_OA2EN BIT(15)
108 #define STM32F7_I2C_OAR2_OA2MSK_MASK GENMASK(10, 8)
109 #define STM32F7_I2C_OAR2_OA2MSK(n) (((n) & 0x7) << 8)
110 #define STM32F7_I2C_OAR2_OA2_7_MASK GENMASK(7, 1)
111 #define STM32F7_I2C_OAR2_OA2_7(n) (((n) & 0x7f) << 1)
112 #define STM32F7_I2C_OAR2_MASK (STM32F7_I2C_OAR2_OA2MSK_MASK \
113 | STM32F7_I2C_OAR2_OA2_7_MASK \
114 | STM32F7_I2C_OAR2_OA2EN)
116 /* STM32F7 I2C Interrupt Status */
117 #define STM32F7_I2C_ISR_ADDCODE_MASK GENMASK(23, 17)
118 #define STM32F7_I2C_ISR_ADDCODE_GET(n) \
119 (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17)
120 #define STM32F7_I2C_ISR_DIR BIT(16)
121 #define STM32F7_I2C_ISR_BUSY BIT(15)
122 #define STM32F7_I2C_ISR_PECERR BIT(11)
123 #define STM32F7_I2C_ISR_ARLO BIT(9)
124 #define STM32F7_I2C_ISR_BERR BIT(8)
125 #define STM32F7_I2C_ISR_TCR BIT(7)
126 #define STM32F7_I2C_ISR_TC BIT(6)
127 #define STM32F7_I2C_ISR_STOPF BIT(5)
128 #define STM32F7_I2C_ISR_NACKF BIT(4)
129 #define STM32F7_I2C_ISR_ADDR BIT(3)
130 #define STM32F7_I2C_ISR_RXNE BIT(2)
131 #define STM32F7_I2C_ISR_TXIS BIT(1)
132 #define STM32F7_I2C_ISR_TXE BIT(0)
134 /* STM32F7 I2C Interrupt Clear */
135 #define STM32F7_I2C_ICR_PECCF BIT(11)
136 #define STM32F7_I2C_ICR_ARLOCF BIT(9)
137 #define STM32F7_I2C_ICR_BERRCF BIT(8)
138 #define STM32F7_I2C_ICR_STOPCF BIT(5)
139 #define STM32F7_I2C_ICR_NACKCF BIT(4)
140 #define STM32F7_I2C_ICR_ADDRCF BIT(3)
142 /* STM32F7 I2C Timing */
143 #define STM32F7_I2C_TIMINGR_PRESC(n) (((n) & 0xf) << 28)
144 #define STM32F7_I2C_TIMINGR_SCLDEL(n) (((n) & 0xf) << 20)
145 #define STM32F7_I2C_TIMINGR_SDADEL(n) (((n) & 0xf) << 16)
146 #define STM32F7_I2C_TIMINGR_SCLH(n) (((n) & 0xff) << 8)
147 #define STM32F7_I2C_TIMINGR_SCLL(n) ((n) & 0xff)
149 #define STM32F7_I2C_MAX_LEN 0xff
150 #define STM32F7_I2C_DMA_LEN_MIN 0x16
151 #define STM32F7_I2C_MAX_SLAVE 0x2
153 #define STM32F7_I2C_DNF_DEFAULT 0
154 #define STM32F7_I2C_DNF_MAX 16
156 #define STM32F7_I2C_ANALOG_FILTER_ENABLE 1
157 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */
158 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
160 #define STM32F7_I2C_RISE_TIME_DEFAULT 25 /* ns */
161 #define STM32F7_I2C_FALL_TIME_DEFAULT 10 /* ns */
163 #define STM32F7_PRESC_MAX BIT(4)
164 #define STM32F7_SCLDEL_MAX BIT(4)
165 #define STM32F7_SDADEL_MAX BIT(4)
166 #define STM32F7_SCLH_MAX BIT(8)
167 #define STM32F7_SCLL_MAX BIT(8)
169 #define STM32F7_AUTOSUSPEND_DELAY (HZ / 100)
172 * struct stm32f7_i2c_regs - i2c f7 registers backup
173 * @cr1: Control register 1
174 * @cr2: Control register 2
175 * @oar1: Own address 1 register
176 * @oar2: Own address 2 register
177 * @pecr: PEC register
178 * @tmgr: Timing register
180 struct stm32f7_i2c_regs {
190 * struct stm32f7_i2c_spec - private i2c specification timing
191 * @rate: I2C bus speed (Hz)
192 * @rate_min: 80% of I2C bus speed (Hz)
193 * @rate_max: 100% of I2C bus speed (Hz)
194 * @fall_max: Max fall time of both SDA and SCL signals (ns)
195 * @rise_max: Max rise time of both SDA and SCL signals (ns)
196 * @hddat_min: Min data hold time (ns)
197 * @vddat_max: Max data valid time (ns)
198 * @sudat_min: Min data setup time (ns)
199 * @l_min: Min low period of the SCL clock (ns)
200 * @h_min: Min high period of the SCL clock (ns)
202 struct stm32f7_i2c_spec {
216 * struct stm32f7_i2c_setup - private I2C timing setup parameters
217 * @speed: I2C speed mode (standard, Fast Plus)
218 * @speed_freq: I2C speed frequency (Hz)
219 * @clock_src: I2C clock source frequency (Hz)
220 * @rise_time: Rise time (ns)
221 * @fall_time: Fall time (ns)
222 * @dnf: Digital filter coefficient (0-16)
223 * @analog_filter: Analog filter delay (On/Off)
225 struct stm32f7_i2c_setup {
226 enum stm32_i2c_speed speed;
236 * struct stm32f7_i2c_timings - private I2C output parameters
238 * @presc: Prescaler value
239 * @scldel: Data setup time
240 * @sdadel: Data hold time
241 * @sclh: SCL high period (master mode)
242 * @scll: SCL low period (master mode)
244 struct stm32f7_i2c_timings {
245 struct list_head node;
254 * struct stm32f7_i2c_msg - client specific data
255 * @addr: 8-bit or 10-bit slave addr, including r/w bit
256 * @count: number of bytes to be transferred
258 * @result: result of the transfer
259 * @stop: last I2C msg to be sent, i.e. STOP to be generated
260 * @smbus: boolean to know if the I2C IP is used in SMBus mode
261 * @size: type of SMBus protocol
262 * @read_write: direction of SMBus protocol
263 * SMBus block read and SMBus block write - block read process call protocols
264 * @smbus_buf: buffer to be used for SMBus protocol transfer. It will
265 * contain a maximum of 32 bytes of data + byte command + byte count + PEC
266 * This buffer has to be 32-bit aligned to be compliant with memory address
267 * register in DMA mode.
269 struct stm32f7_i2c_msg {
278 u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4);
282 * struct stm32f7_i2c_dev - private data of the controller
283 * @adap: I2C adapter for this controller
284 * @dev: device for this controller
285 * @base: virtual memory area
286 * @complete: completion of I2C message
288 * @speed: I2C clock frequency of the controller. Standard, Fast or Fast+
289 * @msg: Pointer to data to be written
290 * @msg_num: number of I2C messages to be executed
291 * @msg_id: message identifiant
292 * @f7_msg: customized i2c msg for driver usage
293 * @setup: I2C timing input setup
294 * @timing: I2C computed timings
295 * @slave: list of slave devices registered on the I2C bus
296 * @slave_running: slave device currently used
297 * @backup_regs: backup of i2c controller registers (for suspend/resume)
298 * @slave_dir: transfer direction for the current slave device
299 * @master_mode: boolean to know in which mode the I2C is running (master or
302 * @use_dma: boolean to know if dma is used in the current transfer
303 * @regmap: holds SYSCFG phandle for Fast Mode Plus bits
305 struct stm32f7_i2c_dev {
306 struct i2c_adapter adap;
309 struct completion complete;
313 unsigned int msg_num;
315 struct stm32f7_i2c_msg f7_msg;
316 struct stm32f7_i2c_setup setup;
317 struct stm32f7_i2c_timings timing;
318 struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE];
319 struct i2c_client *slave_running;
320 struct stm32f7_i2c_regs backup_regs;
323 struct stm32_i2c_dma *dma;
325 struct regmap *regmap;
329 * All these values are coming from I2C Specification, Version 6.0, 4th of
332 * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast,
333 * and Fast-mode Plus I2C-bus devices
335 static struct stm32f7_i2c_spec i2c_specs[] = {
336 [STM32_I2C_SPEED_STANDARD] = {
348 [STM32_I2C_SPEED_FAST] = {
360 [STM32_I2C_SPEED_FAST_PLUS] = {
374 static const struct stm32f7_i2c_setup stm32f7_setup = {
375 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
376 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
377 .dnf = STM32F7_I2C_DNF_DEFAULT,
378 .analog_filter = STM32F7_I2C_ANALOG_FILTER_ENABLE,
381 static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask)
383 writel_relaxed(readl_relaxed(reg) | mask, reg);
386 static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask)
388 writel_relaxed(readl_relaxed(reg) & ~mask, reg);
391 static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)
393 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
396 static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev,
397 struct stm32f7_i2c_setup *setup,
398 struct stm32f7_i2c_timings *output)
400 u32 p_prev = STM32F7_PRESC_MAX;
401 u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
403 u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
405 u32 clk_error_prev = i2cbus;
407 u32 af_delay_min, af_delay_max;
409 u32 clk_min, clk_max;
410 int sdadel_min, sdadel_max;
412 struct stm32f7_i2c_timings *v, *_v, *s;
413 struct list_head solutions;
417 if (setup->speed >= STM32_I2C_SPEED_END) {
418 dev_err(i2c_dev->dev, "speed out of bound {%d/%d}\n",
419 setup->speed, STM32_I2C_SPEED_END - 1);
423 if ((setup->rise_time > i2c_specs[setup->speed].rise_max) ||
424 (setup->fall_time > i2c_specs[setup->speed].fall_max)) {
425 dev_err(i2c_dev->dev,
426 "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
427 setup->rise_time, i2c_specs[setup->speed].rise_max,
428 setup->fall_time, i2c_specs[setup->speed].fall_max);
432 if (setup->dnf > STM32F7_I2C_DNF_MAX) {
433 dev_err(i2c_dev->dev,
434 "DNF out of bound %d/%d\n",
435 setup->dnf, STM32F7_I2C_DNF_MAX);
439 if (setup->speed_freq > i2c_specs[setup->speed].rate) {
440 dev_err(i2c_dev->dev, "ERROR: Freq {%d/%d}\n",
441 setup->speed_freq, i2c_specs[setup->speed].rate);
445 /* Analog and Digital Filters */
447 (setup->analog_filter ?
448 STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0);
450 (setup->analog_filter ?
451 STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0);
452 dnf_delay = setup->dnf * i2cclk;
454 sdadel_min = i2c_specs[setup->speed].hddat_min + setup->fall_time -
455 af_delay_min - (setup->dnf + 3) * i2cclk;
457 sdadel_max = i2c_specs[setup->speed].vddat_max - setup->rise_time -
458 af_delay_max - (setup->dnf + 4) * i2cclk;
460 scldel_min = setup->rise_time + i2c_specs[setup->speed].sudat_min;
467 dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n",
468 sdadel_min, sdadel_max, scldel_min);
470 INIT_LIST_HEAD(&solutions);
471 /* Compute possible values for PRESC, SCLDEL and SDADEL */
472 for (p = 0; p < STM32F7_PRESC_MAX; p++) {
473 for (l = 0; l < STM32F7_SCLDEL_MAX; l++) {
474 u32 scldel = (l + 1) * (p + 1) * i2cclk;
476 if (scldel < scldel_min)
479 for (a = 0; a < STM32F7_SDADEL_MAX; a++) {
480 u32 sdadel = (a * (p + 1) + 1) * i2cclk;
482 if (((sdadel >= sdadel_min) &&
483 (sdadel <= sdadel_max)) &&
485 v = kmalloc(sizeof(*v), GFP_KERNEL);
496 list_add_tail(&v->node,
507 if (list_empty(&solutions)) {
508 dev_err(i2c_dev->dev, "no Prescaler solution\n");
513 tsync = af_delay_min + dnf_delay + (2 * i2cclk);
515 clk_max = NSEC_PER_SEC / i2c_specs[setup->speed].rate_min;
516 clk_min = NSEC_PER_SEC / i2c_specs[setup->speed].rate_max;
519 * Among Prescaler possibilities discovered above figures out SCL Low
520 * and High Period. Provided:
521 * - SCL Low Period has to be higher than SCL Clock Low Period
522 * defined by I2C Specification. I2C Clock has to be lower than
523 * (SCL Low Period - Analog/Digital filters) / 4.
524 * - SCL High Period has to be lower than SCL Clock High Period
525 * defined by I2C Specification
526 * - I2C Clock has to be lower than SCL High Period
528 list_for_each_entry(v, &solutions, node) {
529 u32 prescaler = (v->presc + 1) * i2cclk;
531 for (l = 0; l < STM32F7_SCLL_MAX; l++) {
532 u32 tscl_l = (l + 1) * prescaler + tsync;
534 if ((tscl_l < i2c_specs[setup->speed].l_min) ||
536 ((tscl_l - af_delay_min - dnf_delay) / 4))) {
540 for (h = 0; h < STM32F7_SCLH_MAX; h++) {
541 u32 tscl_h = (h + 1) * prescaler + tsync;
542 u32 tscl = tscl_l + tscl_h +
543 setup->rise_time + setup->fall_time;
545 if ((tscl >= clk_min) && (tscl <= clk_max) &&
546 (tscl_h >= i2c_specs[setup->speed].h_min) &&
548 int clk_error = tscl - i2cbus;
551 clk_error = -clk_error;
553 if (clk_error < clk_error_prev) {
554 clk_error_prev = clk_error;
565 dev_err(i2c_dev->dev, "no solution at all\n");
570 output->presc = s->presc;
571 output->scldel = s->scldel;
572 output->sdadel = s->sdadel;
573 output->scll = s->scll;
574 output->sclh = s->sclh;
576 dev_dbg(i2c_dev->dev,
577 "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
579 output->scldel, output->sdadel,
580 output->scll, output->sclh);
583 /* Release list and memory */
584 list_for_each_entry_safe(v, _v, &solutions, node) {
592 static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev,
593 struct stm32f7_i2c_setup *setup)
597 setup->speed = i2c_dev->speed;
598 setup->speed_freq = i2c_specs[setup->speed].rate;
599 setup->clock_src = clk_get_rate(i2c_dev->clk);
601 if (!setup->clock_src) {
602 dev_err(i2c_dev->dev, "clock rate is 0\n");
607 ret = stm32f7_i2c_compute_timing(i2c_dev, setup,
610 dev_err(i2c_dev->dev,
611 "failed to compute I2C timings.\n");
612 if (i2c_dev->speed > STM32_I2C_SPEED_STANDARD) {
614 setup->speed = i2c_dev->speed;
616 i2c_specs[setup->speed].rate;
617 dev_warn(i2c_dev->dev,
618 "downgrade I2C Speed Freq to (%i)\n",
619 i2c_specs[setup->speed].rate);
627 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n");
631 dev_dbg(i2c_dev->dev, "I2C Speed(%i), Freq(%i), Clk Source(%i)\n",
632 setup->speed, setup->speed_freq, setup->clock_src);
633 dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n",
634 setup->rise_time, setup->fall_time);
635 dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n",
636 (setup->analog_filter ? "On" : "Off"), setup->dnf);
641 static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev)
643 void __iomem *base = i2c_dev->base;
644 u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN;
646 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
649 static void stm32f7_i2c_dma_callback(void *arg)
651 struct stm32f7_i2c_dev *i2c_dev = (struct stm32f7_i2c_dev *)arg;
652 struct stm32_i2c_dma *dma = i2c_dev->dma;
653 struct device *dev = dma->chan_using->device->dev;
655 stm32f7_i2c_disable_dma_req(i2c_dev);
656 dma_unmap_single(dev, dma->dma_buf, dma->dma_len, dma->dma_data_dir);
657 complete(&dma->dma_complete);
660 static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev)
662 struct stm32f7_i2c_timings *t = &i2c_dev->timing;
665 /* Timing settings */
666 timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc);
667 timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel);
668 timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel);
669 timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh);
670 timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll);
671 writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR);
674 if (i2c_dev->setup.analog_filter)
675 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
676 STM32F7_I2C_CR1_ANFOFF);
678 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
679 STM32F7_I2C_CR1_ANFOFF);
680 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
684 static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev)
686 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
687 void __iomem *base = i2c_dev->base;
690 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR);
695 static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev)
697 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
698 void __iomem *base = i2c_dev->base;
701 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR);
704 /* Flush RX buffer has no data is expected */
705 readb_relaxed(base + STM32F7_I2C_RXDR);
709 static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev)
711 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
714 if (i2c_dev->use_dma)
715 f7_msg->count -= STM32F7_I2C_MAX_LEN;
717 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
719 cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK;
720 if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
721 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
723 cr2 &= ~STM32F7_I2C_CR2_RELOAD;
724 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
727 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
730 static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev)
732 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
737 * For I2C_SMBUS_BLOCK_DATA && I2C_SMBUS_BLOCK_PROC_CALL, the first
738 * data received inform us how many data will follow.
740 stm32f7_i2c_read_rx_data(i2c_dev);
743 * Update NBYTES with the value read to continue the transfer
745 val = f7_msg->buf - sizeof(u8);
746 f7_msg->count = *val;
747 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
748 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
749 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
750 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
753 static int stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap)
755 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
757 dev_info(i2c_dev->dev, "Trying to recover bus\n");
759 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
762 stm32f7_i2c_hw_config(i2c_dev);
767 static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev)
772 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR,
774 !(status & STM32F7_I2C_ISR_BUSY),
779 dev_info(i2c_dev->dev, "bus busy\n");
781 ret = stm32f7_i2c_release_bus(&i2c_dev->adap);
783 dev_err(i2c_dev->dev, "Failed to recover the bus (%d)\n", ret);
790 static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
793 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
794 void __iomem *base = i2c_dev->base;
798 f7_msg->addr = msg->addr;
799 f7_msg->buf = msg->buf;
800 f7_msg->count = msg->len;
802 f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1);
804 reinit_completion(&i2c_dev->complete);
806 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
807 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
809 /* Set transfer direction */
810 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
811 if (msg->flags & I2C_M_RD)
812 cr2 |= STM32F7_I2C_CR2_RD_WRN;
814 /* Set slave address */
815 cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10);
816 if (msg->flags & I2C_M_TEN) {
817 cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK;
818 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr);
819 cr2 |= STM32F7_I2C_CR2_ADD10;
821 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK;
822 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
825 /* Set nb bytes to transfer and reload if needed */
826 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
827 if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
828 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
829 cr2 |= STM32F7_I2C_CR2_RELOAD;
831 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
834 /* Enable NACK, STOP, error and transfer complete interrupts */
835 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
836 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
838 /* Clear DMA req and TX/RX interrupt */
839 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
840 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
842 /* Configure DMA or enable RX/TX interrupt */
843 i2c_dev->use_dma = false;
844 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
845 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
846 msg->flags & I2C_M_RD,
847 f7_msg->count, f7_msg->buf,
848 stm32f7_i2c_dma_callback,
851 i2c_dev->use_dma = true;
853 dev_warn(i2c_dev->dev, "can't use DMA\n");
856 if (!i2c_dev->use_dma) {
857 if (msg->flags & I2C_M_RD)
858 cr1 |= STM32F7_I2C_CR1_RXIE;
860 cr1 |= STM32F7_I2C_CR1_TXIE;
862 if (msg->flags & I2C_M_RD)
863 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
865 cr1 |= STM32F7_I2C_CR1_TXDMAEN;
868 /* Configure Start/Repeated Start */
869 cr2 |= STM32F7_I2C_CR2_START;
871 i2c_dev->master_mode = true;
873 /* Write configurations registers */
874 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
875 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
878 static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
879 unsigned short flags, u8 command,
880 union i2c_smbus_data *data)
882 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
883 struct device *dev = i2c_dev->dev;
884 void __iomem *base = i2c_dev->base;
889 reinit_completion(&i2c_dev->complete);
891 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
892 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
894 /* Set transfer direction */
895 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
896 if (f7_msg->read_write)
897 cr2 |= STM32F7_I2C_CR2_RD_WRN;
899 /* Set slave address */
900 cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK);
901 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
903 f7_msg->smbus_buf[0] = command;
904 switch (f7_msg->size) {
905 case I2C_SMBUS_QUICK:
913 case I2C_SMBUS_BYTE_DATA:
914 if (f7_msg->read_write) {
915 f7_msg->stop = false;
917 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
921 f7_msg->smbus_buf[1] = data->byte;
924 case I2C_SMBUS_WORD_DATA:
925 if (f7_msg->read_write) {
926 f7_msg->stop = false;
928 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
932 f7_msg->smbus_buf[1] = data->word & 0xff;
933 f7_msg->smbus_buf[2] = data->word >> 8;
936 case I2C_SMBUS_BLOCK_DATA:
937 if (f7_msg->read_write) {
938 f7_msg->stop = false;
940 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
943 if (data->block[0] > I2C_SMBUS_BLOCK_MAX ||
945 dev_err(dev, "Invalid block write size %d\n",
949 f7_msg->count = data->block[0] + 2;
950 for (i = 1; i < f7_msg->count; i++)
951 f7_msg->smbus_buf[i] = data->block[i - 1];
954 case I2C_SMBUS_PROC_CALL:
955 f7_msg->stop = false;
957 f7_msg->smbus_buf[1] = data->word & 0xff;
958 f7_msg->smbus_buf[2] = data->word >> 8;
959 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
960 f7_msg->read_write = I2C_SMBUS_READ;
962 case I2C_SMBUS_BLOCK_PROC_CALL:
963 f7_msg->stop = false;
964 if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) {
965 dev_err(dev, "Invalid block write size %d\n",
969 f7_msg->count = data->block[0] + 2;
970 for (i = 1; i < f7_msg->count; i++)
971 f7_msg->smbus_buf[i] = data->block[i - 1];
972 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
973 f7_msg->read_write = I2C_SMBUS_READ;
975 case I2C_SMBUS_I2C_BLOCK_DATA:
976 /* Rely on emulated i2c transfer (through master_xfer) */
979 dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size);
983 f7_msg->buf = f7_msg->smbus_buf;
986 if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) {
987 cr1 |= STM32F7_I2C_CR1_PECEN;
988 cr2 |= STM32F7_I2C_CR2_PECBYTE;
989 if (!f7_msg->read_write)
992 cr1 &= ~STM32F7_I2C_CR1_PECEN;
993 cr2 &= ~STM32F7_I2C_CR2_PECBYTE;
996 /* Set number of bytes to be transferred */
997 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
998 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1000 /* Enable NACK, STOP, error and transfer complete interrupts */
1001 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
1002 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
1004 /* Clear DMA req and TX/RX interrupt */
1005 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1006 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1008 /* Configure DMA or enable RX/TX interrupt */
1009 i2c_dev->use_dma = false;
1010 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
1011 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1012 cr2 & STM32F7_I2C_CR2_RD_WRN,
1013 f7_msg->count, f7_msg->buf,
1014 stm32f7_i2c_dma_callback,
1017 i2c_dev->use_dma = true;
1019 dev_warn(i2c_dev->dev, "can't use DMA\n");
1022 if (!i2c_dev->use_dma) {
1023 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1024 cr1 |= STM32F7_I2C_CR1_RXIE;
1026 cr1 |= STM32F7_I2C_CR1_TXIE;
1028 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1029 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1031 cr1 |= STM32F7_I2C_CR1_TXDMAEN;
1035 cr2 |= STM32F7_I2C_CR2_START;
1037 i2c_dev->master_mode = true;
1039 /* Write configurations registers */
1040 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1041 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1046 static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev)
1048 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1049 void __iomem *base = i2c_dev->base;
1053 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
1054 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
1056 /* Set transfer direction */
1057 cr2 |= STM32F7_I2C_CR2_RD_WRN;
1059 switch (f7_msg->size) {
1060 case I2C_SMBUS_BYTE_DATA:
1063 case I2C_SMBUS_WORD_DATA:
1064 case I2C_SMBUS_PROC_CALL:
1067 case I2C_SMBUS_BLOCK_DATA:
1068 case I2C_SMBUS_BLOCK_PROC_CALL:
1070 cr2 |= STM32F7_I2C_CR2_RELOAD;
1074 f7_msg->buf = f7_msg->smbus_buf;
1075 f7_msg->stop = true;
1077 /* Add one byte for PEC if needed */
1078 if (cr1 & STM32F7_I2C_CR1_PECEN)
1081 /* Set number of bytes to be transferred */
1082 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK);
1083 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1086 * Configure RX/TX interrupt:
1088 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE);
1089 cr1 |= STM32F7_I2C_CR1_RXIE;
1092 * Configure DMA or enable RX/TX interrupt:
1093 * For I2C_SMBUS_BLOCK_DATA and I2C_SMBUS_BLOCK_PROC_CALL we don't use
1094 * dma as we don't know in advance how many data will be received
1096 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1097 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1099 i2c_dev->use_dma = false;
1100 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN &&
1101 f7_msg->size != I2C_SMBUS_BLOCK_DATA &&
1102 f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) {
1103 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1104 cr2 & STM32F7_I2C_CR2_RD_WRN,
1105 f7_msg->count, f7_msg->buf,
1106 stm32f7_i2c_dma_callback,
1110 i2c_dev->use_dma = true;
1112 dev_warn(i2c_dev->dev, "can't use DMA\n");
1115 if (!i2c_dev->use_dma)
1116 cr1 |= STM32F7_I2C_CR1_RXIE;
1118 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1120 /* Configure Repeated Start */
1121 cr2 |= STM32F7_I2C_CR2_START;
1123 /* Write configurations registers */
1124 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1125 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1128 static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev)
1130 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1131 u8 count, internal_pec, received_pec;
1133 internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR);
1135 switch (f7_msg->size) {
1136 case I2C_SMBUS_BYTE:
1137 case I2C_SMBUS_BYTE_DATA:
1138 received_pec = f7_msg->smbus_buf[1];
1140 case I2C_SMBUS_WORD_DATA:
1141 case I2C_SMBUS_PROC_CALL:
1142 received_pec = f7_msg->smbus_buf[2];
1144 case I2C_SMBUS_BLOCK_DATA:
1145 case I2C_SMBUS_BLOCK_PROC_CALL:
1146 count = f7_msg->smbus_buf[0];
1147 received_pec = f7_msg->smbus_buf[count];
1150 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n");
1154 if (internal_pec != received_pec) {
1155 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n",
1156 internal_pec, received_pec);
1163 static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode)
1170 if (slave->flags & I2C_CLIENT_TEN) {
1172 * For 10-bit addr, addcode = 11110XY with
1173 * X = Bit 9 of slave address
1174 * Y = Bit 8 of slave address
1176 addr = slave->addr >> 8;
1178 if (addr == addcode)
1181 addr = slave->addr & 0x7f;
1182 if (addr == addcode)
1189 static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev)
1191 struct i2c_client *slave = i2c_dev->slave_running;
1192 void __iomem *base = i2c_dev->base;
1196 if (i2c_dev->slave_dir) {
1197 /* Notify i2c slave that new read transfer is starting */
1198 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
1201 * Disable slave TX config in case of I2C combined message
1202 * (I2C Write followed by I2C Read)
1204 mask = STM32F7_I2C_CR2_RELOAD;
1205 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask);
1206 mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1207 STM32F7_I2C_CR1_TCIE;
1208 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1210 /* Enable TX empty, STOP, NACK interrupts */
1211 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1212 STM32F7_I2C_CR1_TXIE;
1213 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1215 /* Write 1st data byte */
1216 writel_relaxed(value, base + STM32F7_I2C_TXDR);
1218 /* Notify i2c slave that new write transfer is starting */
1219 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
1221 /* Set reload mode to be able to ACK/NACK each received byte */
1222 mask = STM32F7_I2C_CR2_RELOAD;
1223 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1226 * Set STOP, NACK, RX empty and transfer complete interrupts.*
1227 * Set Slave Byte Control to be able to ACK/NACK each data
1230 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1231 STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1232 STM32F7_I2C_CR1_TCIE;
1233 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1237 static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev)
1239 void __iomem *base = i2c_dev->base;
1240 u32 isr, addcode, dir, mask;
1243 isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1244 addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr);
1245 dir = isr & STM32F7_I2C_ISR_DIR;
1247 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1248 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) {
1249 i2c_dev->slave_running = i2c_dev->slave[i];
1250 i2c_dev->slave_dir = dir;
1252 /* Start I2C slave processing */
1253 stm32f7_i2c_slave_start(i2c_dev);
1255 /* Clear ADDR flag */
1256 mask = STM32F7_I2C_ICR_ADDRCF;
1257 writel_relaxed(mask, base + STM32F7_I2C_ICR);
1263 static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1264 struct i2c_client *slave, int *id)
1268 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1269 if (i2c_dev->slave[i] == slave) {
1275 dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr);
1280 static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1281 struct i2c_client *slave, int *id)
1283 struct device *dev = i2c_dev->dev;
1287 * slave[0] supports 7-bit and 10-bit slave address
1288 * slave[1] supports 7-bit slave address only
1290 for (i = STM32F7_I2C_MAX_SLAVE - 1; i >= 0; i--) {
1291 if (i == 1 && (slave->flags & I2C_CLIENT_TEN))
1293 if (!i2c_dev->slave[i]) {
1299 dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr);
1304 static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev)
1308 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1309 if (i2c_dev->slave[i])
1316 static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev)
1321 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1322 if (i2c_dev->slave[i])
1329 static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev)
1331 void __iomem *base = i2c_dev->base;
1332 u32 cr2, status, mask;
1336 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1338 /* Slave transmitter mode */
1339 if (status & STM32F7_I2C_ISR_TXIS) {
1340 i2c_slave_event(i2c_dev->slave_running,
1341 I2C_SLAVE_READ_PROCESSED,
1344 /* Write data byte */
1345 writel_relaxed(val, base + STM32F7_I2C_TXDR);
1348 /* Transfer Complete Reload for Slave receiver mode */
1349 if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) {
1351 * Read data byte then set NBYTES to receive next byte or NACK
1352 * the current received byte
1354 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR);
1355 ret = i2c_slave_event(i2c_dev->slave_running,
1356 I2C_SLAVE_WRITE_RECEIVED,
1359 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
1360 cr2 |= STM32F7_I2C_CR2_NBYTES(1);
1361 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
1363 mask = STM32F7_I2C_CR2_NACK;
1364 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1369 if (status & STM32F7_I2C_ISR_NACKF) {
1370 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1371 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1375 if (status & STM32F7_I2C_ISR_STOPF) {
1376 /* Disable interrupts */
1377 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK);
1379 if (i2c_dev->slave_dir) {
1381 * Flush TX buffer in order to not used the byte in
1382 * TXDR for the next transfer
1384 mask = STM32F7_I2C_ISR_TXE;
1385 stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask);
1388 /* Clear STOP flag */
1389 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1391 /* Notify i2c slave that a STOP flag has been detected */
1392 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val);
1394 i2c_dev->slave_running = NULL;
1397 /* Address match received */
1398 if (status & STM32F7_I2C_ISR_ADDR)
1399 stm32f7_i2c_slave_addr(i2c_dev);
1404 static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
1406 struct stm32f7_i2c_dev *i2c_dev = data;
1407 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1408 void __iomem *base = i2c_dev->base;
1410 int ret = IRQ_HANDLED;
1412 /* Check if the interrupt if for a slave device */
1413 if (!i2c_dev->master_mode) {
1414 ret = stm32f7_i2c_slave_isr_event(i2c_dev);
1418 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1421 if (status & STM32F7_I2C_ISR_TXIS)
1422 stm32f7_i2c_write_tx_data(i2c_dev);
1425 if (status & STM32F7_I2C_ISR_RXNE)
1426 stm32f7_i2c_read_rx_data(i2c_dev);
1429 if (status & STM32F7_I2C_ISR_NACKF) {
1430 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1431 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1432 f7_msg->result = -ENXIO;
1435 /* STOP detection flag */
1436 if (status & STM32F7_I2C_ISR_STOPF) {
1437 /* Disable interrupts */
1438 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1439 mask = STM32F7_I2C_XFER_IRQ_MASK;
1441 mask = STM32F7_I2C_ALL_IRQ_MASK;
1442 stm32f7_i2c_disable_irq(i2c_dev, mask);
1444 /* Clear STOP flag */
1445 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1447 if (i2c_dev->use_dma) {
1448 ret = IRQ_WAKE_THREAD;
1450 i2c_dev->master_mode = false;
1451 complete(&i2c_dev->complete);
1455 /* Transfer complete */
1456 if (status & STM32F7_I2C_ISR_TC) {
1458 mask = STM32F7_I2C_CR2_STOP;
1459 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1460 } else if (i2c_dev->use_dma) {
1461 ret = IRQ_WAKE_THREAD;
1462 } else if (f7_msg->smbus) {
1463 stm32f7_i2c_smbus_rep_start(i2c_dev);
1467 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1471 if (status & STM32F7_I2C_ISR_TCR) {
1473 stm32f7_i2c_smbus_reload(i2c_dev);
1475 stm32f7_i2c_reload(i2c_dev);
1481 static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data)
1483 struct stm32f7_i2c_dev *i2c_dev = data;
1484 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1485 struct stm32_i2c_dma *dma = i2c_dev->dma;
1490 * Wait for dma transfer completion before sending next message or
1491 * notity the end of xfer to the client
1493 ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ);
1495 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__);
1496 stm32f7_i2c_disable_dma_req(i2c_dev);
1497 dmaengine_terminate_all(dma->chan_using);
1498 f7_msg->result = -ETIMEDOUT;
1501 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1503 if (status & STM32F7_I2C_ISR_TC) {
1504 if (f7_msg->smbus) {
1505 stm32f7_i2c_smbus_rep_start(i2c_dev);
1509 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1512 i2c_dev->master_mode = false;
1513 complete(&i2c_dev->complete);
1519 static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data)
1521 struct stm32f7_i2c_dev *i2c_dev = data;
1522 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1523 void __iomem *base = i2c_dev->base;
1524 struct device *dev = i2c_dev->dev;
1525 struct stm32_i2c_dma *dma = i2c_dev->dma;
1528 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1531 if (status & STM32F7_I2C_ISR_BERR) {
1532 dev_err(dev, "<%s>: Bus error\n", __func__);
1533 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR);
1534 stm32f7_i2c_release_bus(&i2c_dev->adap);
1535 f7_msg->result = -EIO;
1538 /* Arbitration loss */
1539 if (status & STM32F7_I2C_ISR_ARLO) {
1540 dev_dbg(dev, "<%s>: Arbitration loss\n", __func__);
1541 writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR);
1542 f7_msg->result = -EAGAIN;
1545 if (status & STM32F7_I2C_ISR_PECERR) {
1546 dev_err(dev, "<%s>: PEC error in reception\n", __func__);
1547 writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR);
1548 f7_msg->result = -EINVAL;
1551 if (!i2c_dev->slave_running) {
1553 /* Disable interrupts */
1554 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1555 mask = STM32F7_I2C_XFER_IRQ_MASK;
1557 mask = STM32F7_I2C_ALL_IRQ_MASK;
1558 stm32f7_i2c_disable_irq(i2c_dev, mask);
1562 if (i2c_dev->use_dma) {
1563 stm32f7_i2c_disable_dma_req(i2c_dev);
1564 dmaengine_terminate_all(dma->chan_using);
1567 i2c_dev->master_mode = false;
1568 complete(&i2c_dev->complete);
1573 static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap,
1574 struct i2c_msg msgs[], int num)
1576 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
1577 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1578 struct stm32_i2c_dma *dma = i2c_dev->dma;
1579 unsigned long time_left;
1582 i2c_dev->msg = msgs;
1583 i2c_dev->msg_num = num;
1584 i2c_dev->msg_id = 0;
1585 f7_msg->smbus = false;
1587 ret = pm_runtime_get_sync(i2c_dev->dev);
1591 ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1595 stm32f7_i2c_xfer_msg(i2c_dev, msgs);
1597 time_left = wait_for_completion_timeout(&i2c_dev->complete,
1598 i2c_dev->adap.timeout);
1599 ret = f7_msg->result;
1602 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n",
1603 i2c_dev->msg->addr);
1604 if (i2c_dev->use_dma)
1605 dmaengine_terminate_all(dma->chan_using);
1610 pm_runtime_mark_last_busy(i2c_dev->dev);
1611 pm_runtime_put_autosuspend(i2c_dev->dev);
1613 return (ret < 0) ? ret : num;
1616 static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
1617 unsigned short flags, char read_write,
1618 u8 command, int size,
1619 union i2c_smbus_data *data)
1621 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter);
1622 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1623 struct stm32_i2c_dma *dma = i2c_dev->dma;
1624 struct device *dev = i2c_dev->dev;
1625 unsigned long timeout;
1628 f7_msg->addr = addr;
1629 f7_msg->size = size;
1630 f7_msg->read_write = read_write;
1631 f7_msg->smbus = true;
1633 ret = pm_runtime_get_sync(dev);
1637 ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1641 ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data);
1645 timeout = wait_for_completion_timeout(&i2c_dev->complete,
1646 i2c_dev->adap.timeout);
1647 ret = f7_msg->result;
1652 dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr);
1653 if (i2c_dev->use_dma)
1654 dmaengine_terminate_all(dma->chan_using);
1660 if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) {
1661 ret = stm32f7_i2c_smbus_check_pec(i2c_dev);
1666 if (read_write && size != I2C_SMBUS_QUICK) {
1668 case I2C_SMBUS_BYTE:
1669 case I2C_SMBUS_BYTE_DATA:
1670 data->byte = f7_msg->smbus_buf[0];
1672 case I2C_SMBUS_WORD_DATA:
1673 case I2C_SMBUS_PROC_CALL:
1674 data->word = f7_msg->smbus_buf[0] |
1675 (f7_msg->smbus_buf[1] << 8);
1677 case I2C_SMBUS_BLOCK_DATA:
1678 case I2C_SMBUS_BLOCK_PROC_CALL:
1679 for (i = 0; i <= f7_msg->smbus_buf[0]; i++)
1680 data->block[i] = f7_msg->smbus_buf[i];
1683 dev_err(dev, "Unsupported smbus transaction\n");
1689 pm_runtime_mark_last_busy(dev);
1690 pm_runtime_put_autosuspend(dev);
1694 static int stm32f7_i2c_reg_slave(struct i2c_client *slave)
1696 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1697 void __iomem *base = i2c_dev->base;
1698 struct device *dev = i2c_dev->dev;
1699 u32 oar1, oar2, mask;
1702 if (slave->flags & I2C_CLIENT_PEC) {
1703 dev_err(dev, "SMBus PEC not supported in slave mode\n");
1707 if (stm32f7_i2c_is_slave_busy(i2c_dev)) {
1708 dev_err(dev, "Too much slave registered\n");
1712 ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id);
1716 ret = pm_runtime_get_sync(dev);
1721 /* Configure Own Address 1 */
1722 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
1723 oar1 &= ~STM32F7_I2C_OAR1_MASK;
1724 if (slave->flags & I2C_CLIENT_TEN) {
1725 oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr);
1726 oar1 |= STM32F7_I2C_OAR1_OA1MODE;
1728 oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr);
1730 oar1 |= STM32F7_I2C_OAR1_OA1EN;
1731 i2c_dev->slave[id] = slave;
1732 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1);
1733 } else if (id == 1) {
1734 /* Configure Own Address 2 */
1735 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
1736 oar2 &= ~STM32F7_I2C_OAR2_MASK;
1737 if (slave->flags & I2C_CLIENT_TEN) {
1742 oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr);
1743 oar2 |= STM32F7_I2C_OAR2_OA2EN;
1744 i2c_dev->slave[id] = slave;
1745 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2);
1752 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK);
1754 /* Enable Address match interrupt, error interrupt and enable I2C */
1755 mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE |
1757 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1761 pm_runtime_mark_last_busy(dev);
1762 pm_runtime_put_autosuspend(dev);
1767 static int stm32f7_i2c_unreg_slave(struct i2c_client *slave)
1769 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1770 void __iomem *base = i2c_dev->base;
1774 ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id);
1778 WARN_ON(!i2c_dev->slave[id]);
1780 ret = pm_runtime_get_sync(i2c_dev->dev);
1785 mask = STM32F7_I2C_OAR1_OA1EN;
1786 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask);
1788 mask = STM32F7_I2C_OAR2_OA2EN;
1789 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask);
1792 i2c_dev->slave[id] = NULL;
1794 if (!(stm32f7_i2c_is_slave_registered(i2c_dev)))
1795 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
1797 pm_runtime_mark_last_busy(i2c_dev->dev);
1798 pm_runtime_put_autosuspend(i2c_dev->dev);
1803 static int stm32f7_i2c_setup_fm_plus_bits(struct platform_device *pdev,
1804 struct stm32f7_i2c_dev *i2c_dev)
1806 struct device_node *np = pdev->dev.of_node;
1810 i2c_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg-fmp");
1811 if (IS_ERR(i2c_dev->regmap)) {
1816 ret = of_property_read_u32_index(np, "st,syscfg-fmp", 1, ®);
1820 ret = of_property_read_u32_index(np, "st,syscfg-fmp", 2, &mask);
1824 return regmap_update_bits(i2c_dev->regmap, reg, mask, mask);
1827 static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
1829 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE |
1830 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
1831 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
1832 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
1833 I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC |
1834 I2C_FUNC_SMBUS_I2C_BLOCK;
1837 static const struct i2c_algorithm stm32f7_i2c_algo = {
1838 .master_xfer = stm32f7_i2c_xfer,
1839 .smbus_xfer = stm32f7_i2c_smbus_xfer,
1840 .functionality = stm32f7_i2c_func,
1841 .reg_slave = stm32f7_i2c_reg_slave,
1842 .unreg_slave = stm32f7_i2c_unreg_slave,
1845 static int stm32f7_i2c_probe(struct platform_device *pdev)
1847 struct stm32f7_i2c_dev *i2c_dev;
1848 const struct stm32f7_i2c_setup *setup;
1849 struct resource *res;
1850 u32 clk_rate, rise_time, fall_time;
1851 struct i2c_adapter *adap;
1852 struct reset_control *rst;
1853 dma_addr_t phy_addr;
1854 int irq_error, irq_event, ret;
1856 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
1860 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1861 i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
1862 if (IS_ERR(i2c_dev->base))
1863 return PTR_ERR(i2c_dev->base);
1864 phy_addr = (dma_addr_t)res->start;
1866 irq_event = platform_get_irq(pdev, 0);
1867 if (irq_event <= 0) {
1868 if (irq_event != -EPROBE_DEFER)
1869 dev_err(&pdev->dev, "Failed to get IRQ event: %d\n",
1871 return irq_event ? : -ENOENT;
1874 irq_error = platform_get_irq(pdev, 1);
1875 if (irq_error <= 0) {
1876 if (irq_error != -EPROBE_DEFER)
1877 dev_err(&pdev->dev, "Failed to get IRQ error: %d\n",
1879 return irq_error ? : -ENOENT;
1882 i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
1883 if (IS_ERR(i2c_dev->clk)) {
1884 dev_err(&pdev->dev, "Error: Missing controller clock\n");
1885 return PTR_ERR(i2c_dev->clk);
1888 ret = clk_prepare_enable(i2c_dev->clk);
1890 dev_err(&pdev->dev, "Failed to prepare_enable clock\n");
1894 i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
1895 ret = device_property_read_u32(&pdev->dev, "clock-frequency",
1897 if (!ret && clk_rate >= 1000000) {
1898 i2c_dev->speed = STM32_I2C_SPEED_FAST_PLUS;
1899 ret = stm32f7_i2c_setup_fm_plus_bits(pdev, i2c_dev);
1902 } else if (!ret && clk_rate >= 400000) {
1903 i2c_dev->speed = STM32_I2C_SPEED_FAST;
1904 } else if (!ret && clk_rate >= 100000) {
1905 i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
1908 rst = devm_reset_control_get(&pdev->dev, NULL);
1910 dev_err(&pdev->dev, "Error: Missing controller reset\n");
1914 reset_control_assert(rst);
1916 reset_control_deassert(rst);
1918 i2c_dev->dev = &pdev->dev;
1920 ret = devm_request_threaded_irq(&pdev->dev, irq_event,
1921 stm32f7_i2c_isr_event,
1922 stm32f7_i2c_isr_event_thread,
1924 pdev->name, i2c_dev);
1926 dev_err(&pdev->dev, "Failed to request irq event %i\n",
1931 ret = devm_request_irq(&pdev->dev, irq_error, stm32f7_i2c_isr_error, 0,
1932 pdev->name, i2c_dev);
1934 dev_err(&pdev->dev, "Failed to request irq error %i\n",
1939 setup = of_device_get_match_data(&pdev->dev);
1941 dev_err(&pdev->dev, "Can't get device data\n");
1945 i2c_dev->setup = *setup;
1947 ret = device_property_read_u32(i2c_dev->dev, "i2c-scl-rising-time-ns",
1950 i2c_dev->setup.rise_time = rise_time;
1952 ret = device_property_read_u32(i2c_dev->dev, "i2c-scl-falling-time-ns",
1955 i2c_dev->setup.fall_time = fall_time;
1957 ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup);
1961 adap = &i2c_dev->adap;
1962 i2c_set_adapdata(adap, i2c_dev);
1963 snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)",
1965 adap->owner = THIS_MODULE;
1966 adap->timeout = 2 * HZ;
1968 adap->algo = &stm32f7_i2c_algo;
1969 adap->dev.parent = &pdev->dev;
1970 adap->dev.of_node = pdev->dev.of_node;
1972 init_completion(&i2c_dev->complete);
1974 /* Init DMA config if supported */
1975 i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr,
1978 if (PTR_ERR(i2c_dev->dma) == -ENODEV)
1979 i2c_dev->dma = NULL;
1980 else if (IS_ERR(i2c_dev->dma)) {
1981 ret = PTR_ERR(i2c_dev->dma);
1982 if (ret != -EPROBE_DEFER)
1984 "Failed to request dma error %i\n", ret);
1988 platform_set_drvdata(pdev, i2c_dev);
1990 pm_runtime_set_autosuspend_delay(i2c_dev->dev,
1991 STM32F7_AUTOSUSPEND_DELAY);
1992 pm_runtime_use_autosuspend(i2c_dev->dev);
1993 pm_runtime_set_active(i2c_dev->dev);
1994 pm_runtime_enable(i2c_dev->dev);
1996 pm_runtime_get_noresume(&pdev->dev);
1998 stm32f7_i2c_hw_config(i2c_dev);
2000 ret = i2c_add_adapter(adap);
2004 dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr);
2006 pm_runtime_mark_last_busy(i2c_dev->dev);
2007 pm_runtime_put_autosuspend(i2c_dev->dev);
2012 pm_runtime_put_noidle(i2c_dev->dev);
2013 pm_runtime_disable(i2c_dev->dev);
2014 pm_runtime_set_suspended(i2c_dev->dev);
2015 pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2018 stm32_i2c_dma_free(i2c_dev->dma);
2019 i2c_dev->dma = NULL;
2023 clk_disable_unprepare(i2c_dev->clk);
2028 static int stm32f7_i2c_remove(struct platform_device *pdev)
2030 struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
2032 i2c_del_adapter(&i2c_dev->adap);
2033 pm_runtime_get_sync(i2c_dev->dev);
2035 pm_runtime_put_noidle(i2c_dev->dev);
2036 pm_runtime_disable(i2c_dev->dev);
2037 pm_runtime_set_suspended(i2c_dev->dev);
2038 pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2041 stm32_i2c_dma_free(i2c_dev->dma);
2042 i2c_dev->dma = NULL;
2045 clk_disable_unprepare(i2c_dev->clk);
2050 static int __maybe_unused stm32f7_i2c_runtime_suspend(struct device *dev)
2052 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2054 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
2055 clk_disable_unprepare(i2c_dev->clk);
2060 static int __maybe_unused stm32f7_i2c_runtime_resume(struct device *dev)
2062 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2065 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
2066 ret = clk_prepare_enable(i2c_dev->clk);
2068 dev_err(dev, "failed to prepare_enable clock\n");
2076 static int __maybe_unused
2077 stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev *i2c_dev)
2080 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2082 ret = pm_runtime_get_sync(i2c_dev->dev);
2086 backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2087 backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
2088 backup_regs->oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
2089 backup_regs->oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
2090 backup_regs->pecr = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR);
2091 backup_regs->tmgr = readl_relaxed(i2c_dev->base + STM32F7_I2C_TIMINGR);
2093 pm_runtime_put_sync(i2c_dev->dev);
2098 static int __maybe_unused
2099 stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev *i2c_dev)
2103 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2105 ret = pm_runtime_get_sync(i2c_dev->dev);
2109 cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2110 if (cr1 & STM32F7_I2C_CR1_PE)
2111 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
2112 STM32F7_I2C_CR1_PE);
2114 writel_relaxed(backup_regs->tmgr, i2c_dev->base + STM32F7_I2C_TIMINGR);
2115 writel_relaxed(backup_regs->cr1 & ~STM32F7_I2C_CR1_PE,
2116 i2c_dev->base + STM32F7_I2C_CR1);
2117 if (backup_regs->cr1 & STM32F7_I2C_CR1_PE)
2118 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
2119 STM32F7_I2C_CR1_PE);
2120 writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2);
2121 writel_relaxed(backup_regs->oar1, i2c_dev->base + STM32F7_I2C_OAR1);
2122 writel_relaxed(backup_regs->oar2, i2c_dev->base + STM32F7_I2C_OAR2);
2123 writel_relaxed(backup_regs->pecr, i2c_dev->base + STM32F7_I2C_PECR);
2125 pm_runtime_put_sync(i2c_dev->dev);
2130 static int __maybe_unused stm32f7_i2c_suspend(struct device *dev)
2132 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2135 i2c_mark_adapter_suspended(&i2c_dev->adap);
2136 ret = stm32f7_i2c_regs_backup(i2c_dev);
2138 i2c_mark_adapter_resumed(&i2c_dev->adap);
2142 pinctrl_pm_select_sleep_state(dev);
2143 pm_runtime_force_suspend(dev);
2148 static int __maybe_unused stm32f7_i2c_resume(struct device *dev)
2150 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2153 ret = pm_runtime_force_resume(dev);
2156 pinctrl_pm_select_default_state(dev);
2158 ret = stm32f7_i2c_regs_restore(i2c_dev);
2161 i2c_mark_adapter_resumed(&i2c_dev->adap);
2166 static const struct dev_pm_ops stm32f7_i2c_pm_ops = {
2167 SET_RUNTIME_PM_OPS(stm32f7_i2c_runtime_suspend,
2168 stm32f7_i2c_runtime_resume, NULL)
2169 SET_SYSTEM_SLEEP_PM_OPS(stm32f7_i2c_suspend, stm32f7_i2c_resume)
2172 static const struct of_device_id stm32f7_i2c_match[] = {
2173 { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup},
2176 MODULE_DEVICE_TABLE(of, stm32f7_i2c_match);
2178 static struct platform_driver stm32f7_i2c_driver = {
2180 .name = "stm32f7-i2c",
2181 .of_match_table = stm32f7_i2c_match,
2182 .pm = &stm32f7_i2c_pm_ops,
2184 .probe = stm32f7_i2c_probe,
2185 .remove = stm32f7_i2c_remove,
2188 module_platform_driver(stm32f7_i2c_driver);
2190 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
2191 MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver");
2192 MODULE_LICENSE("GPL v2");