drivers/i2c/busses/i2c-stm32f7.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for STMicroelectronics STM32F7 I2C controller
   4  *
   5  * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc
   6  * reference manual.
   7  * Please see below a link to the documentation:
   8  * http://www.st.com/resource/en/reference_manual/dm00124865.pdf
   9  *
  10  * Copyright (C) M'boumba Cedric Madianga 2017
  11  * Copyright (C) STMicroelectronics 2017
  12  * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
  13  *
  14  * This driver is based on i2c-stm32f4.c
  15  *
  16  */
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/err.h>
  20 #include <linux/i2c.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/io.h>
  23 #include <linux/iopoll.h>
  24 #include <linux/mfd/syscon.h>
  25 #include <linux/module.h>
  26 #include <linux/of.h>
  27 #include <linux/of_address.h>
  28 #include <linux/of_platform.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/pinctrl/consumer.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/pm_wakeirq.h>
  33 #include <linux/regmap.h>
  34 #include <linux/reset.h>
  35 #include <linux/slab.h>
  36
  37 #include "i2c-stm32.h"
  38
  39 /* STM32F7 I2C registers */
  40 #define STM32F7_I2C_CR1                         0x00
  41 #define STM32F7_I2C_CR2                         0x04
  42 #define STM32F7_I2C_OAR1                        0x08
  43 #define STM32F7_I2C_OAR2                        0x0C
  44 #define STM32F7_I2C_PECR                        0x20
  45 #define STM32F7_I2C_TIMINGR                     0x10
  46 #define STM32F7_I2C_ISR                         0x18
  47 #define STM32F7_I2C_ICR                         0x1C
  48 #define STM32F7_I2C_RXDR                        0x24
  49 #define STM32F7_I2C_TXDR                        0x28
  50
  51 /* STM32F7 I2C control 1 */
  52 #define STM32F7_I2C_CR1_PECEN                   BIT(23)
  53 #define STM32F7_I2C_CR1_WUPEN                   BIT(18)
  54 #define STM32F7_I2C_CR1_SBC                     BIT(16)
  55 #define STM32F7_I2C_CR1_RXDMAEN                 BIT(15)
  56 #define STM32F7_I2C_CR1_TXDMAEN                 BIT(14)
  57 #define STM32F7_I2C_CR1_ANFOFF                  BIT(12)
  58 #define STM32F7_I2C_CR1_ERRIE                   BIT(7)
  59 #define STM32F7_I2C_CR1_TCIE                    BIT(6)
  60 #define STM32F7_I2C_CR1_STOPIE                  BIT(5)
  61 #define STM32F7_I2C_CR1_NACKIE                  BIT(4)
  62 #define STM32F7_I2C_CR1_ADDRIE                  BIT(3)
  63 #define STM32F7_I2C_CR1_RXIE                    BIT(2)
  64 #define STM32F7_I2C_CR1_TXIE                    BIT(1)
  65 #define STM32F7_I2C_CR1_PE                      BIT(0)
  66 #define STM32F7_I2C_ALL_IRQ_MASK                (STM32F7_I2C_CR1_ERRIE \
  67                                                 | STM32F7_I2C_CR1_TCIE \
  68                                                 | STM32F7_I2C_CR1_STOPIE \
  69                                                 | STM32F7_I2C_CR1_NACKIE \
  70                                                 | STM32F7_I2C_CR1_RXIE \
  71                                                 | STM32F7_I2C_CR1_TXIE)
  72 #define STM32F7_I2C_XFER_IRQ_MASK               (STM32F7_I2C_CR1_TCIE \
  73                                                 | STM32F7_I2C_CR1_STOPIE \
  74                                                 | STM32F7_I2C_CR1_NACKIE \
  75                                                 | STM32F7_I2C_CR1_RXIE \
  76                                                 | STM32F7_I2C_CR1_TXIE)
  77
  78 /* STM32F7 I2C control 2 */
  79 #define STM32F7_I2C_CR2_PECBYTE                 BIT(26)
  80 #define STM32F7_I2C_CR2_RELOAD                  BIT(24)
  81 #define STM32F7_I2C_CR2_NBYTES_MASK             GENMASK(23, 16)
  82 #define STM32F7_I2C_CR2_NBYTES(n)               (((n) & 0xff) << 16)
  83 #define STM32F7_I2C_CR2_NACK                    BIT(15)
  84 #define STM32F7_I2C_CR2_STOP                    BIT(14)
  85 #define STM32F7_I2C_CR2_START                   BIT(13)
  86 #define STM32F7_I2C_CR2_HEAD10R                 BIT(12)
  87 #define STM32F7_I2C_CR2_ADD10                   BIT(11)
  88 #define STM32F7_I2C_CR2_RD_WRN                  BIT(10)
  89 #define STM32F7_I2C_CR2_SADD10_MASK             GENMASK(9, 0)
  90 #define STM32F7_I2C_CR2_SADD10(n)               (((n) & \
  91                                                 STM32F7_I2C_CR2_SADD10_MASK))
  92 #define STM32F7_I2C_CR2_SADD7_MASK              GENMASK(7, 1)
  93 #define STM32F7_I2C_CR2_SADD7(n)                (((n) & 0x7f) << 1)
  94
  95 /* STM32F7 I2C Own Address 1 */
  96 #define STM32F7_I2C_OAR1_OA1EN                  BIT(15)
  97 #define STM32F7_I2C_OAR1_OA1MODE                BIT(10)
  98 #define STM32F7_I2C_OAR1_OA1_10_MASK            GENMASK(9, 0)
  99 #define STM32F7_I2C_OAR1_OA1_10(n)              (((n) & \
 100                                                 STM32F7_I2C_OAR1_OA1_10_MASK))
 101 #define STM32F7_I2C_OAR1_OA1_7_MASK             GENMASK(7, 1)
 102 #define STM32F7_I2C_OAR1_OA1_7(n)               (((n) & 0x7f) << 1)
 103 #define STM32F7_I2C_OAR1_MASK                   (STM32F7_I2C_OAR1_OA1_7_MASK \
 104                                                 | STM32F7_I2C_OAR1_OA1_10_MASK \
 105                                                 | STM32F7_I2C_OAR1_OA1EN \
 106                                                 | STM32F7_I2C_OAR1_OA1MODE)
 107
 108 /* STM32F7 I2C Own Address 2 */
 109 #define STM32F7_I2C_OAR2_OA2EN                  BIT(15)
 110 #define STM32F7_I2C_OAR2_OA2MSK_MASK            GENMASK(10, 8)
 111 #define STM32F7_I2C_OAR2_OA2MSK(n)              (((n) & 0x7) << 8)
 112 #define STM32F7_I2C_OAR2_OA2_7_MASK             GENMASK(7, 1)
 113 #define STM32F7_I2C_OAR2_OA2_7(n)               (((n) & 0x7f) << 1)
 114 #define STM32F7_I2C_OAR2_MASK                   (STM32F7_I2C_OAR2_OA2MSK_MASK \
 115                                                 | STM32F7_I2C_OAR2_OA2_7_MASK \
 116                                                 | STM32F7_I2C_OAR2_OA2EN)
 117
 118 /* STM32F7 I2C Interrupt Status */
 119 #define STM32F7_I2C_ISR_ADDCODE_MASK            GENMASK(23, 17)
 120 #define STM32F7_I2C_ISR_ADDCODE_GET(n) \
 121                                 (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17)
 122 #define STM32F7_I2C_ISR_DIR                     BIT(16)
 123 #define STM32F7_I2C_ISR_BUSY                    BIT(15)
 124 #define STM32F7_I2C_ISR_PECERR                  BIT(11)
 125 #define STM32F7_I2C_ISR_ARLO                    BIT(9)
 126 #define STM32F7_I2C_ISR_BERR                    BIT(8)
 127 #define STM32F7_I2C_ISR_TCR                     BIT(7)
 128 #define STM32F7_I2C_ISR_TC                      BIT(6)
 129 #define STM32F7_I2C_ISR_STOPF                   BIT(5)
 130 #define STM32F7_I2C_ISR_NACKF                   BIT(4)
 131 #define STM32F7_I2C_ISR_ADDR                    BIT(3)
 132 #define STM32F7_I2C_ISR_RXNE                    BIT(2)
 133 #define STM32F7_I2C_ISR_TXIS                    BIT(1)
 134 #define STM32F7_I2C_ISR_TXE                     BIT(0)
 135
 136 /* STM32F7 I2C Interrupt Clear */
 137 #define STM32F7_I2C_ICR_PECCF                   BIT(11)
 138 #define STM32F7_I2C_ICR_ARLOCF                  BIT(9)
 139 #define STM32F7_I2C_ICR_BERRCF                  BIT(8)
 140 #define STM32F7_I2C_ICR_STOPCF                  BIT(5)
 141 #define STM32F7_I2C_ICR_NACKCF                  BIT(4)
 142 #define STM32F7_I2C_ICR_ADDRCF                  BIT(3)
 143
 144 /* STM32F7 I2C Timing */
 145 #define STM32F7_I2C_TIMINGR_PRESC(n)            (((n) & 0xf) << 28)
 146 #define STM32F7_I2C_TIMINGR_SCLDEL(n)           (((n) & 0xf) << 20)
 147 #define STM32F7_I2C_TIMINGR_SDADEL(n)           (((n) & 0xf) << 16)
 148 #define STM32F7_I2C_TIMINGR_SCLH(n)             (((n) & 0xff) << 8)
 149 #define STM32F7_I2C_TIMINGR_SCLL(n)             ((n) & 0xff)
 150
 151 #define STM32F7_I2C_MAX_LEN                     0xff
 152 #define STM32F7_I2C_DMA_LEN_MIN                 0x16
 153 #define STM32F7_I2C_MAX_SLAVE                   0x2
 154
 155 #define STM32F7_I2C_DNF_DEFAULT                 0
 156 #define STM32F7_I2C_DNF_MAX                     16
 157
 158 #define STM32F7_I2C_ANALOG_FILTER_ENABLE        1
 159 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN     50      /* ns */
 160 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX     260     /* ns */
 161
 162 #define STM32F7_I2C_RISE_TIME_DEFAULT           25      /* ns */
 163 #define STM32F7_I2C_FALL_TIME_DEFAULT           10      /* ns */
 164
 165 #define STM32F7_PRESC_MAX                       BIT(4)
 166 #define STM32F7_SCLDEL_MAX                      BIT(4)
 167 #define STM32F7_SDADEL_MAX                      BIT(4)
 168 #define STM32F7_SCLH_MAX                        BIT(8)
 169 #define STM32F7_SCLL_MAX                        BIT(8)
 170
 171 #define STM32F7_AUTOSUSPEND_DELAY               (HZ / 100)
 172
 173 /**
 174  * struct stm32f7_i2c_regs - i2c f7 registers backup
 175  * @cr1: Control register 1
 176  * @cr2: Control register 2
 177  * @oar1: Own address 1 register
 178  * @oar2: Own address 2 register
 179  * @tmgr: Timing register
 180  */
 181 struct stm32f7_i2c_regs {
 182         u32 cr1;
 183         u32 cr2;
 184         u32 oar1;
 185         u32 oar2;
 186         u32 tmgr;
 187 };
 188
 189 /**
 190  * struct stm32f7_i2c_spec - private i2c specification timing
 191  * @rate: I2C bus speed (Hz)
 192  * @rate_min: 80% of I2C bus speed (Hz)
 193  * @rate_max: 100% of I2C bus speed (Hz)
 194  * @fall_max: Max fall time of both SDA and SCL signals (ns)
 195  * @rise_max: Max rise time of both SDA and SCL signals (ns)
 196  * @hddat_min: Min data hold time (ns)
 197  * @vddat_max: Max data valid time (ns)
 198  * @sudat_min: Min data setup time (ns)
 199  * @l_min: Min low period of the SCL clock (ns)
 200  * @h_min: Min high period of the SCL clock (ns)
 201  */
 202 struct stm32f7_i2c_spec {
 203         u32 rate;
 204         u32 rate_min;
 205         u32 rate_max;
 206         u32 fall_max;
 207         u32 rise_max;
 208         u32 hddat_min;
 209         u32 vddat_max;
 210         u32 sudat_min;
 211         u32 l_min;
 212         u32 h_min;
 213 };
 214
 215 /**
 216  * struct stm32f7_i2c_setup - private I2C timing setup parameters
 217  * @speed: I2C speed mode (standard, Fast Plus)
 218  * @speed_freq: I2C speed frequency  (Hz)
 219  * @clock_src: I2C clock source frequency (Hz)
 220  * @rise_time: Rise time (ns)
 221  * @fall_time: Fall time (ns)
 222  * @dnf: Digital filter coefficient (0-16)
 223  * @analog_filter: Analog filter delay (On/Off)
 224  * @fmp_clr_offset: Fast Mode Plus clear register offset from set register
 225  */
 226 struct stm32f7_i2c_setup {
 227         enum stm32_i2c_speed speed;
 228         u32 speed_freq;
 229         u32 clock_src;
 230         u32 rise_time;
 231         u32 fall_time;
 232         u8 dnf;
 233         bool analog_filter;
 234         u32 fmp_clr_offset;
 235 };
 236
 237 /**
 238  * struct stm32f7_i2c_timings - private I2C output parameters
 239  * @node: List entry
 240  * @presc: Prescaler value
 241  * @scldel: Data setup time
 242  * @sdadel: Data hold time
 243  * @sclh: SCL high period (master mode)
 244  * @scll: SCL low period (master mode)
 245  */
 246 struct stm32f7_i2c_timings {
 247         struct list_head node;
 248         u8 presc;
 249         u8 scldel;
 250         u8 sdadel;
 251         u8 sclh;
 252         u8 scll;
 253 };
 254
 255 /**
 256  * struct stm32f7_i2c_msg - client specific data
 257  * @addr: 8-bit or 10-bit slave addr, including r/w bit
 258  * @count: number of bytes to be transferred
 259  * @buf: data buffer
 260  * @result: result of the transfer
 261  * @stop: last I2C msg to be sent, i.e. STOP to be generated
 262  * @smbus: boolean to know if the I2C IP is used in SMBus mode
 263  * @size: type of SMBus protocol
 264  * @read_write: direction of SMBus protocol
 265  * SMBus block read and SMBus block write - block read process call protocols
 266  * @smbus_buf: buffer to be used for SMBus protocol transfer. It will
 267  * contain a maximum of 32 bytes of data + byte command + byte count + PEC
 268  * This buffer has to be 32-bit aligned to be compliant with memory address
 269  * register in DMA mode.
 270  */
 271 struct stm32f7_i2c_msg {
 272         u16 addr;
 273         u32 count;
 274         u8 *buf;
 275         int result;
 276         bool stop;
 277         bool smbus;
 278         int size;
 279         char read_write;
 280         u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4);
 281 };
 282
 283 /**
 284  * struct stm32f7_i2c_dev - private data of the controller
 285  * @adap: I2C adapter for this controller
 286  * @dev: device for this controller
 287  * @base: virtual memory area
 288  * @complete: completion of I2C message
 289  * @clk: hw i2c clock
 290  * @speed: I2C clock frequency of the controller. Standard, Fast or Fast+
 291  * @msg: Pointer to data to be written
 292  * @msg_num: number of I2C messages to be executed
 293  * @msg_id: message identifiant
 294  * @f7_msg: customized i2c msg for driver usage
 295  * @setup: I2C timing input setup
 296  * @timing: I2C computed timings
 297  * @slave: list of slave devices registered on the I2C bus
 298  * @slave_running: slave device currently used
 299  * @backup_regs: backup of i2c controller registers (for suspend/resume)
 300  * @slave_dir: transfer direction for the current slave device
 301  * @master_mode: boolean to know in which mode the I2C is running (master or
 302  * slave)
 303  * @dma: dma data
 304  * @use_dma: boolean to know if dma is used in the current transfer
 305  * @regmap: holds SYSCFG phandle for Fast Mode Plus bits
 306  * @fmp_sreg: register address for setting Fast Mode Plus bits
 307  * @fmp_creg: register address for clearing Fast Mode Plus bits
 308  * @fmp_mask: mask for Fast Mode Plus bits in set register
 309  * @wakeup_src: boolean to know if the device is a wakeup source
 310  */
 311 struct stm32f7_i2c_dev {
 312         struct i2c_adapter adap;
 313         struct device *dev;
 314         void __iomem *base;
 315         struct completion complete;
 316         struct clk *clk;
 317         int speed;
 318         struct i2c_msg *msg;
 319         unsigned int msg_num;
 320         unsigned int msg_id;
 321         struct stm32f7_i2c_msg f7_msg;
 322         struct stm32f7_i2c_setup setup;
 323         struct stm32f7_i2c_timings timing;
 324         struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE];
 325         struct i2c_client *slave_running;
 326         struct stm32f7_i2c_regs backup_regs;
 327         u32 slave_dir;
 328         bool master_mode;
 329         struct stm32_i2c_dma *dma;
 330         bool use_dma;
 331         struct regmap *regmap;
 332         u32 fmp_sreg;
 333         u32 fmp_creg;
 334         u32 fmp_mask;
 335         bool wakeup_src;
 336 };
 337
 338 /*
 339  * All these values are coming from I2C Specification, Version 6.0, 4th of
 340  * April 2014.
 341  *
 342  * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast,
 343  * and Fast-mode Plus I2C-bus devices
 344  */
 345 static struct stm32f7_i2c_spec i2c_specs[] = {
 346         [STM32_I2C_SPEED_STANDARD] = {
 347                 .rate = I2C_MAX_STANDARD_MODE_FREQ,
 348                 .rate_min = I2C_MAX_STANDARD_MODE_FREQ * 8 / 10,        /* 80% */
 349                 .rate_max = I2C_MAX_STANDARD_MODE_FREQ,
 350                 .fall_max = 300,
 351                 .rise_max = 1000,
 352                 .hddat_min = 0,
 353                 .vddat_max = 3450,
 354                 .sudat_min = 250,
 355                 .l_min = 4700,
 356                 .h_min = 4000,
 357         },
 358         [STM32_I2C_SPEED_FAST] = {
 359                 .rate = I2C_MAX_FAST_MODE_FREQ,
 360                 .rate_min = I2C_MAX_FAST_MODE_FREQ * 8 / 10,            /* 80% */
 361                 .rate_max = I2C_MAX_FAST_MODE_FREQ,
 362                 .fall_max = 300,
 363                 .rise_max = 300,
 364                 .hddat_min = 0,
 365                 .vddat_max = 900,
 366                 .sudat_min = 100,
 367                 .l_min = 1300,
 368                 .h_min = 600,
 369         },
 370         [STM32_I2C_SPEED_FAST_PLUS] = {
 371                 .rate = I2C_MAX_FAST_MODE_PLUS_FREQ,
 372                 .rate_min = I2C_MAX_FAST_MODE_PLUS_FREQ * 8 / 10,       /* 80% */
 373                 .rate_max = I2C_MAX_FAST_MODE_PLUS_FREQ,
 374                 .fall_max = 100,
 375                 .rise_max = 120,
 376                 .hddat_min = 0,
 377                 .vddat_max = 450,
 378                 .sudat_min = 50,
 379                 .l_min = 500,
 380                 .h_min = 260,
 381         },
 382 };
 383
 384 static const struct stm32f7_i2c_setup stm32f7_setup = {
 385         .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
 386         .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
 387         .dnf = STM32F7_I2C_DNF_DEFAULT,
 388         .analog_filter = STM32F7_I2C_ANALOG_FILTER_ENABLE,
 389 };
 390
 391 static const struct stm32f7_i2c_setup stm32mp15_setup = {
 392         .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
 393         .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
 394         .dnf = STM32F7_I2C_DNF_DEFAULT,
 395         .analog_filter = STM32F7_I2C_ANALOG_FILTER_ENABLE,
 396         .fmp_clr_offset = 0x40,
 397 };
 398
 399 static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask)
 400 {
 401         writel_relaxed(readl_relaxed(reg) | mask, reg);
 402 }
 403
 404 static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask)
 405 {
 406         writel_relaxed(readl_relaxed(reg) & ~mask, reg);
 407 }
 408
 409 static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)
 410 {
 411         stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
 412 }
 413
 414 static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev,
 415                                       struct stm32f7_i2c_setup *setup,
 416                                       struct stm32f7_i2c_timings *output)
 417 {
 418         u32 p_prev = STM32F7_PRESC_MAX;
 419         u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
 420                                        setup->clock_src);
 421         u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
 422                                        setup->speed_freq);
 423         u32 clk_error_prev = i2cbus;
 424         u32 tsync;
 425         u32 af_delay_min, af_delay_max;
 426         u32 dnf_delay;
 427         u32 clk_min, clk_max;
 428         int sdadel_min, sdadel_max;
 429         int scldel_min;
 430         struct stm32f7_i2c_timings *v, *_v, *s;
 431         struct list_head solutions;
 432         u16 p, l, a, h;
 433         int ret = 0;
 434
 435         if (setup->speed >= STM32_I2C_SPEED_END) {
 436                 dev_err(i2c_dev->dev, "speed out of bound {%d/%d}\n",
 437                         setup->speed, STM32_I2C_SPEED_END - 1);
 438                 return -EINVAL;
 439         }
 440
 441         if ((setup->rise_time > i2c_specs[setup->speed].rise_max) ||
 442             (setup->fall_time > i2c_specs[setup->speed].fall_max)) {
 443                 dev_err(i2c_dev->dev,
 444                         "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
 445                         setup->rise_time, i2c_specs[setup->speed].rise_max,
 446                         setup->fall_time, i2c_specs[setup->speed].fall_max);
 447                 return -EINVAL;
 448         }
 449
 450         if (setup->dnf > STM32F7_I2C_DNF_MAX) {
 451                 dev_err(i2c_dev->dev,
 452                         "DNF out of bound %d/%d\n",
 453                         setup->dnf, STM32F7_I2C_DNF_MAX);
 454                 return -EINVAL;
 455         }
 456
 457         if (setup->speed_freq > i2c_specs[setup->speed].rate) {
 458                 dev_err(i2c_dev->dev, "ERROR: Freq {%d/%d}\n",
 459                         setup->speed_freq, i2c_specs[setup->speed].rate);
 460                 return -EINVAL;
 461         }
 462
 463         /*  Analog and Digital Filters */
 464         af_delay_min =
 465                 (setup->analog_filter ?
 466                  STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0);
 467         af_delay_max =
 468                 (setup->analog_filter ?
 469                  STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0);
 470         dnf_delay = setup->dnf * i2cclk;
 471
 472         sdadel_min = i2c_specs[setup->speed].hddat_min + setup->fall_time -
 473                 af_delay_min - (setup->dnf + 3) * i2cclk;
 474
 475         sdadel_max = i2c_specs[setup->speed].vddat_max - setup->rise_time -
 476                 af_delay_max - (setup->dnf + 4) * i2cclk;
 477
 478         scldel_min = setup->rise_time + i2c_specs[setup->speed].sudat_min;
 479
 480         if (sdadel_min < 0)
 481                 sdadel_min = 0;
 482         if (sdadel_max < 0)
 483                 sdadel_max = 0;
 484
 485         dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n",
 486                 sdadel_min, sdadel_max, scldel_min);
 487
 488         INIT_LIST_HEAD(&solutions);
 489         /* Compute possible values for PRESC, SCLDEL and SDADEL */
 490         for (p = 0; p < STM32F7_PRESC_MAX; p++) {
 491                 for (l = 0; l < STM32F7_SCLDEL_MAX; l++) {
 492                         u32 scldel = (l + 1) * (p + 1) * i2cclk;
 493
 494                         if (scldel < scldel_min)
 495                                 continue;
 496
 497                         for (a = 0; a < STM32F7_SDADEL_MAX; a++) {
 498                                 u32 sdadel = (a * (p + 1) + 1) * i2cclk;
 499
 500                                 if (((sdadel >= sdadel_min) &&
 501                                      (sdadel <= sdadel_max)) &&
 502                                     (p != p_prev)) {
 503                                         v = kmalloc(sizeof(*v), GFP_KERNEL);
 504                                         if (!v) {
 505                                                 ret = -ENOMEM;
 506                                                 goto exit;
 507                                         }
 508
 509                                         v->presc = p;
 510                                         v->scldel = l;
 511                                         v->sdadel = a;
 512                                         p_prev = p;
 513
 514                                         list_add_tail(&v->node,
 515                                                       &solutions);
 516                                         break;
 517                                 }
 518                         }
 519
 520                         if (p_prev == p)
 521                                 break;
 522                 }
 523         }
 524
 525         if (list_empty(&solutions)) {
 526                 dev_err(i2c_dev->dev, "no Prescaler solution\n");
 527                 ret = -EPERM;
 528                 goto exit;
 529         }
 530
 531         tsync = af_delay_min + dnf_delay + (2 * i2cclk);
 532         s = NULL;
 533         clk_max = NSEC_PER_SEC / i2c_specs[setup->speed].rate_min;
 534         clk_min = NSEC_PER_SEC / i2c_specs[setup->speed].rate_max;
 535
 536         /*
 537          * Among Prescaler possibilities discovered above figures out SCL Low
 538          * and High Period. Provided:
 539          * - SCL Low Period has to be higher than SCL Clock Low Period
 540          *   defined by I2C Specification. I2C Clock has to be lower than
 541          *   (SCL Low Period - Analog/Digital filters) / 4.
 542          * - SCL High Period has to be lower than SCL Clock High Period
 543          *   defined by I2C Specification
 544          * - I2C Clock has to be lower than SCL High Period
 545          */
 546         list_for_each_entry(v, &solutions, node) {
 547                 u32 prescaler = (v->presc + 1) * i2cclk;
 548
 549                 for (l = 0; l < STM32F7_SCLL_MAX; l++) {
 550                         u32 tscl_l = (l + 1) * prescaler + tsync;
 551
 552                         if ((tscl_l < i2c_specs[setup->speed].l_min) ||
 553                             (i2cclk >=
 554                              ((tscl_l - af_delay_min - dnf_delay) / 4))) {
 555                                 continue;
 556                         }
 557
 558                         for (h = 0; h < STM32F7_SCLH_MAX; h++) {
 559                                 u32 tscl_h = (h + 1) * prescaler + tsync;
 560                                 u32 tscl = tscl_l + tscl_h +
 561                                         setup->rise_time + setup->fall_time;
 562
 563                                 if ((tscl >= clk_min) && (tscl <= clk_max) &&
 564                                     (tscl_h >= i2c_specs[setup->speed].h_min) &&
 565                                     (i2cclk < tscl_h)) {
 566                                         int clk_error = tscl - i2cbus;
 567
 568                                         if (clk_error < 0)
 569                                                 clk_error = -clk_error;
 570
 571                                         if (clk_error < clk_error_prev) {
 572                                                 clk_error_prev = clk_error;
 573                                                 v->scll = l;
 574                                                 v->sclh = h;
 575                                                 s = v;
 576                                         }
 577                                 }
 578                         }
 579                 }
 580         }
 581
 582         if (!s) {
 583                 dev_err(i2c_dev->dev, "no solution at all\n");
 584                 ret = -EPERM;
 585                 goto exit;
 586         }
 587
 588         output->presc = s->presc;
 589         output->scldel = s->scldel;
 590         output->sdadel = s->sdadel;
 591         output->scll = s->scll;
 592         output->sclh = s->sclh;
 593
 594         dev_dbg(i2c_dev->dev,
 595                 "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
 596                 output->presc,
 597                 output->scldel, output->sdadel,
 598                 output->scll, output->sclh);
 599
 600 exit:
 601         /* Release list and memory */
 602         list_for_each_entry_safe(v, _v, &solutions, node) {
 603                 list_del(&v->node);
 604                 kfree(v);
 605         }
 606
 607         return ret;
 608 }
 609
 610 static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev,
 611                                     struct stm32f7_i2c_setup *setup)
 612 {
 613         struct i2c_timings timings, *t = &timings;
 614         int ret = 0;
 615
 616         t->bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
 617         t->scl_rise_ns = i2c_dev->setup.rise_time;
 618         t->scl_fall_ns = i2c_dev->setup.fall_time;
 619
 620         i2c_parse_fw_timings(i2c_dev->dev, t, false);
 621
 622         if (t->bus_freq_hz >= I2C_MAX_FAST_MODE_PLUS_FREQ)
 623                 i2c_dev->speed = STM32_I2C_SPEED_FAST_PLUS;
 624         else if (t->bus_freq_hz >= I2C_MAX_FAST_MODE_FREQ)
 625                 i2c_dev->speed = STM32_I2C_SPEED_FAST;
 626         else
 627                 i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
 628
 629         i2c_dev->setup.rise_time = t->scl_rise_ns;
 630         i2c_dev->setup.fall_time = t->scl_fall_ns;
 631
 632         setup->speed = i2c_dev->speed;
 633         setup->speed_freq = i2c_specs[setup->speed].rate;
 634         setup->clock_src = clk_get_rate(i2c_dev->clk);
 635
 636         if (!setup->clock_src) {
 637                 dev_err(i2c_dev->dev, "clock rate is 0\n");
 638                 return -EINVAL;
 639         }
 640
 641         do {
 642                 ret = stm32f7_i2c_compute_timing(i2c_dev, setup,
 643                                                  &i2c_dev->timing);
 644                 if (ret) {
 645                         dev_err(i2c_dev->dev,
 646                                 "failed to compute I2C timings.\n");
 647                         if (i2c_dev->speed > STM32_I2C_SPEED_STANDARD) {
 648                                 i2c_dev->speed--;
 649                                 setup->speed = i2c_dev->speed;
 650                                 setup->speed_freq =
 651                                         i2c_specs[setup->speed].rate;
 652                                 dev_warn(i2c_dev->dev,
 653                                          "downgrade I2C Speed Freq to (%i)\n",
 654                                          i2c_specs[setup->speed].rate);
 655                         } else {
 656                                 break;
 657                         }
 658                 }
 659         } while (ret);
 660
 661         if (ret) {
 662                 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n");
 663                 return ret;
 664         }
 665
 666         dev_dbg(i2c_dev->dev, "I2C Speed(%i), Freq(%i), Clk Source(%i)\n",
 667                 setup->speed, setup->speed_freq, setup->clock_src);
 668         dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n",
 669                 setup->rise_time, setup->fall_time);
 670         dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n",
 671                 (setup->analog_filter ? "On" : "Off"), setup->dnf);
 672
 673         return 0;
 674 }
 675
 676 static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev)
 677 {
 678         void __iomem *base = i2c_dev->base;
 679         u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN;
 680
 681         stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
 682 }
 683
 684 static void stm32f7_i2c_dma_callback(void *arg)
 685 {
 686         struct stm32f7_i2c_dev *i2c_dev = (struct stm32f7_i2c_dev *)arg;
 687         struct stm32_i2c_dma *dma = i2c_dev->dma;
 688         struct device *dev = dma->chan_using->device->dev;
 689
 690         stm32f7_i2c_disable_dma_req(i2c_dev);
 691         dma_unmap_single(dev, dma->dma_buf, dma->dma_len, dma->dma_data_dir);
 692         complete(&dma->dma_complete);
 693 }
 694
 695 static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev)
 696 {
 697         struct stm32f7_i2c_timings *t = &i2c_dev->timing;
 698         u32 timing = 0;
 699
 700         /* Timing settings */
 701         timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc);
 702         timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel);
 703         timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel);
 704         timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh);
 705         timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll);
 706         writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR);
 707
 708         /* Enable I2C */
 709         if (i2c_dev->setup.analog_filter)
 710                 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
 711                                      STM32F7_I2C_CR1_ANFOFF);
 712         else
 713                 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
 714                                      STM32F7_I2C_CR1_ANFOFF);
 715         stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
 716                              STM32F7_I2C_CR1_PE);
 717 }
 718
 719 static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev)
 720 {
 721         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 722         void __iomem *base = i2c_dev->base;
 723
 724         if (f7_msg->count) {
 725                 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR);
 726                 f7_msg->count--;
 727         }
 728 }
 729
 730 static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev)
 731 {
 732         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 733         void __iomem *base = i2c_dev->base;
 734
 735         if (f7_msg->count) {
 736                 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR);
 737                 f7_msg->count--;
 738         } else {
 739                 /* Flush RX buffer has no data is expected */
 740                 readb_relaxed(base + STM32F7_I2C_RXDR);
 741         }
 742 }
 743
 744 static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev)
 745 {
 746         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 747         u32 cr2;
 748
 749         if (i2c_dev->use_dma)
 750                 f7_msg->count -= STM32F7_I2C_MAX_LEN;
 751
 752         cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
 753
 754         cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK;
 755         if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
 756                 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
 757         } else {
 758                 cr2 &= ~STM32F7_I2C_CR2_RELOAD;
 759                 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
 760         }
 761
 762         writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
 763 }
 764
 765 static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev)
 766 {
 767         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 768         u32 cr2;
 769         u8 *val;
 770
 771         /*
 772          * For I2C_SMBUS_BLOCK_DATA && I2C_SMBUS_BLOCK_PROC_CALL, the first
 773          * data received inform us how many data will follow.
 774          */
 775         stm32f7_i2c_read_rx_data(i2c_dev);
 776
 777         /*
 778          * Update NBYTES with the value read to continue the transfer
 779          */
 780         val = f7_msg->buf - sizeof(u8);
 781         f7_msg->count = *val;
 782         cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
 783         cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
 784         cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
 785         writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
 786 }
 787
 788 static int stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap)
 789 {
 790         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
 791
 792         dev_info(i2c_dev->dev, "Trying to recover bus\n");
 793
 794         stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
 795                              STM32F7_I2C_CR1_PE);
 796
 797         stm32f7_i2c_hw_config(i2c_dev);
 798
 799         return 0;
 800 }
 801
 802 static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev)
 803 {
 804         u32 status;
 805         int ret;
 806
 807         ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR,
 808                                          status,
 809                                          !(status & STM32F7_I2C_ISR_BUSY),
 810                                          10, 1000);
 811         if (!ret)
 812                 return 0;
 813
 814         dev_info(i2c_dev->dev, "bus busy\n");
 815
 816         ret = stm32f7_i2c_release_bus(&i2c_dev->adap);
 817         if (ret) {
 818                 dev_err(i2c_dev->dev, "Failed to recover the bus (%d)\n", ret);
 819                 return ret;
 820         }
 821
 822         return -EBUSY;
 823 }
 824
 825 static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
 826                                  struct i2c_msg *msg)
 827 {
 828         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 829         void __iomem *base = i2c_dev->base;
 830         u32 cr1, cr2;
 831         int ret;
 832
 833         f7_msg->addr = msg->addr;
 834         f7_msg->buf = msg->buf;
 835         f7_msg->count = msg->len;
 836         f7_msg->result = 0;
 837         f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1);
 838
 839         reinit_completion(&i2c_dev->complete);
 840
 841         cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
 842         cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
 843
 844         /* Set transfer direction */
 845         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 846         if (msg->flags & I2C_M_RD)
 847                 cr2 |= STM32F7_I2C_CR2_RD_WRN;
 848
 849         /* Set slave address */
 850         cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10);
 851         if (msg->flags & I2C_M_TEN) {
 852                 cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK;
 853                 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr);
 854                 cr2 |= STM32F7_I2C_CR2_ADD10;
 855         } else {
 856                 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK;
 857                 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
 858         }
 859
 860         /* Set nb bytes to transfer and reload if needed */
 861         cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
 862         if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
 863                 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
 864                 cr2 |= STM32F7_I2C_CR2_RELOAD;
 865         } else {
 866                 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
 867         }
 868
 869         /* Enable NACK, STOP, error and transfer complete interrupts */
 870         cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
 871                 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
 872
 873         /* Clear DMA req and TX/RX interrupt */
 874         cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
 875                         STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
 876
 877         /* Configure DMA or enable RX/TX interrupt */
 878         i2c_dev->use_dma = false;
 879         if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
 880                 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
 881                                               msg->flags & I2C_M_RD,
 882                                               f7_msg->count, f7_msg->buf,
 883                                               stm32f7_i2c_dma_callback,
 884                                               i2c_dev);
 885                 if (!ret)
 886                         i2c_dev->use_dma = true;
 887                 else
 888                         dev_warn(i2c_dev->dev, "can't use DMA\n");
 889         }
 890
 891         if (!i2c_dev->use_dma) {
 892                 if (msg->flags & I2C_M_RD)
 893                         cr1 |= STM32F7_I2C_CR1_RXIE;
 894                 else
 895                         cr1 |= STM32F7_I2C_CR1_TXIE;
 896         } else {
 897                 if (msg->flags & I2C_M_RD)
 898                         cr1 |= STM32F7_I2C_CR1_RXDMAEN;
 899                 else
 900                         cr1 |= STM32F7_I2C_CR1_TXDMAEN;
 901         }
 902
 903         /* Configure Start/Repeated Start */
 904         cr2 |= STM32F7_I2C_CR2_START;
 905
 906         i2c_dev->master_mode = true;
 907
 908         /* Write configurations registers */
 909         writel_relaxed(cr1, base + STM32F7_I2C_CR1);
 910         writel_relaxed(cr2, base + STM32F7_I2C_CR2);
 911 }
 912
 913 static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
 914                                       unsigned short flags, u8 command,
 915                                       union i2c_smbus_data *data)
 916 {
 917         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 918         struct device *dev = i2c_dev->dev;
 919         void __iomem *base = i2c_dev->base;
 920         u32 cr1, cr2;
 921         int i, ret;
 922
 923         f7_msg->result = 0;
 924         reinit_completion(&i2c_dev->complete);
 925
 926         cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
 927         cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
 928
 929         /* Set transfer direction */
 930         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 931         if (f7_msg->read_write)
 932                 cr2 |= STM32F7_I2C_CR2_RD_WRN;
 933
 934         /* Set slave address */
 935         cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK);
 936         cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
 937
 938         f7_msg->smbus_buf[0] = command;
 939         switch (f7_msg->size) {
 940         case I2C_SMBUS_QUICK:
 941                 f7_msg->stop = true;
 942                 f7_msg->count = 0;
 943                 break;
 944         case I2C_SMBUS_BYTE:
 945                 f7_msg->stop = true;
 946                 f7_msg->count = 1;
 947                 break;
 948         case I2C_SMBUS_BYTE_DATA:
 949                 if (f7_msg->read_write) {
 950                         f7_msg->stop = false;
 951                         f7_msg->count = 1;
 952                         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 953                 } else {
 954                         f7_msg->stop = true;
 955                         f7_msg->count = 2;
 956                         f7_msg->smbus_buf[1] = data->byte;
 957                 }
 958                 break;
 959         case I2C_SMBUS_WORD_DATA:
 960                 if (f7_msg->read_write) {
 961                         f7_msg->stop = false;
 962                         f7_msg->count = 1;
 963                         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 964                 } else {
 965                         f7_msg->stop = true;
 966                         f7_msg->count = 3;
 967                         f7_msg->smbus_buf[1] = data->word & 0xff;
 968                         f7_msg->smbus_buf[2] = data->word >> 8;
 969                 }
 970                 break;
 971         case I2C_SMBUS_BLOCK_DATA:
 972                 if (f7_msg->read_write) {
 973                         f7_msg->stop = false;
 974                         f7_msg->count = 1;
 975                         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 976                 } else {
 977                         f7_msg->stop = true;
 978                         if (data->block[0] > I2C_SMBUS_BLOCK_MAX ||
 979                             !data->block[0]) {
 980                                 dev_err(dev, "Invalid block write size %d\n",
 981                                         data->block[0]);
 982                                 return -EINVAL;
 983                         }
 984                         f7_msg->count = data->block[0] + 2;
 985                         for (i = 1; i < f7_msg->count; i++)
 986                                 f7_msg->smbus_buf[i] = data->block[i - 1];
 987                 }
 988                 break;
 989         case I2C_SMBUS_PROC_CALL:
 990                 f7_msg->stop = false;
 991                 f7_msg->count = 3;
 992                 f7_msg->smbus_buf[1] = data->word & 0xff;
 993                 f7_msg->smbus_buf[2] = data->word >> 8;
 994                 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 995                 f7_msg->read_write = I2C_SMBUS_READ;
 996                 break;
 997         case I2C_SMBUS_BLOCK_PROC_CALL:
 998                 f7_msg->stop = false;
 999                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) {
1000                         dev_err(dev, "Invalid block write size %d\n",
1001                                 data->block[0]);
1002                         return -EINVAL;
1003                 }
1004                 f7_msg->count = data->block[0] + 2;
1005                 for (i = 1; i < f7_msg->count; i++)
1006                         f7_msg->smbus_buf[i] = data->block[i - 1];
1007                 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1008                 f7_msg->read_write = I2C_SMBUS_READ;
1009                 break;
1010         case I2C_SMBUS_I2C_BLOCK_DATA:
1011                 /* Rely on emulated i2c transfer (through master_xfer) */
1012                 return -EOPNOTSUPP;
1013         default:
1014                 dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size);
1015                 return -EOPNOTSUPP;
1016         }
1017
1018         f7_msg->buf = f7_msg->smbus_buf;
1019
1020         /* Configure PEC */
1021         if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) {
1022                 cr1 |= STM32F7_I2C_CR1_PECEN;
1023                 cr2 |= STM32F7_I2C_CR2_PECBYTE;
1024                 if (!f7_msg->read_write)
1025                         f7_msg->count++;
1026         } else {
1027                 cr1 &= ~STM32F7_I2C_CR1_PECEN;
1028                 cr2 &= ~STM32F7_I2C_CR2_PECBYTE;
1029         }
1030
1031         /* Set number of bytes to be transferred */
1032         cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
1033         cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1034
1035         /* Enable NACK, STOP, error and transfer complete interrupts */
1036         cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
1037                 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
1038
1039         /* Clear DMA req and TX/RX interrupt */
1040         cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1041                         STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1042
1043         /* Configure DMA or enable RX/TX interrupt */
1044         i2c_dev->use_dma = false;
1045         if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
1046                 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1047                                               cr2 & STM32F7_I2C_CR2_RD_WRN,
1048                                               f7_msg->count, f7_msg->buf,
1049                                               stm32f7_i2c_dma_callback,
1050                                               i2c_dev);
1051                 if (!ret)
1052                         i2c_dev->use_dma = true;
1053                 else
1054                         dev_warn(i2c_dev->dev, "can't use DMA\n");
1055         }
1056
1057         if (!i2c_dev->use_dma) {
1058                 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1059                         cr1 |= STM32F7_I2C_CR1_RXIE;
1060                 else
1061                         cr1 |= STM32F7_I2C_CR1_TXIE;
1062         } else {
1063                 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1064                         cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1065                 else
1066                         cr1 |= STM32F7_I2C_CR1_TXDMAEN;
1067         }
1068
1069         /* Set Start bit */
1070         cr2 |= STM32F7_I2C_CR2_START;
1071
1072         i2c_dev->master_mode = true;
1073
1074         /* Write configurations registers */
1075         writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1076         writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1077
1078         return 0;
1079 }
1080
1081 static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev)
1082 {
1083         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1084         void __iomem *base = i2c_dev->base;
1085         u32 cr1, cr2;
1086         int ret;
1087
1088         cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
1089         cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
1090
1091         /* Set transfer direction */
1092         cr2 |= STM32F7_I2C_CR2_RD_WRN;
1093
1094         switch (f7_msg->size) {
1095         case I2C_SMBUS_BYTE_DATA:
1096                 f7_msg->count = 1;
1097                 break;
1098         case I2C_SMBUS_WORD_DATA:
1099         case I2C_SMBUS_PROC_CALL:
1100                 f7_msg->count = 2;
1101                 break;
1102         case I2C_SMBUS_BLOCK_DATA:
1103         case I2C_SMBUS_BLOCK_PROC_CALL:
1104                 f7_msg->count = 1;
1105                 cr2 |= STM32F7_I2C_CR2_RELOAD;
1106                 break;
1107         }
1108
1109         f7_msg->buf = f7_msg->smbus_buf;
1110         f7_msg->stop = true;
1111
1112         /* Add one byte for PEC if needed */
1113         if (cr1 & STM32F7_I2C_CR1_PECEN)
1114                 f7_msg->count++;
1115
1116         /* Set number of bytes to be transferred */
1117         cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK);
1118         cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1119
1120         /*
1121          * Configure RX/TX interrupt:
1122          */
1123         cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE);
1124         cr1 |= STM32F7_I2C_CR1_RXIE;
1125
1126         /*
1127          * Configure DMA or enable RX/TX interrupt:
1128          * For I2C_SMBUS_BLOCK_DATA and I2C_SMBUS_BLOCK_PROC_CALL we don't use
1129          * dma as we don't know in advance how many data will be received
1130          */
1131         cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1132                  STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1133
1134         i2c_dev->use_dma = false;
1135         if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN &&
1136             f7_msg->size != I2C_SMBUS_BLOCK_DATA &&
1137             f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) {
1138                 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1139                                               cr2 & STM32F7_I2C_CR2_RD_WRN,
1140                                               f7_msg->count, f7_msg->buf,
1141                                               stm32f7_i2c_dma_callback,
1142                                               i2c_dev);
1143
1144                 if (!ret)
1145                         i2c_dev->use_dma = true;
1146                 else
1147                         dev_warn(i2c_dev->dev, "can't use DMA\n");
1148         }
1149
1150         if (!i2c_dev->use_dma)
1151                 cr1 |= STM32F7_I2C_CR1_RXIE;
1152         else
1153                 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1154
1155         /* Configure Repeated Start */
1156         cr2 |= STM32F7_I2C_CR2_START;
1157
1158         /* Write configurations registers */
1159         writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1160         writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1161 }
1162
1163 static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev)
1164 {
1165         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1166         u8 count, internal_pec, received_pec;
1167
1168         internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR);
1169
1170         switch (f7_msg->size) {
1171         case I2C_SMBUS_BYTE:
1172         case I2C_SMBUS_BYTE_DATA:
1173                 received_pec = f7_msg->smbus_buf[1];
1174                 break;
1175         case I2C_SMBUS_WORD_DATA:
1176         case I2C_SMBUS_PROC_CALL:
1177                 received_pec = f7_msg->smbus_buf[2];
1178                 break;
1179         case I2C_SMBUS_BLOCK_DATA:
1180         case I2C_SMBUS_BLOCK_PROC_CALL:
1181                 count = f7_msg->smbus_buf[0];
1182                 received_pec = f7_msg->smbus_buf[count];
1183                 break;
1184         default:
1185                 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n");
1186                 return -EINVAL;
1187         }
1188
1189         if (internal_pec != received_pec) {
1190                 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n",
1191                         internal_pec, received_pec);
1192                 return -EBADMSG;
1193         }
1194
1195         return 0;
1196 }
1197
1198 static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode)
1199 {
1200         u32 addr;
1201
1202         if (!slave)
1203                 return false;
1204
1205         if (slave->flags & I2C_CLIENT_TEN) {
1206                 /*
1207                  * For 10-bit addr, addcode = 11110XY with
1208                  * X = Bit 9 of slave address
1209                  * Y = Bit 8 of slave address
1210                  */
1211                 addr = slave->addr >> 8;
1212                 addr |= 0x78;
1213                 if (addr == addcode)
1214                         return true;
1215         } else {
1216                 addr = slave->addr & 0x7f;
1217                 if (addr == addcode)
1218                         return true;
1219         }
1220
1221         return false;
1222 }
1223
1224 static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev)
1225 {
1226         struct i2c_client *slave = i2c_dev->slave_running;
1227         void __iomem *base = i2c_dev->base;
1228         u32 mask;
1229         u8 value = 0;
1230
1231         if (i2c_dev->slave_dir) {
1232                 /* Notify i2c slave that new read transfer is starting */
1233                 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
1234
1235                 /*
1236                  * Disable slave TX config in case of I2C combined message
1237                  * (I2C Write followed by I2C Read)
1238                  */
1239                 mask = STM32F7_I2C_CR2_RELOAD;
1240                 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask);
1241                 mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1242                        STM32F7_I2C_CR1_TCIE;
1243                 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1244
1245                 /* Enable TX empty, STOP, NACK interrupts */
1246                 mask =  STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1247                         STM32F7_I2C_CR1_TXIE;
1248                 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1249
1250                 /* Write 1st data byte */
1251                 writel_relaxed(value, base + STM32F7_I2C_TXDR);
1252         } else {
1253                 /* Notify i2c slave that new write transfer is starting */
1254                 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
1255
1256                 /* Set reload mode to be able to ACK/NACK each received byte */
1257                 mask = STM32F7_I2C_CR2_RELOAD;
1258                 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1259
1260                 /*
1261                  * Set STOP, NACK, RX empty and transfer complete interrupts.*
1262                  * Set Slave Byte Control to be able to ACK/NACK each data
1263                  * byte received
1264                  */
1265                 mask =  STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1266                         STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1267                         STM32F7_I2C_CR1_TCIE;
1268                 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1269         }
1270 }
1271
1272 static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev)
1273 {
1274         void __iomem *base = i2c_dev->base;
1275         u32 isr, addcode, dir, mask;
1276         int i;
1277
1278         isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1279         addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr);
1280         dir = isr & STM32F7_I2C_ISR_DIR;
1281
1282         for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1283                 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) {
1284                         i2c_dev->slave_running = i2c_dev->slave[i];
1285                         i2c_dev->slave_dir = dir;
1286
1287                         /* Start I2C slave processing */
1288                         stm32f7_i2c_slave_start(i2c_dev);
1289
1290                         /* Clear ADDR flag */
1291                         mask = STM32F7_I2C_ICR_ADDRCF;
1292                         writel_relaxed(mask, base + STM32F7_I2C_ICR);
1293                         break;
1294                 }
1295         }
1296 }
1297
1298 static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1299                                     struct i2c_client *slave, int *id)
1300 {
1301         int i;
1302
1303         for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1304                 if (i2c_dev->slave[i] == slave) {
1305                         *id = i;
1306                         return 0;
1307                 }
1308         }
1309
1310         dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr);
1311
1312         return -ENODEV;
1313 }
1314
1315 static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1316                                          struct i2c_client *slave, int *id)
1317 {
1318         struct device *dev = i2c_dev->dev;
1319         int i;
1320
1321         /*
1322          * slave[0] supports 7-bit and 10-bit slave address
1323          * slave[1] supports 7-bit slave address only
1324          */
1325         for (i = STM32F7_I2C_MAX_SLAVE - 1; i >= 0; i--) {
1326                 if (i == 1 && (slave->flags & I2C_CLIENT_TEN))
1327                         continue;
1328                 if (!i2c_dev->slave[i]) {
1329                         *id = i;
1330                         return 0;
1331                 }
1332         }
1333
1334         dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr);
1335
1336         return -EINVAL;
1337 }
1338
1339 static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev)
1340 {
1341         int i;
1342
1343         for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1344                 if (i2c_dev->slave[i])
1345                         return true;
1346         }
1347
1348         return false;
1349 }
1350
1351 static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev)
1352 {
1353         int i, busy;
1354
1355         busy = 0;
1356         for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1357                 if (i2c_dev->slave[i])
1358                         busy++;
1359         }
1360
1361         return i == busy;
1362 }
1363
1364 static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev)
1365 {
1366         void __iomem *base = i2c_dev->base;
1367         u32 cr2, status, mask;
1368         u8 val;
1369         int ret;
1370
1371         status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1372
1373         /* Slave transmitter mode */
1374         if (status & STM32F7_I2C_ISR_TXIS) {
1375                 i2c_slave_event(i2c_dev->slave_running,
1376                                 I2C_SLAVE_READ_PROCESSED,
1377                                 &val);
1378
1379                 /* Write data byte */
1380                 writel_relaxed(val, base + STM32F7_I2C_TXDR);
1381         }
1382
1383         /* Transfer Complete Reload for Slave receiver mode */
1384         if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) {
1385                 /*
1386                  * Read data byte then set NBYTES to receive next byte or NACK
1387                  * the current received byte
1388                  */
1389                 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR);
1390                 ret = i2c_slave_event(i2c_dev->slave_running,
1391                                       I2C_SLAVE_WRITE_RECEIVED,
1392                                       &val);
1393                 if (!ret) {
1394                         cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
1395                         cr2 |= STM32F7_I2C_CR2_NBYTES(1);
1396                         writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
1397                 } else {
1398                         mask = STM32F7_I2C_CR2_NACK;
1399                         stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1400                 }
1401         }
1402
1403         /* NACK received */
1404         if (status & STM32F7_I2C_ISR_NACKF) {
1405                 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1406                 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1407         }
1408
1409         /* STOP received */
1410         if (status & STM32F7_I2C_ISR_STOPF) {
1411                 /* Disable interrupts */
1412                 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK);
1413
1414                 if (i2c_dev->slave_dir) {
1415                         /*
1416                          * Flush TX buffer in order to not used the byte in
1417                          * TXDR for the next transfer
1418                          */
1419                         mask = STM32F7_I2C_ISR_TXE;
1420                         stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask);
1421                 }
1422
1423                 /* Clear STOP flag */
1424                 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1425
1426                 /* Notify i2c slave that a STOP flag has been detected */
1427                 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val);
1428
1429                 i2c_dev->slave_running = NULL;
1430         }
1431
1432         /* Address match received */
1433         if (status & STM32F7_I2C_ISR_ADDR)
1434                 stm32f7_i2c_slave_addr(i2c_dev);
1435
1436         return IRQ_HANDLED;
1437 }
1438
1439 static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
1440 {
1441         struct stm32f7_i2c_dev *i2c_dev = data;
1442         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1443         void __iomem *base = i2c_dev->base;
1444         u32 status, mask;
1445         int ret = IRQ_HANDLED;
1446
1447         /* Check if the interrupt if for a slave device */
1448         if (!i2c_dev->master_mode) {
1449                 ret = stm32f7_i2c_slave_isr_event(i2c_dev);
1450                 return ret;
1451         }
1452
1453         status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1454
1455         /* Tx empty */
1456         if (status & STM32F7_I2C_ISR_TXIS)
1457                 stm32f7_i2c_write_tx_data(i2c_dev);
1458
1459         /* RX not empty */
1460         if (status & STM32F7_I2C_ISR_RXNE)
1461                 stm32f7_i2c_read_rx_data(i2c_dev);
1462
1463         /* NACK received */
1464         if (status & STM32F7_I2C_ISR_NACKF) {
1465                 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1466                 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1467                 f7_msg->result = -ENXIO;
1468         }
1469
1470         /* STOP detection flag */
1471         if (status & STM32F7_I2C_ISR_STOPF) {
1472                 /* Disable interrupts */
1473                 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1474                         mask = STM32F7_I2C_XFER_IRQ_MASK;
1475                 else
1476                         mask = STM32F7_I2C_ALL_IRQ_MASK;
1477                 stm32f7_i2c_disable_irq(i2c_dev, mask);
1478
1479                 /* Clear STOP flag */
1480                 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1481
1482                 if (i2c_dev->use_dma) {
1483                         ret = IRQ_WAKE_THREAD;
1484                 } else {
1485                         i2c_dev->master_mode = false;
1486                         complete(&i2c_dev->complete);
1487                 }
1488         }
1489
1490         /* Transfer complete */
1491         if (status & STM32F7_I2C_ISR_TC) {
1492                 if (f7_msg->stop) {
1493                         mask = STM32F7_I2C_CR2_STOP;
1494                         stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1495                 } else if (i2c_dev->use_dma) {
1496                         ret = IRQ_WAKE_THREAD;
1497                 } else if (f7_msg->smbus) {
1498                         stm32f7_i2c_smbus_rep_start(i2c_dev);
1499                 } else {
1500                         i2c_dev->msg_id++;
1501                         i2c_dev->msg++;
1502                         stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1503                 }
1504         }
1505
1506         if (status & STM32F7_I2C_ISR_TCR) {
1507                 if (f7_msg->smbus)
1508                         stm32f7_i2c_smbus_reload(i2c_dev);
1509                 else
1510                         stm32f7_i2c_reload(i2c_dev);
1511         }
1512
1513         return ret;
1514 }
1515
1516 static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data)
1517 {
1518         struct stm32f7_i2c_dev *i2c_dev = data;
1519         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1520         struct stm32_i2c_dma *dma = i2c_dev->dma;
1521         u32 status;
1522         int ret;
1523
1524         /*
1525          * Wait for dma transfer completion before sending next message or
1526          * notity the end of xfer to the client
1527          */
1528         ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ);
1529         if (!ret) {
1530                 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__);
1531                 stm32f7_i2c_disable_dma_req(i2c_dev);
1532                 dmaengine_terminate_all(dma->chan_using);
1533                 f7_msg->result = -ETIMEDOUT;
1534         }
1535
1536         status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1537
1538         if (status & STM32F7_I2C_ISR_TC) {
1539                 if (f7_msg->smbus) {
1540                         stm32f7_i2c_smbus_rep_start(i2c_dev);
1541                 } else {
1542                         i2c_dev->msg_id++;
1543                         i2c_dev->msg++;
1544                         stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1545                 }
1546         } else {
1547                 i2c_dev->master_mode = false;
1548                 complete(&i2c_dev->complete);
1549         }
1550
1551         return IRQ_HANDLED;
1552 }
1553
1554 static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data)
1555 {
1556         struct stm32f7_i2c_dev *i2c_dev = data;
1557         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1558         void __iomem *base = i2c_dev->base;
1559         struct device *dev = i2c_dev->dev;
1560         struct stm32_i2c_dma *dma = i2c_dev->dma;
1561         u32 status;
1562
1563         status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1564
1565         /* Bus error */
1566         if (status & STM32F7_I2C_ISR_BERR) {
1567                 dev_err(dev, "<%s>: Bus error\n", __func__);
1568                 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR);
1569                 stm32f7_i2c_release_bus(&i2c_dev->adap);
1570                 f7_msg->result = -EIO;
1571         }
1572
1573         /* Arbitration loss */
1574         if (status & STM32F7_I2C_ISR_ARLO) {
1575                 dev_dbg(dev, "<%s>: Arbitration loss\n", __func__);
1576                 writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR);
1577                 f7_msg->result = -EAGAIN;
1578         }
1579
1580         if (status & STM32F7_I2C_ISR_PECERR) {
1581                 dev_err(dev, "<%s>: PEC error in reception\n", __func__);
1582                 writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR);
1583                 f7_msg->result = -EINVAL;
1584         }
1585
1586         if (!i2c_dev->slave_running) {
1587                 u32 mask;
1588                 /* Disable interrupts */
1589                 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1590                         mask = STM32F7_I2C_XFER_IRQ_MASK;
1591                 else
1592                         mask = STM32F7_I2C_ALL_IRQ_MASK;
1593                 stm32f7_i2c_disable_irq(i2c_dev, mask);
1594         }
1595
1596         /* Disable dma */
1597         if (i2c_dev->use_dma) {
1598                 stm32f7_i2c_disable_dma_req(i2c_dev);
1599                 dmaengine_terminate_all(dma->chan_using);
1600         }
1601
1602         i2c_dev->master_mode = false;
1603         complete(&i2c_dev->complete);
1604
1605         return IRQ_HANDLED;
1606 }
1607
1608 static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap,
1609                             struct i2c_msg msgs[], int num)
1610 {
1611         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
1612         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1613         struct stm32_i2c_dma *dma = i2c_dev->dma;
1614         unsigned long time_left;
1615         int ret;
1616
1617         i2c_dev->msg = msgs;
1618         i2c_dev->msg_num = num;
1619         i2c_dev->msg_id = 0;
1620         f7_msg->smbus = false;
1621
1622         ret = pm_runtime_get_sync(i2c_dev->dev);
1623         if (ret < 0)
1624                 return ret;
1625
1626         ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1627         if (ret)
1628                 goto pm_free;
1629
1630         stm32f7_i2c_xfer_msg(i2c_dev, msgs);
1631
1632         time_left = wait_for_completion_timeout(&i2c_dev->complete,
1633                                                 i2c_dev->adap.timeout);
1634         ret = f7_msg->result;
1635
1636         if (!time_left) {
1637                 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n",
1638                         i2c_dev->msg->addr);
1639                 if (i2c_dev->use_dma)
1640                         dmaengine_terminate_all(dma->chan_using);
1641                 ret = -ETIMEDOUT;
1642         }
1643
1644 pm_free:
1645         pm_runtime_mark_last_busy(i2c_dev->dev);
1646         pm_runtime_put_autosuspend(i2c_dev->dev);
1647
1648         return (ret < 0) ? ret : num;
1649 }
1650
1651 static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
1652                                   unsigned short flags, char read_write,
1653                                   u8 command, int size,
1654                                   union i2c_smbus_data *data)
1655 {
1656         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter);
1657         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1658         struct stm32_i2c_dma *dma = i2c_dev->dma;
1659         struct device *dev = i2c_dev->dev;
1660         unsigned long timeout;
1661         int i, ret;
1662
1663         f7_msg->addr = addr;
1664         f7_msg->size = size;
1665         f7_msg->read_write = read_write;
1666         f7_msg->smbus = true;
1667
1668         ret = pm_runtime_get_sync(dev);
1669         if (ret < 0)
1670                 return ret;
1671
1672         ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1673         if (ret)
1674                 goto pm_free;
1675
1676         ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data);
1677         if (ret)
1678                 goto pm_free;
1679
1680         timeout = wait_for_completion_timeout(&i2c_dev->complete,
1681                                               i2c_dev->adap.timeout);
1682         ret = f7_msg->result;
1683         if (ret)
1684                 goto pm_free;
1685
1686         if (!timeout) {
1687                 dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr);
1688                 if (i2c_dev->use_dma)
1689                         dmaengine_terminate_all(dma->chan_using);
1690                 ret = -ETIMEDOUT;
1691                 goto pm_free;
1692         }
1693
1694         /* Check PEC */
1695         if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) {
1696                 ret = stm32f7_i2c_smbus_check_pec(i2c_dev);
1697                 if (ret)
1698                         goto pm_free;
1699         }
1700
1701         if (read_write && size != I2C_SMBUS_QUICK) {
1702                 switch (size) {
1703                 case I2C_SMBUS_BYTE:
1704                 case I2C_SMBUS_BYTE_DATA:
1705                         data->byte = f7_msg->smbus_buf[0];
1706                 break;
1707                 case I2C_SMBUS_WORD_DATA:
1708                 case I2C_SMBUS_PROC_CALL:
1709                         data->word = f7_msg->smbus_buf[0] |
1710                                 (f7_msg->smbus_buf[1] << 8);
1711                 break;
1712                 case I2C_SMBUS_BLOCK_DATA:
1713                 case I2C_SMBUS_BLOCK_PROC_CALL:
1714                 for (i = 0; i <= f7_msg->smbus_buf[0]; i++)
1715                         data->block[i] = f7_msg->smbus_buf[i];
1716                 break;
1717                 default:
1718                         dev_err(dev, "Unsupported smbus transaction\n");
1719                         ret = -EINVAL;
1720                 }
1721         }
1722
1723 pm_free:
1724         pm_runtime_mark_last_busy(dev);
1725         pm_runtime_put_autosuspend(dev);
1726         return ret;
1727 }
1728
1729 static void stm32f7_i2c_enable_wakeup(struct stm32f7_i2c_dev *i2c_dev,
1730                                       bool enable)
1731 {
1732         void __iomem *base = i2c_dev->base;
1733         u32 mask = STM32F7_I2C_CR1_WUPEN;
1734
1735         if (!i2c_dev->wakeup_src)
1736                 return;
1737
1738         if (enable) {
1739                 device_set_wakeup_enable(i2c_dev->dev, true);
1740                 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1741         } else {
1742                 device_set_wakeup_enable(i2c_dev->dev, false);
1743                 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1744         }
1745 }
1746
1747 static int stm32f7_i2c_reg_slave(struct i2c_client *slave)
1748 {
1749         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1750         void __iomem *base = i2c_dev->base;
1751         struct device *dev = i2c_dev->dev;
1752         u32 oar1, oar2, mask;
1753         int id, ret;
1754
1755         if (slave->flags & I2C_CLIENT_PEC) {
1756                 dev_err(dev, "SMBus PEC not supported in slave mode\n");
1757                 return -EINVAL;
1758         }
1759
1760         if (stm32f7_i2c_is_slave_busy(i2c_dev)) {
1761                 dev_err(dev, "Too much slave registered\n");
1762                 return -EBUSY;
1763         }
1764
1765         ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id);
1766         if (ret)
1767                 return ret;
1768
1769         ret = pm_runtime_get_sync(dev);
1770         if (ret < 0)
1771                 return ret;
1772
1773         if (!stm32f7_i2c_is_slave_registered(i2c_dev))
1774                 stm32f7_i2c_enable_wakeup(i2c_dev, true);
1775
1776         if (id == 0) {
1777                 /* Configure Own Address 1 */
1778                 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
1779                 oar1 &= ~STM32F7_I2C_OAR1_MASK;
1780                 if (slave->flags & I2C_CLIENT_TEN) {
1781                         oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr);
1782                         oar1 |= STM32F7_I2C_OAR1_OA1MODE;
1783                 } else {
1784                         oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr);
1785                 }
1786                 oar1 |= STM32F7_I2C_OAR1_OA1EN;
1787                 i2c_dev->slave[id] = slave;
1788                 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1);
1789         } else if (id == 1) {
1790                 /* Configure Own Address 2 */
1791                 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
1792                 oar2 &= ~STM32F7_I2C_OAR2_MASK;
1793                 if (slave->flags & I2C_CLIENT_TEN) {
1794                         ret = -EOPNOTSUPP;
1795                         goto pm_free;
1796                 }
1797
1798                 oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr);
1799                 oar2 |= STM32F7_I2C_OAR2_OA2EN;
1800                 i2c_dev->slave[id] = slave;
1801                 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2);
1802         } else {
1803                 ret = -ENODEV;
1804                 goto pm_free;
1805         }
1806
1807         /* Enable ACK */
1808         stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK);
1809
1810         /* Enable Address match interrupt, error interrupt and enable I2C  */
1811         mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE |
1812                 STM32F7_I2C_CR1_PE;
1813         stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1814
1815         ret = 0;
1816 pm_free:
1817         if (!stm32f7_i2c_is_slave_registered(i2c_dev))
1818                 stm32f7_i2c_enable_wakeup(i2c_dev, false);
1819
1820         pm_runtime_mark_last_busy(dev);
1821         pm_runtime_put_autosuspend(dev);
1822
1823         return ret;
1824 }
1825
1826 static int stm32f7_i2c_unreg_slave(struct i2c_client *slave)
1827 {
1828         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1829         void __iomem *base = i2c_dev->base;
1830         u32 mask;
1831         int id, ret;
1832
1833         ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id);
1834         if (ret)
1835                 return ret;
1836
1837         WARN_ON(!i2c_dev->slave[id]);
1838
1839         ret = pm_runtime_get_sync(i2c_dev->dev);
1840         if (ret < 0)
1841                 return ret;
1842
1843         if (id == 0) {
1844                 mask = STM32F7_I2C_OAR1_OA1EN;
1845                 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask);
1846         } else {
1847                 mask = STM32F7_I2C_OAR2_OA2EN;
1848                 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask);
1849         }
1850
1851         i2c_dev->slave[id] = NULL;
1852
1853         if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
1854                 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
1855                 stm32f7_i2c_enable_wakeup(i2c_dev, false);
1856         }
1857
1858         pm_runtime_mark_last_busy(i2c_dev->dev);
1859         pm_runtime_put_autosuspend(i2c_dev->dev);
1860
1861         return 0;
1862 }
1863
1864 static int stm32f7_i2c_write_fm_plus_bits(struct stm32f7_i2c_dev *i2c_dev,
1865                                           bool enable)
1866 {
1867         int ret;
1868
1869         if (i2c_dev->speed != STM32_I2C_SPEED_FAST_PLUS ||
1870             IS_ERR_OR_NULL(i2c_dev->regmap))
1871                 /* Optional */
1872                 return 0;
1873
1874         if (i2c_dev->fmp_sreg == i2c_dev->fmp_creg)
1875                 ret = regmap_update_bits(i2c_dev->regmap,
1876                                          i2c_dev->fmp_sreg,
1877                                          i2c_dev->fmp_mask,
1878                                          enable ? i2c_dev->fmp_mask : 0);
1879         else
1880                 ret = regmap_write(i2c_dev->regmap,
1881                                    enable ? i2c_dev->fmp_sreg :
1882                                             i2c_dev->fmp_creg,
1883                                    i2c_dev->fmp_mask);
1884
1885         return ret;
1886 }
1887
1888 static int stm32f7_i2c_setup_fm_plus_bits(struct platform_device *pdev,
1889                                           struct stm32f7_i2c_dev *i2c_dev)
1890 {
1891         struct device_node *np = pdev->dev.of_node;
1892         int ret;
1893
1894         i2c_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg-fmp");
1895         if (IS_ERR(i2c_dev->regmap))
1896                 /* Optional */
1897                 return 0;
1898
1899         ret = of_property_read_u32_index(np, "st,syscfg-fmp", 1,
1900                                          &i2c_dev->fmp_sreg);
1901         if (ret)
1902                 return ret;
1903
1904         i2c_dev->fmp_creg = i2c_dev->fmp_sreg +
1905                                i2c_dev->setup.fmp_clr_offset;
1906
1907         return of_property_read_u32_index(np, "st,syscfg-fmp", 2,
1908                                           &i2c_dev->fmp_mask);
1909 }
1910
1911 static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
1912 {
1913         return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE |
1914                 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
1915                 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
1916                 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
1917                 I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC |
1918                 I2C_FUNC_SMBUS_I2C_BLOCK;
1919 }
1920
1921 static const struct i2c_algorithm stm32f7_i2c_algo = {
1922         .master_xfer = stm32f7_i2c_xfer,
1923         .smbus_xfer = stm32f7_i2c_smbus_xfer,
1924         .functionality = stm32f7_i2c_func,
1925         .reg_slave = stm32f7_i2c_reg_slave,
1926         .unreg_slave = stm32f7_i2c_unreg_slave,
1927 };
1928
1929 static int stm32f7_i2c_probe(struct platform_device *pdev)
1930 {
1931         struct stm32f7_i2c_dev *i2c_dev;
1932         const struct stm32f7_i2c_setup *setup;
1933         struct resource *res;
1934         struct i2c_adapter *adap;
1935         struct reset_control *rst;
1936         dma_addr_t phy_addr;
1937         int irq_error, irq_event, ret;
1938
1939         i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
1940         if (!i2c_dev)
1941                 return -ENOMEM;
1942
1943         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1944         i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
1945         if (IS_ERR(i2c_dev->base))
1946                 return PTR_ERR(i2c_dev->base);
1947         phy_addr = (dma_addr_t)res->start;
1948
1949         irq_event = platform_get_irq(pdev, 0);
1950         if (irq_event <= 0) {
1951                 if (irq_event != -EPROBE_DEFER)
1952                         dev_err(&pdev->dev, "Failed to get IRQ event: %d\n",
1953                                 irq_event);
1954                 return irq_event ? : -ENOENT;
1955         }
1956
1957         irq_error = platform_get_irq(pdev, 1);
1958         if (irq_error <= 0) {
1959                 if (irq_error != -EPROBE_DEFER)
1960                         dev_err(&pdev->dev, "Failed to get IRQ error: %d\n",
1961                                 irq_error);
1962                 return irq_error ? : -ENOENT;
1963         }
1964
1965         i2c_dev->wakeup_src = of_property_read_bool(pdev->dev.of_node,
1966                                                     "wakeup-source");
1967
1968         i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
1969         if (IS_ERR(i2c_dev->clk)) {
1970                 dev_err(&pdev->dev, "Error: Missing controller clock\n");
1971                 return PTR_ERR(i2c_dev->clk);
1972         }
1973
1974         ret = clk_prepare_enable(i2c_dev->clk);
1975         if (ret) {
1976                 dev_err(&pdev->dev, "Failed to prepare_enable clock\n");
1977                 return ret;
1978         }
1979
1980         rst = devm_reset_control_get(&pdev->dev, NULL);
1981         if (IS_ERR(rst)) {
1982                 dev_err(&pdev->dev, "Error: Missing controller reset\n");
1983                 ret = PTR_ERR(rst);
1984                 goto clk_free;
1985         }
1986         reset_control_assert(rst);
1987         udelay(2);
1988         reset_control_deassert(rst);
1989
1990         i2c_dev->dev = &pdev->dev;
1991
1992         ret = devm_request_threaded_irq(&pdev->dev, irq_event,
1993                                         stm32f7_i2c_isr_event,
1994                                         stm32f7_i2c_isr_event_thread,
1995                                         IRQF_ONESHOT,
1996                                         pdev->name, i2c_dev);
1997         if (ret) {
1998                 dev_err(&pdev->dev, "Failed to request irq event %i\n",
1999                         irq_event);
2000                 goto clk_free;
2001         }
2002
2003         ret = devm_request_irq(&pdev->dev, irq_error, stm32f7_i2c_isr_error, 0,
2004                                pdev->name, i2c_dev);
2005         if (ret) {
2006                 dev_err(&pdev->dev, "Failed to request irq error %i\n",
2007                         irq_error);
2008                 goto clk_free;
2009         }
2010
2011         setup = of_device_get_match_data(&pdev->dev);
2012         if (!setup) {
2013                 dev_err(&pdev->dev, "Can't get device data\n");
2014                 ret = -ENODEV;
2015                 goto clk_free;
2016         }
2017         i2c_dev->setup = *setup;
2018
2019         ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup);
2020         if (ret)
2021                 goto clk_free;
2022
2023         if (i2c_dev->speed == STM32_I2C_SPEED_FAST_PLUS) {
2024                 ret = stm32f7_i2c_setup_fm_plus_bits(pdev, i2c_dev);
2025                 if (ret)
2026                         goto clk_free;
2027                 ret = stm32f7_i2c_write_fm_plus_bits(i2c_dev, true);
2028                 if (ret)
2029                         goto clk_free;
2030         }
2031
2032         adap = &i2c_dev->adap;
2033         i2c_set_adapdata(adap, i2c_dev);
2034         snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)",
2035                  &res->start);
2036         adap->owner = THIS_MODULE;
2037         adap->timeout = 2 * HZ;
2038         adap->retries = 3;
2039         adap->algo = &stm32f7_i2c_algo;
2040         adap->dev.parent = &pdev->dev;
2041         adap->dev.of_node = pdev->dev.of_node;
2042
2043         init_completion(&i2c_dev->complete);
2044
2045         /* Init DMA config if supported */
2046         i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr,
2047                                              STM32F7_I2C_TXDR,
2048                                              STM32F7_I2C_RXDR);
2049         if (PTR_ERR(i2c_dev->dma) == -ENODEV)
2050                 i2c_dev->dma = NULL;
2051         else if (IS_ERR(i2c_dev->dma)) {
2052                 ret = PTR_ERR(i2c_dev->dma);
2053                 if (ret != -EPROBE_DEFER)
2054                         dev_err(&pdev->dev,
2055                                 "Failed to request dma error %i\n", ret);
2056                 goto fmp_clear;
2057         }
2058
2059         if (i2c_dev->wakeup_src) {
2060                 device_set_wakeup_capable(i2c_dev->dev, true);
2061
2062                 ret = dev_pm_set_wake_irq(i2c_dev->dev, irq_event);
2063                 if (ret) {
2064                         dev_err(i2c_dev->dev, "Failed to set wake up irq\n");
2065                         goto clr_wakeup_capable;
2066                 }
2067         }
2068
2069         platform_set_drvdata(pdev, i2c_dev);
2070
2071         pm_runtime_set_autosuspend_delay(i2c_dev->dev,
2072                                          STM32F7_AUTOSUSPEND_DELAY);
2073         pm_runtime_use_autosuspend(i2c_dev->dev);
2074         pm_runtime_set_active(i2c_dev->dev);
2075         pm_runtime_enable(i2c_dev->dev);
2076
2077         pm_runtime_get_noresume(&pdev->dev);
2078
2079         stm32f7_i2c_hw_config(i2c_dev);
2080
2081         ret = i2c_add_adapter(adap);
2082         if (ret)
2083                 goto pm_disable;
2084
2085         dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr);
2086
2087         pm_runtime_mark_last_busy(i2c_dev->dev);
2088         pm_runtime_put_autosuspend(i2c_dev->dev);
2089
2090         return 0;
2091
2092 pm_disable:
2093         pm_runtime_put_noidle(i2c_dev->dev);
2094         pm_runtime_disable(i2c_dev->dev);
2095         pm_runtime_set_suspended(i2c_dev->dev);
2096         pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2097
2098         if (i2c_dev->wakeup_src)
2099                 dev_pm_clear_wake_irq(i2c_dev->dev);
2100
2101 clr_wakeup_capable:
2102         if (i2c_dev->wakeup_src)
2103                 device_set_wakeup_capable(i2c_dev->dev, false);
2104
2105         if (i2c_dev->dma) {
2106                 stm32_i2c_dma_free(i2c_dev->dma);
2107                 i2c_dev->dma = NULL;
2108         }
2109
2110 fmp_clear:
2111         stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2112
2113 clk_free:
2114         clk_disable_unprepare(i2c_dev->clk);
2115
2116         return ret;
2117 }
2118
2119 static int stm32f7_i2c_remove(struct platform_device *pdev)
2120 {
2121         struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
2122
2123         i2c_del_adapter(&i2c_dev->adap);
2124         pm_runtime_get_sync(i2c_dev->dev);
2125
2126         if (i2c_dev->wakeup_src) {
2127                 dev_pm_clear_wake_irq(i2c_dev->dev);
2128                 /*
2129                  * enforce that wakeup is disabled and that the device
2130                  * is marked as non wakeup capable
2131                  */
2132                 device_init_wakeup(i2c_dev->dev, false);
2133         }
2134
2135         pm_runtime_put_noidle(i2c_dev->dev);
2136         pm_runtime_disable(i2c_dev->dev);
2137         pm_runtime_set_suspended(i2c_dev->dev);
2138         pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2139
2140         if (i2c_dev->dma) {
2141                 stm32_i2c_dma_free(i2c_dev->dma);
2142                 i2c_dev->dma = NULL;
2143         }
2144
2145         stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2146
2147         clk_disable_unprepare(i2c_dev->clk);
2148
2149         return 0;
2150 }
2151
2152 static int __maybe_unused stm32f7_i2c_runtime_suspend(struct device *dev)
2153 {
2154         struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2155
2156         if (!stm32f7_i2c_is_slave_registered(i2c_dev))
2157                 clk_disable_unprepare(i2c_dev->clk);
2158
2159         return 0;
2160 }
2161
2162 static int __maybe_unused stm32f7_i2c_runtime_resume(struct device *dev)
2163 {
2164         struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2165         int ret;
2166
2167         if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
2168                 ret = clk_prepare_enable(i2c_dev->clk);
2169                 if (ret) {
2170                         dev_err(dev, "failed to prepare_enable clock\n");
2171                         return ret;
2172                 }
2173         }
2174
2175         return 0;
2176 }
2177
2178 #ifdef CONFIG_PM_SLEEP
2179 static int stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev *i2c_dev)
2180 {
2181         int ret;
2182         struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2183
2184         ret = pm_runtime_get_sync(i2c_dev->dev);
2185         if (ret < 0)
2186                 return ret;
2187
2188         backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2189         backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
2190         backup_regs->oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
2191         backup_regs->oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
2192         backup_regs->tmgr = readl_relaxed(i2c_dev->base + STM32F7_I2C_TIMINGR);
2193         stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2194
2195         pm_runtime_put_sync(i2c_dev->dev);
2196
2197         return ret;
2198 }
2199
2200 static int stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev *i2c_dev)
2201 {
2202         u32 cr1;
2203         int ret;
2204         struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2205
2206         ret = pm_runtime_get_sync(i2c_dev->dev);
2207         if (ret < 0)
2208                 return ret;
2209
2210         cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2211         if (cr1 & STM32F7_I2C_CR1_PE)
2212                 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
2213                                      STM32F7_I2C_CR1_PE);
2214
2215         writel_relaxed(backup_regs->tmgr, i2c_dev->base + STM32F7_I2C_TIMINGR);
2216         writel_relaxed(backup_regs->cr1 & ~STM32F7_I2C_CR1_PE,
2217                        i2c_dev->base + STM32F7_I2C_CR1);
2218         if (backup_regs->cr1 & STM32F7_I2C_CR1_PE)
2219                 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
2220                                      STM32F7_I2C_CR1_PE);
2221         writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2);
2222         writel_relaxed(backup_regs->oar1, i2c_dev->base + STM32F7_I2C_OAR1);
2223         writel_relaxed(backup_regs->oar2, i2c_dev->base + STM32F7_I2C_OAR2);
2224         stm32f7_i2c_write_fm_plus_bits(i2c_dev, true);
2225
2226         pm_runtime_put_sync(i2c_dev->dev);
2227
2228         return ret;
2229 }
2230
2231 static int stm32f7_i2c_suspend(struct device *dev)
2232 {
2233         struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2234         int ret;
2235
2236         i2c_mark_adapter_suspended(&i2c_dev->adap);
2237
2238         if (!device_may_wakeup(dev) && !dev->power.wakeup_path) {
2239                 ret = stm32f7_i2c_regs_backup(i2c_dev);
2240                 if (ret < 0) {
2241                         i2c_mark_adapter_resumed(&i2c_dev->adap);
2242                         return ret;
2243                 }
2244
2245                 pinctrl_pm_select_sleep_state(dev);
2246                 pm_runtime_force_suspend(dev);
2247         }
2248
2249         return 0;
2250 }
2251
2252 static int stm32f7_i2c_resume(struct device *dev)
2253 {
2254         struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2255         int ret;
2256
2257         if (!device_may_wakeup(dev) && !dev->power.wakeup_path) {
2258                 ret = pm_runtime_force_resume(dev);
2259                 if (ret < 0)
2260                         return ret;
2261                 pinctrl_pm_select_default_state(dev);
2262
2263                 ret = stm32f7_i2c_regs_restore(i2c_dev);
2264                 if (ret < 0)
2265                         return ret;
2266         }
2267
2268         i2c_mark_adapter_resumed(&i2c_dev->adap);
2269
2270         return 0;
2271 }
2272 #endif
2273
2274 static const struct dev_pm_ops stm32f7_i2c_pm_ops = {
2275         SET_RUNTIME_PM_OPS(stm32f7_i2c_runtime_suspend,
2276                            stm32f7_i2c_runtime_resume, NULL)
2277         SET_SYSTEM_SLEEP_PM_OPS(stm32f7_i2c_suspend, stm32f7_i2c_resume)
2278 };
2279
2280 static const struct of_device_id stm32f7_i2c_match[] = {
2281         { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup},
2282         { .compatible = "st,stm32mp15-i2c", .data = &stm32mp15_setup},
2283         {},
2284 };
2285 MODULE_DEVICE_TABLE(of, stm32f7_i2c_match);
2286
2287 static struct platform_driver stm32f7_i2c_driver = {
2288         .driver = {
2289                 .name = "stm32f7-i2c",
2290                 .of_match_table = stm32f7_i2c_match,
2291                 .pm = &stm32f7_i2c_pm_ops,
2292         },
2293         .probe = stm32f7_i2c_probe,
2294         .remove = stm32f7_i2c_remove,
2295 };
2296
2297 module_platform_driver(stm32f7_i2c_driver);
2298
2299 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
2300 MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver");
2301 MODULE_LICENSE("GPL v2");