2 * Driver for STMicroelectronics STM32F7 I2C controller
4 * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc
6 * Please see below a link to the documentation:
7 * http://www.st.com/resource/en/reference_manual/dm00124865.pdf
9 * Copyright (C) M'boumba Cedric Madianga 2017
10 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
12 * This driver is based on i2c-stm32f4.c
14 * License terms: GNU General Public License (GPL), version 2
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/err.h>
19 #include <linux/i2c.h>
20 #include <linux/interrupt.h>
22 #include <linux/iopoll.h>
23 #include <linux/module.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_platform.h>
28 #include <linux/platform_device.h>
29 #include <linux/reset.h>
30 #include <linux/slab.h>
32 #include "i2c-stm32.h"
34 /* STM32F7 I2C registers */
35 #define STM32F7_I2C_CR1 0x00
36 #define STM32F7_I2C_CR2 0x04
37 #define STM32F7_I2C_TIMINGR 0x10
38 #define STM32F7_I2C_ISR 0x18
39 #define STM32F7_I2C_ICR 0x1C
40 #define STM32F7_I2C_RXDR 0x24
41 #define STM32F7_I2C_TXDR 0x28
43 /* STM32F7 I2C control 1 */
44 #define STM32F7_I2C_CR1_ANFOFF BIT(12)
45 #define STM32F7_I2C_CR1_ERRIE BIT(7)
46 #define STM32F7_I2C_CR1_TCIE BIT(6)
47 #define STM32F7_I2C_CR1_STOPIE BIT(5)
48 #define STM32F7_I2C_CR1_NACKIE BIT(4)
49 #define STM32F7_I2C_CR1_ADDRIE BIT(3)
50 #define STM32F7_I2C_CR1_RXIE BIT(2)
51 #define STM32F7_I2C_CR1_TXIE BIT(1)
52 #define STM32F7_I2C_CR1_PE BIT(0)
53 #define STM32F7_I2C_ALL_IRQ_MASK (STM32F7_I2C_CR1_ERRIE \
54 | STM32F7_I2C_CR1_TCIE \
55 | STM32F7_I2C_CR1_STOPIE \
56 | STM32F7_I2C_CR1_NACKIE \
57 | STM32F7_I2C_CR1_RXIE \
58 | STM32F7_I2C_CR1_TXIE)
60 /* STM32F7 I2C control 2 */
61 #define STM32F7_I2C_CR2_RELOAD BIT(24)
62 #define STM32F7_I2C_CR2_NBYTES_MASK GENMASK(23, 16)
63 #define STM32F7_I2C_CR2_NBYTES(n) (((n) & 0xff) << 16)
64 #define STM32F7_I2C_CR2_NACK BIT(15)
65 #define STM32F7_I2C_CR2_STOP BIT(14)
66 #define STM32F7_I2C_CR2_START BIT(13)
67 #define STM32F7_I2C_CR2_RD_WRN BIT(10)
68 #define STM32F7_I2C_CR2_SADD7_MASK GENMASK(7, 1)
69 #define STM32F7_I2C_CR2_SADD7(n) (((n) & 0x7f) << 1)
71 /* STM32F7 I2C Interrupt Status */
72 #define STM32F7_I2C_ISR_BUSY BIT(15)
73 #define STM32F7_I2C_ISR_ARLO BIT(9)
74 #define STM32F7_I2C_ISR_BERR BIT(8)
75 #define STM32F7_I2C_ISR_TCR BIT(7)
76 #define STM32F7_I2C_ISR_TC BIT(6)
77 #define STM32F7_I2C_ISR_STOPF BIT(5)
78 #define STM32F7_I2C_ISR_NACKF BIT(4)
79 #define STM32F7_I2C_ISR_RXNE BIT(2)
80 #define STM32F7_I2C_ISR_TXIS BIT(1)
82 /* STM32F7 I2C Interrupt Clear */
83 #define STM32F7_I2C_ICR_ARLOCF BIT(9)
84 #define STM32F7_I2C_ICR_BERRCF BIT(8)
85 #define STM32F7_I2C_ICR_STOPCF BIT(5)
86 #define STM32F7_I2C_ICR_NACKCF BIT(4)
88 /* STM32F7 I2C Timing */
89 #define STM32F7_I2C_TIMINGR_PRESC(n) (((n) & 0xf) << 28)
90 #define STM32F7_I2C_TIMINGR_SCLDEL(n) (((n) & 0xf) << 20)
91 #define STM32F7_I2C_TIMINGR_SDADEL(n) (((n) & 0xf) << 16)
92 #define STM32F7_I2C_TIMINGR_SCLH(n) (((n) & 0xff) << 8)
93 #define STM32F7_I2C_TIMINGR_SCLL(n) ((n) & 0xff)
95 #define STM32F7_I2C_MAX_LEN 0xff
97 #define STM32F7_I2C_DNF_DEFAULT 0
98 #define STM32F7_I2C_DNF_MAX 16
100 #define STM32F7_I2C_ANALOG_FILTER_ENABLE 1
101 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */
102 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
104 #define STM32F7_I2C_RISE_TIME_DEFAULT 25 /* ns */
105 #define STM32F7_I2C_FALL_TIME_DEFAULT 10 /* ns */
107 #define STM32F7_PRESC_MAX BIT(4)
108 #define STM32F7_SCLDEL_MAX BIT(4)
109 #define STM32F7_SDADEL_MAX BIT(4)
110 #define STM32F7_SCLH_MAX BIT(8)
111 #define STM32F7_SCLL_MAX BIT(8)
114 * struct stm32f7_i2c_spec - private i2c specification timing
115 * @rate: I2C bus speed (Hz)
116 * @rate_min: 80% of I2C bus speed (Hz)
117 * @rate_max: 100% of I2C bus speed (Hz)
118 * @fall_max: Max fall time of both SDA and SCL signals (ns)
119 * @rise_max: Max rise time of both SDA and SCL signals (ns)
120 * @hddat_min: Min data hold time (ns)
121 * @vddat_max: Max data valid time (ns)
122 * @sudat_min: Min data setup time (ns)
123 * @l_min: Min low period of the SCL clock (ns)
124 * @h_min: Min high period of the SCL clock (ns)
126 struct stm32f7_i2c_spec {
140 * struct stm32f7_i2c_setup - private I2C timing setup parameters
141 * @speed: I2C speed mode (standard, Fast Plus)
142 * @speed_freq: I2C speed frequency (Hz)
143 * @clock_src: I2C clock source frequency (Hz)
144 * @rise_time: Rise time (ns)
145 * @fall_time: Fall time (ns)
146 * @dnf: Digital filter coefficient (0-16)
147 * @analog_filter: Analog filter delay (On/Off)
149 struct stm32f7_i2c_setup {
150 enum stm32_i2c_speed speed;
160 * struct stm32f7_i2c_timings - private I2C output parameters
161 * @prec: Prescaler value
162 * @scldel: Data setup time
163 * @sdadel: Data hold time
164 * @sclh: SCL high period (master mode)
165 * @sclh: SCL low period (master mode)
167 struct stm32f7_i2c_timings {
168 struct list_head node;
177 * struct stm32f7_i2c_msg - client specific data
178 * @addr: 8-bit slave addr, including r/w bit
179 * @count: number of bytes to be transferred
181 * @result: result of the transfer
182 * @stop: last I2C msg to be sent, i.e. STOP to be generated
184 struct stm32f7_i2c_msg {
193 * struct stm32f7_i2c_dev - private data of the controller
194 * @adap: I2C adapter for this controller
195 * @dev: device for this controller
196 * @base: virtual memory area
197 * @complete: completion of I2C message
199 * @speed: I2C clock frequency of the controller. Standard, Fast or Fast+
200 * @msg: Pointer to data to be written
201 * @msg_num: number of I2C messages to be executed
202 * @msg_id: message identifiant
203 * @f7_msg: customized i2c msg for driver usage
204 * @setup: I2C timing input setup
205 * @timing: I2C computed timings
207 struct stm32f7_i2c_dev {
208 struct i2c_adapter adap;
211 struct completion complete;
215 unsigned int msg_num;
217 struct stm32f7_i2c_msg f7_msg;
218 struct stm32f7_i2c_setup setup;
219 struct stm32f7_i2c_timings timing;
223 * All these values are coming from I2C Specification, Version 6.0, 4th of
226 * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast,
227 * and Fast-mode Plus I2C-bus devices
229 static struct stm32f7_i2c_spec i2c_specs[] = {
230 [STM32_I2C_SPEED_STANDARD] = {
242 [STM32_I2C_SPEED_FAST] = {
254 [STM32_I2C_SPEED_FAST_PLUS] = {
268 static const struct stm32f7_i2c_setup stm32f7_setup = {
269 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
270 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
271 .dnf = STM32F7_I2C_DNF_DEFAULT,
272 .analog_filter = STM32F7_I2C_ANALOG_FILTER_ENABLE,
275 static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask)
277 writel_relaxed(readl_relaxed(reg) | mask, reg);
280 static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask)
282 writel_relaxed(readl_relaxed(reg) & ~mask, reg);
285 static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev,
286 struct stm32f7_i2c_setup *setup,
287 struct stm32f7_i2c_timings *output)
289 u32 p_prev = STM32F7_PRESC_MAX;
290 u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
292 u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
294 u32 clk_error_prev = i2cbus;
296 u32 af_delay_min, af_delay_max;
298 u32 clk_min, clk_max;
299 int sdadel_min, sdadel_max;
301 struct stm32f7_i2c_timings *v, *_v, *s;
302 struct list_head solutions;
306 if (setup->speed >= STM32_I2C_SPEED_END) {
307 dev_err(i2c_dev->dev, "speed out of bound {%d/%d}\n",
308 setup->speed, STM32_I2C_SPEED_END - 1);
312 if ((setup->rise_time > i2c_specs[setup->speed].rise_max) ||
313 (setup->fall_time > i2c_specs[setup->speed].fall_max)) {
314 dev_err(i2c_dev->dev,
315 "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
316 setup->rise_time, i2c_specs[setup->speed].rise_max,
317 setup->fall_time, i2c_specs[setup->speed].fall_max);
321 if (setup->dnf > STM32F7_I2C_DNF_MAX) {
322 dev_err(i2c_dev->dev,
323 "DNF out of bound %d/%d\n",
324 setup->dnf, STM32F7_I2C_DNF_MAX);
328 if (setup->speed_freq > i2c_specs[setup->speed].rate) {
329 dev_err(i2c_dev->dev, "ERROR: Freq {%d/%d}\n",
330 setup->speed_freq, i2c_specs[setup->speed].rate);
334 /* Analog and Digital Filters */
336 (setup->analog_filter ?
337 STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0);
339 (setup->analog_filter ?
340 STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0);
341 dnf_delay = setup->dnf * i2cclk;
343 sdadel_min = setup->fall_time - i2c_specs[setup->speed].hddat_min -
344 af_delay_min - (setup->dnf + 3) * i2cclk;
346 sdadel_max = i2c_specs[setup->speed].vddat_max - setup->rise_time -
347 af_delay_max - (setup->dnf + 4) * i2cclk;
349 scldel_min = setup->rise_time + i2c_specs[setup->speed].sudat_min;
356 dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n",
357 sdadel_min, sdadel_max, scldel_min);
359 INIT_LIST_HEAD(&solutions);
360 /* Compute possible values for PRESC, SCLDEL and SDADEL */
361 for (p = 0; p < STM32F7_PRESC_MAX; p++) {
362 for (l = 0; l < STM32F7_SCLDEL_MAX; l++) {
363 u32 scldel = (l + 1) * (p + 1) * i2cclk;
365 if (scldel < scldel_min)
368 for (a = 0; a < STM32F7_SDADEL_MAX; a++) {
369 u32 sdadel = (a * (p + 1) + 1) * i2cclk;
371 if (((sdadel >= sdadel_min) &&
372 (sdadel <= sdadel_max)) &&
374 v = kmalloc(sizeof(*v), GFP_KERNEL);
385 list_add_tail(&v->node,
392 if (list_empty(&solutions)) {
393 dev_err(i2c_dev->dev, "no Prescaler solution\n");
398 tsync = af_delay_min + dnf_delay + (2 * i2cclk);
400 clk_max = NSEC_PER_SEC / i2c_specs[setup->speed].rate_min;
401 clk_min = NSEC_PER_SEC / i2c_specs[setup->speed].rate_max;
404 * Among Prescaler possibilities discovered above figures out SCL Low
405 * and High Period. Provided:
406 * - SCL Low Period has to be higher than SCL Clock Low Period
407 * defined by I2C Specification. I2C Clock has to be lower than
408 * (SCL Low Period - Analog/Digital filters) / 4.
409 * - SCL High Period has to be lower than SCL Clock High Period
410 * defined by I2C Specification
411 * - I2C Clock has to be lower than SCL High Period
413 list_for_each_entry(v, &solutions, node) {
414 u32 prescaler = (v->presc + 1) * i2cclk;
416 for (l = 0; l < STM32F7_SCLL_MAX; l++) {
417 u32 tscl_l = (l + 1) * prescaler + tsync;
419 if ((tscl_l < i2c_specs[setup->speed].l_min) ||
421 ((tscl_l - af_delay_min - dnf_delay) / 4))) {
425 for (h = 0; h < STM32F7_SCLH_MAX; h++) {
426 u32 tscl_h = (h + 1) * prescaler + tsync;
427 u32 tscl = tscl_l + tscl_h +
428 setup->rise_time + setup->fall_time;
430 if ((tscl >= clk_min) && (tscl <= clk_max) &&
431 (tscl_h >= i2c_specs[setup->speed].h_min) &&
433 int clk_error = tscl - i2cbus;
436 clk_error = -clk_error;
438 if (clk_error < clk_error_prev) {
439 clk_error_prev = clk_error;
450 dev_err(i2c_dev->dev, "no solution at all\n");
455 output->presc = s->presc;
456 output->scldel = s->scldel;
457 output->sdadel = s->sdadel;
458 output->scll = s->scll;
459 output->sclh = s->sclh;
461 dev_dbg(i2c_dev->dev,
462 "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
464 output->scldel, output->sdadel,
465 output->scll, output->sclh);
468 /* Release list and memory */
469 list_for_each_entry_safe(v, _v, &solutions, node) {
477 static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev,
478 struct stm32f7_i2c_setup *setup)
482 setup->speed = i2c_dev->speed;
483 setup->speed_freq = i2c_specs[setup->speed].rate;
484 setup->clock_src = clk_get_rate(i2c_dev->clk);
486 if (!setup->clock_src) {
487 dev_err(i2c_dev->dev, "clock rate is 0\n");
492 ret = stm32f7_i2c_compute_timing(i2c_dev, setup,
495 dev_err(i2c_dev->dev,
496 "failed to compute I2C timings.\n");
497 if (i2c_dev->speed > STM32_I2C_SPEED_STANDARD) {
499 setup->speed = i2c_dev->speed;
501 i2c_specs[setup->speed].rate;
502 dev_warn(i2c_dev->dev,
503 "downgrade I2C Speed Freq to (%i)\n",
504 i2c_specs[setup->speed].rate);
512 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n");
516 dev_dbg(i2c_dev->dev, "I2C Speed(%i), Freq(%i), Clk Source(%i)\n",
517 setup->speed, setup->speed_freq, setup->clock_src);
518 dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n",
519 setup->rise_time, setup->fall_time);
520 dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n",
521 (setup->analog_filter ? "On" : "Off"), setup->dnf);
526 static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev)
528 struct stm32f7_i2c_timings *t = &i2c_dev->timing;
531 /* Timing settings */
532 timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc);
533 timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel);
534 timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel);
535 timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh);
536 timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll);
537 writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR);
540 if (i2c_dev->setup.analog_filter)
541 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
542 STM32F7_I2C_CR1_ANFOFF);
544 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
545 STM32F7_I2C_CR1_ANFOFF);
546 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
550 static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev)
552 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
553 void __iomem *base = i2c_dev->base;
556 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR);
561 static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev)
563 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
564 void __iomem *base = i2c_dev->base;
567 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR);
572 static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev)
574 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
577 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
579 cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK;
580 if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
581 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
583 cr2 &= ~STM32F7_I2C_CR2_RELOAD;
584 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
587 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
590 static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev)
595 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR,
597 !(status & STM32F7_I2C_ISR_BUSY),
600 dev_dbg(i2c_dev->dev, "bus busy\n");
607 static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
610 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
611 void __iomem *base = i2c_dev->base;
614 f7_msg->addr = msg->addr;
615 f7_msg->buf = msg->buf;
616 f7_msg->count = msg->len;
618 f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1);
620 reinit_completion(&i2c_dev->complete);
622 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
623 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
625 /* Set transfer direction */
626 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
627 if (msg->flags & I2C_M_RD)
628 cr2 |= STM32F7_I2C_CR2_RD_WRN;
630 /* Set slave address */
631 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK;
632 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
634 /* Set nb bytes to transfer and reload if needed */
635 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
636 if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
637 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
638 cr2 |= STM32F7_I2C_CR2_RELOAD;
640 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
643 /* Enable NACK, STOP, error and transfer complete interrupts */
644 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
645 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
647 /* Clear TX/RX interrupt */
648 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE);
650 /* Enable RX/TX interrupt according to msg direction */
651 if (msg->flags & I2C_M_RD)
652 cr1 |= STM32F7_I2C_CR1_RXIE;
654 cr1 |= STM32F7_I2C_CR1_TXIE;
656 /* Configure Start/Repeated Start */
657 cr2 |= STM32F7_I2C_CR2_START;
659 /* Write configurations registers */
660 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
661 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
664 static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)
666 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
669 static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
671 struct stm32f7_i2c_dev *i2c_dev = data;
672 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
673 void __iomem *base = i2c_dev->base;
676 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
679 if (status & STM32F7_I2C_ISR_TXIS)
680 stm32f7_i2c_write_tx_data(i2c_dev);
683 if (status & STM32F7_I2C_ISR_RXNE)
684 stm32f7_i2c_read_rx_data(i2c_dev);
687 if (status & STM32F7_I2C_ISR_NACKF) {
688 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
689 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
690 f7_msg->result = -ENXIO;
693 /* STOP detection flag */
694 if (status & STM32F7_I2C_ISR_STOPF) {
695 /* Disable interrupts */
696 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
698 /* Clear STOP flag */
699 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
701 complete(&i2c_dev->complete);
704 /* Transfer complete */
705 if (status & STM32F7_I2C_ISR_TC) {
707 mask = STM32F7_I2C_CR2_STOP;
708 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
712 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
717 * Transfer Complete Reload: 255 data bytes have been transferred
718 * We have to prepare the I2C controller to transfer the remaining
721 if (status & STM32F7_I2C_ISR_TCR)
722 stm32f7_i2c_reload(i2c_dev);
727 static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data)
729 struct stm32f7_i2c_dev *i2c_dev = data;
730 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
731 void __iomem *base = i2c_dev->base;
732 struct device *dev = i2c_dev->dev;
735 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
738 if (status & STM32F7_I2C_ISR_BERR) {
739 dev_err(dev, "<%s>: Bus error\n", __func__);
740 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR);
741 f7_msg->result = -EIO;
744 /* Arbitration loss */
745 if (status & STM32F7_I2C_ISR_ARLO) {
746 dev_dbg(dev, "<%s>: Arbitration loss\n", __func__);
747 writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR);
748 f7_msg->result = -EAGAIN;
751 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
753 complete(&i2c_dev->complete);
758 static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap,
759 struct i2c_msg msgs[], int num)
761 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
762 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
763 unsigned long time_left;
767 i2c_dev->msg_num = num;
770 ret = clk_enable(i2c_dev->clk);
772 dev_err(i2c_dev->dev, "Failed to enable clock\n");
776 ret = stm32f7_i2c_wait_free_bus(i2c_dev);
780 stm32f7_i2c_xfer_msg(i2c_dev, msgs);
782 time_left = wait_for_completion_timeout(&i2c_dev->complete,
783 i2c_dev->adap.timeout);
784 ret = f7_msg->result;
787 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n",
793 clk_disable(i2c_dev->clk);
795 return (ret < 0) ? ret : num;
798 static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
800 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
803 static struct i2c_algorithm stm32f7_i2c_algo = {
804 .master_xfer = stm32f7_i2c_xfer,
805 .functionality = stm32f7_i2c_func,
808 static int stm32f7_i2c_probe(struct platform_device *pdev)
810 struct device_node *np = pdev->dev.of_node;
811 struct stm32f7_i2c_dev *i2c_dev;
812 const struct stm32f7_i2c_setup *setup;
813 struct resource *res;
814 u32 irq_error, irq_event, clk_rate, rise_time, fall_time;
815 struct i2c_adapter *adap;
816 struct reset_control *rst;
819 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
823 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
824 i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
825 if (IS_ERR(i2c_dev->base))
826 return PTR_ERR(i2c_dev->base);
828 irq_event = irq_of_parse_and_map(np, 0);
830 dev_err(&pdev->dev, "IRQ event missing or invalid\n");
834 irq_error = irq_of_parse_and_map(np, 1);
836 dev_err(&pdev->dev, "IRQ error missing or invalid\n");
840 i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
841 if (IS_ERR(i2c_dev->clk)) {
842 dev_err(&pdev->dev, "Error: Missing controller clock\n");
843 return PTR_ERR(i2c_dev->clk);
845 ret = clk_prepare_enable(i2c_dev->clk);
847 dev_err(&pdev->dev, "Failed to prepare_enable clock\n");
851 i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
852 ret = device_property_read_u32(&pdev->dev, "clock-frequency",
854 if (!ret && clk_rate >= 1000000)
855 i2c_dev->speed = STM32_I2C_SPEED_FAST_PLUS;
856 else if (!ret && clk_rate >= 400000)
857 i2c_dev->speed = STM32_I2C_SPEED_FAST;
858 else if (!ret && clk_rate >= 100000)
859 i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
861 rst = devm_reset_control_get(&pdev->dev, NULL);
863 dev_err(&pdev->dev, "Error: Missing controller reset\n");
867 reset_control_assert(rst);
869 reset_control_deassert(rst);
871 i2c_dev->dev = &pdev->dev;
873 ret = devm_request_irq(&pdev->dev, irq_event, stm32f7_i2c_isr_event, 0,
874 pdev->name, i2c_dev);
876 dev_err(&pdev->dev, "Failed to request irq event %i\n",
881 ret = devm_request_irq(&pdev->dev, irq_error, stm32f7_i2c_isr_error, 0,
882 pdev->name, i2c_dev);
884 dev_err(&pdev->dev, "Failed to request irq error %i\n",
889 setup = of_device_get_match_data(&pdev->dev);
890 i2c_dev->setup = *setup;
892 ret = device_property_read_u32(i2c_dev->dev, "i2c-scl-rising-time-ns",
895 i2c_dev->setup.rise_time = rise_time;
897 ret = device_property_read_u32(i2c_dev->dev, "i2c-scl-falling-time-ns",
900 i2c_dev->setup.fall_time = fall_time;
902 ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup);
906 stm32f7_i2c_hw_config(i2c_dev);
908 adap = &i2c_dev->adap;
909 i2c_set_adapdata(adap, i2c_dev);
910 snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)",
912 adap->owner = THIS_MODULE;
913 adap->timeout = 2 * HZ;
915 adap->algo = &stm32f7_i2c_algo;
916 adap->dev.parent = &pdev->dev;
917 adap->dev.of_node = pdev->dev.of_node;
919 init_completion(&i2c_dev->complete);
921 ret = i2c_add_adapter(adap);
925 platform_set_drvdata(pdev, i2c_dev);
927 clk_disable(i2c_dev->clk);
929 dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr);
934 clk_disable_unprepare(i2c_dev->clk);
939 static int stm32f7_i2c_remove(struct platform_device *pdev)
941 struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
943 i2c_del_adapter(&i2c_dev->adap);
945 clk_unprepare(i2c_dev->clk);
950 static const struct of_device_id stm32f7_i2c_match[] = {
951 { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup},
954 MODULE_DEVICE_TABLE(of, stm32f7_i2c_match);
956 static struct platform_driver stm32f7_i2c_driver = {
958 .name = "stm32f7-i2c",
959 .of_match_table = stm32f7_i2c_match,
961 .probe = stm32f7_i2c_probe,
962 .remove = stm32f7_i2c_remove,
965 module_platform_driver(stm32f7_i2c_driver);
967 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
968 MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver");
969 MODULE_LICENSE("GPL v2");