drivers/i2c/busses/i2c-stm32f7.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for STMicroelectronics STM32F7 I2C controller
   4  *
   5  * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc
   6  * reference manual.
   7  * Please see below a link to the documentation:
   8  * http://www.st.com/resource/en/reference_manual/dm00124865.pdf
   9  *
  10  * Copyright (C) M'boumba Cedric Madianga 2017
  11  * Copyright (C) STMicroelectronics 2017
  12  * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
  13  *
  14  * This driver is based on i2c-stm32f4.c
  15  *
  16  */
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/err.h>
  20 #include <linux/i2c.h>
  21 #include <linux/i2c-smbus.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/io.h>
  24 #include <linux/iopoll.h>
  25 #include <linux/mfd/syscon.h>
  26 #include <linux/module.h>
  27 #include <linux/of.h>
  28 #include <linux/of_address.h>
  29 #include <linux/of_platform.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/pinctrl/consumer.h>
  32 #include <linux/pm_runtime.h>
  33 #include <linux/pm_wakeirq.h>
  34 #include <linux/regmap.h>
  35 #include <linux/reset.h>
  36 #include <linux/slab.h>
  37
  38 #include "i2c-stm32.h"
  39
  40 /* STM32F7 I2C registers */
  41 #define STM32F7_I2C_CR1                         0x00
  42 #define STM32F7_I2C_CR2                         0x04
  43 #define STM32F7_I2C_OAR1                        0x08
  44 #define STM32F7_I2C_OAR2                        0x0C
  45 #define STM32F7_I2C_PECR                        0x20
  46 #define STM32F7_I2C_TIMINGR                     0x10
  47 #define STM32F7_I2C_ISR                         0x18
  48 #define STM32F7_I2C_ICR                         0x1C
  49 #define STM32F7_I2C_RXDR                        0x24
  50 #define STM32F7_I2C_TXDR                        0x28
  51
  52 /* STM32F7 I2C control 1 */
  53 #define STM32F7_I2C_CR1_PECEN                   BIT(23)
  54 #define STM32F7_I2C_CR1_SMBHEN                  BIT(20)
  55 #define STM32F7_I2C_CR1_WUPEN                   BIT(18)
  56 #define STM32F7_I2C_CR1_SBC                     BIT(16)
  57 #define STM32F7_I2C_CR1_RXDMAEN                 BIT(15)
  58 #define STM32F7_I2C_CR1_TXDMAEN                 BIT(14)
  59 #define STM32F7_I2C_CR1_ANFOFF                  BIT(12)
  60 #define STM32F7_I2C_CR1_ERRIE                   BIT(7)
  61 #define STM32F7_I2C_CR1_TCIE                    BIT(6)
  62 #define STM32F7_I2C_CR1_STOPIE                  BIT(5)
  63 #define STM32F7_I2C_CR1_NACKIE                  BIT(4)
  64 #define STM32F7_I2C_CR1_ADDRIE                  BIT(3)
  65 #define STM32F7_I2C_CR1_RXIE                    BIT(2)
  66 #define STM32F7_I2C_CR1_TXIE                    BIT(1)
  67 #define STM32F7_I2C_CR1_PE                      BIT(0)
  68 #define STM32F7_I2C_ALL_IRQ_MASK                (STM32F7_I2C_CR1_ERRIE \
  69                                                 | STM32F7_I2C_CR1_TCIE \
  70                                                 | STM32F7_I2C_CR1_STOPIE \
  71                                                 | STM32F7_I2C_CR1_NACKIE \
  72                                                 | STM32F7_I2C_CR1_RXIE \
  73                                                 | STM32F7_I2C_CR1_TXIE)
  74 #define STM32F7_I2C_XFER_IRQ_MASK               (STM32F7_I2C_CR1_TCIE \
  75                                                 | STM32F7_I2C_CR1_STOPIE \
  76                                                 | STM32F7_I2C_CR1_NACKIE \
  77                                                 | STM32F7_I2C_CR1_RXIE \
  78                                                 | STM32F7_I2C_CR1_TXIE)
  79
  80 /* STM32F7 I2C control 2 */
  81 #define STM32F7_I2C_CR2_PECBYTE                 BIT(26)
  82 #define STM32F7_I2C_CR2_RELOAD                  BIT(24)
  83 #define STM32F7_I2C_CR2_NBYTES_MASK             GENMASK(23, 16)
  84 #define STM32F7_I2C_CR2_NBYTES(n)               (((n) & 0xff) << 16)
  85 #define STM32F7_I2C_CR2_NACK                    BIT(15)
  86 #define STM32F7_I2C_CR2_STOP                    BIT(14)
  87 #define STM32F7_I2C_CR2_START                   BIT(13)
  88 #define STM32F7_I2C_CR2_HEAD10R                 BIT(12)
  89 #define STM32F7_I2C_CR2_ADD10                   BIT(11)
  90 #define STM32F7_I2C_CR2_RD_WRN                  BIT(10)
  91 #define STM32F7_I2C_CR2_SADD10_MASK             GENMASK(9, 0)
  92 #define STM32F7_I2C_CR2_SADD10(n)               (((n) & \
  93                                                 STM32F7_I2C_CR2_SADD10_MASK))
  94 #define STM32F7_I2C_CR2_SADD7_MASK              GENMASK(7, 1)
  95 #define STM32F7_I2C_CR2_SADD7(n)                (((n) & 0x7f) << 1)
  96
  97 /* STM32F7 I2C Own Address 1 */
  98 #define STM32F7_I2C_OAR1_OA1EN                  BIT(15)
  99 #define STM32F7_I2C_OAR1_OA1MODE                BIT(10)
 100 #define STM32F7_I2C_OAR1_OA1_10_MASK            GENMASK(9, 0)
 101 #define STM32F7_I2C_OAR1_OA1_10(n)              (((n) & \
 102                                                 STM32F7_I2C_OAR1_OA1_10_MASK))
 103 #define STM32F7_I2C_OAR1_OA1_7_MASK             GENMASK(7, 1)
 104 #define STM32F7_I2C_OAR1_OA1_7(n)               (((n) & 0x7f) << 1)
 105 #define STM32F7_I2C_OAR1_MASK                   (STM32F7_I2C_OAR1_OA1_7_MASK \
 106                                                 | STM32F7_I2C_OAR1_OA1_10_MASK \
 107                                                 | STM32F7_I2C_OAR1_OA1EN \
 108                                                 | STM32F7_I2C_OAR1_OA1MODE)
 109
 110 /* STM32F7 I2C Own Address 2 */
 111 #define STM32F7_I2C_OAR2_OA2EN                  BIT(15)
 112 #define STM32F7_I2C_OAR2_OA2MSK_MASK            GENMASK(10, 8)
 113 #define STM32F7_I2C_OAR2_OA2MSK(n)              (((n) & 0x7) << 8)
 114 #define STM32F7_I2C_OAR2_OA2_7_MASK             GENMASK(7, 1)
 115 #define STM32F7_I2C_OAR2_OA2_7(n)               (((n) & 0x7f) << 1)
 116 #define STM32F7_I2C_OAR2_MASK                   (STM32F7_I2C_OAR2_OA2MSK_MASK \
 117                                                 | STM32F7_I2C_OAR2_OA2_7_MASK \
 118                                                 | STM32F7_I2C_OAR2_OA2EN)
 119
 120 /* STM32F7 I2C Interrupt Status */
 121 #define STM32F7_I2C_ISR_ADDCODE_MASK            GENMASK(23, 17)
 122 #define STM32F7_I2C_ISR_ADDCODE_GET(n) \
 123                                 (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17)
 124 #define STM32F7_I2C_ISR_DIR                     BIT(16)
 125 #define STM32F7_I2C_ISR_BUSY                    BIT(15)
 126 #define STM32F7_I2C_ISR_PECERR                  BIT(11)
 127 #define STM32F7_I2C_ISR_ARLO                    BIT(9)
 128 #define STM32F7_I2C_ISR_BERR                    BIT(8)
 129 #define STM32F7_I2C_ISR_TCR                     BIT(7)
 130 #define STM32F7_I2C_ISR_TC                      BIT(6)
 131 #define STM32F7_I2C_ISR_STOPF                   BIT(5)
 132 #define STM32F7_I2C_ISR_NACKF                   BIT(4)
 133 #define STM32F7_I2C_ISR_ADDR                    BIT(3)
 134 #define STM32F7_I2C_ISR_RXNE                    BIT(2)
 135 #define STM32F7_I2C_ISR_TXIS                    BIT(1)
 136 #define STM32F7_I2C_ISR_TXE                     BIT(0)
 137
 138 /* STM32F7 I2C Interrupt Clear */
 139 #define STM32F7_I2C_ICR_PECCF                   BIT(11)
 140 #define STM32F7_I2C_ICR_ARLOCF                  BIT(9)
 141 #define STM32F7_I2C_ICR_BERRCF                  BIT(8)
 142 #define STM32F7_I2C_ICR_STOPCF                  BIT(5)
 143 #define STM32F7_I2C_ICR_NACKCF                  BIT(4)
 144 #define STM32F7_I2C_ICR_ADDRCF                  BIT(3)
 145
 146 /* STM32F7 I2C Timing */
 147 #define STM32F7_I2C_TIMINGR_PRESC(n)            (((n) & 0xf) << 28)
 148 #define STM32F7_I2C_TIMINGR_SCLDEL(n)           (((n) & 0xf) << 20)
 149 #define STM32F7_I2C_TIMINGR_SDADEL(n)           (((n) & 0xf) << 16)
 150 #define STM32F7_I2C_TIMINGR_SCLH(n)             (((n) & 0xff) << 8)
 151 #define STM32F7_I2C_TIMINGR_SCLL(n)             ((n) & 0xff)
 152
 153 #define STM32F7_I2C_MAX_LEN                     0xff
 154 #define STM32F7_I2C_DMA_LEN_MIN                 0x16
 155 enum {
 156         STM32F7_SLAVE_HOSTNOTIFY,
 157         STM32F7_SLAVE_7_10_BITS_ADDR,
 158         STM32F7_SLAVE_7_BITS_ADDR,
 159         STM32F7_I2C_MAX_SLAVE
 160 };
 161
 162 #define STM32F7_I2C_DNF_DEFAULT                 0
 163 #define STM32F7_I2C_DNF_MAX                     16
 164
 165 #define STM32F7_I2C_ANALOG_FILTER_ENABLE        1
 166 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN     50      /* ns */
 167 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX     260     /* ns */
 168
 169 #define STM32F7_I2C_RISE_TIME_DEFAULT           25      /* ns */
 170 #define STM32F7_I2C_FALL_TIME_DEFAULT           10      /* ns */
 171
 172 #define STM32F7_PRESC_MAX                       BIT(4)
 173 #define STM32F7_SCLDEL_MAX                      BIT(4)
 174 #define STM32F7_SDADEL_MAX                      BIT(4)
 175 #define STM32F7_SCLH_MAX                        BIT(8)
 176 #define STM32F7_SCLL_MAX                        BIT(8)
 177
 178 #define STM32F7_AUTOSUSPEND_DELAY               (HZ / 100)
 179
 180 /**
 181  * struct stm32f7_i2c_regs - i2c f7 registers backup
 182  * @cr1: Control register 1
 183  * @cr2: Control register 2
 184  * @oar1: Own address 1 register
 185  * @oar2: Own address 2 register
 186  * @tmgr: Timing register
 187  */
 188 struct stm32f7_i2c_regs {
 189         u32 cr1;
 190         u32 cr2;
 191         u32 oar1;
 192         u32 oar2;
 193         u32 tmgr;
 194 };
 195
 196 /**
 197  * struct stm32f7_i2c_spec - private i2c specification timing
 198  * @rate: I2C bus speed (Hz)
 199  * @fall_max: Max fall time of both SDA and SCL signals (ns)
 200  * @rise_max: Max rise time of both SDA and SCL signals (ns)
 201  * @hddat_min: Min data hold time (ns)
 202  * @vddat_max: Max data valid time (ns)
 203  * @sudat_min: Min data setup time (ns)
 204  * @l_min: Min low period of the SCL clock (ns)
 205  * @h_min: Min high period of the SCL clock (ns)
 206  */
 207 struct stm32f7_i2c_spec {
 208         u32 rate;
 209         u32 fall_max;
 210         u32 rise_max;
 211         u32 hddat_min;
 212         u32 vddat_max;
 213         u32 sudat_min;
 214         u32 l_min;
 215         u32 h_min;
 216 };
 217
 218 /**
 219  * struct stm32f7_i2c_setup - private I2C timing setup parameters
 220  * @speed_freq: I2C speed frequency  (Hz)
 221  * @clock_src: I2C clock source frequency (Hz)
 222  * @rise_time: Rise time (ns)
 223  * @fall_time: Fall time (ns)
 224  * @dnf: Digital filter coefficient (0-16)
 225  * @analog_filter: Analog filter delay (On/Off)
 226  * @fmp_clr_offset: Fast Mode Plus clear register offset from set register
 227  */
 228 struct stm32f7_i2c_setup {
 229         u32 speed_freq;
 230         u32 clock_src;
 231         u32 rise_time;
 232         u32 fall_time;
 233         u8 dnf;
 234         bool analog_filter;
 235         u32 fmp_clr_offset;
 236 };
 237
 238 /**
 239  * struct stm32f7_i2c_timings - private I2C output parameters
 240  * @node: List entry
 241  * @presc: Prescaler value
 242  * @scldel: Data setup time
 243  * @sdadel: Data hold time
 244  * @sclh: SCL high period (master mode)
 245  * @scll: SCL low period (master mode)
 246  */
 247 struct stm32f7_i2c_timings {
 248         struct list_head node;
 249         u8 presc;
 250         u8 scldel;
 251         u8 sdadel;
 252         u8 sclh;
 253         u8 scll;
 254 };
 255
 256 /**
 257  * struct stm32f7_i2c_msg - client specific data
 258  * @addr: 8-bit or 10-bit slave addr, including r/w bit
 259  * @count: number of bytes to be transferred
 260  * @buf: data buffer
 261  * @result: result of the transfer
 262  * @stop: last I2C msg to be sent, i.e. STOP to be generated
 263  * @smbus: boolean to know if the I2C IP is used in SMBus mode
 264  * @size: type of SMBus protocol
 265  * @read_write: direction of SMBus protocol
 266  * SMBus block read and SMBus block write - block read process call protocols
 267  * @smbus_buf: buffer to be used for SMBus protocol transfer. It will
 268  * contain a maximum of 32 bytes of data + byte command + byte count + PEC
 269  * This buffer has to be 32-bit aligned to be compliant with memory address
 270  * register in DMA mode.
 271  */
 272 struct stm32f7_i2c_msg {
 273         u16 addr;
 274         u32 count;
 275         u8 *buf;
 276         int result;
 277         bool stop;
 278         bool smbus;
 279         int size;
 280         char read_write;
 281         u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4);
 282 };
 283
 284 /**
 285  * struct stm32f7_i2c_dev - private data of the controller
 286  * @adap: I2C adapter for this controller
 287  * @dev: device for this controller
 288  * @base: virtual memory area
 289  * @complete: completion of I2C message
 290  * @clk: hw i2c clock
 291  * @bus_rate: I2C clock frequency of the controller
 292  * @msg: Pointer to data to be written
 293  * @msg_num: number of I2C messages to be executed
 294  * @msg_id: message identifiant
 295  * @f7_msg: customized i2c msg for driver usage
 296  * @setup: I2C timing input setup
 297  * @timing: I2C computed timings
 298  * @slave: list of slave devices registered on the I2C bus
 299  * @slave_running: slave device currently used
 300  * @backup_regs: backup of i2c controller registers (for suspend/resume)
 301  * @slave_dir: transfer direction for the current slave device
 302  * @master_mode: boolean to know in which mode the I2C is running (master or
 303  * slave)
 304  * @dma: dma data
 305  * @use_dma: boolean to know if dma is used in the current transfer
 306  * @regmap: holds SYSCFG phandle for Fast Mode Plus bits
 307  * @fmp_sreg: register address for setting Fast Mode Plus bits
 308  * @fmp_creg: register address for clearing Fast Mode Plus bits
 309  * @fmp_mask: mask for Fast Mode Plus bits in set register
 310  * @wakeup_src: boolean to know if the device is a wakeup source
 311  * @smbus_mode: states that the controller is configured in SMBus mode
 312  * @host_notify_client: SMBus host-notify client
 313  */
 314 struct stm32f7_i2c_dev {
 315         struct i2c_adapter adap;
 316         struct device *dev;
 317         void __iomem *base;
 318         struct completion complete;
 319         struct clk *clk;
 320         unsigned int bus_rate;
 321         struct i2c_msg *msg;
 322         unsigned int msg_num;
 323         unsigned int msg_id;
 324         struct stm32f7_i2c_msg f7_msg;
 325         struct stm32f7_i2c_setup setup;
 326         struct stm32f7_i2c_timings timing;
 327         struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE];
 328         struct i2c_client *slave_running;
 329         struct stm32f7_i2c_regs backup_regs;
 330         u32 slave_dir;
 331         bool master_mode;
 332         struct stm32_i2c_dma *dma;
 333         bool use_dma;
 334         struct regmap *regmap;
 335         u32 fmp_sreg;
 336         u32 fmp_creg;
 337         u32 fmp_mask;
 338         bool wakeup_src;
 339         bool smbus_mode;
 340         struct i2c_client *host_notify_client;
 341 };
 342
 343 /*
 344  * All these values are coming from I2C Specification, Version 6.0, 4th of
 345  * April 2014.
 346  *
 347  * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast,
 348  * and Fast-mode Plus I2C-bus devices
 349  */
 350 static struct stm32f7_i2c_spec stm32f7_i2c_specs[] = {
 351         {
 352                 .rate = I2C_MAX_STANDARD_MODE_FREQ,
 353                 .fall_max = 300,
 354                 .rise_max = 1000,
 355                 .hddat_min = 0,
 356                 .vddat_max = 3450,
 357                 .sudat_min = 250,
 358                 .l_min = 4700,
 359                 .h_min = 4000,
 360         },
 361         {
 362                 .rate = I2C_MAX_FAST_MODE_FREQ,
 363                 .fall_max = 300,
 364                 .rise_max = 300,
 365                 .hddat_min = 0,
 366                 .vddat_max = 900,
 367                 .sudat_min = 100,
 368                 .l_min = 1300,
 369                 .h_min = 600,
 370         },
 371         {
 372                 .rate = I2C_MAX_FAST_MODE_PLUS_FREQ,
 373                 .fall_max = 100,
 374                 .rise_max = 120,
 375                 .hddat_min = 0,
 376                 .vddat_max = 450,
 377                 .sudat_min = 50,
 378                 .l_min = 500,
 379                 .h_min = 260,
 380         },
 381 };
 382
 383 static const struct stm32f7_i2c_setup stm32f7_setup = {
 384         .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
 385         .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
 386         .dnf = STM32F7_I2C_DNF_DEFAULT,
 387         .analog_filter = STM32F7_I2C_ANALOG_FILTER_ENABLE,
 388 };
 389
 390 static const struct stm32f7_i2c_setup stm32mp15_setup = {
 391         .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
 392         .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
 393         .dnf = STM32F7_I2C_DNF_DEFAULT,
 394         .analog_filter = STM32F7_I2C_ANALOG_FILTER_ENABLE,
 395         .fmp_clr_offset = 0x40,
 396 };
 397
 398 static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask)
 399 {
 400         writel_relaxed(readl_relaxed(reg) | mask, reg);
 401 }
 402
 403 static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask)
 404 {
 405         writel_relaxed(readl_relaxed(reg) & ~mask, reg);
 406 }
 407
 408 static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)
 409 {
 410         stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
 411 }
 412
 413 static struct stm32f7_i2c_spec *stm32f7_get_specs(u32 rate)
 414 {
 415         int i;
 416
 417         for (i = 0; i < ARRAY_SIZE(stm32f7_i2c_specs); i++)
 418                 if (rate <= stm32f7_i2c_specs[i].rate)
 419                         return &stm32f7_i2c_specs[i];
 420
 421         return ERR_PTR(-EINVAL);
 422 }
 423
 424 #define RATE_MIN(rate)  ((rate) * 8 / 10)
 425 static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev,
 426                                       struct stm32f7_i2c_setup *setup,
 427                                       struct stm32f7_i2c_timings *output)
 428 {
 429         struct stm32f7_i2c_spec *specs;
 430         u32 p_prev = STM32F7_PRESC_MAX;
 431         u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
 432                                        setup->clock_src);
 433         u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
 434                                        setup->speed_freq);
 435         u32 clk_error_prev = i2cbus;
 436         u32 tsync;
 437         u32 af_delay_min, af_delay_max;
 438         u32 dnf_delay;
 439         u32 clk_min, clk_max;
 440         int sdadel_min, sdadel_max;
 441         int scldel_min;
 442         struct stm32f7_i2c_timings *v, *_v, *s;
 443         struct list_head solutions;
 444         u16 p, l, a, h;
 445         int ret = 0;
 446
 447         specs = stm32f7_get_specs(setup->speed_freq);
 448         if (specs == ERR_PTR(-EINVAL)) {
 449                 dev_err(i2c_dev->dev, "speed out of bound {%d}\n",
 450                         setup->speed_freq);
 451                 return -EINVAL;
 452         }
 453
 454         if ((setup->rise_time > specs->rise_max) ||
 455             (setup->fall_time > specs->fall_max)) {
 456                 dev_err(i2c_dev->dev,
 457                         "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
 458                         setup->rise_time, specs->rise_max,
 459                         setup->fall_time, specs->fall_max);
 460                 return -EINVAL;
 461         }
 462
 463         if (setup->dnf > STM32F7_I2C_DNF_MAX) {
 464                 dev_err(i2c_dev->dev,
 465                         "DNF out of bound %d/%d\n",
 466                         setup->dnf, STM32F7_I2C_DNF_MAX);
 467                 return -EINVAL;
 468         }
 469
 470         /*  Analog and Digital Filters */
 471         af_delay_min =
 472                 (setup->analog_filter ?
 473                  STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0);
 474         af_delay_max =
 475                 (setup->analog_filter ?
 476                  STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0);
 477         dnf_delay = setup->dnf * i2cclk;
 478
 479         sdadel_min = specs->hddat_min + setup->fall_time -
 480                 af_delay_min - (setup->dnf + 3) * i2cclk;
 481
 482         sdadel_max = specs->vddat_max - setup->rise_time -
 483                 af_delay_max - (setup->dnf + 4) * i2cclk;
 484
 485         scldel_min = setup->rise_time + specs->sudat_min;
 486
 487         if (sdadel_min < 0)
 488                 sdadel_min = 0;
 489         if (sdadel_max < 0)
 490                 sdadel_max = 0;
 491
 492         dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n",
 493                 sdadel_min, sdadel_max, scldel_min);
 494
 495         INIT_LIST_HEAD(&solutions);
 496         /* Compute possible values for PRESC, SCLDEL and SDADEL */
 497         for (p = 0; p < STM32F7_PRESC_MAX; p++) {
 498                 for (l = 0; l < STM32F7_SCLDEL_MAX; l++) {
 499                         u32 scldel = (l + 1) * (p + 1) * i2cclk;
 500
 501                         if (scldel < scldel_min)
 502                                 continue;
 503
 504                         for (a = 0; a < STM32F7_SDADEL_MAX; a++) {
 505                                 u32 sdadel = (a * (p + 1) + 1) * i2cclk;
 506
 507                                 if (((sdadel >= sdadel_min) &&
 508                                      (sdadel <= sdadel_max)) &&
 509                                     (p != p_prev)) {
 510                                         v = kmalloc(sizeof(*v), GFP_KERNEL);
 511                                         if (!v) {
 512                                                 ret = -ENOMEM;
 513                                                 goto exit;
 514                                         }
 515
 516                                         v->presc = p;
 517                                         v->scldel = l;
 518                                         v->sdadel = a;
 519                                         p_prev = p;
 520
 521                                         list_add_tail(&v->node,
 522                                                       &solutions);
 523                                         break;
 524                                 }
 525                         }
 526
 527                         if (p_prev == p)
 528                                 break;
 529                 }
 530         }
 531
 532         if (list_empty(&solutions)) {
 533                 dev_err(i2c_dev->dev, "no Prescaler solution\n");
 534                 ret = -EPERM;
 535                 goto exit;
 536         }
 537
 538         tsync = af_delay_min + dnf_delay + (2 * i2cclk);
 539         s = NULL;
 540         clk_max = NSEC_PER_SEC / RATE_MIN(setup->speed_freq);
 541         clk_min = NSEC_PER_SEC / setup->speed_freq;
 542
 543         /*
 544          * Among Prescaler possibilities discovered above figures out SCL Low
 545          * and High Period. Provided:
 546          * - SCL Low Period has to be higher than SCL Clock Low Period
 547          *   defined by I2C Specification. I2C Clock has to be lower than
 548          *   (SCL Low Period - Analog/Digital filters) / 4.
 549          * - SCL High Period has to be lower than SCL Clock High Period
 550          *   defined by I2C Specification
 551          * - I2C Clock has to be lower than SCL High Period
 552          */
 553         list_for_each_entry(v, &solutions, node) {
 554                 u32 prescaler = (v->presc + 1) * i2cclk;
 555
 556                 for (l = 0; l < STM32F7_SCLL_MAX; l++) {
 557                         u32 tscl_l = (l + 1) * prescaler + tsync;
 558
 559                         if ((tscl_l < specs->l_min) ||
 560                             (i2cclk >=
 561                              ((tscl_l - af_delay_min - dnf_delay) / 4))) {
 562                                 continue;
 563                         }
 564
 565                         for (h = 0; h < STM32F7_SCLH_MAX; h++) {
 566                                 u32 tscl_h = (h + 1) * prescaler + tsync;
 567                                 u32 tscl = tscl_l + tscl_h +
 568                                         setup->rise_time + setup->fall_time;
 569
 570                                 if ((tscl >= clk_min) && (tscl <= clk_max) &&
 571                                     (tscl_h >= specs->h_min) &&
 572                                     (i2cclk < tscl_h)) {
 573                                         int clk_error = tscl - i2cbus;
 574
 575                                         if (clk_error < 0)
 576                                                 clk_error = -clk_error;
 577
 578                                         if (clk_error < clk_error_prev) {
 579                                                 clk_error_prev = clk_error;
 580                                                 v->scll = l;
 581                                                 v->sclh = h;
 582                                                 s = v;
 583                                         }
 584                                 }
 585                         }
 586                 }
 587         }
 588
 589         if (!s) {
 590                 dev_err(i2c_dev->dev, "no solution at all\n");
 591                 ret = -EPERM;
 592                 goto exit;
 593         }
 594
 595         output->presc = s->presc;
 596         output->scldel = s->scldel;
 597         output->sdadel = s->sdadel;
 598         output->scll = s->scll;
 599         output->sclh = s->sclh;
 600
 601         dev_dbg(i2c_dev->dev,
 602                 "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
 603                 output->presc,
 604                 output->scldel, output->sdadel,
 605                 output->scll, output->sclh);
 606
 607 exit:
 608         /* Release list and memory */
 609         list_for_each_entry_safe(v, _v, &solutions, node) {
 610                 list_del(&v->node);
 611                 kfree(v);
 612         }
 613
 614         return ret;
 615 }
 616
 617 static u32 stm32f7_get_lower_rate(u32 rate)
 618 {
 619         int i = ARRAY_SIZE(stm32f7_i2c_specs);
 620
 621         while (--i)
 622                 if (stm32f7_i2c_specs[i].rate < rate)
 623                         break;
 624
 625         return stm32f7_i2c_specs[i].rate;
 626 }
 627
 628 static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev,
 629                                     struct stm32f7_i2c_setup *setup)
 630 {
 631         struct i2c_timings timings, *t = &timings;
 632         int ret = 0;
 633
 634         t->bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
 635         t->scl_rise_ns = i2c_dev->setup.rise_time;
 636         t->scl_fall_ns = i2c_dev->setup.fall_time;
 637
 638         i2c_parse_fw_timings(i2c_dev->dev, t, false);
 639
 640         if (t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) {
 641                 dev_err(i2c_dev->dev, "Invalid bus speed (%i>%i)\n",
 642                         t->bus_freq_hz, I2C_MAX_FAST_MODE_PLUS_FREQ);
 643                 return -EINVAL;
 644         }
 645
 646         setup->speed_freq = t->bus_freq_hz;
 647         i2c_dev->setup.rise_time = t->scl_rise_ns;
 648         i2c_dev->setup.fall_time = t->scl_fall_ns;
 649         setup->clock_src = clk_get_rate(i2c_dev->clk);
 650
 651         if (!setup->clock_src) {
 652                 dev_err(i2c_dev->dev, "clock rate is 0\n");
 653                 return -EINVAL;
 654         }
 655
 656         do {
 657                 ret = stm32f7_i2c_compute_timing(i2c_dev, setup,
 658                                                  &i2c_dev->timing);
 659                 if (ret) {
 660                         dev_err(i2c_dev->dev,
 661                                 "failed to compute I2C timings.\n");
 662                         if (setup->speed_freq <= I2C_MAX_STANDARD_MODE_FREQ)
 663                                 break;
 664                         setup->speed_freq =
 665                                 stm32f7_get_lower_rate(setup->speed_freq);
 666                         dev_warn(i2c_dev->dev,
 667                                  "downgrade I2C Speed Freq to (%i)\n",
 668                                  setup->speed_freq);
 669                 }
 670         } while (ret);
 671
 672         if (ret) {
 673                 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n");
 674                 return ret;
 675         }
 676
 677         dev_dbg(i2c_dev->dev, "I2C Speed(%i), Clk Source(%i)\n",
 678                 setup->speed_freq, setup->clock_src);
 679         dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n",
 680                 setup->rise_time, setup->fall_time);
 681         dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n",
 682                 (setup->analog_filter ? "On" : "Off"), setup->dnf);
 683
 684         i2c_dev->bus_rate = setup->speed_freq;
 685
 686         return 0;
 687 }
 688
 689 static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev)
 690 {
 691         void __iomem *base = i2c_dev->base;
 692         u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN;
 693
 694         stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
 695 }
 696
 697 static void stm32f7_i2c_dma_callback(void *arg)
 698 {
 699         struct stm32f7_i2c_dev *i2c_dev = (struct stm32f7_i2c_dev *)arg;
 700         struct stm32_i2c_dma *dma = i2c_dev->dma;
 701         struct device *dev = dma->chan_using->device->dev;
 702
 703         stm32f7_i2c_disable_dma_req(i2c_dev);
 704         dma_unmap_single(dev, dma->dma_buf, dma->dma_len, dma->dma_data_dir);
 705         complete(&dma->dma_complete);
 706 }
 707
 708 static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev)
 709 {
 710         struct stm32f7_i2c_timings *t = &i2c_dev->timing;
 711         u32 timing = 0;
 712
 713         /* Timing settings */
 714         timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc);
 715         timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel);
 716         timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel);
 717         timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh);
 718         timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll);
 719         writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR);
 720
 721         /* Enable I2C */
 722         if (i2c_dev->setup.analog_filter)
 723                 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
 724                                      STM32F7_I2C_CR1_ANFOFF);
 725         else
 726                 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
 727                                      STM32F7_I2C_CR1_ANFOFF);
 728         stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
 729                              STM32F7_I2C_CR1_PE);
 730 }
 731
 732 static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev)
 733 {
 734         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 735         void __iomem *base = i2c_dev->base;
 736
 737         if (f7_msg->count) {
 738                 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR);
 739                 f7_msg->count--;
 740         }
 741 }
 742
 743 static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev)
 744 {
 745         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 746         void __iomem *base = i2c_dev->base;
 747
 748         if (f7_msg->count) {
 749                 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR);
 750                 f7_msg->count--;
 751         } else {
 752                 /* Flush RX buffer has no data is expected */
 753                 readb_relaxed(base + STM32F7_I2C_RXDR);
 754         }
 755 }
 756
 757 static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev)
 758 {
 759         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 760         u32 cr2;
 761
 762         if (i2c_dev->use_dma)
 763                 f7_msg->count -= STM32F7_I2C_MAX_LEN;
 764
 765         cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
 766
 767         cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK;
 768         if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
 769                 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
 770         } else {
 771                 cr2 &= ~STM32F7_I2C_CR2_RELOAD;
 772                 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
 773         }
 774
 775         writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
 776 }
 777
 778 static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev)
 779 {
 780         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 781         u32 cr2;
 782         u8 *val;
 783
 784         /*
 785          * For I2C_SMBUS_BLOCK_DATA && I2C_SMBUS_BLOCK_PROC_CALL, the first
 786          * data received inform us how many data will follow.
 787          */
 788         stm32f7_i2c_read_rx_data(i2c_dev);
 789
 790         /*
 791          * Update NBYTES with the value read to continue the transfer
 792          */
 793         val = f7_msg->buf - sizeof(u8);
 794         f7_msg->count = *val;
 795         cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
 796         cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
 797         cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
 798         writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
 799 }
 800
 801 static int stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap)
 802 {
 803         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
 804
 805         dev_info(i2c_dev->dev, "Trying to recover bus\n");
 806
 807         stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
 808                              STM32F7_I2C_CR1_PE);
 809
 810         stm32f7_i2c_hw_config(i2c_dev);
 811
 812         return 0;
 813 }
 814
 815 static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev)
 816 {
 817         u32 status;
 818         int ret;
 819
 820         ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR,
 821                                          status,
 822                                          !(status & STM32F7_I2C_ISR_BUSY),
 823                                          10, 1000);
 824         if (!ret)
 825                 return 0;
 826
 827         dev_info(i2c_dev->dev, "bus busy\n");
 828
 829         ret = stm32f7_i2c_release_bus(&i2c_dev->adap);
 830         if (ret) {
 831                 dev_err(i2c_dev->dev, "Failed to recover the bus (%d)\n", ret);
 832                 return ret;
 833         }
 834
 835         return -EBUSY;
 836 }
 837
 838 static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
 839                                  struct i2c_msg *msg)
 840 {
 841         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 842         void __iomem *base = i2c_dev->base;
 843         u32 cr1, cr2;
 844         int ret;
 845
 846         f7_msg->addr = msg->addr;
 847         f7_msg->buf = msg->buf;
 848         f7_msg->count = msg->len;
 849         f7_msg->result = 0;
 850         f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1);
 851
 852         reinit_completion(&i2c_dev->complete);
 853
 854         cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
 855         cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
 856
 857         /* Set transfer direction */
 858         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 859         if (msg->flags & I2C_M_RD)
 860                 cr2 |= STM32F7_I2C_CR2_RD_WRN;
 861
 862         /* Set slave address */
 863         cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10);
 864         if (msg->flags & I2C_M_TEN) {
 865                 cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK;
 866                 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr);
 867                 cr2 |= STM32F7_I2C_CR2_ADD10;
 868         } else {
 869                 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK;
 870                 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
 871         }
 872
 873         /* Set nb bytes to transfer and reload if needed */
 874         cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
 875         if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
 876                 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
 877                 cr2 |= STM32F7_I2C_CR2_RELOAD;
 878         } else {
 879                 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
 880         }
 881
 882         /* Enable NACK, STOP, error and transfer complete interrupts */
 883         cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
 884                 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
 885
 886         /* Clear DMA req and TX/RX interrupt */
 887         cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
 888                         STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
 889
 890         /* Configure DMA or enable RX/TX interrupt */
 891         i2c_dev->use_dma = false;
 892         if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
 893                 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
 894                                               msg->flags & I2C_M_RD,
 895                                               f7_msg->count, f7_msg->buf,
 896                                               stm32f7_i2c_dma_callback,
 897                                               i2c_dev);
 898                 if (!ret)
 899                         i2c_dev->use_dma = true;
 900                 else
 901                         dev_warn(i2c_dev->dev, "can't use DMA\n");
 902         }
 903
 904         if (!i2c_dev->use_dma) {
 905                 if (msg->flags & I2C_M_RD)
 906                         cr1 |= STM32F7_I2C_CR1_RXIE;
 907                 else
 908                         cr1 |= STM32F7_I2C_CR1_TXIE;
 909         } else {
 910                 if (msg->flags & I2C_M_RD)
 911                         cr1 |= STM32F7_I2C_CR1_RXDMAEN;
 912                 else
 913                         cr1 |= STM32F7_I2C_CR1_TXDMAEN;
 914         }
 915
 916         /* Configure Start/Repeated Start */
 917         cr2 |= STM32F7_I2C_CR2_START;
 918
 919         i2c_dev->master_mode = true;
 920
 921         /* Write configurations registers */
 922         writel_relaxed(cr1, base + STM32F7_I2C_CR1);
 923         writel_relaxed(cr2, base + STM32F7_I2C_CR2);
 924 }
 925
 926 static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
 927                                       unsigned short flags, u8 command,
 928                                       union i2c_smbus_data *data)
 929 {
 930         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 931         struct device *dev = i2c_dev->dev;
 932         void __iomem *base = i2c_dev->base;
 933         u32 cr1, cr2;
 934         int i, ret;
 935
 936         f7_msg->result = 0;
 937         reinit_completion(&i2c_dev->complete);
 938
 939         cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
 940         cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
 941
 942         /* Set transfer direction */
 943         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 944         if (f7_msg->read_write)
 945                 cr2 |= STM32F7_I2C_CR2_RD_WRN;
 946
 947         /* Set slave address */
 948         cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK);
 949         cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
 950
 951         f7_msg->smbus_buf[0] = command;
 952         switch (f7_msg->size) {
 953         case I2C_SMBUS_QUICK:
 954                 f7_msg->stop = true;
 955                 f7_msg->count = 0;
 956                 break;
 957         case I2C_SMBUS_BYTE:
 958                 f7_msg->stop = true;
 959                 f7_msg->count = 1;
 960                 break;
 961         case I2C_SMBUS_BYTE_DATA:
 962                 if (f7_msg->read_write) {
 963                         f7_msg->stop = false;
 964                         f7_msg->count = 1;
 965                         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 966                 } else {
 967                         f7_msg->stop = true;
 968                         f7_msg->count = 2;
 969                         f7_msg->smbus_buf[1] = data->byte;
 970                 }
 971                 break;
 972         case I2C_SMBUS_WORD_DATA:
 973                 if (f7_msg->read_write) {
 974                         f7_msg->stop = false;
 975                         f7_msg->count = 1;
 976                         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 977                 } else {
 978                         f7_msg->stop = true;
 979                         f7_msg->count = 3;
 980                         f7_msg->smbus_buf[1] = data->word & 0xff;
 981                         f7_msg->smbus_buf[2] = data->word >> 8;
 982                 }
 983                 break;
 984         case I2C_SMBUS_BLOCK_DATA:
 985                 if (f7_msg->read_write) {
 986                         f7_msg->stop = false;
 987                         f7_msg->count = 1;
 988                         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 989                 } else {
 990                         f7_msg->stop = true;
 991                         if (data->block[0] > I2C_SMBUS_BLOCK_MAX ||
 992                             !data->block[0]) {
 993                                 dev_err(dev, "Invalid block write size %d\n",
 994                                         data->block[0]);
 995                                 return -EINVAL;
 996                         }
 997                         f7_msg->count = data->block[0] + 2;
 998                         for (i = 1; i < f7_msg->count; i++)
 999                                 f7_msg->smbus_buf[i] = data->block[i - 1];
1000                 }
1001                 break;
1002         case I2C_SMBUS_PROC_CALL:
1003                 f7_msg->stop = false;
1004                 f7_msg->count = 3;
1005                 f7_msg->smbus_buf[1] = data->word & 0xff;
1006                 f7_msg->smbus_buf[2] = data->word >> 8;
1007                 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1008                 f7_msg->read_write = I2C_SMBUS_READ;
1009                 break;
1010         case I2C_SMBUS_BLOCK_PROC_CALL:
1011                 f7_msg->stop = false;
1012                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) {
1013                         dev_err(dev, "Invalid block write size %d\n",
1014                                 data->block[0]);
1015                         return -EINVAL;
1016                 }
1017                 f7_msg->count = data->block[0] + 2;
1018                 for (i = 1; i < f7_msg->count; i++)
1019                         f7_msg->smbus_buf[i] = data->block[i - 1];
1020                 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1021                 f7_msg->read_write = I2C_SMBUS_READ;
1022                 break;
1023         case I2C_SMBUS_I2C_BLOCK_DATA:
1024                 /* Rely on emulated i2c transfer (through master_xfer) */
1025                 return -EOPNOTSUPP;
1026         default:
1027                 dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size);
1028                 return -EOPNOTSUPP;
1029         }
1030
1031         f7_msg->buf = f7_msg->smbus_buf;
1032
1033         /* Configure PEC */
1034         if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) {
1035                 cr1 |= STM32F7_I2C_CR1_PECEN;
1036                 cr2 |= STM32F7_I2C_CR2_PECBYTE;
1037                 if (!f7_msg->read_write)
1038                         f7_msg->count++;
1039         } else {
1040                 cr1 &= ~STM32F7_I2C_CR1_PECEN;
1041                 cr2 &= ~STM32F7_I2C_CR2_PECBYTE;
1042         }
1043
1044         /* Set number of bytes to be transferred */
1045         cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
1046         cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1047
1048         /* Enable NACK, STOP, error and transfer complete interrupts */
1049         cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
1050                 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
1051
1052         /* Clear DMA req and TX/RX interrupt */
1053         cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1054                         STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1055
1056         /* Configure DMA or enable RX/TX interrupt */
1057         i2c_dev->use_dma = false;
1058         if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
1059                 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1060                                               cr2 & STM32F7_I2C_CR2_RD_WRN,
1061                                               f7_msg->count, f7_msg->buf,
1062                                               stm32f7_i2c_dma_callback,
1063                                               i2c_dev);
1064                 if (!ret)
1065                         i2c_dev->use_dma = true;
1066                 else
1067                         dev_warn(i2c_dev->dev, "can't use DMA\n");
1068         }
1069
1070         if (!i2c_dev->use_dma) {
1071                 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1072                         cr1 |= STM32F7_I2C_CR1_RXIE;
1073                 else
1074                         cr1 |= STM32F7_I2C_CR1_TXIE;
1075         } else {
1076                 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1077                         cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1078                 else
1079                         cr1 |= STM32F7_I2C_CR1_TXDMAEN;
1080         }
1081
1082         /* Set Start bit */
1083         cr2 |= STM32F7_I2C_CR2_START;
1084
1085         i2c_dev->master_mode = true;
1086
1087         /* Write configurations registers */
1088         writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1089         writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1090
1091         return 0;
1092 }
1093
1094 static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev)
1095 {
1096         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1097         void __iomem *base = i2c_dev->base;
1098         u32 cr1, cr2;
1099         int ret;
1100
1101         cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
1102         cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
1103
1104         /* Set transfer direction */
1105         cr2 |= STM32F7_I2C_CR2_RD_WRN;
1106
1107         switch (f7_msg->size) {
1108         case I2C_SMBUS_BYTE_DATA:
1109                 f7_msg->count = 1;
1110                 break;
1111         case I2C_SMBUS_WORD_DATA:
1112         case I2C_SMBUS_PROC_CALL:
1113                 f7_msg->count = 2;
1114                 break;
1115         case I2C_SMBUS_BLOCK_DATA:
1116         case I2C_SMBUS_BLOCK_PROC_CALL:
1117                 f7_msg->count = 1;
1118                 cr2 |= STM32F7_I2C_CR2_RELOAD;
1119                 break;
1120         }
1121
1122         f7_msg->buf = f7_msg->smbus_buf;
1123         f7_msg->stop = true;
1124
1125         /* Add one byte for PEC if needed */
1126         if (cr1 & STM32F7_I2C_CR1_PECEN)
1127                 f7_msg->count++;
1128
1129         /* Set number of bytes to be transferred */
1130         cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK);
1131         cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1132
1133         /*
1134          * Configure RX/TX interrupt:
1135          */
1136         cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE);
1137         cr1 |= STM32F7_I2C_CR1_RXIE;
1138
1139         /*
1140          * Configure DMA or enable RX/TX interrupt:
1141          * For I2C_SMBUS_BLOCK_DATA and I2C_SMBUS_BLOCK_PROC_CALL we don't use
1142          * dma as we don't know in advance how many data will be received
1143          */
1144         cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1145                  STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1146
1147         i2c_dev->use_dma = false;
1148         if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN &&
1149             f7_msg->size != I2C_SMBUS_BLOCK_DATA &&
1150             f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) {
1151                 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1152                                               cr2 & STM32F7_I2C_CR2_RD_WRN,
1153                                               f7_msg->count, f7_msg->buf,
1154                                               stm32f7_i2c_dma_callback,
1155                                               i2c_dev);
1156
1157                 if (!ret)
1158                         i2c_dev->use_dma = true;
1159                 else
1160                         dev_warn(i2c_dev->dev, "can't use DMA\n");
1161         }
1162
1163         if (!i2c_dev->use_dma)
1164                 cr1 |= STM32F7_I2C_CR1_RXIE;
1165         else
1166                 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1167
1168         /* Configure Repeated Start */
1169         cr2 |= STM32F7_I2C_CR2_START;
1170
1171         /* Write configurations registers */
1172         writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1173         writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1174 }
1175
1176 static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev)
1177 {
1178         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1179         u8 count, internal_pec, received_pec;
1180
1181         internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR);
1182
1183         switch (f7_msg->size) {
1184         case I2C_SMBUS_BYTE:
1185         case I2C_SMBUS_BYTE_DATA:
1186                 received_pec = f7_msg->smbus_buf[1];
1187                 break;
1188         case I2C_SMBUS_WORD_DATA:
1189         case I2C_SMBUS_PROC_CALL:
1190                 received_pec = f7_msg->smbus_buf[2];
1191                 break;
1192         case I2C_SMBUS_BLOCK_DATA:
1193         case I2C_SMBUS_BLOCK_PROC_CALL:
1194                 count = f7_msg->smbus_buf[0];
1195                 received_pec = f7_msg->smbus_buf[count];
1196                 break;
1197         default:
1198                 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n");
1199                 return -EINVAL;
1200         }
1201
1202         if (internal_pec != received_pec) {
1203                 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n",
1204                         internal_pec, received_pec);
1205                 return -EBADMSG;
1206         }
1207
1208         return 0;
1209 }
1210
1211 static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode)
1212 {
1213         u32 addr;
1214
1215         if (!slave)
1216                 return false;
1217
1218         if (slave->flags & I2C_CLIENT_TEN) {
1219                 /*
1220                  * For 10-bit addr, addcode = 11110XY with
1221                  * X = Bit 9 of slave address
1222                  * Y = Bit 8 of slave address
1223                  */
1224                 addr = slave->addr >> 8;
1225                 addr |= 0x78;
1226                 if (addr == addcode)
1227                         return true;
1228         } else {
1229                 addr = slave->addr & 0x7f;
1230                 if (addr == addcode)
1231                         return true;
1232         }
1233
1234         return false;
1235 }
1236
1237 static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev)
1238 {
1239         struct i2c_client *slave = i2c_dev->slave_running;
1240         void __iomem *base = i2c_dev->base;
1241         u32 mask;
1242         u8 value = 0;
1243
1244         if (i2c_dev->slave_dir) {
1245                 /* Notify i2c slave that new read transfer is starting */
1246                 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
1247
1248                 /*
1249                  * Disable slave TX config in case of I2C combined message
1250                  * (I2C Write followed by I2C Read)
1251                  */
1252                 mask = STM32F7_I2C_CR2_RELOAD;
1253                 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask);
1254                 mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1255                        STM32F7_I2C_CR1_TCIE;
1256                 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1257
1258                 /* Enable TX empty, STOP, NACK interrupts */
1259                 mask =  STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1260                         STM32F7_I2C_CR1_TXIE;
1261                 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1262
1263                 /* Write 1st data byte */
1264                 writel_relaxed(value, base + STM32F7_I2C_TXDR);
1265         } else {
1266                 /* Notify i2c slave that new write transfer is starting */
1267                 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
1268
1269                 /* Set reload mode to be able to ACK/NACK each received byte */
1270                 mask = STM32F7_I2C_CR2_RELOAD;
1271                 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1272
1273                 /*
1274                  * Set STOP, NACK, RX empty and transfer complete interrupts.*
1275                  * Set Slave Byte Control to be able to ACK/NACK each data
1276                  * byte received
1277                  */
1278                 mask =  STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1279                         STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1280                         STM32F7_I2C_CR1_TCIE;
1281                 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1282         }
1283 }
1284
1285 static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev)
1286 {
1287         void __iomem *base = i2c_dev->base;
1288         u32 isr, addcode, dir, mask;
1289         int i;
1290
1291         isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1292         addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr);
1293         dir = isr & STM32F7_I2C_ISR_DIR;
1294
1295         for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1296                 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) {
1297                         i2c_dev->slave_running = i2c_dev->slave[i];
1298                         i2c_dev->slave_dir = dir;
1299
1300                         /* Start I2C slave processing */
1301                         stm32f7_i2c_slave_start(i2c_dev);
1302
1303                         /* Clear ADDR flag */
1304                         mask = STM32F7_I2C_ICR_ADDRCF;
1305                         writel_relaxed(mask, base + STM32F7_I2C_ICR);
1306                         break;
1307                 }
1308         }
1309 }
1310
1311 static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1312                                     struct i2c_client *slave, int *id)
1313 {
1314         int i;
1315
1316         for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1317                 if (i2c_dev->slave[i] == slave) {
1318                         *id = i;
1319                         return 0;
1320                 }
1321         }
1322
1323         dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr);
1324
1325         return -ENODEV;
1326 }
1327
1328 static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1329                                          struct i2c_client *slave, int *id)
1330 {
1331         struct device *dev = i2c_dev->dev;
1332         int i;
1333
1334         /*
1335          * slave[STM32F7_SLAVE_HOSTNOTIFY] support only SMBus Host address (0x8)
1336          * slave[STM32F7_SLAVE_7_10_BITS_ADDR] supports 7-bit and 10-bit slave address
1337          * slave[STM32F7_SLAVE_7_BITS_ADDR] supports 7-bit slave address only
1338          */
1339         if (i2c_dev->smbus_mode && (slave->addr == 0x08)) {
1340                 if (i2c_dev->slave[STM32F7_SLAVE_HOSTNOTIFY])
1341                         goto fail;
1342                 *id = STM32F7_SLAVE_HOSTNOTIFY;
1343                 return 0;
1344         }
1345
1346         for (i = STM32F7_I2C_MAX_SLAVE - 1; i > STM32F7_SLAVE_HOSTNOTIFY; i--) {
1347                 if ((i == STM32F7_SLAVE_7_BITS_ADDR) &&
1348                     (slave->flags & I2C_CLIENT_TEN))
1349                         continue;
1350                 if (!i2c_dev->slave[i]) {
1351                         *id = i;
1352                         return 0;
1353                 }
1354         }
1355
1356 fail:
1357         dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr);
1358
1359         return -EINVAL;
1360 }
1361
1362 static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev)
1363 {
1364         int i;
1365
1366         for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1367                 if (i2c_dev->slave[i])
1368                         return true;
1369         }
1370
1371         return false;
1372 }
1373
1374 static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev)
1375 {
1376         int i, busy;
1377
1378         busy = 0;
1379         for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1380                 if (i2c_dev->slave[i])
1381                         busy++;
1382         }
1383
1384         return i == busy;
1385 }
1386
1387 static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev)
1388 {
1389         void __iomem *base = i2c_dev->base;
1390         u32 cr2, status, mask;
1391         u8 val;
1392         int ret;
1393
1394         status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1395
1396         /* Slave transmitter mode */
1397         if (status & STM32F7_I2C_ISR_TXIS) {
1398                 i2c_slave_event(i2c_dev->slave_running,
1399                                 I2C_SLAVE_READ_PROCESSED,
1400                                 &val);
1401
1402                 /* Write data byte */
1403                 writel_relaxed(val, base + STM32F7_I2C_TXDR);
1404         }
1405
1406         /* Transfer Complete Reload for Slave receiver mode */
1407         if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) {
1408                 /*
1409                  * Read data byte then set NBYTES to receive next byte or NACK
1410                  * the current received byte
1411                  */
1412                 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR);
1413                 ret = i2c_slave_event(i2c_dev->slave_running,
1414                                       I2C_SLAVE_WRITE_RECEIVED,
1415                                       &val);
1416                 if (!ret) {
1417                         cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
1418                         cr2 |= STM32F7_I2C_CR2_NBYTES(1);
1419                         writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
1420                 } else {
1421                         mask = STM32F7_I2C_CR2_NACK;
1422                         stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1423                 }
1424         }
1425
1426         /* NACK received */
1427         if (status & STM32F7_I2C_ISR_NACKF) {
1428                 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1429                 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1430         }
1431
1432         /* STOP received */
1433         if (status & STM32F7_I2C_ISR_STOPF) {
1434                 /* Disable interrupts */
1435                 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK);
1436
1437                 if (i2c_dev->slave_dir) {
1438                         /*
1439                          * Flush TX buffer in order to not used the byte in
1440                          * TXDR for the next transfer
1441                          */
1442                         mask = STM32F7_I2C_ISR_TXE;
1443                         stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask);
1444                 }
1445
1446                 /* Clear STOP flag */
1447                 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1448
1449                 /* Notify i2c slave that a STOP flag has been detected */
1450                 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val);
1451
1452                 i2c_dev->slave_running = NULL;
1453         }
1454
1455         /* Address match received */
1456         if (status & STM32F7_I2C_ISR_ADDR)
1457                 stm32f7_i2c_slave_addr(i2c_dev);
1458
1459         return IRQ_HANDLED;
1460 }
1461
1462 static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
1463 {
1464         struct stm32f7_i2c_dev *i2c_dev = data;
1465         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1466         void __iomem *base = i2c_dev->base;
1467         u32 status, mask;
1468         int ret = IRQ_HANDLED;
1469
1470         /* Check if the interrupt if for a slave device */
1471         if (!i2c_dev->master_mode) {
1472                 ret = stm32f7_i2c_slave_isr_event(i2c_dev);
1473                 return ret;
1474         }
1475
1476         status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1477
1478         /* Tx empty */
1479         if (status & STM32F7_I2C_ISR_TXIS)
1480                 stm32f7_i2c_write_tx_data(i2c_dev);
1481
1482         /* RX not empty */
1483         if (status & STM32F7_I2C_ISR_RXNE)
1484                 stm32f7_i2c_read_rx_data(i2c_dev);
1485
1486         /* NACK received */
1487         if (status & STM32F7_I2C_ISR_NACKF) {
1488                 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK (addr %x)\n",
1489                         __func__, f7_msg->addr);
1490                 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1491                 f7_msg->result = -ENXIO;
1492         }
1493
1494         /* STOP detection flag */
1495         if (status & STM32F7_I2C_ISR_STOPF) {
1496                 /* Disable interrupts */
1497                 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1498                         mask = STM32F7_I2C_XFER_IRQ_MASK;
1499                 else
1500                         mask = STM32F7_I2C_ALL_IRQ_MASK;
1501                 stm32f7_i2c_disable_irq(i2c_dev, mask);
1502
1503                 /* Clear STOP flag */
1504                 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1505
1506                 if (i2c_dev->use_dma) {
1507                         ret = IRQ_WAKE_THREAD;
1508                 } else {
1509                         i2c_dev->master_mode = false;
1510                         complete(&i2c_dev->complete);
1511                 }
1512         }
1513
1514         /* Transfer complete */
1515         if (status & STM32F7_I2C_ISR_TC) {
1516                 if (f7_msg->stop) {
1517                         mask = STM32F7_I2C_CR2_STOP;
1518                         stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1519                 } else if (i2c_dev->use_dma) {
1520                         ret = IRQ_WAKE_THREAD;
1521                 } else if (f7_msg->smbus) {
1522                         stm32f7_i2c_smbus_rep_start(i2c_dev);
1523                 } else {
1524                         i2c_dev->msg_id++;
1525                         i2c_dev->msg++;
1526                         stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1527                 }
1528         }
1529
1530         if (status & STM32F7_I2C_ISR_TCR) {
1531                 if (f7_msg->smbus)
1532                         stm32f7_i2c_smbus_reload(i2c_dev);
1533                 else
1534                         stm32f7_i2c_reload(i2c_dev);
1535         }
1536
1537         return ret;
1538 }
1539
1540 static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data)
1541 {
1542         struct stm32f7_i2c_dev *i2c_dev = data;
1543         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1544         struct stm32_i2c_dma *dma = i2c_dev->dma;
1545         u32 status;
1546         int ret;
1547
1548         /*
1549          * Wait for dma transfer completion before sending next message or
1550          * notity the end of xfer to the client
1551          */
1552         ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ);
1553         if (!ret) {
1554                 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__);
1555                 stm32f7_i2c_disable_dma_req(i2c_dev);
1556                 dmaengine_terminate_all(dma->chan_using);
1557                 f7_msg->result = -ETIMEDOUT;
1558         }
1559
1560         status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1561
1562         if (status & STM32F7_I2C_ISR_TC) {
1563                 if (f7_msg->smbus) {
1564                         stm32f7_i2c_smbus_rep_start(i2c_dev);
1565                 } else {
1566                         i2c_dev->msg_id++;
1567                         i2c_dev->msg++;
1568                         stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1569                 }
1570         } else {
1571                 i2c_dev->master_mode = false;
1572                 complete(&i2c_dev->complete);
1573         }
1574
1575         return IRQ_HANDLED;
1576 }
1577
1578 static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data)
1579 {
1580         struct stm32f7_i2c_dev *i2c_dev = data;
1581         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1582         void __iomem *base = i2c_dev->base;
1583         struct device *dev = i2c_dev->dev;
1584         struct stm32_i2c_dma *dma = i2c_dev->dma;
1585         u32 status;
1586
1587         status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1588
1589         /* Bus error */
1590         if (status & STM32F7_I2C_ISR_BERR) {
1591                 dev_err(dev, "<%s>: Bus error\n", __func__);
1592                 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR);
1593                 stm32f7_i2c_release_bus(&i2c_dev->adap);
1594                 f7_msg->result = -EIO;
1595         }
1596
1597         /* Arbitration loss */
1598         if (status & STM32F7_I2C_ISR_ARLO) {
1599                 dev_dbg(dev, "<%s>: Arbitration loss\n", __func__);
1600                 writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR);
1601                 f7_msg->result = -EAGAIN;
1602         }
1603
1604         if (status & STM32F7_I2C_ISR_PECERR) {
1605                 dev_err(dev, "<%s>: PEC error in reception\n", __func__);
1606                 writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR);
1607                 f7_msg->result = -EINVAL;
1608         }
1609
1610         if (!i2c_dev->slave_running) {
1611                 u32 mask;
1612                 /* Disable interrupts */
1613                 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1614                         mask = STM32F7_I2C_XFER_IRQ_MASK;
1615                 else
1616                         mask = STM32F7_I2C_ALL_IRQ_MASK;
1617                 stm32f7_i2c_disable_irq(i2c_dev, mask);
1618         }
1619
1620         /* Disable dma */
1621         if (i2c_dev->use_dma) {
1622                 stm32f7_i2c_disable_dma_req(i2c_dev);
1623                 dmaengine_terminate_all(dma->chan_using);
1624         }
1625
1626         i2c_dev->master_mode = false;
1627         complete(&i2c_dev->complete);
1628
1629         return IRQ_HANDLED;
1630 }
1631
1632 static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap,
1633                             struct i2c_msg msgs[], int num)
1634 {
1635         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
1636         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1637         struct stm32_i2c_dma *dma = i2c_dev->dma;
1638         unsigned long time_left;
1639         int ret;
1640
1641         i2c_dev->msg = msgs;
1642         i2c_dev->msg_num = num;
1643         i2c_dev->msg_id = 0;
1644         f7_msg->smbus = false;
1645
1646         ret = pm_runtime_get_sync(i2c_dev->dev);
1647         if (ret < 0)
1648                 return ret;
1649
1650         ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1651         if (ret)
1652                 goto pm_free;
1653
1654         stm32f7_i2c_xfer_msg(i2c_dev, msgs);
1655
1656         time_left = wait_for_completion_timeout(&i2c_dev->complete,
1657                                                 i2c_dev->adap.timeout);
1658         ret = f7_msg->result;
1659
1660         if (!time_left) {
1661                 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n",
1662                         i2c_dev->msg->addr);
1663                 if (i2c_dev->use_dma)
1664                         dmaengine_terminate_all(dma->chan_using);
1665                 ret = -ETIMEDOUT;
1666         }
1667
1668 pm_free:
1669         pm_runtime_mark_last_busy(i2c_dev->dev);
1670         pm_runtime_put_autosuspend(i2c_dev->dev);
1671
1672         return (ret < 0) ? ret : num;
1673 }
1674
1675 static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
1676                                   unsigned short flags, char read_write,
1677                                   u8 command, int size,
1678                                   union i2c_smbus_data *data)
1679 {
1680         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter);
1681         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1682         struct stm32_i2c_dma *dma = i2c_dev->dma;
1683         struct device *dev = i2c_dev->dev;
1684         unsigned long timeout;
1685         int i, ret;
1686
1687         f7_msg->addr = addr;
1688         f7_msg->size = size;
1689         f7_msg->read_write = read_write;
1690         f7_msg->smbus = true;
1691
1692         ret = pm_runtime_get_sync(dev);
1693         if (ret < 0)
1694                 return ret;
1695
1696         ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1697         if (ret)
1698                 goto pm_free;
1699
1700         ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data);
1701         if (ret)
1702                 goto pm_free;
1703
1704         timeout = wait_for_completion_timeout(&i2c_dev->complete,
1705                                               i2c_dev->adap.timeout);
1706         ret = f7_msg->result;
1707         if (ret)
1708                 goto pm_free;
1709
1710         if (!timeout) {
1711                 dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr);
1712                 if (i2c_dev->use_dma)
1713                         dmaengine_terminate_all(dma->chan_using);
1714                 ret = -ETIMEDOUT;
1715                 goto pm_free;
1716         }
1717
1718         /* Check PEC */
1719         if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) {
1720                 ret = stm32f7_i2c_smbus_check_pec(i2c_dev);
1721                 if (ret)
1722                         goto pm_free;
1723         }
1724
1725         if (read_write && size != I2C_SMBUS_QUICK) {
1726                 switch (size) {
1727                 case I2C_SMBUS_BYTE:
1728                 case I2C_SMBUS_BYTE_DATA:
1729                         data->byte = f7_msg->smbus_buf[0];
1730                 break;
1731                 case I2C_SMBUS_WORD_DATA:
1732                 case I2C_SMBUS_PROC_CALL:
1733                         data->word = f7_msg->smbus_buf[0] |
1734                                 (f7_msg->smbus_buf[1] << 8);
1735                 break;
1736                 case I2C_SMBUS_BLOCK_DATA:
1737                 case I2C_SMBUS_BLOCK_PROC_CALL:
1738                 for (i = 0; i <= f7_msg->smbus_buf[0]; i++)
1739                         data->block[i] = f7_msg->smbus_buf[i];
1740                 break;
1741                 default:
1742                         dev_err(dev, "Unsupported smbus transaction\n");
1743                         ret = -EINVAL;
1744                 }
1745         }
1746
1747 pm_free:
1748         pm_runtime_mark_last_busy(dev);
1749         pm_runtime_put_autosuspend(dev);
1750         return ret;
1751 }
1752
1753 static void stm32f7_i2c_enable_wakeup(struct stm32f7_i2c_dev *i2c_dev,
1754                                       bool enable)
1755 {
1756         void __iomem *base = i2c_dev->base;
1757         u32 mask = STM32F7_I2C_CR1_WUPEN;
1758
1759         if (!i2c_dev->wakeup_src)
1760                 return;
1761
1762         if (enable) {
1763                 device_set_wakeup_enable(i2c_dev->dev, true);
1764                 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1765         } else {
1766                 device_set_wakeup_enable(i2c_dev->dev, false);
1767                 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1768         }
1769 }
1770
1771 static int stm32f7_i2c_reg_slave(struct i2c_client *slave)
1772 {
1773         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1774         void __iomem *base = i2c_dev->base;
1775         struct device *dev = i2c_dev->dev;
1776         u32 oar1, oar2, mask;
1777         int id, ret;
1778
1779         if (slave->flags & I2C_CLIENT_PEC) {
1780                 dev_err(dev, "SMBus PEC not supported in slave mode\n");
1781                 return -EINVAL;
1782         }
1783
1784         if (stm32f7_i2c_is_slave_busy(i2c_dev)) {
1785                 dev_err(dev, "Too much slave registered\n");
1786                 return -EBUSY;
1787         }
1788
1789         ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id);
1790         if (ret)
1791                 return ret;
1792
1793         ret = pm_runtime_get_sync(dev);
1794         if (ret < 0)
1795                 return ret;
1796
1797         if (!stm32f7_i2c_is_slave_registered(i2c_dev))
1798                 stm32f7_i2c_enable_wakeup(i2c_dev, true);
1799
1800         switch (id) {
1801         case 0:
1802                 /* Slave SMBus Host */
1803                 i2c_dev->slave[id] = slave;
1804                 break;
1805
1806         case 1:
1807                 /* Configure Own Address 1 */
1808                 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
1809                 oar1 &= ~STM32F7_I2C_OAR1_MASK;
1810                 if (slave->flags & I2C_CLIENT_TEN) {
1811                         oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr);
1812                         oar1 |= STM32F7_I2C_OAR1_OA1MODE;
1813                 } else {
1814                         oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr);
1815                 }
1816                 oar1 |= STM32F7_I2C_OAR1_OA1EN;
1817                 i2c_dev->slave[id] = slave;
1818                 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1);
1819                 break;
1820
1821         case 2:
1822                 /* Configure Own Address 2 */
1823                 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
1824                 oar2 &= ~STM32F7_I2C_OAR2_MASK;
1825                 if (slave->flags & I2C_CLIENT_TEN) {
1826                         ret = -EOPNOTSUPP;
1827                         goto pm_free;
1828                 }
1829
1830                 oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr);
1831                 oar2 |= STM32F7_I2C_OAR2_OA2EN;
1832                 i2c_dev->slave[id] = slave;
1833                 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2);
1834                 break;
1835
1836         default:
1837                 dev_err(dev, "I2C slave id not supported\n");
1838                 ret = -ENODEV;
1839                 goto pm_free;
1840         }
1841
1842         /* Enable ACK */
1843         stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK);
1844
1845         /* Enable Address match interrupt, error interrupt and enable I2C  */
1846         mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE |
1847                 STM32F7_I2C_CR1_PE;
1848         stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1849
1850         ret = 0;
1851 pm_free:
1852         if (!stm32f7_i2c_is_slave_registered(i2c_dev))
1853                 stm32f7_i2c_enable_wakeup(i2c_dev, false);
1854
1855         pm_runtime_mark_last_busy(dev);
1856         pm_runtime_put_autosuspend(dev);
1857
1858         return ret;
1859 }
1860
1861 static int stm32f7_i2c_unreg_slave(struct i2c_client *slave)
1862 {
1863         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1864         void __iomem *base = i2c_dev->base;
1865         u32 mask;
1866         int id, ret;
1867
1868         ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id);
1869         if (ret)
1870                 return ret;
1871
1872         WARN_ON(!i2c_dev->slave[id]);
1873
1874         ret = pm_runtime_get_sync(i2c_dev->dev);
1875         if (ret < 0)
1876                 return ret;
1877
1878         if (id == 1) {
1879                 mask = STM32F7_I2C_OAR1_OA1EN;
1880                 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask);
1881         } else if (id == 2) {
1882                 mask = STM32F7_I2C_OAR2_OA2EN;
1883                 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask);
1884         }
1885
1886         i2c_dev->slave[id] = NULL;
1887
1888         if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
1889                 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
1890                 stm32f7_i2c_enable_wakeup(i2c_dev, false);
1891         }
1892
1893         pm_runtime_mark_last_busy(i2c_dev->dev);
1894         pm_runtime_put_autosuspend(i2c_dev->dev);
1895
1896         return 0;
1897 }
1898
1899 static int stm32f7_i2c_write_fm_plus_bits(struct stm32f7_i2c_dev *i2c_dev,
1900                                           bool enable)
1901 {
1902         int ret;
1903
1904         if (i2c_dev->bus_rate <= I2C_MAX_FAST_MODE_FREQ ||
1905             IS_ERR_OR_NULL(i2c_dev->regmap))
1906                 /* Optional */
1907                 return 0;
1908
1909         if (i2c_dev->fmp_sreg == i2c_dev->fmp_creg)
1910                 ret = regmap_update_bits(i2c_dev->regmap,
1911                                          i2c_dev->fmp_sreg,
1912                                          i2c_dev->fmp_mask,
1913                                          enable ? i2c_dev->fmp_mask : 0);
1914         else
1915                 ret = regmap_write(i2c_dev->regmap,
1916                                    enable ? i2c_dev->fmp_sreg :
1917                                             i2c_dev->fmp_creg,
1918                                    i2c_dev->fmp_mask);
1919
1920         return ret;
1921 }
1922
1923 static int stm32f7_i2c_setup_fm_plus_bits(struct platform_device *pdev,
1924                                           struct stm32f7_i2c_dev *i2c_dev)
1925 {
1926         struct device_node *np = pdev->dev.of_node;
1927         int ret;
1928
1929         i2c_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg-fmp");
1930         if (IS_ERR(i2c_dev->regmap))
1931                 /* Optional */
1932                 return 0;
1933
1934         ret = of_property_read_u32_index(np, "st,syscfg-fmp", 1,
1935                                          &i2c_dev->fmp_sreg);
1936         if (ret)
1937                 return ret;
1938
1939         i2c_dev->fmp_creg = i2c_dev->fmp_sreg +
1940                                i2c_dev->setup.fmp_clr_offset;
1941
1942         return of_property_read_u32_index(np, "st,syscfg-fmp", 2,
1943                                           &i2c_dev->fmp_mask);
1944 }
1945
1946 static int stm32f7_i2c_enable_smbus_host(struct stm32f7_i2c_dev *i2c_dev)
1947 {
1948         struct i2c_adapter *adap = &i2c_dev->adap;
1949         void __iomem *base = i2c_dev->base;
1950         struct i2c_client *client;
1951
1952         client = i2c_new_slave_host_notify_device(adap);
1953         if (IS_ERR(client))
1954                 return PTR_ERR(client);
1955
1956         i2c_dev->host_notify_client = client;
1957
1958         /* Enable SMBus Host address */
1959         stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_SMBHEN);
1960
1961         return 0;
1962 }
1963
1964 static void stm32f7_i2c_disable_smbus_host(struct stm32f7_i2c_dev *i2c_dev)
1965 {
1966         void __iomem *base = i2c_dev->base;
1967
1968         if (i2c_dev->host_notify_client) {
1969                 /* Disable SMBus Host address */
1970                 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1,
1971                                      STM32F7_I2C_CR1_SMBHEN);
1972                 i2c_free_slave_host_notify_device(i2c_dev->host_notify_client);
1973         }
1974 }
1975
1976 static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
1977 {
1978         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1979
1980         u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE |
1981                    I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
1982                    I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
1983                    I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
1984                    I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC |
1985                    I2C_FUNC_SMBUS_I2C_BLOCK;
1986
1987         if (i2c_dev->smbus_mode)
1988                 func |= I2C_FUNC_SMBUS_HOST_NOTIFY;
1989
1990         return func;
1991 }
1992
1993 static const struct i2c_algorithm stm32f7_i2c_algo = {
1994         .master_xfer = stm32f7_i2c_xfer,
1995         .smbus_xfer = stm32f7_i2c_smbus_xfer,
1996         .functionality = stm32f7_i2c_func,
1997         .reg_slave = stm32f7_i2c_reg_slave,
1998         .unreg_slave = stm32f7_i2c_unreg_slave,
1999 };
2000
2001 static int stm32f7_i2c_probe(struct platform_device *pdev)
2002 {
2003         struct stm32f7_i2c_dev *i2c_dev;
2004         const struct stm32f7_i2c_setup *setup;
2005         struct resource *res;
2006         struct i2c_adapter *adap;
2007         struct reset_control *rst;
2008         dma_addr_t phy_addr;
2009         int irq_error, irq_event, ret;
2010
2011         i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
2012         if (!i2c_dev)
2013                 return -ENOMEM;
2014
2015         i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2016         if (IS_ERR(i2c_dev->base))
2017                 return PTR_ERR(i2c_dev->base);
2018         phy_addr = (dma_addr_t)res->start;
2019
2020         irq_event = platform_get_irq(pdev, 0);
2021         if (irq_event <= 0) {
2022                 if (irq_event != -EPROBE_DEFER)
2023                         dev_err(&pdev->dev, "Failed to get IRQ event: %d\n",
2024                                 irq_event);
2025                 return irq_event ? : -ENOENT;
2026         }
2027
2028         irq_error = platform_get_irq(pdev, 1);
2029         if (irq_error <= 0) {
2030                 if (irq_error != -EPROBE_DEFER)
2031                         dev_err(&pdev->dev, "Failed to get IRQ error: %d\n",
2032                                 irq_error);
2033                 return irq_error ? : -ENOENT;
2034         }
2035
2036         i2c_dev->wakeup_src = of_property_read_bool(pdev->dev.of_node,
2037                                                     "wakeup-source");
2038
2039         i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
2040         if (IS_ERR(i2c_dev->clk))
2041                 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_dev->clk),
2042                                      "Failed to get controller clock\n");
2043
2044         ret = clk_prepare_enable(i2c_dev->clk);
2045         if (ret) {
2046                 dev_err(&pdev->dev, "Failed to prepare_enable clock\n");
2047                 return ret;
2048         }
2049
2050         rst = devm_reset_control_get(&pdev->dev, NULL);
2051         if (IS_ERR(rst)) {
2052                 ret = dev_err_probe(&pdev->dev, PTR_ERR(rst),
2053                                     "Error: Missing reset ctrl\n");
2054                 goto clk_free;
2055         }
2056         reset_control_assert(rst);
2057         udelay(2);
2058         reset_control_deassert(rst);
2059
2060         i2c_dev->dev = &pdev->dev;
2061
2062         ret = devm_request_threaded_irq(&pdev->dev, irq_event,
2063                                         stm32f7_i2c_isr_event,
2064                                         stm32f7_i2c_isr_event_thread,
2065                                         IRQF_ONESHOT,
2066                                         pdev->name, i2c_dev);
2067         if (ret) {
2068                 dev_err(&pdev->dev, "Failed to request irq event %i\n",
2069                         irq_event);
2070                 goto clk_free;
2071         }
2072
2073         ret = devm_request_irq(&pdev->dev, irq_error, stm32f7_i2c_isr_error, 0,
2074                                pdev->name, i2c_dev);
2075         if (ret) {
2076                 dev_err(&pdev->dev, "Failed to request irq error %i\n",
2077                         irq_error);
2078                 goto clk_free;
2079         }
2080
2081         setup = of_device_get_match_data(&pdev->dev);
2082         if (!setup) {
2083                 dev_err(&pdev->dev, "Can't get device data\n");
2084                 ret = -ENODEV;
2085                 goto clk_free;
2086         }
2087         i2c_dev->setup = *setup;
2088
2089         ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup);
2090         if (ret)
2091                 goto clk_free;
2092
2093         /* Setup Fast mode plus if necessary */
2094         if (i2c_dev->bus_rate > I2C_MAX_FAST_MODE_FREQ) {
2095                 ret = stm32f7_i2c_setup_fm_plus_bits(pdev, i2c_dev);
2096                 if (ret)
2097                         goto clk_free;
2098                 ret = stm32f7_i2c_write_fm_plus_bits(i2c_dev, true);
2099                 if (ret)
2100                         goto clk_free;
2101         }
2102
2103         adap = &i2c_dev->adap;
2104         i2c_set_adapdata(adap, i2c_dev);
2105         snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)",
2106                  &res->start);
2107         adap->owner = THIS_MODULE;
2108         adap->timeout = 2 * HZ;
2109         adap->retries = 3;
2110         adap->algo = &stm32f7_i2c_algo;
2111         adap->dev.parent = &pdev->dev;
2112         adap->dev.of_node = pdev->dev.of_node;
2113
2114         init_completion(&i2c_dev->complete);
2115
2116         /* Init DMA config if supported */
2117         i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr,
2118                                              STM32F7_I2C_TXDR,
2119                                              STM32F7_I2C_RXDR);
2120         if (IS_ERR(i2c_dev->dma)) {
2121                 ret = PTR_ERR(i2c_dev->dma);
2122                 /* DMA support is optional, only report other errors */
2123                 if (ret != -ENODEV)
2124                         goto fmp_clear;
2125                 dev_dbg(i2c_dev->dev, "No DMA option: fallback using interrupts\n");
2126                 i2c_dev->dma = NULL;
2127         }
2128
2129         if (i2c_dev->wakeup_src) {
2130                 device_set_wakeup_capable(i2c_dev->dev, true);
2131
2132                 ret = dev_pm_set_wake_irq(i2c_dev->dev, irq_event);
2133                 if (ret) {
2134                         dev_err(i2c_dev->dev, "Failed to set wake up irq\n");
2135                         goto clr_wakeup_capable;
2136                 }
2137         }
2138
2139         platform_set_drvdata(pdev, i2c_dev);
2140
2141         pm_runtime_set_autosuspend_delay(i2c_dev->dev,
2142                                          STM32F7_AUTOSUSPEND_DELAY);
2143         pm_runtime_use_autosuspend(i2c_dev->dev);
2144         pm_runtime_set_active(i2c_dev->dev);
2145         pm_runtime_enable(i2c_dev->dev);
2146
2147         pm_runtime_get_noresume(&pdev->dev);
2148
2149         stm32f7_i2c_hw_config(i2c_dev);
2150
2151         i2c_dev->smbus_mode = of_property_read_bool(pdev->dev.of_node, "smbus");
2152
2153         ret = i2c_add_adapter(adap);
2154         if (ret)
2155                 goto pm_disable;
2156
2157         if (i2c_dev->smbus_mode) {
2158                 ret = stm32f7_i2c_enable_smbus_host(i2c_dev);
2159                 if (ret) {
2160                         dev_err(i2c_dev->dev,
2161                                 "failed to enable SMBus Host-Notify protocol (%d)\n",
2162                                 ret);
2163                         goto i2c_adapter_remove;
2164                 }
2165         }
2166
2167         dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr);
2168
2169         pm_runtime_mark_last_busy(i2c_dev->dev);
2170         pm_runtime_put_autosuspend(i2c_dev->dev);
2171
2172         return 0;
2173
2174 i2c_adapter_remove:
2175         i2c_del_adapter(adap);
2176
2177 pm_disable:
2178         pm_runtime_put_noidle(i2c_dev->dev);
2179         pm_runtime_disable(i2c_dev->dev);
2180         pm_runtime_set_suspended(i2c_dev->dev);
2181         pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2182
2183         if (i2c_dev->wakeup_src)
2184                 dev_pm_clear_wake_irq(i2c_dev->dev);
2185
2186 clr_wakeup_capable:
2187         if (i2c_dev->wakeup_src)
2188                 device_set_wakeup_capable(i2c_dev->dev, false);
2189
2190         if (i2c_dev->dma) {
2191                 stm32_i2c_dma_free(i2c_dev->dma);
2192                 i2c_dev->dma = NULL;
2193         }
2194
2195 fmp_clear:
2196         stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2197
2198 clk_free:
2199         clk_disable_unprepare(i2c_dev->clk);
2200
2201         return ret;
2202 }
2203
2204 static int stm32f7_i2c_remove(struct platform_device *pdev)
2205 {
2206         struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
2207
2208         stm32f7_i2c_disable_smbus_host(i2c_dev);
2209
2210         i2c_del_adapter(&i2c_dev->adap);
2211         pm_runtime_get_sync(i2c_dev->dev);
2212
2213         if (i2c_dev->wakeup_src) {
2214                 dev_pm_clear_wake_irq(i2c_dev->dev);
2215                 /*
2216                  * enforce that wakeup is disabled and that the device
2217                  * is marked as non wakeup capable
2218                  */
2219                 device_init_wakeup(i2c_dev->dev, false);
2220         }
2221
2222         pm_runtime_put_noidle(i2c_dev->dev);
2223         pm_runtime_disable(i2c_dev->dev);
2224         pm_runtime_set_suspended(i2c_dev->dev);
2225         pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2226
2227         if (i2c_dev->dma) {
2228                 stm32_i2c_dma_free(i2c_dev->dma);
2229                 i2c_dev->dma = NULL;
2230         }
2231
2232         stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2233
2234         clk_disable_unprepare(i2c_dev->clk);
2235
2236         return 0;
2237 }
2238
2239 static int __maybe_unused stm32f7_i2c_runtime_suspend(struct device *dev)
2240 {
2241         struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2242
2243         if (!stm32f7_i2c_is_slave_registered(i2c_dev))
2244                 clk_disable_unprepare(i2c_dev->clk);
2245
2246         return 0;
2247 }
2248
2249 static int __maybe_unused stm32f7_i2c_runtime_resume(struct device *dev)
2250 {
2251         struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2252         int ret;
2253
2254         if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
2255                 ret = clk_prepare_enable(i2c_dev->clk);
2256                 if (ret) {
2257                         dev_err(dev, "failed to prepare_enable clock\n");
2258                         return ret;
2259                 }
2260         }
2261
2262         return 0;
2263 }
2264
2265 #ifdef CONFIG_PM_SLEEP
2266 static int stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev *i2c_dev)
2267 {
2268         int ret;
2269         struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2270
2271         ret = pm_runtime_get_sync(i2c_dev->dev);
2272         if (ret < 0)
2273                 return ret;
2274
2275         backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2276         backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
2277         backup_regs->oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
2278         backup_regs->oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
2279         backup_regs->tmgr = readl_relaxed(i2c_dev->base + STM32F7_I2C_TIMINGR);
2280         stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2281
2282         pm_runtime_put_sync(i2c_dev->dev);
2283
2284         return ret;
2285 }
2286
2287 static int stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev *i2c_dev)
2288 {
2289         u32 cr1;
2290         int ret;
2291         struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2292
2293         ret = pm_runtime_get_sync(i2c_dev->dev);
2294         if (ret < 0)
2295                 return ret;
2296
2297         cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2298         if (cr1 & STM32F7_I2C_CR1_PE)
2299                 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
2300                                      STM32F7_I2C_CR1_PE);
2301
2302         writel_relaxed(backup_regs->tmgr, i2c_dev->base + STM32F7_I2C_TIMINGR);
2303         writel_relaxed(backup_regs->cr1 & ~STM32F7_I2C_CR1_PE,
2304                        i2c_dev->base + STM32F7_I2C_CR1);
2305         if (backup_regs->cr1 & STM32F7_I2C_CR1_PE)
2306                 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
2307                                      STM32F7_I2C_CR1_PE);
2308         writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2);
2309         writel_relaxed(backup_regs->oar1, i2c_dev->base + STM32F7_I2C_OAR1);
2310         writel_relaxed(backup_regs->oar2, i2c_dev->base + STM32F7_I2C_OAR2);
2311         stm32f7_i2c_write_fm_plus_bits(i2c_dev, true);
2312
2313         pm_runtime_put_sync(i2c_dev->dev);
2314
2315         return ret;
2316 }
2317
2318 static int stm32f7_i2c_suspend(struct device *dev)
2319 {
2320         struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2321         int ret;
2322
2323         i2c_mark_adapter_suspended(&i2c_dev->adap);
2324
2325         if (!device_may_wakeup(dev) && !dev->power.wakeup_path) {
2326                 ret = stm32f7_i2c_regs_backup(i2c_dev);
2327                 if (ret < 0) {
2328                         i2c_mark_adapter_resumed(&i2c_dev->adap);
2329                         return ret;
2330                 }
2331
2332                 pinctrl_pm_select_sleep_state(dev);
2333                 pm_runtime_force_suspend(dev);
2334         }
2335
2336         return 0;
2337 }
2338
2339 static int stm32f7_i2c_resume(struct device *dev)
2340 {
2341         struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2342         int ret;
2343
2344         if (!device_may_wakeup(dev) && !dev->power.wakeup_path) {
2345                 ret = pm_runtime_force_resume(dev);
2346                 if (ret < 0)
2347                         return ret;
2348                 pinctrl_pm_select_default_state(dev);
2349
2350                 ret = stm32f7_i2c_regs_restore(i2c_dev);
2351                 if (ret < 0)
2352                         return ret;
2353         }
2354
2355         i2c_mark_adapter_resumed(&i2c_dev->adap);
2356
2357         return 0;
2358 }
2359 #endif
2360
2361 static const struct dev_pm_ops stm32f7_i2c_pm_ops = {
2362         SET_RUNTIME_PM_OPS(stm32f7_i2c_runtime_suspend,
2363                            stm32f7_i2c_runtime_resume, NULL)
2364         SET_SYSTEM_SLEEP_PM_OPS(stm32f7_i2c_suspend, stm32f7_i2c_resume)
2365 };
2366
2367 static const struct of_device_id stm32f7_i2c_match[] = {
2368         { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup},
2369         { .compatible = "st,stm32mp15-i2c", .data = &stm32mp15_setup},
2370         {},
2371 };
2372 MODULE_DEVICE_TABLE(of, stm32f7_i2c_match);
2373
2374 static struct platform_driver stm32f7_i2c_driver = {
2375         .driver = {
2376                 .name = "stm32f7-i2c",
2377                 .of_match_table = stm32f7_i2c_match,
2378                 .pm = &stm32f7_i2c_pm_ops,
2379         },
2380         .probe = stm32f7_i2c_probe,
2381         .remove = stm32f7_i2c_remove,
2382 };
2383
2384 module_platform_driver(stm32f7_i2c_driver);
2385
2386 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
2387 MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver");
2388 MODULE_LICENSE("GPL v2");