drivers/i2c/busses/i2c-stm32f7.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for STMicroelectronics STM32F7 I2C controller
   4  *
   5  * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc
   6  * reference manual.
   7  * Please see below a link to the documentation:
   8  * http://www.st.com/resource/en/reference_manual/dm00124865.pdf
   9  *
  10  * Copyright (C) M'boumba Cedric Madianga 2017
  11  * Copyright (C) STMicroelectronics 2017
  12  * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
  13  *
  14  * This driver is based on i2c-stm32f4.c
  15  *
  16  */
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/err.h>
  20 #include <linux/i2c.h>
  21 #include <linux/i2c-smbus.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/io.h>
  24 #include <linux/iopoll.h>
  25 #include <linux/mfd/syscon.h>
  26 #include <linux/module.h>
  27 #include <linux/of.h>
  28 #include <linux/of_address.h>
  29 #include <linux/of_platform.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/pinctrl/consumer.h>
  32 #include <linux/pm_runtime.h>
  33 #include <linux/pm_wakeirq.h>
  34 #include <linux/regmap.h>
  35 #include <linux/reset.h>
  36 #include <linux/slab.h>
  37
  38 #include "i2c-stm32.h"
  39
  40 /* STM32F7 I2C registers */
  41 #define STM32F7_I2C_CR1                         0x00
  42 #define STM32F7_I2C_CR2                         0x04
  43 #define STM32F7_I2C_OAR1                        0x08
  44 #define STM32F7_I2C_OAR2                        0x0C
  45 #define STM32F7_I2C_PECR                        0x20
  46 #define STM32F7_I2C_TIMINGR                     0x10
  47 #define STM32F7_I2C_ISR                         0x18
  48 #define STM32F7_I2C_ICR                         0x1C
  49 #define STM32F7_I2C_RXDR                        0x24
  50 #define STM32F7_I2C_TXDR                        0x28
  51
  52 /* STM32F7 I2C control 1 */
  53 #define STM32F7_I2C_CR1_PECEN                   BIT(23)
  54 #define STM32F7_I2C_CR1_SMBHEN                  BIT(20)
  55 #define STM32F7_I2C_CR1_WUPEN                   BIT(18)
  56 #define STM32F7_I2C_CR1_SBC                     BIT(16)
  57 #define STM32F7_I2C_CR1_RXDMAEN                 BIT(15)
  58 #define STM32F7_I2C_CR1_TXDMAEN                 BIT(14)
  59 #define STM32F7_I2C_CR1_ANFOFF                  BIT(12)
  60 #define STM32F7_I2C_CR1_DNF_MASK                GENMASK(11, 8)
  61 #define STM32F7_I2C_CR1_DNF(n)                  (((n) & 0xf) << 8)
  62 #define STM32F7_I2C_CR1_ERRIE                   BIT(7)
  63 #define STM32F7_I2C_CR1_TCIE                    BIT(6)
  64 #define STM32F7_I2C_CR1_STOPIE                  BIT(5)
  65 #define STM32F7_I2C_CR1_NACKIE                  BIT(4)
  66 #define STM32F7_I2C_CR1_ADDRIE                  BIT(3)
  67 #define STM32F7_I2C_CR1_RXIE                    BIT(2)
  68 #define STM32F7_I2C_CR1_TXIE                    BIT(1)
  69 #define STM32F7_I2C_CR1_PE                      BIT(0)
  70 #define STM32F7_I2C_ALL_IRQ_MASK                (STM32F7_I2C_CR1_ERRIE \
  71                                                 | STM32F7_I2C_CR1_TCIE \
  72                                                 | STM32F7_I2C_CR1_STOPIE \
  73                                                 | STM32F7_I2C_CR1_NACKIE \
  74                                                 | STM32F7_I2C_CR1_RXIE \
  75                                                 | STM32F7_I2C_CR1_TXIE)
  76 #define STM32F7_I2C_XFER_IRQ_MASK               (STM32F7_I2C_CR1_TCIE \
  77                                                 | STM32F7_I2C_CR1_STOPIE \
  78                                                 | STM32F7_I2C_CR1_NACKIE \
  79                                                 | STM32F7_I2C_CR1_RXIE \
  80                                                 | STM32F7_I2C_CR1_TXIE)
  81
  82 /* STM32F7 I2C control 2 */
  83 #define STM32F7_I2C_CR2_PECBYTE                 BIT(26)
  84 #define STM32F7_I2C_CR2_RELOAD                  BIT(24)
  85 #define STM32F7_I2C_CR2_NBYTES_MASK             GENMASK(23, 16)
  86 #define STM32F7_I2C_CR2_NBYTES(n)               (((n) & 0xff) << 16)
  87 #define STM32F7_I2C_CR2_NACK                    BIT(15)
  88 #define STM32F7_I2C_CR2_STOP                    BIT(14)
  89 #define STM32F7_I2C_CR2_START                   BIT(13)
  90 #define STM32F7_I2C_CR2_HEAD10R                 BIT(12)
  91 #define STM32F7_I2C_CR2_ADD10                   BIT(11)
  92 #define STM32F7_I2C_CR2_RD_WRN                  BIT(10)
  93 #define STM32F7_I2C_CR2_SADD10_MASK             GENMASK(9, 0)
  94 #define STM32F7_I2C_CR2_SADD10(n)               (((n) & \
  95                                                 STM32F7_I2C_CR2_SADD10_MASK))
  96 #define STM32F7_I2C_CR2_SADD7_MASK              GENMASK(7, 1)
  97 #define STM32F7_I2C_CR2_SADD7(n)                (((n) & 0x7f) << 1)
  98
  99 /* STM32F7 I2C Own Address 1 */
 100 #define STM32F7_I2C_OAR1_OA1EN                  BIT(15)
 101 #define STM32F7_I2C_OAR1_OA1MODE                BIT(10)
 102 #define STM32F7_I2C_OAR1_OA1_10_MASK            GENMASK(9, 0)
 103 #define STM32F7_I2C_OAR1_OA1_10(n)              (((n) & \
 104                                                 STM32F7_I2C_OAR1_OA1_10_MASK))
 105 #define STM32F7_I2C_OAR1_OA1_7_MASK             GENMASK(7, 1)
 106 #define STM32F7_I2C_OAR1_OA1_7(n)               (((n) & 0x7f) << 1)
 107 #define STM32F7_I2C_OAR1_MASK                   (STM32F7_I2C_OAR1_OA1_7_MASK \
 108                                                 | STM32F7_I2C_OAR1_OA1_10_MASK \
 109                                                 | STM32F7_I2C_OAR1_OA1EN \
 110                                                 | STM32F7_I2C_OAR1_OA1MODE)
 111
 112 /* STM32F7 I2C Own Address 2 */
 113 #define STM32F7_I2C_OAR2_OA2EN                  BIT(15)
 114 #define STM32F7_I2C_OAR2_OA2MSK_MASK            GENMASK(10, 8)
 115 #define STM32F7_I2C_OAR2_OA2MSK(n)              (((n) & 0x7) << 8)
 116 #define STM32F7_I2C_OAR2_OA2_7_MASK             GENMASK(7, 1)
 117 #define STM32F7_I2C_OAR2_OA2_7(n)               (((n) & 0x7f) << 1)
 118 #define STM32F7_I2C_OAR2_MASK                   (STM32F7_I2C_OAR2_OA2MSK_MASK \
 119                                                 | STM32F7_I2C_OAR2_OA2_7_MASK \
 120                                                 | STM32F7_I2C_OAR2_OA2EN)
 121
 122 /* STM32F7 I2C Interrupt Status */
 123 #define STM32F7_I2C_ISR_ADDCODE_MASK            GENMASK(23, 17)
 124 #define STM32F7_I2C_ISR_ADDCODE_GET(n) \
 125                                 (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17)
 126 #define STM32F7_I2C_ISR_DIR                     BIT(16)
 127 #define STM32F7_I2C_ISR_BUSY                    BIT(15)
 128 #define STM32F7_I2C_ISR_PECERR                  BIT(11)
 129 #define STM32F7_I2C_ISR_ARLO                    BIT(9)
 130 #define STM32F7_I2C_ISR_BERR                    BIT(8)
 131 #define STM32F7_I2C_ISR_TCR                     BIT(7)
 132 #define STM32F7_I2C_ISR_TC                      BIT(6)
 133 #define STM32F7_I2C_ISR_STOPF                   BIT(5)
 134 #define STM32F7_I2C_ISR_NACKF                   BIT(4)
 135 #define STM32F7_I2C_ISR_ADDR                    BIT(3)
 136 #define STM32F7_I2C_ISR_RXNE                    BIT(2)
 137 #define STM32F7_I2C_ISR_TXIS                    BIT(1)
 138 #define STM32F7_I2C_ISR_TXE                     BIT(0)
 139
 140 /* STM32F7 I2C Interrupt Clear */
 141 #define STM32F7_I2C_ICR_PECCF                   BIT(11)
 142 #define STM32F7_I2C_ICR_ARLOCF                  BIT(9)
 143 #define STM32F7_I2C_ICR_BERRCF                  BIT(8)
 144 #define STM32F7_I2C_ICR_STOPCF                  BIT(5)
 145 #define STM32F7_I2C_ICR_NACKCF                  BIT(4)
 146 #define STM32F7_I2C_ICR_ADDRCF                  BIT(3)
 147
 148 /* STM32F7 I2C Timing */
 149 #define STM32F7_I2C_TIMINGR_PRESC(n)            (((n) & 0xf) << 28)
 150 #define STM32F7_I2C_TIMINGR_SCLDEL(n)           (((n) & 0xf) << 20)
 151 #define STM32F7_I2C_TIMINGR_SDADEL(n)           (((n) & 0xf) << 16)
 152 #define STM32F7_I2C_TIMINGR_SCLH(n)             (((n) & 0xff) << 8)
 153 #define STM32F7_I2C_TIMINGR_SCLL(n)             ((n) & 0xff)
 154
 155 #define STM32F7_I2C_MAX_LEN                     0xff
 156 #define STM32F7_I2C_DMA_LEN_MIN                 0x16
 157 enum {
 158         STM32F7_SLAVE_HOSTNOTIFY,
 159         STM32F7_SLAVE_7_10_BITS_ADDR,
 160         STM32F7_SLAVE_7_BITS_ADDR,
 161         STM32F7_I2C_MAX_SLAVE
 162 };
 163
 164 #define STM32F7_I2C_DNF_DEFAULT                 0
 165 #define STM32F7_I2C_DNF_MAX                     15
 166
 167 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN     50      /* ns */
 168 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX     260     /* ns */
 169
 170 #define STM32F7_I2C_RISE_TIME_DEFAULT           25      /* ns */
 171 #define STM32F7_I2C_FALL_TIME_DEFAULT           10      /* ns */
 172
 173 #define STM32F7_PRESC_MAX                       BIT(4)
 174 #define STM32F7_SCLDEL_MAX                      BIT(4)
 175 #define STM32F7_SDADEL_MAX                      BIT(4)
 176 #define STM32F7_SCLH_MAX                        BIT(8)
 177 #define STM32F7_SCLL_MAX                        BIT(8)
 178
 179 #define STM32F7_AUTOSUSPEND_DELAY               (HZ / 100)
 180
 181 /**
 182  * struct stm32f7_i2c_regs - i2c f7 registers backup
 183  * @cr1: Control register 1
 184  * @cr2: Control register 2
 185  * @oar1: Own address 1 register
 186  * @oar2: Own address 2 register
 187  * @tmgr: Timing register
 188  */
 189 struct stm32f7_i2c_regs {
 190         u32 cr1;
 191         u32 cr2;
 192         u32 oar1;
 193         u32 oar2;
 194         u32 tmgr;
 195 };
 196
 197 /**
 198  * struct stm32f7_i2c_spec - private i2c specification timing
 199  * @rate: I2C bus speed (Hz)
 200  * @fall_max: Max fall time of both SDA and SCL signals (ns)
 201  * @rise_max: Max rise time of both SDA and SCL signals (ns)
 202  * @hddat_min: Min data hold time (ns)
 203  * @vddat_max: Max data valid time (ns)
 204  * @sudat_min: Min data setup time (ns)
 205  * @l_min: Min low period of the SCL clock (ns)
 206  * @h_min: Min high period of the SCL clock (ns)
 207  */
 208 struct stm32f7_i2c_spec {
 209         u32 rate;
 210         u32 fall_max;
 211         u32 rise_max;
 212         u32 hddat_min;
 213         u32 vddat_max;
 214         u32 sudat_min;
 215         u32 l_min;
 216         u32 h_min;
 217 };
 218
 219 /**
 220  * struct stm32f7_i2c_setup - private I2C timing setup parameters
 221  * @speed_freq: I2C speed frequency  (Hz)
 222  * @clock_src: I2C clock source frequency (Hz)
 223  * @rise_time: Rise time (ns)
 224  * @fall_time: Fall time (ns)
 225  * @fmp_clr_offset: Fast Mode Plus clear register offset from set register
 226  */
 227 struct stm32f7_i2c_setup {
 228         u32 speed_freq;
 229         u32 clock_src;
 230         u32 rise_time;
 231         u32 fall_time;
 232         u32 fmp_clr_offset;
 233 };
 234
 235 /**
 236  * struct stm32f7_i2c_timings - private I2C output parameters
 237  * @node: List entry
 238  * @presc: Prescaler value
 239  * @scldel: Data setup time
 240  * @sdadel: Data hold time
 241  * @sclh: SCL high period (master mode)
 242  * @scll: SCL low period (master mode)
 243  */
 244 struct stm32f7_i2c_timings {
 245         struct list_head node;
 246         u8 presc;
 247         u8 scldel;
 248         u8 sdadel;
 249         u8 sclh;
 250         u8 scll;
 251 };
 252
 253 /**
 254  * struct stm32f7_i2c_msg - client specific data
 255  * @addr: 8-bit or 10-bit slave addr, including r/w bit
 256  * @count: number of bytes to be transferred
 257  * @buf: data buffer
 258  * @result: result of the transfer
 259  * @stop: last I2C msg to be sent, i.e. STOP to be generated
 260  * @smbus: boolean to know if the I2C IP is used in SMBus mode
 261  * @size: type of SMBus protocol
 262  * @read_write: direction of SMBus protocol
 263  * SMBus block read and SMBus block write - block read process call protocols
 264  * @smbus_buf: buffer to be used for SMBus protocol transfer. It will
 265  * contain a maximum of 32 bytes of data + byte command + byte count + PEC
 266  * This buffer has to be 32-bit aligned to be compliant with memory address
 267  * register in DMA mode.
 268  */
 269 struct stm32f7_i2c_msg {
 270         u16 addr;
 271         u32 count;
 272         u8 *buf;
 273         int result;
 274         bool stop;
 275         bool smbus;
 276         int size;
 277         char read_write;
 278         u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4);
 279 };
 280
 281 /**
 282  * struct stm32f7_i2c_dev - private data of the controller
 283  * @adap: I2C adapter for this controller
 284  * @dev: device for this controller
 285  * @base: virtual memory area
 286  * @complete: completion of I2C message
 287  * @clk: hw i2c clock
 288  * @bus_rate: I2C clock frequency of the controller
 289  * @msg: Pointer to data to be written
 290  * @msg_num: number of I2C messages to be executed
 291  * @msg_id: message identifiant
 292  * @f7_msg: customized i2c msg for driver usage
 293  * @setup: I2C timing input setup
 294  * @timing: I2C computed timings
 295  * @slave: list of slave devices registered on the I2C bus
 296  * @slave_running: slave device currently used
 297  * @backup_regs: backup of i2c controller registers (for suspend/resume)
 298  * @slave_dir: transfer direction for the current slave device
 299  * @master_mode: boolean to know in which mode the I2C is running (master or
 300  * slave)
 301  * @dma: dma data
 302  * @use_dma: boolean to know if dma is used in the current transfer
 303  * @regmap: holds SYSCFG phandle for Fast Mode Plus bits
 304  * @fmp_sreg: register address for setting Fast Mode Plus bits
 305  * @fmp_creg: register address for clearing Fast Mode Plus bits
 306  * @fmp_mask: mask for Fast Mode Plus bits in set register
 307  * @wakeup_src: boolean to know if the device is a wakeup source
 308  * @smbus_mode: states that the controller is configured in SMBus mode
 309  * @host_notify_client: SMBus host-notify client
 310  * @analog_filter: boolean to indicate enabling of the analog filter
 311  * @dnf_dt: value of digital filter requested via dt
 312  * @dnf: value of digital filter to apply
 313  */
 314 struct stm32f7_i2c_dev {
 315         struct i2c_adapter adap;
 316         struct device *dev;
 317         void __iomem *base;
 318         struct completion complete;
 319         struct clk *clk;
 320         unsigned int bus_rate;
 321         struct i2c_msg *msg;
 322         unsigned int msg_num;
 323         unsigned int msg_id;
 324         struct stm32f7_i2c_msg f7_msg;
 325         struct stm32f7_i2c_setup setup;
 326         struct stm32f7_i2c_timings timing;
 327         struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE];
 328         struct i2c_client *slave_running;
 329         struct stm32f7_i2c_regs backup_regs;
 330         u32 slave_dir;
 331         bool master_mode;
 332         struct stm32_i2c_dma *dma;
 333         bool use_dma;
 334         struct regmap *regmap;
 335         u32 fmp_sreg;
 336         u32 fmp_creg;
 337         u32 fmp_mask;
 338         bool wakeup_src;
 339         bool smbus_mode;
 340         struct i2c_client *host_notify_client;
 341         bool analog_filter;
 342         u32 dnf_dt;
 343         u32 dnf;
 344 };
 345
 346 /*
 347  * All these values are coming from I2C Specification, Version 6.0, 4th of
 348  * April 2014.
 349  *
 350  * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast,
 351  * and Fast-mode Plus I2C-bus devices
 352  */
 353 static struct stm32f7_i2c_spec stm32f7_i2c_specs[] = {
 354         {
 355                 .rate = I2C_MAX_STANDARD_MODE_FREQ,
 356                 .fall_max = 300,
 357                 .rise_max = 1000,
 358                 .hddat_min = 0,
 359                 .vddat_max = 3450,
 360                 .sudat_min = 250,
 361                 .l_min = 4700,
 362                 .h_min = 4000,
 363         },
 364         {
 365                 .rate = I2C_MAX_FAST_MODE_FREQ,
 366                 .fall_max = 300,
 367                 .rise_max = 300,
 368                 .hddat_min = 0,
 369                 .vddat_max = 900,
 370                 .sudat_min = 100,
 371                 .l_min = 1300,
 372                 .h_min = 600,
 373         },
 374         {
 375                 .rate = I2C_MAX_FAST_MODE_PLUS_FREQ,
 376                 .fall_max = 100,
 377                 .rise_max = 120,
 378                 .hddat_min = 0,
 379                 .vddat_max = 450,
 380                 .sudat_min = 50,
 381                 .l_min = 500,
 382                 .h_min = 260,
 383         },
 384 };
 385
 386 static const struct stm32f7_i2c_setup stm32f7_setup = {
 387         .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
 388         .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
 389 };
 390
 391 static const struct stm32f7_i2c_setup stm32mp15_setup = {
 392         .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
 393         .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
 394         .fmp_clr_offset = 0x40,
 395 };
 396
 397 static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask)
 398 {
 399         writel_relaxed(readl_relaxed(reg) | mask, reg);
 400 }
 401
 402 static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask)
 403 {
 404         writel_relaxed(readl_relaxed(reg) & ~mask, reg);
 405 }
 406
 407 static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)
 408 {
 409         stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
 410 }
 411
 412 static struct stm32f7_i2c_spec *stm32f7_get_specs(u32 rate)
 413 {
 414         int i;
 415
 416         for (i = 0; i < ARRAY_SIZE(stm32f7_i2c_specs); i++)
 417                 if (rate <= stm32f7_i2c_specs[i].rate)
 418                         return &stm32f7_i2c_specs[i];
 419
 420         return ERR_PTR(-EINVAL);
 421 }
 422
 423 #define RATE_MIN(rate)  ((rate) * 8 / 10)
 424 static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev,
 425                                       struct stm32f7_i2c_setup *setup,
 426                                       struct stm32f7_i2c_timings *output)
 427 {
 428         struct stm32f7_i2c_spec *specs;
 429         u32 p_prev = STM32F7_PRESC_MAX;
 430         u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
 431                                        setup->clock_src);
 432         u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
 433                                        setup->speed_freq);
 434         u32 clk_error_prev = i2cbus;
 435         u32 tsync;
 436         u32 af_delay_min, af_delay_max;
 437         u32 dnf_delay;
 438         u32 clk_min, clk_max;
 439         int sdadel_min, sdadel_max;
 440         int scldel_min;
 441         struct stm32f7_i2c_timings *v, *_v, *s;
 442         struct list_head solutions;
 443         u16 p, l, a, h;
 444         int ret = 0;
 445
 446         specs = stm32f7_get_specs(setup->speed_freq);
 447         if (specs == ERR_PTR(-EINVAL)) {
 448                 dev_err(i2c_dev->dev, "speed out of bound {%d}\n",
 449                         setup->speed_freq);
 450                 return -EINVAL;
 451         }
 452
 453         if ((setup->rise_time > specs->rise_max) ||
 454             (setup->fall_time > specs->fall_max)) {
 455                 dev_err(i2c_dev->dev,
 456                         "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
 457                         setup->rise_time, specs->rise_max,
 458                         setup->fall_time, specs->fall_max);
 459                 return -EINVAL;
 460         }
 461
 462         i2c_dev->dnf = DIV_ROUND_CLOSEST(i2c_dev->dnf_dt, i2cclk);
 463         if (i2c_dev->dnf > STM32F7_I2C_DNF_MAX) {
 464                 dev_err(i2c_dev->dev,
 465                         "DNF out of bound %d/%d\n",
 466                         i2c_dev->dnf * i2cclk, STM32F7_I2C_DNF_MAX * i2cclk);
 467                 return -EINVAL;
 468         }
 469
 470         /*  Analog and Digital Filters */
 471         af_delay_min =
 472                 (i2c_dev->analog_filter ?
 473                  STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0);
 474         af_delay_max =
 475                 (i2c_dev->analog_filter ?
 476                  STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0);
 477         dnf_delay = i2c_dev->dnf * i2cclk;
 478
 479         sdadel_min = specs->hddat_min + setup->fall_time -
 480                 af_delay_min - (i2c_dev->dnf + 3) * i2cclk;
 481
 482         sdadel_max = specs->vddat_max - setup->rise_time -
 483                 af_delay_max - (i2c_dev->dnf + 4) * i2cclk;
 484
 485         scldel_min = setup->rise_time + specs->sudat_min;
 486
 487         if (sdadel_min < 0)
 488                 sdadel_min = 0;
 489         if (sdadel_max < 0)
 490                 sdadel_max = 0;
 491
 492         dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n",
 493                 sdadel_min, sdadel_max, scldel_min);
 494
 495         INIT_LIST_HEAD(&solutions);
 496         /* Compute possible values for PRESC, SCLDEL and SDADEL */
 497         for (p = 0; p < STM32F7_PRESC_MAX; p++) {
 498                 for (l = 0; l < STM32F7_SCLDEL_MAX; l++) {
 499                         u32 scldel = (l + 1) * (p + 1) * i2cclk;
 500
 501                         if (scldel < scldel_min)
 502                                 continue;
 503
 504                         for (a = 0; a < STM32F7_SDADEL_MAX; a++) {
 505                                 u32 sdadel = (a * (p + 1) + 1) * i2cclk;
 506
 507                                 if (((sdadel >= sdadel_min) &&
 508                                      (sdadel <= sdadel_max)) &&
 509                                     (p != p_prev)) {
 510                                         v = kmalloc(sizeof(*v), GFP_KERNEL);
 511                                         if (!v) {
 512                                                 ret = -ENOMEM;
 513                                                 goto exit;
 514                                         }
 515
 516                                         v->presc = p;
 517                                         v->scldel = l;
 518                                         v->sdadel = a;
 519                                         p_prev = p;
 520
 521                                         list_add_tail(&v->node,
 522                                                       &solutions);
 523                                         break;
 524                                 }
 525                         }
 526
 527                         if (p_prev == p)
 528                                 break;
 529                 }
 530         }
 531
 532         if (list_empty(&solutions)) {
 533                 dev_err(i2c_dev->dev, "no Prescaler solution\n");
 534                 ret = -EPERM;
 535                 goto exit;
 536         }
 537
 538         tsync = af_delay_min + dnf_delay + (2 * i2cclk);
 539         s = NULL;
 540         clk_max = NSEC_PER_SEC / RATE_MIN(setup->speed_freq);
 541         clk_min = NSEC_PER_SEC / setup->speed_freq;
 542
 543         /*
 544          * Among Prescaler possibilities discovered above figures out SCL Low
 545          * and High Period. Provided:
 546          * - SCL Low Period has to be higher than SCL Clock Low Period
 547          *   defined by I2C Specification. I2C Clock has to be lower than
 548          *   (SCL Low Period - Analog/Digital filters) / 4.
 549          * - SCL High Period has to be lower than SCL Clock High Period
 550          *   defined by I2C Specification
 551          * - I2C Clock has to be lower than SCL High Period
 552          */
 553         list_for_each_entry(v, &solutions, node) {
 554                 u32 prescaler = (v->presc + 1) * i2cclk;
 555
 556                 for (l = 0; l < STM32F7_SCLL_MAX; l++) {
 557                         u32 tscl_l = (l + 1) * prescaler + tsync;
 558
 559                         if ((tscl_l < specs->l_min) ||
 560                             (i2cclk >=
 561                              ((tscl_l - af_delay_min - dnf_delay) / 4))) {
 562                                 continue;
 563                         }
 564
 565                         for (h = 0; h < STM32F7_SCLH_MAX; h++) {
 566                                 u32 tscl_h = (h + 1) * prescaler + tsync;
 567                                 u32 tscl = tscl_l + tscl_h +
 568                                         setup->rise_time + setup->fall_time;
 569
 570                                 if ((tscl >= clk_min) && (tscl <= clk_max) &&
 571                                     (tscl_h >= specs->h_min) &&
 572                                     (i2cclk < tscl_h)) {
 573                                         int clk_error = tscl - i2cbus;
 574
 575                                         if (clk_error < 0)
 576                                                 clk_error = -clk_error;
 577
 578                                         if (clk_error < clk_error_prev) {
 579                                                 clk_error_prev = clk_error;
 580                                                 v->scll = l;
 581                                                 v->sclh = h;
 582                                                 s = v;
 583                                         }
 584                                 }
 585                         }
 586                 }
 587         }
 588
 589         if (!s) {
 590                 dev_err(i2c_dev->dev, "no solution at all\n");
 591                 ret = -EPERM;
 592                 goto exit;
 593         }
 594
 595         output->presc = s->presc;
 596         output->scldel = s->scldel;
 597         output->sdadel = s->sdadel;
 598         output->scll = s->scll;
 599         output->sclh = s->sclh;
 600
 601         dev_dbg(i2c_dev->dev,
 602                 "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
 603                 output->presc,
 604                 output->scldel, output->sdadel,
 605                 output->scll, output->sclh);
 606
 607 exit:
 608         /* Release list and memory */
 609         list_for_each_entry_safe(v, _v, &solutions, node) {
 610                 list_del(&v->node);
 611                 kfree(v);
 612         }
 613
 614         return ret;
 615 }
 616
 617 static u32 stm32f7_get_lower_rate(u32 rate)
 618 {
 619         int i = ARRAY_SIZE(stm32f7_i2c_specs);
 620
 621         while (--i)
 622                 if (stm32f7_i2c_specs[i].rate < rate)
 623                         break;
 624
 625         return stm32f7_i2c_specs[i].rate;
 626 }
 627
 628 static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev,
 629                                     struct stm32f7_i2c_setup *setup)
 630 {
 631         struct i2c_timings timings, *t = &timings;
 632         int ret = 0;
 633
 634         t->bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
 635         t->scl_rise_ns = i2c_dev->setup.rise_time;
 636         t->scl_fall_ns = i2c_dev->setup.fall_time;
 637
 638         i2c_parse_fw_timings(i2c_dev->dev, t, false);
 639
 640         if (t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) {
 641                 dev_err(i2c_dev->dev, "Invalid bus speed (%i>%i)\n",
 642                         t->bus_freq_hz, I2C_MAX_FAST_MODE_PLUS_FREQ);
 643                 return -EINVAL;
 644         }
 645
 646         setup->speed_freq = t->bus_freq_hz;
 647         i2c_dev->setup.rise_time = t->scl_rise_ns;
 648         i2c_dev->setup.fall_time = t->scl_fall_ns;
 649         i2c_dev->dnf_dt = t->digital_filter_width_ns;
 650         setup->clock_src = clk_get_rate(i2c_dev->clk);
 651
 652         if (!setup->clock_src) {
 653                 dev_err(i2c_dev->dev, "clock rate is 0\n");
 654                 return -EINVAL;
 655         }
 656
 657         if (!of_property_read_bool(i2c_dev->dev->of_node, "i2c-digital-filter"))
 658                 i2c_dev->dnf_dt = STM32F7_I2C_DNF_DEFAULT;
 659
 660         do {
 661                 ret = stm32f7_i2c_compute_timing(i2c_dev, setup,
 662                                                  &i2c_dev->timing);
 663                 if (ret) {
 664                         dev_err(i2c_dev->dev,
 665                                 "failed to compute I2C timings.\n");
 666                         if (setup->speed_freq <= I2C_MAX_STANDARD_MODE_FREQ)
 667                                 break;
 668                         setup->speed_freq =
 669                                 stm32f7_get_lower_rate(setup->speed_freq);
 670                         dev_warn(i2c_dev->dev,
 671                                  "downgrade I2C Speed Freq to (%i)\n",
 672                                  setup->speed_freq);
 673                 }
 674         } while (ret);
 675
 676         if (ret) {
 677                 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n");
 678                 return ret;
 679         }
 680
 681         i2c_dev->analog_filter = of_property_read_bool(i2c_dev->dev->of_node,
 682                                                        "i2c-analog-filter");
 683
 684         dev_dbg(i2c_dev->dev, "I2C Speed(%i), Clk Source(%i)\n",
 685                 setup->speed_freq, setup->clock_src);
 686         dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n",
 687                 setup->rise_time, setup->fall_time);
 688         dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n",
 689                 (i2c_dev->analog_filter ? "On" : "Off"), i2c_dev->dnf);
 690
 691         i2c_dev->bus_rate = setup->speed_freq;
 692
 693         return 0;
 694 }
 695
 696 static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev)
 697 {
 698         void __iomem *base = i2c_dev->base;
 699         u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN;
 700
 701         stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
 702 }
 703
 704 static void stm32f7_i2c_dma_callback(void *arg)
 705 {
 706         struct stm32f7_i2c_dev *i2c_dev = (struct stm32f7_i2c_dev *)arg;
 707         struct stm32_i2c_dma *dma = i2c_dev->dma;
 708         struct device *dev = dma->chan_using->device->dev;
 709
 710         stm32f7_i2c_disable_dma_req(i2c_dev);
 711         dma_unmap_single(dev, dma->dma_buf, dma->dma_len, dma->dma_data_dir);
 712         complete(&dma->dma_complete);
 713 }
 714
 715 static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev)
 716 {
 717         struct stm32f7_i2c_timings *t = &i2c_dev->timing;
 718         u32 timing = 0;
 719
 720         /* Timing settings */
 721         timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc);
 722         timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel);
 723         timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel);
 724         timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh);
 725         timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll);
 726         writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR);
 727
 728         /* Configure the Analog Filter */
 729         if (i2c_dev->analog_filter)
 730                 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
 731                                      STM32F7_I2C_CR1_ANFOFF);
 732         else
 733                 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
 734                                      STM32F7_I2C_CR1_ANFOFF);
 735
 736         /* Program the Digital Filter */
 737         stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
 738                              STM32F7_I2C_CR1_DNF_MASK);
 739         stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
 740                              STM32F7_I2C_CR1_DNF(i2c_dev->dnf));
 741
 742         stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
 743                              STM32F7_I2C_CR1_PE);
 744 }
 745
 746 static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev)
 747 {
 748         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 749         void __iomem *base = i2c_dev->base;
 750
 751         if (f7_msg->count) {
 752                 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR);
 753                 f7_msg->count--;
 754         }
 755 }
 756
 757 static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev)
 758 {
 759         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 760         void __iomem *base = i2c_dev->base;
 761
 762         if (f7_msg->count) {
 763                 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR);
 764                 f7_msg->count--;
 765         } else {
 766                 /* Flush RX buffer has no data is expected */
 767                 readb_relaxed(base + STM32F7_I2C_RXDR);
 768         }
 769 }
 770
 771 static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev)
 772 {
 773         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 774         u32 cr2;
 775
 776         if (i2c_dev->use_dma)
 777                 f7_msg->count -= STM32F7_I2C_MAX_LEN;
 778
 779         cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
 780
 781         cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK;
 782         if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
 783                 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
 784         } else {
 785                 cr2 &= ~STM32F7_I2C_CR2_RELOAD;
 786                 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
 787         }
 788
 789         writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
 790 }
 791
 792 static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev)
 793 {
 794         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 795         u32 cr2;
 796         u8 *val;
 797
 798         /*
 799          * For I2C_SMBUS_BLOCK_DATA && I2C_SMBUS_BLOCK_PROC_CALL, the first
 800          * data received inform us how many data will follow.
 801          */
 802         stm32f7_i2c_read_rx_data(i2c_dev);
 803
 804         /*
 805          * Update NBYTES with the value read to continue the transfer
 806          */
 807         val = f7_msg->buf - sizeof(u8);
 808         f7_msg->count = *val;
 809         cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
 810         cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
 811         cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
 812         writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
 813 }
 814
 815 static int stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap)
 816 {
 817         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
 818
 819         dev_info(i2c_dev->dev, "Trying to recover bus\n");
 820
 821         stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
 822                              STM32F7_I2C_CR1_PE);
 823
 824         stm32f7_i2c_hw_config(i2c_dev);
 825
 826         return 0;
 827 }
 828
 829 static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev)
 830 {
 831         u32 status;
 832         int ret;
 833
 834         ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR,
 835                                          status,
 836                                          !(status & STM32F7_I2C_ISR_BUSY),
 837                                          10, 1000);
 838         if (!ret)
 839                 return 0;
 840
 841         dev_info(i2c_dev->dev, "bus busy\n");
 842
 843         ret = stm32f7_i2c_release_bus(&i2c_dev->adap);
 844         if (ret) {
 845                 dev_err(i2c_dev->dev, "Failed to recover the bus (%d)\n", ret);
 846                 return ret;
 847         }
 848
 849         return -EBUSY;
 850 }
 851
 852 static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
 853                                  struct i2c_msg *msg)
 854 {
 855         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 856         void __iomem *base = i2c_dev->base;
 857         u32 cr1, cr2;
 858         int ret;
 859
 860         f7_msg->addr = msg->addr;
 861         f7_msg->buf = msg->buf;
 862         f7_msg->count = msg->len;
 863         f7_msg->result = 0;
 864         f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1);
 865
 866         reinit_completion(&i2c_dev->complete);
 867
 868         cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
 869         cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
 870
 871         /* Set transfer direction */
 872         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 873         if (msg->flags & I2C_M_RD)
 874                 cr2 |= STM32F7_I2C_CR2_RD_WRN;
 875
 876         /* Set slave address */
 877         cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10);
 878         if (msg->flags & I2C_M_TEN) {
 879                 cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK;
 880                 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr);
 881                 cr2 |= STM32F7_I2C_CR2_ADD10;
 882         } else {
 883                 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK;
 884                 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
 885         }
 886
 887         /* Set nb bytes to transfer and reload if needed */
 888         cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
 889         if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
 890                 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
 891                 cr2 |= STM32F7_I2C_CR2_RELOAD;
 892         } else {
 893                 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
 894         }
 895
 896         /* Enable NACK, STOP, error and transfer complete interrupts */
 897         cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
 898                 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
 899
 900         /* Clear DMA req and TX/RX interrupt */
 901         cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
 902                         STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
 903
 904         /* Configure DMA or enable RX/TX interrupt */
 905         i2c_dev->use_dma = false;
 906         if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
 907                 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
 908                                               msg->flags & I2C_M_RD,
 909                                               f7_msg->count, f7_msg->buf,
 910                                               stm32f7_i2c_dma_callback,
 911                                               i2c_dev);
 912                 if (!ret)
 913                         i2c_dev->use_dma = true;
 914                 else
 915                         dev_warn(i2c_dev->dev, "can't use DMA\n");
 916         }
 917
 918         if (!i2c_dev->use_dma) {
 919                 if (msg->flags & I2C_M_RD)
 920                         cr1 |= STM32F7_I2C_CR1_RXIE;
 921                 else
 922                         cr1 |= STM32F7_I2C_CR1_TXIE;
 923         } else {
 924                 if (msg->flags & I2C_M_RD)
 925                         cr1 |= STM32F7_I2C_CR1_RXDMAEN;
 926                 else
 927                         cr1 |= STM32F7_I2C_CR1_TXDMAEN;
 928         }
 929
 930         /* Configure Start/Repeated Start */
 931         cr2 |= STM32F7_I2C_CR2_START;
 932
 933         i2c_dev->master_mode = true;
 934
 935         /* Write configurations registers */
 936         writel_relaxed(cr1, base + STM32F7_I2C_CR1);
 937         writel_relaxed(cr2, base + STM32F7_I2C_CR2);
 938 }
 939
 940 static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
 941                                       unsigned short flags, u8 command,
 942                                       union i2c_smbus_data *data)
 943 {
 944         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 945         struct device *dev = i2c_dev->dev;
 946         void __iomem *base = i2c_dev->base;
 947         u32 cr1, cr2;
 948         int i, ret;
 949
 950         f7_msg->result = 0;
 951         reinit_completion(&i2c_dev->complete);
 952
 953         cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
 954         cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
 955
 956         /* Set transfer direction */
 957         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 958         if (f7_msg->read_write)
 959                 cr2 |= STM32F7_I2C_CR2_RD_WRN;
 960
 961         /* Set slave address */
 962         cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK);
 963         cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
 964
 965         f7_msg->smbus_buf[0] = command;
 966         switch (f7_msg->size) {
 967         case I2C_SMBUS_QUICK:
 968                 f7_msg->stop = true;
 969                 f7_msg->count = 0;
 970                 break;
 971         case I2C_SMBUS_BYTE:
 972                 f7_msg->stop = true;
 973                 f7_msg->count = 1;
 974                 break;
 975         case I2C_SMBUS_BYTE_DATA:
 976                 if (f7_msg->read_write) {
 977                         f7_msg->stop = false;
 978                         f7_msg->count = 1;
 979                         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 980                 } else {
 981                         f7_msg->stop = true;
 982                         f7_msg->count = 2;
 983                         f7_msg->smbus_buf[1] = data->byte;
 984                 }
 985                 break;
 986         case I2C_SMBUS_WORD_DATA:
 987                 if (f7_msg->read_write) {
 988                         f7_msg->stop = false;
 989                         f7_msg->count = 1;
 990                         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 991                 } else {
 992                         f7_msg->stop = true;
 993                         f7_msg->count = 3;
 994                         f7_msg->smbus_buf[1] = data->word & 0xff;
 995                         f7_msg->smbus_buf[2] = data->word >> 8;
 996                 }
 997                 break;
 998         case I2C_SMBUS_BLOCK_DATA:
 999                 if (f7_msg->read_write) {
1000                         f7_msg->stop = false;
1001                         f7_msg->count = 1;
1002                         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1003                 } else {
1004                         f7_msg->stop = true;
1005                         if (data->block[0] > I2C_SMBUS_BLOCK_MAX ||
1006                             !data->block[0]) {
1007                                 dev_err(dev, "Invalid block write size %d\n",
1008                                         data->block[0]);
1009                                 return -EINVAL;
1010                         }
1011                         f7_msg->count = data->block[0] + 2;
1012                         for (i = 1; i < f7_msg->count; i++)
1013                                 f7_msg->smbus_buf[i] = data->block[i - 1];
1014                 }
1015                 break;
1016         case I2C_SMBUS_PROC_CALL:
1017                 f7_msg->stop = false;
1018                 f7_msg->count = 3;
1019                 f7_msg->smbus_buf[1] = data->word & 0xff;
1020                 f7_msg->smbus_buf[2] = data->word >> 8;
1021                 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1022                 f7_msg->read_write = I2C_SMBUS_READ;
1023                 break;
1024         case I2C_SMBUS_BLOCK_PROC_CALL:
1025                 f7_msg->stop = false;
1026                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) {
1027                         dev_err(dev, "Invalid block write size %d\n",
1028                                 data->block[0]);
1029                         return -EINVAL;
1030                 }
1031                 f7_msg->count = data->block[0] + 2;
1032                 for (i = 1; i < f7_msg->count; i++)
1033                         f7_msg->smbus_buf[i] = data->block[i - 1];
1034                 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1035                 f7_msg->read_write = I2C_SMBUS_READ;
1036                 break;
1037         case I2C_SMBUS_I2C_BLOCK_DATA:
1038                 /* Rely on emulated i2c transfer (through master_xfer) */
1039                 return -EOPNOTSUPP;
1040         default:
1041                 dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size);
1042                 return -EOPNOTSUPP;
1043         }
1044
1045         f7_msg->buf = f7_msg->smbus_buf;
1046
1047         /* Configure PEC */
1048         if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) {
1049                 cr1 |= STM32F7_I2C_CR1_PECEN;
1050                 cr2 |= STM32F7_I2C_CR2_PECBYTE;
1051                 if (!f7_msg->read_write)
1052                         f7_msg->count++;
1053         } else {
1054                 cr1 &= ~STM32F7_I2C_CR1_PECEN;
1055                 cr2 &= ~STM32F7_I2C_CR2_PECBYTE;
1056         }
1057
1058         /* Set number of bytes to be transferred */
1059         cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
1060         cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1061
1062         /* Enable NACK, STOP, error and transfer complete interrupts */
1063         cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
1064                 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
1065
1066         /* Clear DMA req and TX/RX interrupt */
1067         cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1068                         STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1069
1070         /* Configure DMA or enable RX/TX interrupt */
1071         i2c_dev->use_dma = false;
1072         if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
1073                 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1074                                               cr2 & STM32F7_I2C_CR2_RD_WRN,
1075                                               f7_msg->count, f7_msg->buf,
1076                                               stm32f7_i2c_dma_callback,
1077                                               i2c_dev);
1078                 if (!ret)
1079                         i2c_dev->use_dma = true;
1080                 else
1081                         dev_warn(i2c_dev->dev, "can't use DMA\n");
1082         }
1083
1084         if (!i2c_dev->use_dma) {
1085                 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1086                         cr1 |= STM32F7_I2C_CR1_RXIE;
1087                 else
1088                         cr1 |= STM32F7_I2C_CR1_TXIE;
1089         } else {
1090                 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1091                         cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1092                 else
1093                         cr1 |= STM32F7_I2C_CR1_TXDMAEN;
1094         }
1095
1096         /* Set Start bit */
1097         cr2 |= STM32F7_I2C_CR2_START;
1098
1099         i2c_dev->master_mode = true;
1100
1101         /* Write configurations registers */
1102         writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1103         writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1104
1105         return 0;
1106 }
1107
1108 static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev)
1109 {
1110         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1111         void __iomem *base = i2c_dev->base;
1112         u32 cr1, cr2;
1113         int ret;
1114
1115         cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
1116         cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
1117
1118         /* Set transfer direction */
1119         cr2 |= STM32F7_I2C_CR2_RD_WRN;
1120
1121         switch (f7_msg->size) {
1122         case I2C_SMBUS_BYTE_DATA:
1123                 f7_msg->count = 1;
1124                 break;
1125         case I2C_SMBUS_WORD_DATA:
1126         case I2C_SMBUS_PROC_CALL:
1127                 f7_msg->count = 2;
1128                 break;
1129         case I2C_SMBUS_BLOCK_DATA:
1130         case I2C_SMBUS_BLOCK_PROC_CALL:
1131                 f7_msg->count = 1;
1132                 cr2 |= STM32F7_I2C_CR2_RELOAD;
1133                 break;
1134         }
1135
1136         f7_msg->buf = f7_msg->smbus_buf;
1137         f7_msg->stop = true;
1138
1139         /* Add one byte for PEC if needed */
1140         if (cr1 & STM32F7_I2C_CR1_PECEN)
1141                 f7_msg->count++;
1142
1143         /* Set number of bytes to be transferred */
1144         cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK);
1145         cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1146
1147         /*
1148          * Configure RX/TX interrupt:
1149          */
1150         cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE);
1151         cr1 |= STM32F7_I2C_CR1_RXIE;
1152
1153         /*
1154          * Configure DMA or enable RX/TX interrupt:
1155          * For I2C_SMBUS_BLOCK_DATA and I2C_SMBUS_BLOCK_PROC_CALL we don't use
1156          * dma as we don't know in advance how many data will be received
1157          */
1158         cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1159                  STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1160
1161         i2c_dev->use_dma = false;
1162         if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN &&
1163             f7_msg->size != I2C_SMBUS_BLOCK_DATA &&
1164             f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) {
1165                 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1166                                               cr2 & STM32F7_I2C_CR2_RD_WRN,
1167                                               f7_msg->count, f7_msg->buf,
1168                                               stm32f7_i2c_dma_callback,
1169                                               i2c_dev);
1170
1171                 if (!ret)
1172                         i2c_dev->use_dma = true;
1173                 else
1174                         dev_warn(i2c_dev->dev, "can't use DMA\n");
1175         }
1176
1177         if (!i2c_dev->use_dma)
1178                 cr1 |= STM32F7_I2C_CR1_RXIE;
1179         else
1180                 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1181
1182         /* Configure Repeated Start */
1183         cr2 |= STM32F7_I2C_CR2_START;
1184
1185         /* Write configurations registers */
1186         writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1187         writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1188 }
1189
1190 static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev)
1191 {
1192         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1193         u8 count, internal_pec, received_pec;
1194
1195         internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR);
1196
1197         switch (f7_msg->size) {
1198         case I2C_SMBUS_BYTE:
1199         case I2C_SMBUS_BYTE_DATA:
1200                 received_pec = f7_msg->smbus_buf[1];
1201                 break;
1202         case I2C_SMBUS_WORD_DATA:
1203         case I2C_SMBUS_PROC_CALL:
1204                 received_pec = f7_msg->smbus_buf[2];
1205                 break;
1206         case I2C_SMBUS_BLOCK_DATA:
1207         case I2C_SMBUS_BLOCK_PROC_CALL:
1208                 count = f7_msg->smbus_buf[0];
1209                 received_pec = f7_msg->smbus_buf[count];
1210                 break;
1211         default:
1212                 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n");
1213                 return -EINVAL;
1214         }
1215
1216         if (internal_pec != received_pec) {
1217                 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n",
1218                         internal_pec, received_pec);
1219                 return -EBADMSG;
1220         }
1221
1222         return 0;
1223 }
1224
1225 static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode)
1226 {
1227         u32 addr;
1228
1229         if (!slave)
1230                 return false;
1231
1232         if (slave->flags & I2C_CLIENT_TEN) {
1233                 /*
1234                  * For 10-bit addr, addcode = 11110XY with
1235                  * X = Bit 9 of slave address
1236                  * Y = Bit 8 of slave address
1237                  */
1238                 addr = slave->addr >> 8;
1239                 addr |= 0x78;
1240                 if (addr == addcode)
1241                         return true;
1242         } else {
1243                 addr = slave->addr & 0x7f;
1244                 if (addr == addcode)
1245                         return true;
1246         }
1247
1248         return false;
1249 }
1250
1251 static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev)
1252 {
1253         struct i2c_client *slave = i2c_dev->slave_running;
1254         void __iomem *base = i2c_dev->base;
1255         u32 mask;
1256         u8 value = 0;
1257
1258         if (i2c_dev->slave_dir) {
1259                 /* Notify i2c slave that new read transfer is starting */
1260                 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
1261
1262                 /*
1263                  * Disable slave TX config in case of I2C combined message
1264                  * (I2C Write followed by I2C Read)
1265                  */
1266                 mask = STM32F7_I2C_CR2_RELOAD;
1267                 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask);
1268                 mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1269                        STM32F7_I2C_CR1_TCIE;
1270                 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1271
1272                 /* Enable TX empty, STOP, NACK interrupts */
1273                 mask =  STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1274                         STM32F7_I2C_CR1_TXIE;
1275                 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1276
1277                 /* Write 1st data byte */
1278                 writel_relaxed(value, base + STM32F7_I2C_TXDR);
1279         } else {
1280                 /* Notify i2c slave that new write transfer is starting */
1281                 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
1282
1283                 /* Set reload mode to be able to ACK/NACK each received byte */
1284                 mask = STM32F7_I2C_CR2_RELOAD;
1285                 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1286
1287                 /*
1288                  * Set STOP, NACK, RX empty and transfer complete interrupts.*
1289                  * Set Slave Byte Control to be able to ACK/NACK each data
1290                  * byte received
1291                  */
1292                 mask =  STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1293                         STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1294                         STM32F7_I2C_CR1_TCIE;
1295                 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1296         }
1297 }
1298
1299 static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev)
1300 {
1301         void __iomem *base = i2c_dev->base;
1302         u32 isr, addcode, dir, mask;
1303         int i;
1304
1305         isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1306         addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr);
1307         dir = isr & STM32F7_I2C_ISR_DIR;
1308
1309         for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1310                 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) {
1311                         i2c_dev->slave_running = i2c_dev->slave[i];
1312                         i2c_dev->slave_dir = dir;
1313
1314                         /* Start I2C slave processing */
1315                         stm32f7_i2c_slave_start(i2c_dev);
1316
1317                         /* Clear ADDR flag */
1318                         mask = STM32F7_I2C_ICR_ADDRCF;
1319                         writel_relaxed(mask, base + STM32F7_I2C_ICR);
1320                         break;
1321                 }
1322         }
1323 }
1324
1325 static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1326                                     struct i2c_client *slave, int *id)
1327 {
1328         int i;
1329
1330         for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1331                 if (i2c_dev->slave[i] == slave) {
1332                         *id = i;
1333                         return 0;
1334                 }
1335         }
1336
1337         dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr);
1338
1339         return -ENODEV;
1340 }
1341
1342 static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1343                                          struct i2c_client *slave, int *id)
1344 {
1345         struct device *dev = i2c_dev->dev;
1346         int i;
1347
1348         /*
1349          * slave[STM32F7_SLAVE_HOSTNOTIFY] support only SMBus Host address (0x8)
1350          * slave[STM32F7_SLAVE_7_10_BITS_ADDR] supports 7-bit and 10-bit slave address
1351          * slave[STM32F7_SLAVE_7_BITS_ADDR] supports 7-bit slave address only
1352          */
1353         if (i2c_dev->smbus_mode && (slave->addr == 0x08)) {
1354                 if (i2c_dev->slave[STM32F7_SLAVE_HOSTNOTIFY])
1355                         goto fail;
1356                 *id = STM32F7_SLAVE_HOSTNOTIFY;
1357                 return 0;
1358         }
1359
1360         for (i = STM32F7_I2C_MAX_SLAVE - 1; i > STM32F7_SLAVE_HOSTNOTIFY; i--) {
1361                 if ((i == STM32F7_SLAVE_7_BITS_ADDR) &&
1362                     (slave->flags & I2C_CLIENT_TEN))
1363                         continue;
1364                 if (!i2c_dev->slave[i]) {
1365                         *id = i;
1366                         return 0;
1367                 }
1368         }
1369
1370 fail:
1371         dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr);
1372
1373         return -EINVAL;
1374 }
1375
1376 static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev)
1377 {
1378         int i;
1379
1380         for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1381                 if (i2c_dev->slave[i])
1382                         return true;
1383         }
1384
1385         return false;
1386 }
1387
1388 static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev)
1389 {
1390         int i, busy;
1391
1392         busy = 0;
1393         for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1394                 if (i2c_dev->slave[i])
1395                         busy++;
1396         }
1397
1398         return i == busy;
1399 }
1400
1401 static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev)
1402 {
1403         void __iomem *base = i2c_dev->base;
1404         u32 cr2, status, mask;
1405         u8 val;
1406         int ret;
1407
1408         status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1409
1410         /* Slave transmitter mode */
1411         if (status & STM32F7_I2C_ISR_TXIS) {
1412                 i2c_slave_event(i2c_dev->slave_running,
1413                                 I2C_SLAVE_READ_PROCESSED,
1414                                 &val);
1415
1416                 /* Write data byte */
1417                 writel_relaxed(val, base + STM32F7_I2C_TXDR);
1418         }
1419
1420         /* Transfer Complete Reload for Slave receiver mode */
1421         if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) {
1422                 /*
1423                  * Read data byte then set NBYTES to receive next byte or NACK
1424                  * the current received byte
1425                  */
1426                 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR);
1427                 ret = i2c_slave_event(i2c_dev->slave_running,
1428                                       I2C_SLAVE_WRITE_RECEIVED,
1429                                       &val);
1430                 if (!ret) {
1431                         cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
1432                         cr2 |= STM32F7_I2C_CR2_NBYTES(1);
1433                         writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
1434                 } else {
1435                         mask = STM32F7_I2C_CR2_NACK;
1436                         stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1437                 }
1438         }
1439
1440         /* NACK received */
1441         if (status & STM32F7_I2C_ISR_NACKF) {
1442                 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1443                 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1444         }
1445
1446         /* STOP received */
1447         if (status & STM32F7_I2C_ISR_STOPF) {
1448                 /* Disable interrupts */
1449                 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK);
1450
1451                 if (i2c_dev->slave_dir) {
1452                         /*
1453                          * Flush TX buffer in order to not used the byte in
1454                          * TXDR for the next transfer
1455                          */
1456                         mask = STM32F7_I2C_ISR_TXE;
1457                         stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask);
1458                 }
1459
1460                 /* Clear STOP flag */
1461                 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1462
1463                 /* Notify i2c slave that a STOP flag has been detected */
1464                 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val);
1465
1466                 i2c_dev->slave_running = NULL;
1467         }
1468
1469         /* Address match received */
1470         if (status & STM32F7_I2C_ISR_ADDR)
1471                 stm32f7_i2c_slave_addr(i2c_dev);
1472
1473         return IRQ_HANDLED;
1474 }
1475
1476 static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
1477 {
1478         struct stm32f7_i2c_dev *i2c_dev = data;
1479         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1480         void __iomem *base = i2c_dev->base;
1481         u32 status, mask;
1482         int ret = IRQ_HANDLED;
1483
1484         /* Check if the interrupt if for a slave device */
1485         if (!i2c_dev->master_mode) {
1486                 ret = stm32f7_i2c_slave_isr_event(i2c_dev);
1487                 return ret;
1488         }
1489
1490         status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1491
1492         /* Tx empty */
1493         if (status & STM32F7_I2C_ISR_TXIS)
1494                 stm32f7_i2c_write_tx_data(i2c_dev);
1495
1496         /* RX not empty */
1497         if (status & STM32F7_I2C_ISR_RXNE)
1498                 stm32f7_i2c_read_rx_data(i2c_dev);
1499
1500         /* NACK received */
1501         if (status & STM32F7_I2C_ISR_NACKF) {
1502                 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK (addr %x)\n",
1503                         __func__, f7_msg->addr);
1504                 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1505                 f7_msg->result = -ENXIO;
1506         }
1507
1508         /* STOP detection flag */
1509         if (status & STM32F7_I2C_ISR_STOPF) {
1510                 /* Disable interrupts */
1511                 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1512                         mask = STM32F7_I2C_XFER_IRQ_MASK;
1513                 else
1514                         mask = STM32F7_I2C_ALL_IRQ_MASK;
1515                 stm32f7_i2c_disable_irq(i2c_dev, mask);
1516
1517                 /* Clear STOP flag */
1518                 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1519
1520                 if (i2c_dev->use_dma) {
1521                         ret = IRQ_WAKE_THREAD;
1522                 } else {
1523                         i2c_dev->master_mode = false;
1524                         complete(&i2c_dev->complete);
1525                 }
1526         }
1527
1528         /* Transfer complete */
1529         if (status & STM32F7_I2C_ISR_TC) {
1530                 if (f7_msg->stop) {
1531                         mask = STM32F7_I2C_CR2_STOP;
1532                         stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1533                 } else if (i2c_dev->use_dma) {
1534                         ret = IRQ_WAKE_THREAD;
1535                 } else if (f7_msg->smbus) {
1536                         stm32f7_i2c_smbus_rep_start(i2c_dev);
1537                 } else {
1538                         i2c_dev->msg_id++;
1539                         i2c_dev->msg++;
1540                         stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1541                 }
1542         }
1543
1544         if (status & STM32F7_I2C_ISR_TCR) {
1545                 if (f7_msg->smbus)
1546                         stm32f7_i2c_smbus_reload(i2c_dev);
1547                 else
1548                         stm32f7_i2c_reload(i2c_dev);
1549         }
1550
1551         return ret;
1552 }
1553
1554 static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data)
1555 {
1556         struct stm32f7_i2c_dev *i2c_dev = data;
1557         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1558         struct stm32_i2c_dma *dma = i2c_dev->dma;
1559         u32 status;
1560         int ret;
1561
1562         /*
1563          * Wait for dma transfer completion before sending next message or
1564          * notity the end of xfer to the client
1565          */
1566         ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ);
1567         if (!ret) {
1568                 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__);
1569                 stm32f7_i2c_disable_dma_req(i2c_dev);
1570                 dmaengine_terminate_all(dma->chan_using);
1571                 f7_msg->result = -ETIMEDOUT;
1572         }
1573
1574         status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1575
1576         if (status & STM32F7_I2C_ISR_TC) {
1577                 if (f7_msg->smbus) {
1578                         stm32f7_i2c_smbus_rep_start(i2c_dev);
1579                 } else {
1580                         i2c_dev->msg_id++;
1581                         i2c_dev->msg++;
1582                         stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1583                 }
1584         } else {
1585                 i2c_dev->master_mode = false;
1586                 complete(&i2c_dev->complete);
1587         }
1588
1589         return IRQ_HANDLED;
1590 }
1591
1592 static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data)
1593 {
1594         struct stm32f7_i2c_dev *i2c_dev = data;
1595         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1596         void __iomem *base = i2c_dev->base;
1597         struct device *dev = i2c_dev->dev;
1598         struct stm32_i2c_dma *dma = i2c_dev->dma;
1599         u32 status;
1600
1601         status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1602
1603         /* Bus error */
1604         if (status & STM32F7_I2C_ISR_BERR) {
1605                 dev_err(dev, "<%s>: Bus error accessing addr 0x%x\n",
1606                         __func__, f7_msg->addr);
1607                 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR);
1608                 stm32f7_i2c_release_bus(&i2c_dev->adap);
1609                 f7_msg->result = -EIO;
1610         }
1611
1612         /* Arbitration loss */
1613         if (status & STM32F7_I2C_ISR_ARLO) {
1614                 dev_dbg(dev, "<%s>: Arbitration loss accessing addr 0x%x\n",
1615                         __func__, f7_msg->addr);
1616                 writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR);
1617                 f7_msg->result = -EAGAIN;
1618         }
1619
1620         if (status & STM32F7_I2C_ISR_PECERR) {
1621                 dev_err(dev, "<%s>: PEC error in reception accessing addr 0x%x\n",
1622                         __func__, f7_msg->addr);
1623                 writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR);
1624                 f7_msg->result = -EINVAL;
1625         }
1626
1627         if (!i2c_dev->slave_running) {
1628                 u32 mask;
1629                 /* Disable interrupts */
1630                 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1631                         mask = STM32F7_I2C_XFER_IRQ_MASK;
1632                 else
1633                         mask = STM32F7_I2C_ALL_IRQ_MASK;
1634                 stm32f7_i2c_disable_irq(i2c_dev, mask);
1635         }
1636
1637         /* Disable dma */
1638         if (i2c_dev->use_dma) {
1639                 stm32f7_i2c_disable_dma_req(i2c_dev);
1640                 dmaengine_terminate_all(dma->chan_using);
1641         }
1642
1643         i2c_dev->master_mode = false;
1644         complete(&i2c_dev->complete);
1645
1646         return IRQ_HANDLED;
1647 }
1648
1649 static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap,
1650                             struct i2c_msg msgs[], int num)
1651 {
1652         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
1653         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1654         struct stm32_i2c_dma *dma = i2c_dev->dma;
1655         unsigned long time_left;
1656         int ret;
1657
1658         i2c_dev->msg = msgs;
1659         i2c_dev->msg_num = num;
1660         i2c_dev->msg_id = 0;
1661         f7_msg->smbus = false;
1662
1663         ret = pm_runtime_get_sync(i2c_dev->dev);
1664         if (ret < 0)
1665                 return ret;
1666
1667         ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1668         if (ret)
1669                 goto pm_free;
1670
1671         stm32f7_i2c_xfer_msg(i2c_dev, msgs);
1672
1673         time_left = wait_for_completion_timeout(&i2c_dev->complete,
1674                                                 i2c_dev->adap.timeout);
1675         ret = f7_msg->result;
1676
1677         if (!time_left) {
1678                 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n",
1679                         i2c_dev->msg->addr);
1680                 if (i2c_dev->use_dma)
1681                         dmaengine_terminate_all(dma->chan_using);
1682                 ret = -ETIMEDOUT;
1683         }
1684
1685 pm_free:
1686         pm_runtime_mark_last_busy(i2c_dev->dev);
1687         pm_runtime_put_autosuspend(i2c_dev->dev);
1688
1689         return (ret < 0) ? ret : num;
1690 }
1691
1692 static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
1693                                   unsigned short flags, char read_write,
1694                                   u8 command, int size,
1695                                   union i2c_smbus_data *data)
1696 {
1697         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter);
1698         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1699         struct stm32_i2c_dma *dma = i2c_dev->dma;
1700         struct device *dev = i2c_dev->dev;
1701         unsigned long timeout;
1702         int i, ret;
1703
1704         f7_msg->addr = addr;
1705         f7_msg->size = size;
1706         f7_msg->read_write = read_write;
1707         f7_msg->smbus = true;
1708
1709         ret = pm_runtime_get_sync(dev);
1710         if (ret < 0)
1711                 return ret;
1712
1713         ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1714         if (ret)
1715                 goto pm_free;
1716
1717         ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data);
1718         if (ret)
1719                 goto pm_free;
1720
1721         timeout = wait_for_completion_timeout(&i2c_dev->complete,
1722                                               i2c_dev->adap.timeout);
1723         ret = f7_msg->result;
1724         if (ret)
1725                 goto pm_free;
1726
1727         if (!timeout) {
1728                 dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr);
1729                 if (i2c_dev->use_dma)
1730                         dmaengine_terminate_all(dma->chan_using);
1731                 ret = -ETIMEDOUT;
1732                 goto pm_free;
1733         }
1734
1735         /* Check PEC */
1736         if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) {
1737                 ret = stm32f7_i2c_smbus_check_pec(i2c_dev);
1738                 if (ret)
1739                         goto pm_free;
1740         }
1741
1742         if (read_write && size != I2C_SMBUS_QUICK) {
1743                 switch (size) {
1744                 case I2C_SMBUS_BYTE:
1745                 case I2C_SMBUS_BYTE_DATA:
1746                         data->byte = f7_msg->smbus_buf[0];
1747                 break;
1748                 case I2C_SMBUS_WORD_DATA:
1749                 case I2C_SMBUS_PROC_CALL:
1750                         data->word = f7_msg->smbus_buf[0] |
1751                                 (f7_msg->smbus_buf[1] << 8);
1752                 break;
1753                 case I2C_SMBUS_BLOCK_DATA:
1754                 case I2C_SMBUS_BLOCK_PROC_CALL:
1755                 for (i = 0; i <= f7_msg->smbus_buf[0]; i++)
1756                         data->block[i] = f7_msg->smbus_buf[i];
1757                 break;
1758                 default:
1759                         dev_err(dev, "Unsupported smbus transaction\n");
1760                         ret = -EINVAL;
1761                 }
1762         }
1763
1764 pm_free:
1765         pm_runtime_mark_last_busy(dev);
1766         pm_runtime_put_autosuspend(dev);
1767         return ret;
1768 }
1769
1770 static void stm32f7_i2c_enable_wakeup(struct stm32f7_i2c_dev *i2c_dev,
1771                                       bool enable)
1772 {
1773         void __iomem *base = i2c_dev->base;
1774         u32 mask = STM32F7_I2C_CR1_WUPEN;
1775
1776         if (!i2c_dev->wakeup_src)
1777                 return;
1778
1779         if (enable) {
1780                 device_set_wakeup_enable(i2c_dev->dev, true);
1781                 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1782         } else {
1783                 device_set_wakeup_enable(i2c_dev->dev, false);
1784                 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1785         }
1786 }
1787
1788 static int stm32f7_i2c_reg_slave(struct i2c_client *slave)
1789 {
1790         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1791         void __iomem *base = i2c_dev->base;
1792         struct device *dev = i2c_dev->dev;
1793         u32 oar1, oar2, mask;
1794         int id, ret;
1795
1796         if (slave->flags & I2C_CLIENT_PEC) {
1797                 dev_err(dev, "SMBus PEC not supported in slave mode\n");
1798                 return -EINVAL;
1799         }
1800
1801         if (stm32f7_i2c_is_slave_busy(i2c_dev)) {
1802                 dev_err(dev, "Too much slave registered\n");
1803                 return -EBUSY;
1804         }
1805
1806         ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id);
1807         if (ret)
1808                 return ret;
1809
1810         ret = pm_runtime_get_sync(dev);
1811         if (ret < 0)
1812                 return ret;
1813
1814         if (!stm32f7_i2c_is_slave_registered(i2c_dev))
1815                 stm32f7_i2c_enable_wakeup(i2c_dev, true);
1816
1817         switch (id) {
1818         case 0:
1819                 /* Slave SMBus Host */
1820                 i2c_dev->slave[id] = slave;
1821                 break;
1822
1823         case 1:
1824                 /* Configure Own Address 1 */
1825                 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
1826                 oar1 &= ~STM32F7_I2C_OAR1_MASK;
1827                 if (slave->flags & I2C_CLIENT_TEN) {
1828                         oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr);
1829                         oar1 |= STM32F7_I2C_OAR1_OA1MODE;
1830                 } else {
1831                         oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr);
1832                 }
1833                 oar1 |= STM32F7_I2C_OAR1_OA1EN;
1834                 i2c_dev->slave[id] = slave;
1835                 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1);
1836                 break;
1837
1838         case 2:
1839                 /* Configure Own Address 2 */
1840                 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
1841                 oar2 &= ~STM32F7_I2C_OAR2_MASK;
1842                 if (slave->flags & I2C_CLIENT_TEN) {
1843                         ret = -EOPNOTSUPP;
1844                         goto pm_free;
1845                 }
1846
1847                 oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr);
1848                 oar2 |= STM32F7_I2C_OAR2_OA2EN;
1849                 i2c_dev->slave[id] = slave;
1850                 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2);
1851                 break;
1852
1853         default:
1854                 dev_err(dev, "I2C slave id not supported\n");
1855                 ret = -ENODEV;
1856                 goto pm_free;
1857         }
1858
1859         /* Enable ACK */
1860         stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK);
1861
1862         /* Enable Address match interrupt, error interrupt and enable I2C  */
1863         mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE |
1864                 STM32F7_I2C_CR1_PE;
1865         stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1866
1867         ret = 0;
1868 pm_free:
1869         if (!stm32f7_i2c_is_slave_registered(i2c_dev))
1870                 stm32f7_i2c_enable_wakeup(i2c_dev, false);
1871
1872         pm_runtime_mark_last_busy(dev);
1873         pm_runtime_put_autosuspend(dev);
1874
1875         return ret;
1876 }
1877
1878 static int stm32f7_i2c_unreg_slave(struct i2c_client *slave)
1879 {
1880         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1881         void __iomem *base = i2c_dev->base;
1882         u32 mask;
1883         int id, ret;
1884
1885         ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id);
1886         if (ret)
1887                 return ret;
1888
1889         WARN_ON(!i2c_dev->slave[id]);
1890
1891         ret = pm_runtime_get_sync(i2c_dev->dev);
1892         if (ret < 0)
1893                 return ret;
1894
1895         if (id == 1) {
1896                 mask = STM32F7_I2C_OAR1_OA1EN;
1897                 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask);
1898         } else if (id == 2) {
1899                 mask = STM32F7_I2C_OAR2_OA2EN;
1900                 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask);
1901         }
1902
1903         i2c_dev->slave[id] = NULL;
1904
1905         if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
1906                 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
1907                 stm32f7_i2c_enable_wakeup(i2c_dev, false);
1908         }
1909
1910         pm_runtime_mark_last_busy(i2c_dev->dev);
1911         pm_runtime_put_autosuspend(i2c_dev->dev);
1912
1913         return 0;
1914 }
1915
1916 static int stm32f7_i2c_write_fm_plus_bits(struct stm32f7_i2c_dev *i2c_dev,
1917                                           bool enable)
1918 {
1919         int ret;
1920
1921         if (i2c_dev->bus_rate <= I2C_MAX_FAST_MODE_FREQ ||
1922             IS_ERR_OR_NULL(i2c_dev->regmap))
1923                 /* Optional */
1924                 return 0;
1925
1926         if (i2c_dev->fmp_sreg == i2c_dev->fmp_creg)
1927                 ret = regmap_update_bits(i2c_dev->regmap,
1928                                          i2c_dev->fmp_sreg,
1929                                          i2c_dev->fmp_mask,
1930                                          enable ? i2c_dev->fmp_mask : 0);
1931         else
1932                 ret = regmap_write(i2c_dev->regmap,
1933                                    enable ? i2c_dev->fmp_sreg :
1934                                             i2c_dev->fmp_creg,
1935                                    i2c_dev->fmp_mask);
1936
1937         return ret;
1938 }
1939
1940 static int stm32f7_i2c_setup_fm_plus_bits(struct platform_device *pdev,
1941                                           struct stm32f7_i2c_dev *i2c_dev)
1942 {
1943         struct device_node *np = pdev->dev.of_node;
1944         int ret;
1945
1946         i2c_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg-fmp");
1947         if (IS_ERR(i2c_dev->regmap))
1948                 /* Optional */
1949                 return 0;
1950
1951         ret = of_property_read_u32_index(np, "st,syscfg-fmp", 1,
1952                                          &i2c_dev->fmp_sreg);
1953         if (ret)
1954                 return ret;
1955
1956         i2c_dev->fmp_creg = i2c_dev->fmp_sreg +
1957                                i2c_dev->setup.fmp_clr_offset;
1958
1959         return of_property_read_u32_index(np, "st,syscfg-fmp", 2,
1960                                           &i2c_dev->fmp_mask);
1961 }
1962
1963 static int stm32f7_i2c_enable_smbus_host(struct stm32f7_i2c_dev *i2c_dev)
1964 {
1965         struct i2c_adapter *adap = &i2c_dev->adap;
1966         void __iomem *base = i2c_dev->base;
1967         struct i2c_client *client;
1968
1969         client = i2c_new_slave_host_notify_device(adap);
1970         if (IS_ERR(client))
1971                 return PTR_ERR(client);
1972
1973         i2c_dev->host_notify_client = client;
1974
1975         /* Enable SMBus Host address */
1976         stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_SMBHEN);
1977
1978         return 0;
1979 }
1980
1981 static void stm32f7_i2c_disable_smbus_host(struct stm32f7_i2c_dev *i2c_dev)
1982 {
1983         void __iomem *base = i2c_dev->base;
1984
1985         if (i2c_dev->host_notify_client) {
1986                 /* Disable SMBus Host address */
1987                 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1,
1988                                      STM32F7_I2C_CR1_SMBHEN);
1989                 i2c_free_slave_host_notify_device(i2c_dev->host_notify_client);
1990         }
1991 }
1992
1993 static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
1994 {
1995         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1996
1997         u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE |
1998                    I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
1999                    I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
2000                    I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
2001                    I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC |
2002                    I2C_FUNC_SMBUS_I2C_BLOCK;
2003
2004         if (i2c_dev->smbus_mode)
2005                 func |= I2C_FUNC_SMBUS_HOST_NOTIFY;
2006
2007         return func;
2008 }
2009
2010 static const struct i2c_algorithm stm32f7_i2c_algo = {
2011         .master_xfer = stm32f7_i2c_xfer,
2012         .smbus_xfer = stm32f7_i2c_smbus_xfer,
2013         .functionality = stm32f7_i2c_func,
2014         .reg_slave = stm32f7_i2c_reg_slave,
2015         .unreg_slave = stm32f7_i2c_unreg_slave,
2016 };
2017
2018 static int stm32f7_i2c_probe(struct platform_device *pdev)
2019 {
2020         struct stm32f7_i2c_dev *i2c_dev;
2021         const struct stm32f7_i2c_setup *setup;
2022         struct resource *res;
2023         struct i2c_adapter *adap;
2024         struct reset_control *rst;
2025         dma_addr_t phy_addr;
2026         int irq_error, irq_event, ret;
2027
2028         i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
2029         if (!i2c_dev)
2030                 return -ENOMEM;
2031
2032         i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2033         if (IS_ERR(i2c_dev->base))
2034                 return PTR_ERR(i2c_dev->base);
2035         phy_addr = (dma_addr_t)res->start;
2036
2037         irq_event = platform_get_irq(pdev, 0);
2038         if (irq_event <= 0)
2039                 return irq_event ? : -ENOENT;
2040
2041         irq_error = platform_get_irq(pdev, 1);
2042         if (irq_error <= 0)
2043                 return irq_error ? : -ENOENT;
2044
2045         i2c_dev->wakeup_src = of_property_read_bool(pdev->dev.of_node,
2046                                                     "wakeup-source");
2047
2048         i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
2049         if (IS_ERR(i2c_dev->clk))
2050                 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_dev->clk),
2051                                      "Failed to get controller clock\n");
2052
2053         ret = clk_prepare_enable(i2c_dev->clk);
2054         if (ret) {
2055                 dev_err(&pdev->dev, "Failed to prepare_enable clock\n");
2056                 return ret;
2057         }
2058
2059         rst = devm_reset_control_get(&pdev->dev, NULL);
2060         if (IS_ERR(rst)) {
2061                 ret = dev_err_probe(&pdev->dev, PTR_ERR(rst),
2062                                     "Error: Missing reset ctrl\n");
2063                 goto clk_free;
2064         }
2065         reset_control_assert(rst);
2066         udelay(2);
2067         reset_control_deassert(rst);
2068
2069         i2c_dev->dev = &pdev->dev;
2070
2071         ret = devm_request_threaded_irq(&pdev->dev, irq_event,
2072                                         stm32f7_i2c_isr_event,
2073                                         stm32f7_i2c_isr_event_thread,
2074                                         IRQF_ONESHOT,
2075                                         pdev->name, i2c_dev);
2076         if (ret) {
2077                 dev_err(&pdev->dev, "Failed to request irq event %i\n",
2078                         irq_event);
2079                 goto clk_free;
2080         }
2081
2082         ret = devm_request_irq(&pdev->dev, irq_error, stm32f7_i2c_isr_error, 0,
2083                                pdev->name, i2c_dev);
2084         if (ret) {
2085                 dev_err(&pdev->dev, "Failed to request irq error %i\n",
2086                         irq_error);
2087                 goto clk_free;
2088         }
2089
2090         setup = of_device_get_match_data(&pdev->dev);
2091         if (!setup) {
2092                 dev_err(&pdev->dev, "Can't get device data\n");
2093                 ret = -ENODEV;
2094                 goto clk_free;
2095         }
2096         i2c_dev->setup = *setup;
2097
2098         ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup);
2099         if (ret)
2100                 goto clk_free;
2101
2102         /* Setup Fast mode plus if necessary */
2103         if (i2c_dev->bus_rate > I2C_MAX_FAST_MODE_FREQ) {
2104                 ret = stm32f7_i2c_setup_fm_plus_bits(pdev, i2c_dev);
2105                 if (ret)
2106                         goto clk_free;
2107                 ret = stm32f7_i2c_write_fm_plus_bits(i2c_dev, true);
2108                 if (ret)
2109                         goto clk_free;
2110         }
2111
2112         adap = &i2c_dev->adap;
2113         i2c_set_adapdata(adap, i2c_dev);
2114         snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)",
2115                  &res->start);
2116         adap->owner = THIS_MODULE;
2117         adap->timeout = 2 * HZ;
2118         adap->retries = 3;
2119         adap->algo = &stm32f7_i2c_algo;
2120         adap->dev.parent = &pdev->dev;
2121         adap->dev.of_node = pdev->dev.of_node;
2122
2123         init_completion(&i2c_dev->complete);
2124
2125         /* Init DMA config if supported */
2126         i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr,
2127                                              STM32F7_I2C_TXDR,
2128                                              STM32F7_I2C_RXDR);
2129         if (IS_ERR(i2c_dev->dma)) {
2130                 ret = PTR_ERR(i2c_dev->dma);
2131                 /* DMA support is optional, only report other errors */
2132                 if (ret != -ENODEV)
2133                         goto fmp_clear;
2134                 dev_dbg(i2c_dev->dev, "No DMA option: fallback using interrupts\n");
2135                 i2c_dev->dma = NULL;
2136         }
2137
2138         if (i2c_dev->wakeup_src) {
2139                 device_set_wakeup_capable(i2c_dev->dev, true);
2140
2141                 ret = dev_pm_set_wake_irq(i2c_dev->dev, irq_event);
2142                 if (ret) {
2143                         dev_err(i2c_dev->dev, "Failed to set wake up irq\n");
2144                         goto clr_wakeup_capable;
2145                 }
2146         }
2147
2148         platform_set_drvdata(pdev, i2c_dev);
2149
2150         pm_runtime_set_autosuspend_delay(i2c_dev->dev,
2151                                          STM32F7_AUTOSUSPEND_DELAY);
2152         pm_runtime_use_autosuspend(i2c_dev->dev);
2153         pm_runtime_set_active(i2c_dev->dev);
2154         pm_runtime_enable(i2c_dev->dev);
2155
2156         pm_runtime_get_noresume(&pdev->dev);
2157
2158         stm32f7_i2c_hw_config(i2c_dev);
2159
2160         i2c_dev->smbus_mode = of_property_read_bool(pdev->dev.of_node, "smbus");
2161
2162         ret = i2c_add_adapter(adap);
2163         if (ret)
2164                 goto pm_disable;
2165
2166         if (i2c_dev->smbus_mode) {
2167                 ret = stm32f7_i2c_enable_smbus_host(i2c_dev);
2168                 if (ret) {
2169                         dev_err(i2c_dev->dev,
2170                                 "failed to enable SMBus Host-Notify protocol (%d)\n",
2171                                 ret);
2172                         goto i2c_adapter_remove;
2173                 }
2174         }
2175
2176         dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr);
2177
2178         pm_runtime_mark_last_busy(i2c_dev->dev);
2179         pm_runtime_put_autosuspend(i2c_dev->dev);
2180
2181         return 0;
2182
2183 i2c_adapter_remove:
2184         i2c_del_adapter(adap);
2185
2186 pm_disable:
2187         pm_runtime_put_noidle(i2c_dev->dev);
2188         pm_runtime_disable(i2c_dev->dev);
2189         pm_runtime_set_suspended(i2c_dev->dev);
2190         pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2191
2192         if (i2c_dev->wakeup_src)
2193                 dev_pm_clear_wake_irq(i2c_dev->dev);
2194
2195 clr_wakeup_capable:
2196         if (i2c_dev->wakeup_src)
2197                 device_set_wakeup_capable(i2c_dev->dev, false);
2198
2199         if (i2c_dev->dma) {
2200                 stm32_i2c_dma_free(i2c_dev->dma);
2201                 i2c_dev->dma = NULL;
2202         }
2203
2204 fmp_clear:
2205         stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2206
2207 clk_free:
2208         clk_disable_unprepare(i2c_dev->clk);
2209
2210         return ret;
2211 }
2212
2213 static int stm32f7_i2c_remove(struct platform_device *pdev)
2214 {
2215         struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
2216
2217         stm32f7_i2c_disable_smbus_host(i2c_dev);
2218
2219         i2c_del_adapter(&i2c_dev->adap);
2220         pm_runtime_get_sync(i2c_dev->dev);
2221
2222         if (i2c_dev->wakeup_src) {
2223                 dev_pm_clear_wake_irq(i2c_dev->dev);
2224                 /*
2225                  * enforce that wakeup is disabled and that the device
2226                  * is marked as non wakeup capable
2227                  */
2228                 device_init_wakeup(i2c_dev->dev, false);
2229         }
2230
2231         pm_runtime_put_noidle(i2c_dev->dev);
2232         pm_runtime_disable(i2c_dev->dev);
2233         pm_runtime_set_suspended(i2c_dev->dev);
2234         pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2235
2236         if (i2c_dev->dma) {
2237                 stm32_i2c_dma_free(i2c_dev->dma);
2238                 i2c_dev->dma = NULL;
2239         }
2240
2241         stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2242
2243         clk_disable_unprepare(i2c_dev->clk);
2244
2245         return 0;
2246 }
2247
2248 static int __maybe_unused stm32f7_i2c_runtime_suspend(struct device *dev)
2249 {
2250         struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2251
2252         if (!stm32f7_i2c_is_slave_registered(i2c_dev))
2253                 clk_disable_unprepare(i2c_dev->clk);
2254
2255         return 0;
2256 }
2257
2258 static int __maybe_unused stm32f7_i2c_runtime_resume(struct device *dev)
2259 {
2260         struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2261         int ret;
2262
2263         if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
2264                 ret = clk_prepare_enable(i2c_dev->clk);
2265                 if (ret) {
2266                         dev_err(dev, "failed to prepare_enable clock\n");
2267                         return ret;
2268                 }
2269         }
2270
2271         return 0;
2272 }
2273
2274 static int __maybe_unused stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev *i2c_dev)
2275 {
2276         int ret;
2277         struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2278
2279         ret = pm_runtime_get_sync(i2c_dev->dev);
2280         if (ret < 0)
2281                 return ret;
2282
2283         backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2284         backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
2285         backup_regs->oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
2286         backup_regs->oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
2287         backup_regs->tmgr = readl_relaxed(i2c_dev->base + STM32F7_I2C_TIMINGR);
2288         stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2289
2290         pm_runtime_put_sync(i2c_dev->dev);
2291
2292         return ret;
2293 }
2294
2295 static int __maybe_unused stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev *i2c_dev)
2296 {
2297         u32 cr1;
2298         int ret;
2299         struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2300
2301         ret = pm_runtime_get_sync(i2c_dev->dev);
2302         if (ret < 0)
2303                 return ret;
2304
2305         cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2306         if (cr1 & STM32F7_I2C_CR1_PE)
2307                 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
2308                                      STM32F7_I2C_CR1_PE);
2309
2310         writel_relaxed(backup_regs->tmgr, i2c_dev->base + STM32F7_I2C_TIMINGR);
2311         writel_relaxed(backup_regs->cr1 & ~STM32F7_I2C_CR1_PE,
2312                        i2c_dev->base + STM32F7_I2C_CR1);
2313         if (backup_regs->cr1 & STM32F7_I2C_CR1_PE)
2314                 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
2315                                      STM32F7_I2C_CR1_PE);
2316         writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2);
2317         writel_relaxed(backup_regs->oar1, i2c_dev->base + STM32F7_I2C_OAR1);
2318         writel_relaxed(backup_regs->oar2, i2c_dev->base + STM32F7_I2C_OAR2);
2319         stm32f7_i2c_write_fm_plus_bits(i2c_dev, true);
2320
2321         pm_runtime_put_sync(i2c_dev->dev);
2322
2323         return ret;
2324 }
2325
2326 static int __maybe_unused stm32f7_i2c_suspend(struct device *dev)
2327 {
2328         struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2329         int ret;
2330
2331         i2c_mark_adapter_suspended(&i2c_dev->adap);
2332
2333         if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) {
2334                 ret = stm32f7_i2c_regs_backup(i2c_dev);
2335                 if (ret < 0) {
2336                         i2c_mark_adapter_resumed(&i2c_dev->adap);
2337                         return ret;
2338                 }
2339
2340                 pinctrl_pm_select_sleep_state(dev);
2341                 pm_runtime_force_suspend(dev);
2342         }
2343
2344         return 0;
2345 }
2346
2347 static int __maybe_unused stm32f7_i2c_resume(struct device *dev)
2348 {
2349         struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2350         int ret;
2351
2352         if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) {
2353                 ret = pm_runtime_force_resume(dev);
2354                 if (ret < 0)
2355                         return ret;
2356                 pinctrl_pm_select_default_state(dev);
2357
2358                 ret = stm32f7_i2c_regs_restore(i2c_dev);
2359                 if (ret < 0)
2360                         return ret;
2361         }
2362
2363         i2c_mark_adapter_resumed(&i2c_dev->adap);
2364
2365         return 0;
2366 }
2367
2368 static const struct dev_pm_ops stm32f7_i2c_pm_ops = {
2369         SET_RUNTIME_PM_OPS(stm32f7_i2c_runtime_suspend,
2370                            stm32f7_i2c_runtime_resume, NULL)
2371         SET_SYSTEM_SLEEP_PM_OPS(stm32f7_i2c_suspend, stm32f7_i2c_resume)
2372 };
2373
2374 static const struct of_device_id stm32f7_i2c_match[] = {
2375         { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup},
2376         { .compatible = "st,stm32mp15-i2c", .data = &stm32mp15_setup},
2377         {},
2378 };
2379 MODULE_DEVICE_TABLE(of, stm32f7_i2c_match);
2380
2381 static struct platform_driver stm32f7_i2c_driver = {
2382         .driver = {
2383                 .name = "stm32f7-i2c",
2384                 .of_match_table = stm32f7_i2c_match,
2385                 .pm = &stm32f7_i2c_pm_ops,
2386         },
2387         .probe = stm32f7_i2c_probe,
2388         .remove = stm32f7_i2c_remove,
2389 };
2390
2391 module_platform_driver(stm32f7_i2c_driver);
2392
2393 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
2394 MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver");
2395 MODULE_LICENSE("GPL v2");