i2c: drivers: Use generic definitions for bus frequencies
[linux-2.6-microblaze.git] / drivers / i2c / busses / i2c-sprd.c
1 /*
2  * Copyright (C) 2017 Spreadtrum Communications Inc.
3  *
4  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5  */
6
7 #include <linux/clk.h>
8 #include <linux/delay.h>
9 #include <linux/err.h>
10 #include <linux/io.h>
11 #include <linux/i2c.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/of_device.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm_runtime.h>
20
21 #define I2C_CTL                 0x00
22 #define I2C_ADDR_CFG            0x04
23 #define I2C_COUNT               0x08
24 #define I2C_RX                  0x0c
25 #define I2C_TX                  0x10
26 #define I2C_STATUS              0x14
27 #define I2C_HSMODE_CFG          0x18
28 #define I2C_VERSION             0x1c
29 #define ADDR_DVD0               0x20
30 #define ADDR_DVD1               0x24
31 #define ADDR_STA0_DVD           0x28
32 #define ADDR_RST                0x2c
33
34 /* I2C_CTL */
35 #define STP_EN                  BIT(20)
36 #define FIFO_AF_LVL_MASK        GENMASK(19, 16)
37 #define FIFO_AF_LVL             16
38 #define FIFO_AE_LVL_MASK        GENMASK(15, 12)
39 #define FIFO_AE_LVL             12
40 #define I2C_DMA_EN              BIT(11)
41 #define FULL_INTEN              BIT(10)
42 #define EMPTY_INTEN             BIT(9)
43 #define I2C_DVD_OPT             BIT(8)
44 #define I2C_OUT_OPT             BIT(7)
45 #define I2C_TRIM_OPT            BIT(6)
46 #define I2C_HS_MODE             BIT(4)
47 #define I2C_MODE                BIT(3)
48 #define I2C_EN                  BIT(2)
49 #define I2C_INT_EN              BIT(1)
50 #define I2C_START               BIT(0)
51
52 /* I2C_STATUS */
53 #define SDA_IN                  BIT(21)
54 #define SCL_IN                  BIT(20)
55 #define FIFO_FULL               BIT(4)
56 #define FIFO_EMPTY              BIT(3)
57 #define I2C_INT                 BIT(2)
58 #define I2C_RX_ACK              BIT(1)
59 #define I2C_BUSY                BIT(0)
60
61 /* ADDR_RST */
62 #define I2C_RST                 BIT(0)
63
64 #define I2C_FIFO_DEEP           12
65 #define I2C_FIFO_FULL_THLD      15
66 #define I2C_FIFO_EMPTY_THLD     4
67 #define I2C_DATA_STEP           8
68 #define I2C_ADDR_DVD0_CALC(high, low)   \
69         ((((high) & GENMASK(15, 0)) << 16) | ((low) & GENMASK(15, 0)))
70 #define I2C_ADDR_DVD1_CALC(high, low)   \
71         (((high) & GENMASK(31, 16)) | (((low) & GENMASK(31, 16)) >> 16))
72
73 /* timeout (ms) for pm runtime autosuspend */
74 #define SPRD_I2C_PM_TIMEOUT     1000
75
76 /* SPRD i2c data structure */
77 struct sprd_i2c {
78         struct i2c_adapter adap;
79         struct device *dev;
80         void __iomem *base;
81         struct i2c_msg *msg;
82         struct clk *clk;
83         u32 src_clk;
84         u32 bus_freq;
85         struct completion complete;
86         u8 *buf;
87         u32 count;
88         int irq;
89         int err;
90 };
91
92 static void sprd_i2c_set_count(struct sprd_i2c *i2c_dev, u32 count)
93 {
94         writel(count, i2c_dev->base + I2C_COUNT);
95 }
96
97 static void sprd_i2c_send_stop(struct sprd_i2c *i2c_dev, int stop)
98 {
99         u32 tmp = readl(i2c_dev->base + I2C_CTL);
100
101         if (stop)
102                 writel(tmp & ~STP_EN, i2c_dev->base + I2C_CTL);
103         else
104                 writel(tmp | STP_EN, i2c_dev->base + I2C_CTL);
105 }
106
107 static void sprd_i2c_clear_start(struct sprd_i2c *i2c_dev)
108 {
109         u32 tmp = readl(i2c_dev->base + I2C_CTL);
110
111         writel(tmp & ~I2C_START, i2c_dev->base + I2C_CTL);
112 }
113
114 static void sprd_i2c_clear_ack(struct sprd_i2c *i2c_dev)
115 {
116         u32 tmp = readl(i2c_dev->base + I2C_STATUS);
117
118         writel(tmp & ~I2C_RX_ACK, i2c_dev->base + I2C_STATUS);
119 }
120
121 static void sprd_i2c_clear_irq(struct sprd_i2c *i2c_dev)
122 {
123         u32 tmp = readl(i2c_dev->base + I2C_STATUS);
124
125         writel(tmp & ~I2C_INT, i2c_dev->base + I2C_STATUS);
126 }
127
128 static void sprd_i2c_reset_fifo(struct sprd_i2c *i2c_dev)
129 {
130         writel(I2C_RST, i2c_dev->base + ADDR_RST);
131 }
132
133 static void sprd_i2c_set_devaddr(struct sprd_i2c *i2c_dev, struct i2c_msg *m)
134 {
135         writel(m->addr << 1, i2c_dev->base + I2C_ADDR_CFG);
136 }
137
138 static void sprd_i2c_write_bytes(struct sprd_i2c *i2c_dev, u8 *buf, u32 len)
139 {
140         u32 i;
141
142         for (i = 0; i < len; i++)
143                 writeb(buf[i], i2c_dev->base + I2C_TX);
144 }
145
146 static void sprd_i2c_read_bytes(struct sprd_i2c *i2c_dev, u8 *buf, u32 len)
147 {
148         u32 i;
149
150         for (i = 0; i < len; i++)
151                 buf[i] = readb(i2c_dev->base + I2C_RX);
152 }
153
154 static void sprd_i2c_set_full_thld(struct sprd_i2c *i2c_dev, u32 full_thld)
155 {
156         u32 tmp = readl(i2c_dev->base + I2C_CTL);
157
158         tmp &= ~FIFO_AF_LVL_MASK;
159         tmp |= full_thld << FIFO_AF_LVL;
160         writel(tmp, i2c_dev->base + I2C_CTL);
161 };
162
163 static void sprd_i2c_set_empty_thld(struct sprd_i2c *i2c_dev, u32 empty_thld)
164 {
165         u32 tmp = readl(i2c_dev->base + I2C_CTL);
166
167         tmp &= ~FIFO_AE_LVL_MASK;
168         tmp |= empty_thld << FIFO_AE_LVL;
169         writel(tmp, i2c_dev->base + I2C_CTL);
170 };
171
172 static void sprd_i2c_set_fifo_full_int(struct sprd_i2c *i2c_dev, int enable)
173 {
174         u32 tmp = readl(i2c_dev->base + I2C_CTL);
175
176         if (enable)
177                 tmp |= FULL_INTEN;
178         else
179                 tmp &= ~FULL_INTEN;
180
181         writel(tmp, i2c_dev->base + I2C_CTL);
182 };
183
184 static void sprd_i2c_set_fifo_empty_int(struct sprd_i2c *i2c_dev, int enable)
185 {
186         u32 tmp = readl(i2c_dev->base + I2C_CTL);
187
188         if (enable)
189                 tmp |= EMPTY_INTEN;
190         else
191                 tmp &= ~EMPTY_INTEN;
192
193         writel(tmp, i2c_dev->base + I2C_CTL);
194 };
195
196 static void sprd_i2c_opt_start(struct sprd_i2c *i2c_dev)
197 {
198         u32 tmp = readl(i2c_dev->base + I2C_CTL);
199
200         writel(tmp | I2C_START, i2c_dev->base + I2C_CTL);
201 }
202
203 static void sprd_i2c_opt_mode(struct sprd_i2c *i2c_dev, int rw)
204 {
205         u32 cmd = readl(i2c_dev->base + I2C_CTL) & ~I2C_MODE;
206
207         writel(cmd | rw << 3, i2c_dev->base + I2C_CTL);
208 }
209
210 static void sprd_i2c_data_transfer(struct sprd_i2c *i2c_dev)
211 {
212         u32 i2c_count = i2c_dev->count;
213         u32 need_tran = i2c_count <= I2C_FIFO_DEEP ? i2c_count : I2C_FIFO_DEEP;
214         struct i2c_msg *msg = i2c_dev->msg;
215
216         if (msg->flags & I2C_M_RD) {
217                 sprd_i2c_read_bytes(i2c_dev, i2c_dev->buf, I2C_FIFO_FULL_THLD);
218                 i2c_dev->count -= I2C_FIFO_FULL_THLD;
219                 i2c_dev->buf += I2C_FIFO_FULL_THLD;
220
221                 /*
222                  * If the read data count is larger than rx fifo full threshold,
223                  * we should enable the rx fifo full interrupt to read data
224                  * again.
225                  */
226                 if (i2c_dev->count >= I2C_FIFO_FULL_THLD)
227                         sprd_i2c_set_fifo_full_int(i2c_dev, 1);
228         } else {
229                 sprd_i2c_write_bytes(i2c_dev, i2c_dev->buf, need_tran);
230                 i2c_dev->buf += need_tran;
231                 i2c_dev->count -= need_tran;
232
233                 /*
234                  * If the write data count is arger than tx fifo depth which
235                  * means we can not write all data in one time, then we should
236                  * enable the tx fifo empty interrupt to write again.
237                  */
238                 if (i2c_count > I2C_FIFO_DEEP)
239                         sprd_i2c_set_fifo_empty_int(i2c_dev, 1);
240         }
241 }
242
243 static int sprd_i2c_handle_msg(struct i2c_adapter *i2c_adap,
244                                struct i2c_msg *msg, bool is_last_msg)
245 {
246         struct sprd_i2c *i2c_dev = i2c_adap->algo_data;
247
248         i2c_dev->msg = msg;
249         i2c_dev->buf = msg->buf;
250         i2c_dev->count = msg->len;
251
252         reinit_completion(&i2c_dev->complete);
253         sprd_i2c_reset_fifo(i2c_dev);
254         sprd_i2c_set_devaddr(i2c_dev, msg);
255         sprd_i2c_set_count(i2c_dev, msg->len);
256
257         if (msg->flags & I2C_M_RD) {
258                 sprd_i2c_opt_mode(i2c_dev, 1);
259                 sprd_i2c_send_stop(i2c_dev, 1);
260         } else {
261                 sprd_i2c_opt_mode(i2c_dev, 0);
262                 sprd_i2c_send_stop(i2c_dev, !!is_last_msg);
263         }
264
265         /*
266          * We should enable rx fifo full interrupt to get data when receiving
267          * full data.
268          */
269         if (msg->flags & I2C_M_RD)
270                 sprd_i2c_set_fifo_full_int(i2c_dev, 1);
271         else
272                 sprd_i2c_data_transfer(i2c_dev);
273
274         sprd_i2c_opt_start(i2c_dev);
275
276         wait_for_completion(&i2c_dev->complete);
277
278         return i2c_dev->err;
279 }
280
281 static int sprd_i2c_master_xfer(struct i2c_adapter *i2c_adap,
282                                 struct i2c_msg *msgs, int num)
283 {
284         struct sprd_i2c *i2c_dev = i2c_adap->algo_data;
285         int im, ret;
286
287         ret = pm_runtime_get_sync(i2c_dev->dev);
288         if (ret < 0)
289                 return ret;
290
291         for (im = 0; im < num - 1; im++) {
292                 ret = sprd_i2c_handle_msg(i2c_adap, &msgs[im], 0);
293                 if (ret)
294                         goto err_msg;
295         }
296
297         ret = sprd_i2c_handle_msg(i2c_adap, &msgs[im++], 1);
298
299 err_msg:
300         pm_runtime_mark_last_busy(i2c_dev->dev);
301         pm_runtime_put_autosuspend(i2c_dev->dev);
302
303         return ret < 0 ? ret : im;
304 }
305
306 static u32 sprd_i2c_func(struct i2c_adapter *adap)
307 {
308         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
309 }
310
311 static const struct i2c_algorithm sprd_i2c_algo = {
312         .master_xfer = sprd_i2c_master_xfer,
313         .functionality = sprd_i2c_func,
314 };
315
316 static void sprd_i2c_set_clk(struct sprd_i2c *i2c_dev, u32 freq)
317 {
318         u32 apb_clk = i2c_dev->src_clk;
319         /*
320          * From I2C databook, the prescale calculation formula:
321          * prescale = freq_i2c / (4 * freq_scl) - 1;
322          */
323         u32 i2c_dvd = apb_clk / (4 * freq) - 1;
324         /*
325          * From I2C databook, the high period of SCL clock is recommended as
326          * 40% (2/5), and the low period of SCL clock is recommended as 60%
327          * (3/5), then the formula should be:
328          * high = (prescale * 2 * 2) / 5
329          * low = (prescale * 2 * 3) / 5
330          */
331         u32 high = ((i2c_dvd << 1) * 2) / 5;
332         u32 low = ((i2c_dvd << 1) * 3) / 5;
333         u32 div0 = I2C_ADDR_DVD0_CALC(high, low);
334         u32 div1 = I2C_ADDR_DVD1_CALC(high, low);
335
336         writel(div0, i2c_dev->base + ADDR_DVD0);
337         writel(div1, i2c_dev->base + ADDR_DVD1);
338
339         /* Start hold timing = hold time(us) * source clock */
340         if (freq == I2C_MAX_FAST_MODE_FREQ)
341                 writel((6 * apb_clk) / 10000000, i2c_dev->base + ADDR_STA0_DVD);
342         else if (freq == I2C_MAX_STANDARD_MODE_FREQ)
343                 writel((4 * apb_clk) / 1000000, i2c_dev->base + ADDR_STA0_DVD);
344 }
345
346 static void sprd_i2c_enable(struct sprd_i2c *i2c_dev)
347 {
348         u32 tmp = I2C_DVD_OPT;
349
350         writel(tmp, i2c_dev->base + I2C_CTL);
351
352         sprd_i2c_set_full_thld(i2c_dev, I2C_FIFO_FULL_THLD);
353         sprd_i2c_set_empty_thld(i2c_dev, I2C_FIFO_EMPTY_THLD);
354
355         sprd_i2c_set_clk(i2c_dev, i2c_dev->bus_freq);
356         sprd_i2c_reset_fifo(i2c_dev);
357         sprd_i2c_clear_irq(i2c_dev);
358
359         tmp = readl(i2c_dev->base + I2C_CTL);
360         writel(tmp | I2C_EN | I2C_INT_EN, i2c_dev->base + I2C_CTL);
361 }
362
363 static irqreturn_t sprd_i2c_isr_thread(int irq, void *dev_id)
364 {
365         struct sprd_i2c *i2c_dev = dev_id;
366         struct i2c_msg *msg = i2c_dev->msg;
367         bool ack = !(readl(i2c_dev->base + I2C_STATUS) & I2C_RX_ACK);
368         u32 i2c_tran;
369
370         if (msg->flags & I2C_M_RD)
371                 i2c_tran = i2c_dev->count >= I2C_FIFO_FULL_THLD;
372         else
373                 i2c_tran = i2c_dev->count;
374
375         /*
376          * If we got one ACK from slave when writing data, and we did not
377          * finish this transmission (i2c_tran is not zero), then we should
378          * continue to write data.
379          *
380          * For reading data, ack is always true, if i2c_tran is not 0 which
381          * means we still need to contine to read data from slave.
382          */
383         if (i2c_tran && ack) {
384                 sprd_i2c_data_transfer(i2c_dev);
385                 return IRQ_HANDLED;
386         }
387
388         i2c_dev->err = 0;
389
390         /*
391          * If we did not get one ACK from slave when writing data, we should
392          * return -EIO to notify users.
393          */
394         if (!ack)
395                 i2c_dev->err = -EIO;
396         else if (msg->flags & I2C_M_RD && i2c_dev->count)
397                 sprd_i2c_read_bytes(i2c_dev, i2c_dev->buf, i2c_dev->count);
398
399         /* Transmission is done and clear ack and start operation */
400         sprd_i2c_clear_ack(i2c_dev);
401         sprd_i2c_clear_start(i2c_dev);
402         complete(&i2c_dev->complete);
403
404         return IRQ_HANDLED;
405 }
406
407 static irqreturn_t sprd_i2c_isr(int irq, void *dev_id)
408 {
409         struct sprd_i2c *i2c_dev = dev_id;
410         struct i2c_msg *msg = i2c_dev->msg;
411         bool ack = !(readl(i2c_dev->base + I2C_STATUS) & I2C_RX_ACK);
412         u32 i2c_tran;
413
414         if (msg->flags & I2C_M_RD)
415                 i2c_tran = i2c_dev->count >= I2C_FIFO_FULL_THLD;
416         else
417                 i2c_tran = i2c_dev->count;
418
419         /*
420          * If we did not get one ACK from slave when writing data, then we
421          * should finish this transmission since we got some errors.
422          *
423          * When writing data, if i2c_tran == 0 which means we have writen
424          * done all data, then we can finish this transmission.
425          *
426          * When reading data, if conut < rx fifo full threshold, which
427          * means we can read all data in one time, then we can finish this
428          * transmission too.
429          */
430         if (!i2c_tran || !ack) {
431                 sprd_i2c_clear_start(i2c_dev);
432                 sprd_i2c_clear_irq(i2c_dev);
433         }
434
435         sprd_i2c_set_fifo_empty_int(i2c_dev, 0);
436         sprd_i2c_set_fifo_full_int(i2c_dev, 0);
437
438         return IRQ_WAKE_THREAD;
439 }
440
441 static int sprd_i2c_clk_init(struct sprd_i2c *i2c_dev)
442 {
443         struct clk *clk_i2c, *clk_parent;
444
445         clk_i2c = devm_clk_get(i2c_dev->dev, "i2c");
446         if (IS_ERR(clk_i2c)) {
447                 dev_warn(i2c_dev->dev, "i2c%d can't get the i2c clock\n",
448                          i2c_dev->adap.nr);
449                 clk_i2c = NULL;
450         }
451
452         clk_parent = devm_clk_get(i2c_dev->dev, "source");
453         if (IS_ERR(clk_parent)) {
454                 dev_warn(i2c_dev->dev, "i2c%d can't get the source clock\n",
455                          i2c_dev->adap.nr);
456                 clk_parent = NULL;
457         }
458
459         if (clk_set_parent(clk_i2c, clk_parent))
460                 i2c_dev->src_clk = clk_get_rate(clk_i2c);
461         else
462                 i2c_dev->src_clk = 26000000;
463
464         dev_dbg(i2c_dev->dev, "i2c%d set source clock is %d\n",
465                 i2c_dev->adap.nr, i2c_dev->src_clk);
466
467         i2c_dev->clk = devm_clk_get(i2c_dev->dev, "enable");
468         if (IS_ERR(i2c_dev->clk)) {
469                 dev_err(i2c_dev->dev, "i2c%d can't get the enable clock\n",
470                         i2c_dev->adap.nr);
471                 return PTR_ERR(i2c_dev->clk);
472         }
473
474         return 0;
475 }
476
477 static int sprd_i2c_probe(struct platform_device *pdev)
478 {
479         struct device *dev = &pdev->dev;
480         struct sprd_i2c *i2c_dev;
481         u32 prop;
482         int ret;
483
484         pdev->id = of_alias_get_id(dev->of_node, "i2c");
485
486         i2c_dev = devm_kzalloc(dev, sizeof(struct sprd_i2c), GFP_KERNEL);
487         if (!i2c_dev)
488                 return -ENOMEM;
489
490         i2c_dev->base = devm_platform_ioremap_resource(pdev, 0);
491         if (IS_ERR(i2c_dev->base))
492                 return PTR_ERR(i2c_dev->base);
493
494         i2c_dev->irq = platform_get_irq(pdev, 0);
495         if (i2c_dev->irq < 0) {
496                 dev_err(&pdev->dev, "failed to get irq resource\n");
497                 return i2c_dev->irq;
498         }
499
500         i2c_set_adapdata(&i2c_dev->adap, i2c_dev);
501         init_completion(&i2c_dev->complete);
502         snprintf(i2c_dev->adap.name, sizeof(i2c_dev->adap.name),
503                  "%s", "sprd-i2c");
504
505         i2c_dev->bus_freq = I2C_MAX_STANDARD_MODE_FREQ;
506         i2c_dev->adap.owner = THIS_MODULE;
507         i2c_dev->dev = dev;
508         i2c_dev->adap.retries = 3;
509         i2c_dev->adap.algo = &sprd_i2c_algo;
510         i2c_dev->adap.algo_data = i2c_dev;
511         i2c_dev->adap.dev.parent = dev;
512         i2c_dev->adap.nr = pdev->id;
513         i2c_dev->adap.dev.of_node = dev->of_node;
514
515         if (!of_property_read_u32(dev->of_node, "clock-frequency", &prop))
516                 i2c_dev->bus_freq = prop;
517
518         /* We only support 100k and 400k now, otherwise will return error. */
519         if (i2c_dev->bus_freq != I2C_MAX_STANDARD_MODE_FREQ &&
520             i2c_dev->bus_freq != I2C_MAX_FAST_MODE_FREQ)
521                 return -EINVAL;
522
523         ret = sprd_i2c_clk_init(i2c_dev);
524         if (ret)
525                 return ret;
526
527         platform_set_drvdata(pdev, i2c_dev);
528
529         ret = clk_prepare_enable(i2c_dev->clk);
530         if (ret)
531                 return ret;
532
533         sprd_i2c_enable(i2c_dev);
534
535         pm_runtime_set_autosuspend_delay(i2c_dev->dev, SPRD_I2C_PM_TIMEOUT);
536         pm_runtime_use_autosuspend(i2c_dev->dev);
537         pm_runtime_set_active(i2c_dev->dev);
538         pm_runtime_enable(i2c_dev->dev);
539
540         ret = pm_runtime_get_sync(i2c_dev->dev);
541         if (ret < 0)
542                 goto err_rpm_put;
543
544         ret = devm_request_threaded_irq(dev, i2c_dev->irq,
545                 sprd_i2c_isr, sprd_i2c_isr_thread,
546                 IRQF_NO_SUSPEND | IRQF_ONESHOT,
547                 pdev->name, i2c_dev);
548         if (ret) {
549                 dev_err(&pdev->dev, "failed to request irq %d\n", i2c_dev->irq);
550                 goto err_rpm_put;
551         }
552
553         ret = i2c_add_numbered_adapter(&i2c_dev->adap);
554         if (ret) {
555                 dev_err(&pdev->dev, "add adapter failed\n");
556                 goto err_rpm_put;
557         }
558
559         pm_runtime_mark_last_busy(i2c_dev->dev);
560         pm_runtime_put_autosuspend(i2c_dev->dev);
561         return 0;
562
563 err_rpm_put:
564         pm_runtime_put_noidle(i2c_dev->dev);
565         pm_runtime_disable(i2c_dev->dev);
566         clk_disable_unprepare(i2c_dev->clk);
567         return ret;
568 }
569
570 static int sprd_i2c_remove(struct platform_device *pdev)
571 {
572         struct sprd_i2c *i2c_dev = platform_get_drvdata(pdev);
573         int ret;
574
575         ret = pm_runtime_get_sync(i2c_dev->dev);
576         if (ret < 0)
577                 return ret;
578
579         i2c_del_adapter(&i2c_dev->adap);
580         clk_disable_unprepare(i2c_dev->clk);
581
582         pm_runtime_put_noidle(i2c_dev->dev);
583         pm_runtime_disable(i2c_dev->dev);
584
585         return 0;
586 }
587
588 static int __maybe_unused sprd_i2c_suspend_noirq(struct device *dev)
589 {
590         struct sprd_i2c *i2c_dev = dev_get_drvdata(dev);
591
592         i2c_mark_adapter_suspended(&i2c_dev->adap);
593         return pm_runtime_force_suspend(dev);
594 }
595
596 static int __maybe_unused sprd_i2c_resume_noirq(struct device *dev)
597 {
598         struct sprd_i2c *i2c_dev = dev_get_drvdata(dev);
599
600         i2c_mark_adapter_resumed(&i2c_dev->adap);
601         return pm_runtime_force_resume(dev);
602 }
603
604 static int __maybe_unused sprd_i2c_runtime_suspend(struct device *dev)
605 {
606         struct sprd_i2c *i2c_dev = dev_get_drvdata(dev);
607
608         clk_disable_unprepare(i2c_dev->clk);
609
610         return 0;
611 }
612
613 static int __maybe_unused sprd_i2c_runtime_resume(struct device *dev)
614 {
615         struct sprd_i2c *i2c_dev = dev_get_drvdata(dev);
616         int ret;
617
618         ret = clk_prepare_enable(i2c_dev->clk);
619         if (ret)
620                 return ret;
621
622         sprd_i2c_enable(i2c_dev);
623
624         return 0;
625 }
626
627 static const struct dev_pm_ops sprd_i2c_pm_ops = {
628         SET_RUNTIME_PM_OPS(sprd_i2c_runtime_suspend,
629                            sprd_i2c_runtime_resume, NULL)
630
631         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sprd_i2c_suspend_noirq,
632                                       sprd_i2c_resume_noirq)
633 };
634
635 static const struct of_device_id sprd_i2c_of_match[] = {
636         { .compatible = "sprd,sc9860-i2c", },
637         {},
638 };
639
640 static struct platform_driver sprd_i2c_driver = {
641         .probe = sprd_i2c_probe,
642         .remove = sprd_i2c_remove,
643         .driver = {
644                    .name = "sprd-i2c",
645                    .of_match_table = sprd_i2c_of_match,
646                    .pm = &sprd_i2c_pm_ops,
647         },
648 };
649
650 module_platform_driver(sprd_i2c_driver);
651
652 MODULE_DESCRIPTION("Spreadtrum I2C master controller driver");
653 MODULE_LICENSE("GPL v2");