drivers/i2c/busses/i2c-sh_mobile.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SuperH Mobile I2C Controller
   4  *
   5  * Copyright (C) 2014 Wolfram Sang <wsa@sang-engineering.com>
   6  *
   7  * Copyright (C) 2008 Magnus Damm
   8  *
   9  * Portions of the code based on out-of-tree driver i2c-sh7343.c
  10  * Copyright (c) 2006 Carlos Munoz <carlos@kenati.com>
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/delay.h>
  15 #include <linux/dmaengine.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/err.h>
  18 #include <linux/i2c.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/io.h>
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/of_device.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/slab.h>
  28
  29 /* Transmit operation:                                                      */
  30 /*                                                                          */
  31 /* 0 byte transmit                                                          */
  32 /* BUS:     S     A8     ACK   P(*)                                         */
  33 /* IRQ:       DTE   WAIT                                                    */
  34 /* ICIC:                                                                    */
  35 /* ICCR: 0x94       0x90                                                    */
  36 /* ICDR:      A8                                                            */
  37 /*                                                                          */
  38 /* 1 byte transmit                                                          */
  39 /* BUS:     S     A8     ACK   D8(1)   ACK   P(*)                           */
  40 /* IRQ:       DTE   WAIT         WAIT                                       */
  41 /* ICIC:      -DTE                                                          */
  42 /* ICCR: 0x94                    0x90                                       */
  43 /* ICDR:      A8    D8(1)                                                   */
  44 /*                                                                          */
  45 /* 2 byte transmit                                                          */
  46 /* BUS:     S     A8     ACK   D8(1)   ACK   D8(2)   ACK   P(*)             */
  47 /* IRQ:       DTE   WAIT         WAIT          WAIT                         */
  48 /* ICIC:      -DTE                                                          */
  49 /* ICCR: 0x94                                  0x90                         */
  50 /* ICDR:      A8    D8(1)        D8(2)                                      */
  51 /*                                                                          */
  52 /* 3 bytes or more, +---------+ gets repeated                               */
  53 /*                                                                          */
  54 /*                                                                          */
  55 /* Receive operation:                                                       */
  56 /*                                                                          */
  57 /* 0 byte receive - not supported since slave may hold SDA low              */
  58 /*                                                                          */
  59 /* 1 byte receive       [TX] | [RX]                                         */
  60 /* BUS:     S     A8     ACK | D8(1)   ACK   P(*)                           */
  61 /* IRQ:       DTE   WAIT     |   WAIT     DTE                               */
  62 /* ICIC:      -DTE           |   +DTE                                       */
  63 /* ICCR: 0x94       0x81     |   0xc0                                       */
  64 /* ICDR:      A8             |            D8(1)                             */
  65 /*                                                                          */
  66 /* 2 byte receive        [TX]| [RX]                                         */
  67 /* BUS:     S     A8     ACK | D8(1)   ACK   D8(2)   ACK   P(*)             */
  68 /* IRQ:       DTE   WAIT     |   WAIT          WAIT     DTE                 */
  69 /* ICIC:      -DTE           |                 +DTE                         */
  70 /* ICCR: 0x94       0x81     |                 0xc0                         */
  71 /* ICDR:      A8             |                 D8(1)    D8(2)               */
  72 /*                                                                          */
  73 /* 3 byte receive       [TX] | [RX]                                     (*) */
  74 /* BUS:     S     A8     ACK | D8(1)   ACK   D8(2)   ACK   D8(3)   ACK    P */
  75 /* IRQ:       DTE   WAIT     |   WAIT          WAIT         WAIT      DTE   */
  76 /* ICIC:      -DTE           |                              +DTE            */
  77 /* ICCR: 0x94       0x81     |                              0xc0            */
  78 /* ICDR:      A8             |                 D8(1)        D8(2)     D8(3) */
  79 /*                                                                          */
  80 /* 4 bytes or more, this part is repeated    +---------+                    */
  81 /*                                                                          */
  82 /*                                                                          */
  83 /* Interrupt order and BUSY flag                                            */
  84 /*     ___                                                 _                */
  85 /* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/                 */
  86 /* SCL      \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/                   */
  87 /*                                                                          */
  88 /*        S   D7  D6  D5  D4  D3  D2  D1  D0              P(*)              */
  89 /*                                           ___                            */
  90 /* WAIT IRQ ________________________________/   \___________                */
  91 /* TACK IRQ ____________________________________/   \_______                */
  92 /* DTE  IRQ __________________________________________/   \_                */
  93 /* AL   IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX                */
  94 /*         _______________________________________________                  */
  95 /* BUSY __/                                               \_                */
  96 /*                                                                          */
  97 /* (*) The STOP condition is only sent by the master at the end of the last */
  98 /* I2C message or if the I2C_M_STOP flag is set. Similarly, the BUSY bit is */
  99 /* only cleared after the STOP condition, so, between messages we have to   */
 100 /* poll for the DTE bit.                                                    */
 101 /*                                                                          */
 102
 103 enum sh_mobile_i2c_op {
 104         OP_START = 0,
 105         OP_TX_FIRST,
 106         OP_TX,
 107         OP_TX_STOP,
 108         OP_TX_TO_RX,
 109         OP_RX,
 110         OP_RX_STOP,
 111         OP_RX_STOP_DATA,
 112 };
 113
 114 struct sh_mobile_i2c_data {
 115         struct device *dev;
 116         void __iomem *reg;
 117         struct i2c_adapter adap;
 118         unsigned long bus_speed;
 119         unsigned int clks_per_count;
 120         struct clk *clk;
 121         u_int8_t icic;
 122         u_int8_t flags;
 123         u_int16_t iccl;
 124         u_int16_t icch;
 125
 126         spinlock_t lock;
 127         wait_queue_head_t wait;
 128         struct i2c_msg *msg;
 129         int pos;
 130         int sr;
 131         bool send_stop;
 132         bool stop_after_dma;
 133
 134         struct resource *res;
 135         struct dma_chan *dma_tx;
 136         struct dma_chan *dma_rx;
 137         struct scatterlist sg;
 138         enum dma_data_direction dma_direction;
 139         u8 *dma_buf;
 140 };
 141
 142 struct sh_mobile_dt_config {
 143         int clks_per_count;
 144         int (*setup)(struct sh_mobile_i2c_data *pd);
 145 };
 146
 147 #define IIC_FLAG_HAS_ICIC67     (1 << 0)
 148
 149 #define STANDARD_MODE           100000
 150 #define FAST_MODE               400000
 151
 152 /* Register offsets */
 153 #define ICDR                    0x00
 154 #define ICCR                    0x04
 155 #define ICSR                    0x08
 156 #define ICIC                    0x0c
 157 #define ICCL                    0x10
 158 #define ICCH                    0x14
 159 #define ICSTART                 0x70
 160
 161 /* Register bits */
 162 #define ICCR_ICE                0x80
 163 #define ICCR_RACK               0x40
 164 #define ICCR_TRS                0x10
 165 #define ICCR_BBSY               0x04
 166 #define ICCR_SCP                0x01
 167
 168 #define ICSR_SCLM               0x80
 169 #define ICSR_SDAM               0x40
 170 #define SW_DONE                 0x20
 171 #define ICSR_BUSY               0x10
 172 #define ICSR_AL                 0x08
 173 #define ICSR_TACK               0x04
 174 #define ICSR_WAIT               0x02
 175 #define ICSR_DTE                0x01
 176
 177 #define ICIC_ICCLB8             0x80
 178 #define ICIC_ICCHB8             0x40
 179 #define ICIC_TDMAE              0x20
 180 #define ICIC_RDMAE              0x10
 181 #define ICIC_ALE                0x08
 182 #define ICIC_TACKE              0x04
 183 #define ICIC_WAITE              0x02
 184 #define ICIC_DTEE               0x01
 185
 186 #define ICSTART_ICSTART         0x10
 187
 188 static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data)
 189 {
 190         if (offs == ICIC)
 191                 data |= pd->icic;
 192
 193         iowrite8(data, pd->reg + offs);
 194 }
 195
 196 static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs)
 197 {
 198         return ioread8(pd->reg + offs);
 199 }
 200
 201 static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs,
 202                         unsigned char set, unsigned char clr)
 203 {
 204         iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr);
 205 }
 206
 207 static u32 sh_mobile_i2c_iccl(unsigned long count_khz, u32 tLOW, u32 tf)
 208 {
 209         /*
 210          * Conditional expression:
 211          *   ICCL >= COUNT_CLK * (tLOW + tf)
 212          *
 213          * SH-Mobile IIC hardware starts counting the LOW period of
 214          * the SCL signal (tLOW) as soon as it pulls the SCL line.
 215          * In order to meet the tLOW timing spec, we need to take into
 216          * account the fall time of SCL signal (tf).  Default tf value
 217          * should be 0.3 us, for safety.
 218          */
 219         return (((count_khz * (tLOW + tf)) + 5000) / 10000);
 220 }
 221
 222 static u32 sh_mobile_i2c_icch(unsigned long count_khz, u32 tHIGH, u32 tf)
 223 {
 224         /*
 225          * Conditional expression:
 226          *   ICCH >= COUNT_CLK * (tHIGH + tf)
 227          *
 228          * SH-Mobile IIC hardware is aware of SCL transition period 'tr',
 229          * and can ignore it.  SH-Mobile IIC controller starts counting
 230          * the HIGH period of the SCL signal (tHIGH) after the SCL input
 231          * voltage increases at VIH.
 232          *
 233          * Afterward it turned out calculating ICCH using only tHIGH spec
 234          * will result in violation of the tHD;STA timing spec.  We need
 235          * to take into account the fall time of SDA signal (tf) at START
 236          * condition, in order to meet both tHIGH and tHD;STA specs.
 237          */
 238         return (((count_khz * (tHIGH + tf)) + 5000) / 10000);
 239 }
 240
 241 static int sh_mobile_i2c_check_timing(struct sh_mobile_i2c_data *pd)
 242 {
 243         u16 max_val = pd->flags & IIC_FLAG_HAS_ICIC67 ? 0x1ff : 0xff;
 244
 245         if (pd->iccl > max_val || pd->icch > max_val) {
 246                 dev_err(pd->dev, "timing values out of range: L/H=0x%x/0x%x\n",
 247                         pd->iccl, pd->icch);
 248                 return -EINVAL;
 249         }
 250
 251         /* one more bit of ICCL in ICIC */
 252         if (pd->iccl & 0x100)
 253                 pd->icic |= ICIC_ICCLB8;
 254         else
 255                 pd->icic &= ~ICIC_ICCLB8;
 256
 257         /* one more bit of ICCH in ICIC */
 258         if (pd->icch & 0x100)
 259                 pd->icic |= ICIC_ICCHB8;
 260         else
 261                 pd->icic &= ~ICIC_ICCHB8;
 262
 263         dev_dbg(pd->dev, "timing values: L/H=0x%x/0x%x\n", pd->iccl, pd->icch);
 264         return 0;
 265 }
 266
 267 static int sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd)
 268 {
 269         unsigned long i2c_clk_khz;
 270         u32 tHIGH, tLOW, tf;
 271
 272         i2c_clk_khz = clk_get_rate(pd->clk) / 1000 / pd->clks_per_count;
 273
 274         if (pd->bus_speed == STANDARD_MODE) {
 275                 tLOW    = 47;   /* tLOW = 4.7 us */
 276                 tHIGH   = 40;   /* tHD;STA = tHIGH = 4.0 us */
 277                 tf      = 3;    /* tf = 0.3 us */
 278         } else if (pd->bus_speed == FAST_MODE) {
 279                 tLOW    = 13;   /* tLOW = 1.3 us */
 280                 tHIGH   = 6;    /* tHD;STA = tHIGH = 0.6 us */
 281                 tf      = 3;    /* tf = 0.3 us */
 282         } else {
 283                 dev_err(pd->dev, "unrecognized bus speed %lu Hz\n",
 284                         pd->bus_speed);
 285                 return -EINVAL;
 286         }
 287
 288         pd->iccl = sh_mobile_i2c_iccl(i2c_clk_khz, tLOW, tf);
 289         pd->icch = sh_mobile_i2c_icch(i2c_clk_khz, tHIGH, tf);
 290
 291         return sh_mobile_i2c_check_timing(pd);
 292 }
 293
 294 static int sh_mobile_i2c_v2_init(struct sh_mobile_i2c_data *pd)
 295 {
 296         unsigned long clks_per_cycle;
 297
 298         /* L = 5, H = 4, L + H = 9 */
 299         clks_per_cycle = clk_get_rate(pd->clk) / pd->bus_speed;
 300         pd->iccl = DIV_ROUND_UP(clks_per_cycle * 5 / 9 - 1, pd->clks_per_count);
 301         pd->icch = DIV_ROUND_UP(clks_per_cycle * 4 / 9 - 5, pd->clks_per_count);
 302
 303         return sh_mobile_i2c_check_timing(pd);
 304 }
 305
 306 static unsigned char i2c_op(struct sh_mobile_i2c_data *pd, enum sh_mobile_i2c_op op)
 307 {
 308         unsigned char ret = 0;
 309         unsigned long flags;
 310
 311         dev_dbg(pd->dev, "op %d\n", op);
 312
 313         spin_lock_irqsave(&pd->lock, flags);
 314
 315         switch (op) {
 316         case OP_START: /* issue start and trigger DTE interrupt */
 317                 iic_wr(pd, ICCR, ICCR_ICE | ICCR_TRS | ICCR_BBSY);
 318                 break;
 319         case OP_TX_FIRST: /* disable DTE interrupt and write client address */
 320                 iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
 321                 iic_wr(pd, ICDR, i2c_8bit_addr_from_msg(pd->msg));
 322                 break;
 323         case OP_TX: /* write data */
 324                 iic_wr(pd, ICDR, pd->msg->buf[pd->pos]);
 325                 break;
 326         case OP_TX_STOP: /* issue a stop (or rep_start) */
 327                 iic_wr(pd, ICCR, pd->send_stop ? ICCR_ICE | ICCR_TRS
 328                                                : ICCR_ICE | ICCR_TRS | ICCR_BBSY);
 329                 break;
 330         case OP_TX_TO_RX: /* select read mode */
 331                 iic_wr(pd, ICCR, ICCR_ICE | ICCR_SCP);
 332                 break;
 333         case OP_RX: /* just read data */
 334                 ret = iic_rd(pd, ICDR);
 335                 break;
 336         case OP_RX_STOP: /* enable DTE interrupt, issue stop */
 337                 iic_wr(pd, ICIC,
 338                        ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
 339                 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
 340                 break;
 341         case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
 342                 iic_wr(pd, ICIC,
 343                        ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
 344                 ret = iic_rd(pd, ICDR);
 345                 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
 346                 break;
 347         }
 348
 349         spin_unlock_irqrestore(&pd->lock, flags);
 350
 351         dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret);
 352         return ret;
 353 }
 354
 355 static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd)
 356 {
 357         if (pd->pos == pd->msg->len) {
 358                 i2c_op(pd, OP_TX_STOP);
 359                 return 1;
 360         }
 361
 362         if (pd->pos == -1)
 363                 i2c_op(pd, OP_TX_FIRST);
 364         else
 365                 i2c_op(pd, OP_TX);
 366
 367         pd->pos++;
 368         return 0;
 369 }
 370
 371 static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd)
 372 {
 373         unsigned char data;
 374         int real_pos;
 375
 376         do {
 377                 if (pd->pos == -1) {
 378                         i2c_op(pd, OP_TX_FIRST);
 379                         break;
 380                 }
 381
 382                 if (pd->pos == 0) {
 383                         i2c_op(pd, OP_TX_TO_RX);
 384                         break;
 385                 }
 386
 387                 real_pos = pd->pos - 2;
 388
 389                 if (pd->pos == pd->msg->len) {
 390                         if (pd->stop_after_dma) {
 391                                 /* Simulate PIO end condition after DMA transfer */
 392                                 i2c_op(pd, OP_RX_STOP);
 393                                 pd->pos++;
 394                                 break;
 395                         }
 396
 397                         if (real_pos < 0) {
 398                                 i2c_op(pd, OP_RX_STOP);
 399                                 break;
 400                         }
 401                         data = i2c_op(pd, OP_RX_STOP_DATA);
 402                 } else if (real_pos >= 0) {
 403                         data = i2c_op(pd, OP_RX);
 404                 }
 405
 406                 if (real_pos >= 0)
 407                         pd->msg->buf[real_pos] = data;
 408         } while (0);
 409
 410         pd->pos++;
 411         return pd->pos == (pd->msg->len + 2);
 412 }
 413
 414 static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
 415 {
 416         struct sh_mobile_i2c_data *pd = dev_id;
 417         unsigned char sr;
 418         int wakeup = 0;
 419
 420         sr = iic_rd(pd, ICSR);
 421         pd->sr |= sr; /* remember state */
 422
 423         dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr,
 424                (pd->msg->flags & I2C_M_RD) ? "read" : "write",
 425                pd->pos, pd->msg->len);
 426
 427         /* Kick off TxDMA after preface was done */
 428         if (pd->dma_direction == DMA_TO_DEVICE && pd->pos == 0)
 429                 iic_set_clr(pd, ICIC, ICIC_TDMAE, 0);
 430         else if (sr & (ICSR_AL | ICSR_TACK))
 431                 /* don't interrupt transaction - continue to issue stop */
 432                 iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK));
 433         else if (pd->msg->flags & I2C_M_RD)
 434                 wakeup = sh_mobile_i2c_isr_rx(pd);
 435         else
 436                 wakeup = sh_mobile_i2c_isr_tx(pd);
 437
 438         /* Kick off RxDMA after preface was done */
 439         if (pd->dma_direction == DMA_FROM_DEVICE && pd->pos == 1)
 440                 iic_set_clr(pd, ICIC, ICIC_RDMAE, 0);
 441
 442         if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */
 443                 iic_wr(pd, ICSR, sr & ~ICSR_WAIT);
 444
 445         if (wakeup) {
 446                 pd->sr |= SW_DONE;
 447                 wake_up(&pd->wait);
 448         }
 449
 450         /* defeat write posting to avoid spurious WAIT interrupts */
 451         iic_rd(pd, ICSR);
 452
 453         return IRQ_HANDLED;
 454 }
 455
 456 static void sh_mobile_i2c_dma_unmap(struct sh_mobile_i2c_data *pd)
 457 {
 458         struct dma_chan *chan = pd->dma_direction == DMA_FROM_DEVICE
 459                                 ? pd->dma_rx : pd->dma_tx;
 460
 461         dma_unmap_single(chan->device->dev, sg_dma_address(&pd->sg),
 462                          pd->msg->len, pd->dma_direction);
 463
 464         pd->dma_direction = DMA_NONE;
 465 }
 466
 467 static void sh_mobile_i2c_cleanup_dma(struct sh_mobile_i2c_data *pd)
 468 {
 469         if (pd->dma_direction == DMA_NONE)
 470                 return;
 471         else if (pd->dma_direction == DMA_FROM_DEVICE)
 472                 dmaengine_terminate_all(pd->dma_rx);
 473         else if (pd->dma_direction == DMA_TO_DEVICE)
 474                 dmaengine_terminate_all(pd->dma_tx);
 475
 476         sh_mobile_i2c_dma_unmap(pd);
 477 }
 478
 479 static void sh_mobile_i2c_dma_callback(void *data)
 480 {
 481         struct sh_mobile_i2c_data *pd = data;
 482
 483         sh_mobile_i2c_dma_unmap(pd);
 484         pd->pos = pd->msg->len;
 485         pd->stop_after_dma = true;
 486
 487         iic_set_clr(pd, ICIC, 0, ICIC_TDMAE | ICIC_RDMAE);
 488 }
 489
 490 static struct dma_chan *sh_mobile_i2c_request_dma_chan(struct device *dev,
 491                                 enum dma_transfer_direction dir, dma_addr_t port_addr)
 492 {
 493         struct dma_chan *chan;
 494         struct dma_slave_config cfg;
 495         char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx";
 496         int ret;
 497
 498         chan = dma_request_slave_channel_reason(dev, chan_name);
 499         if (IS_ERR(chan)) {
 500                 dev_dbg(dev, "request_channel failed for %s (%ld)\n", chan_name,
 501                         PTR_ERR(chan));
 502                 return chan;
 503         }
 504
 505         memset(&cfg, 0, sizeof(cfg));
 506         cfg.direction = dir;
 507         if (dir == DMA_MEM_TO_DEV) {
 508                 cfg.dst_addr = port_addr;
 509                 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 510         } else {
 511                 cfg.src_addr = port_addr;
 512                 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 513         }
 514
 515         ret = dmaengine_slave_config(chan, &cfg);
 516         if (ret) {
 517                 dev_dbg(dev, "slave_config failed for %s (%d)\n", chan_name, ret);
 518                 dma_release_channel(chan);
 519                 return ERR_PTR(ret);
 520         }
 521
 522         dev_dbg(dev, "got DMA channel for %s\n", chan_name);
 523         return chan;
 524 }
 525
 526 static void sh_mobile_i2c_xfer_dma(struct sh_mobile_i2c_data *pd)
 527 {
 528         bool read = pd->msg->flags & I2C_M_RD;
 529         enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
 530         struct dma_chan *chan = read ? pd->dma_rx : pd->dma_tx;
 531         struct dma_async_tx_descriptor *txdesc;
 532         dma_addr_t dma_addr;
 533         dma_cookie_t cookie;
 534
 535         if (PTR_ERR(chan) == -EPROBE_DEFER) {
 536                 if (read)
 537                         chan = pd->dma_rx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_DEV_TO_MEM,
 538                                                                            pd->res->start + ICDR);
 539                 else
 540                         chan = pd->dma_tx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_MEM_TO_DEV,
 541                                                                            pd->res->start + ICDR);
 542         }
 543
 544         if (IS_ERR(chan))
 545                 return;
 546
 547         dma_addr = dma_map_single(chan->device->dev, pd->dma_buf, pd->msg->len, dir);
 548         if (dma_mapping_error(chan->device->dev, dma_addr)) {
 549                 dev_dbg(pd->dev, "dma map failed, using PIO\n");
 550                 return;
 551         }
 552
 553         sg_dma_len(&pd->sg) = pd->msg->len;
 554         sg_dma_address(&pd->sg) = dma_addr;
 555
 556         pd->dma_direction = dir;
 557
 558         txdesc = dmaengine_prep_slave_sg(chan, &pd->sg, 1,
 559                                          read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV,
 560                                          DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 561         if (!txdesc) {
 562                 dev_dbg(pd->dev, "dma prep slave sg failed, using PIO\n");
 563                 sh_mobile_i2c_cleanup_dma(pd);
 564                 return;
 565         }
 566
 567         txdesc->callback = sh_mobile_i2c_dma_callback;
 568         txdesc->callback_param = pd;
 569
 570         cookie = dmaengine_submit(txdesc);
 571         if (dma_submit_error(cookie)) {
 572                 dev_dbg(pd->dev, "submitting dma failed, using PIO\n");
 573                 sh_mobile_i2c_cleanup_dma(pd);
 574                 return;
 575         }
 576
 577         dma_async_issue_pending(chan);
 578 }
 579
 580 static void start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg,
 581                      bool do_init)
 582 {
 583         if (do_init) {
 584                 /* Initialize channel registers */
 585                 iic_wr(pd, ICCR, ICCR_SCP);
 586
 587                 /* Enable channel and configure rx ack */
 588                 iic_wr(pd, ICCR, ICCR_ICE | ICCR_SCP);
 589
 590                 /* Set the clock */
 591                 iic_wr(pd, ICCL, pd->iccl & 0xff);
 592                 iic_wr(pd, ICCH, pd->icch & 0xff);
 593         }
 594
 595         pd->msg = usr_msg;
 596         pd->pos = -1;
 597         pd->sr = 0;
 598
 599         pd->dma_buf = i2c_get_dma_safe_msg_buf(pd->msg, 8);
 600         if (pd->dma_buf)
 601                 sh_mobile_i2c_xfer_dma(pd);
 602
 603         /* Enable all interrupts to begin with */
 604         iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
 605 }
 606
 607 static int poll_dte(struct sh_mobile_i2c_data *pd)
 608 {
 609         int i;
 610
 611         for (i = 1000; i; i--) {
 612                 u_int8_t val = iic_rd(pd, ICSR);
 613
 614                 if (val & ICSR_DTE)
 615                         break;
 616
 617                 if (val & ICSR_TACK)
 618                         return -ENXIO;
 619
 620                 udelay(10);
 621         }
 622
 623         return i ? 0 : -ETIMEDOUT;
 624 }
 625
 626 static int poll_busy(struct sh_mobile_i2c_data *pd)
 627 {
 628         int i;
 629
 630         for (i = 1000; i; i--) {
 631                 u_int8_t val = iic_rd(pd, ICSR);
 632
 633                 dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr);
 634
 635                 /* the interrupt handler may wake us up before the
 636                  * transfer is finished, so poll the hardware
 637                  * until we're done.
 638                  */
 639                 if (!(val & ICSR_BUSY)) {
 640                         /* handle missing acknowledge and arbitration lost */
 641                         val |= pd->sr;
 642                         if (val & ICSR_TACK)
 643                                 return -ENXIO;
 644                         if (val & ICSR_AL)
 645                                 return -EAGAIN;
 646                         break;
 647                 }
 648
 649                 udelay(10);
 650         }
 651
 652         return i ? 0 : -ETIMEDOUT;
 653 }
 654
 655 static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
 656                               struct i2c_msg *msgs,
 657                               int num)
 658 {
 659         struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter);
 660         struct i2c_msg  *msg;
 661         int err = 0;
 662         int i;
 663         long timeout;
 664
 665         /* Wake up device and enable clock */
 666         pm_runtime_get_sync(pd->dev);
 667
 668         /* Process all messages */
 669         for (i = 0; i < num; i++) {
 670                 bool do_start = pd->send_stop || !i;
 671                 msg = &msgs[i];
 672                 pd->send_stop = i == num - 1 || msg->flags & I2C_M_STOP;
 673                 pd->stop_after_dma = false;
 674
 675                 start_ch(pd, msg, do_start);
 676
 677                 if (do_start)
 678                         i2c_op(pd, OP_START);
 679
 680                 /* The interrupt handler takes care of the rest... */
 681                 timeout = wait_event_timeout(pd->wait,
 682                                        pd->sr & (ICSR_TACK | SW_DONE),
 683                                        adapter->timeout);
 684
 685                 /* 'stop_after_dma' tells if DMA transfer was complete */
 686                 i2c_put_dma_safe_msg_buf(pd->dma_buf, pd->msg, pd->stop_after_dma);
 687
 688                 if (!timeout) {
 689                         dev_err(pd->dev, "Transfer request timed out\n");
 690                         if (pd->dma_direction != DMA_NONE)
 691                                 sh_mobile_i2c_cleanup_dma(pd);
 692
 693                         err = -ETIMEDOUT;
 694                         break;
 695                 }
 696
 697                 if (pd->send_stop)
 698                         err = poll_busy(pd);
 699                 else
 700                         err = poll_dte(pd);
 701                 if (err < 0)
 702                         break;
 703         }
 704
 705         /* Disable channel */
 706         iic_wr(pd, ICCR, ICCR_SCP);
 707
 708         /* Disable clock and mark device as idle */
 709         pm_runtime_put_sync(pd->dev);
 710
 711         return err ?: num;
 712 }
 713
 714 static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter)
 715 {
 716         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
 717 }
 718
 719 static const struct i2c_algorithm sh_mobile_i2c_algorithm = {
 720         .functionality  = sh_mobile_i2c_func,
 721         .master_xfer    = sh_mobile_i2c_xfer,
 722 };
 723
 724 static const struct i2c_adapter_quirks sh_mobile_i2c_quirks = {
 725         .flags = I2C_AQ_NO_ZERO_LEN_READ,
 726 };
 727
 728 /*
 729  * r8a7740 chip has lasting errata on I2C I/O pad reset.
 730  * this is work-around for it.
 731  */
 732 static int sh_mobile_i2c_r8a7740_workaround(struct sh_mobile_i2c_data *pd)
 733 {
 734         iic_set_clr(pd, ICCR, ICCR_ICE, 0);
 735         iic_rd(pd, ICCR); /* dummy read */
 736
 737         iic_set_clr(pd, ICSTART, ICSTART_ICSTART, 0);
 738         iic_rd(pd, ICSTART); /* dummy read */
 739
 740         udelay(10);
 741
 742         iic_wr(pd, ICCR, ICCR_SCP);
 743         iic_wr(pd, ICSTART, 0);
 744
 745         udelay(10);
 746
 747         iic_wr(pd, ICCR, ICCR_TRS);
 748         udelay(10);
 749         iic_wr(pd, ICCR, 0);
 750         udelay(10);
 751         iic_wr(pd, ICCR, ICCR_TRS);
 752         udelay(10);
 753
 754         return sh_mobile_i2c_init(pd);
 755 }
 756
 757 static const struct sh_mobile_dt_config default_dt_config = {
 758         .clks_per_count = 1,
 759         .setup = sh_mobile_i2c_init,
 760 };
 761
 762 static const struct sh_mobile_dt_config fast_clock_dt_config = {
 763         .clks_per_count = 2,
 764         .setup = sh_mobile_i2c_init,
 765 };
 766
 767 static const struct sh_mobile_dt_config v2_freq_calc_dt_config = {
 768         .clks_per_count = 2,
 769         .setup = sh_mobile_i2c_v2_init,
 770 };
 771
 772 static const struct sh_mobile_dt_config r8a7740_dt_config = {
 773         .clks_per_count = 1,
 774         .setup = sh_mobile_i2c_r8a7740_workaround,
 775 };
 776
 777 static const struct of_device_id sh_mobile_i2c_dt_ids[] = {
 778         { .compatible = "renesas,iic-r8a73a4", .data = &fast_clock_dt_config },
 779         { .compatible = "renesas,iic-r8a7740", .data = &r8a7740_dt_config },
 780         { .compatible = "renesas,iic-r8a774c0", .data = &fast_clock_dt_config },
 781         { .compatible = "renesas,iic-r8a7790", .data = &v2_freq_calc_dt_config },
 782         { .compatible = "renesas,iic-r8a7791", .data = &fast_clock_dt_config },
 783         { .compatible = "renesas,iic-r8a7792", .data = &fast_clock_dt_config },
 784         { .compatible = "renesas,iic-r8a7793", .data = &fast_clock_dt_config },
 785         { .compatible = "renesas,iic-r8a7794", .data = &fast_clock_dt_config },
 786         { .compatible = "renesas,rcar-gen2-iic", .data = &fast_clock_dt_config },
 787         { .compatible = "renesas,iic-r8a7795", .data = &fast_clock_dt_config },
 788         { .compatible = "renesas,rcar-gen3-iic", .data = &fast_clock_dt_config },
 789         { .compatible = "renesas,iic-r8a77990", .data = &fast_clock_dt_config },
 790         { .compatible = "renesas,iic-sh73a0", .data = &fast_clock_dt_config },
 791         { .compatible = "renesas,rmobile-iic", .data = &default_dt_config },
 792         {},
 793 };
 794 MODULE_DEVICE_TABLE(of, sh_mobile_i2c_dt_ids);
 795
 796 static void sh_mobile_i2c_release_dma(struct sh_mobile_i2c_data *pd)
 797 {
 798         if (!IS_ERR(pd->dma_tx)) {
 799                 dma_release_channel(pd->dma_tx);
 800                 pd->dma_tx = ERR_PTR(-EPROBE_DEFER);
 801         }
 802
 803         if (!IS_ERR(pd->dma_rx)) {
 804                 dma_release_channel(pd->dma_rx);
 805                 pd->dma_rx = ERR_PTR(-EPROBE_DEFER);
 806         }
 807 }
 808
 809 static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, struct sh_mobile_i2c_data *pd)
 810 {
 811         struct resource *res;
 812         resource_size_t n;
 813         int k = 0, ret;
 814
 815         while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) {
 816                 for (n = res->start; n <= res->end; n++) {
 817                         ret = devm_request_irq(&dev->dev, n, sh_mobile_i2c_isr,
 818                                           0, dev_name(&dev->dev), pd);
 819                         if (ret) {
 820                                 dev_err(&dev->dev, "cannot request IRQ %pa\n", &n);
 821                                 return ret;
 822                         }
 823                 }
 824                 k++;
 825         }
 826
 827         return k > 0 ? 0 : -ENOENT;
 828 }
 829
 830 static int sh_mobile_i2c_probe(struct platform_device *dev)
 831 {
 832         struct sh_mobile_i2c_data *pd;
 833         struct i2c_adapter *adap;
 834         struct resource *res;
 835         const struct sh_mobile_dt_config *config;
 836         int ret;
 837         u32 bus_speed;
 838
 839         pd = devm_kzalloc(&dev->dev, sizeof(struct sh_mobile_i2c_data), GFP_KERNEL);
 840         if (!pd)
 841                 return -ENOMEM;
 842
 843         pd->clk = devm_clk_get(&dev->dev, NULL);
 844         if (IS_ERR(pd->clk)) {
 845                 dev_err(&dev->dev, "cannot get clock\n");
 846                 return PTR_ERR(pd->clk);
 847         }
 848
 849         ret = sh_mobile_i2c_hook_irqs(dev, pd);
 850         if (ret)
 851                 return ret;
 852
 853         pd->dev = &dev->dev;
 854         platform_set_drvdata(dev, pd);
 855
 856         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
 857
 858         pd->res = res;
 859         pd->reg = devm_ioremap_resource(&dev->dev, res);
 860         if (IS_ERR(pd->reg))
 861                 return PTR_ERR(pd->reg);
 862
 863         ret = of_property_read_u32(dev->dev.of_node, "clock-frequency", &bus_speed);
 864         pd->bus_speed = (ret || !bus_speed) ? STANDARD_MODE : bus_speed;
 865         pd->clks_per_count = 1;
 866
 867         /* Newer variants come with two new bits in ICIC */
 868         if (resource_size(res) > 0x17)
 869                 pd->flags |= IIC_FLAG_HAS_ICIC67;
 870
 871         pm_runtime_enable(&dev->dev);
 872         pm_runtime_get_sync(&dev->dev);
 873
 874         config = of_device_get_match_data(&dev->dev);
 875         if (config) {
 876                 pd->clks_per_count = config->clks_per_count;
 877                 ret = config->setup(pd);
 878         } else {
 879                 ret = sh_mobile_i2c_init(pd);
 880         }
 881
 882         pm_runtime_put_sync(&dev->dev);
 883         if (ret)
 884                 return ret;
 885
 886         /* Init DMA */
 887         sg_init_table(&pd->sg, 1);
 888         pd->dma_direction = DMA_NONE;
 889         pd->dma_rx = pd->dma_tx = ERR_PTR(-EPROBE_DEFER);
 890
 891         /* setup the private data */
 892         adap = &pd->adap;
 893         i2c_set_adapdata(adap, pd);
 894
 895         adap->owner = THIS_MODULE;
 896         adap->algo = &sh_mobile_i2c_algorithm;
 897         adap->quirks = &sh_mobile_i2c_quirks;
 898         adap->dev.parent = &dev->dev;
 899         adap->retries = 5;
 900         adap->nr = dev->id;
 901         adap->dev.of_node = dev->dev.of_node;
 902
 903         strlcpy(adap->name, dev->name, sizeof(adap->name));
 904
 905         spin_lock_init(&pd->lock);
 906         init_waitqueue_head(&pd->wait);
 907
 908         ret = i2c_add_numbered_adapter(adap);
 909         if (ret < 0) {
 910                 sh_mobile_i2c_release_dma(pd);
 911                 return ret;
 912         }
 913
 914         dev_info(&dev->dev, "I2C adapter %d, bus speed %lu Hz\n", adap->nr, pd->bus_speed);
 915
 916         return 0;
 917 }
 918
 919 static int sh_mobile_i2c_remove(struct platform_device *dev)
 920 {
 921         struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
 922
 923         i2c_del_adapter(&pd->adap);
 924         sh_mobile_i2c_release_dma(pd);
 925         pm_runtime_disable(&dev->dev);
 926         return 0;
 927 }
 928
 929 static struct platform_driver sh_mobile_i2c_driver = {
 930         .driver         = {
 931                 .name           = "i2c-sh_mobile",
 932                 .of_match_table = sh_mobile_i2c_dt_ids,
 933         },
 934         .probe          = sh_mobile_i2c_probe,
 935         .remove         = sh_mobile_i2c_remove,
 936 };
 937
 938 static int __init sh_mobile_i2c_adap_init(void)
 939 {
 940         return platform_driver_register(&sh_mobile_i2c_driver);
 941 }
 942 subsys_initcall(sh_mobile_i2c_adap_init);
 943
 944 static void __exit sh_mobile_i2c_adap_exit(void)
 945 {
 946         platform_driver_unregister(&sh_mobile_i2c_driver);
 947 }
 948 module_exit(sh_mobile_i2c_adap_exit);
 949
 950 MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver");
 951 MODULE_AUTHOR("Magnus Damm and Wolfram Sang");
 952 MODULE_LICENSE("GPL v2");
 953 MODULE_ALIAS("platform:i2c-sh_mobile");