1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013 Wolfram Sang <wsa@sang-engineering.com>
6 * Copyright (C) 2013 Renesas Solutions Corp.
10 * This i2c core has a lot of interrupts, namely 8. We use their chaining as
11 * some kind of state machine.
13 * 1) The main xfer routine kicks off a transmission by putting the start bit
14 * (or repeated start) on the bus and enabling the transmit interrupt (TIE)
15 * since we need to send the slave address + RW bit in every case.
17 * 2) TIE sends slave address + RW bit and selects how to continue.
19 * 3a) Write case: We keep utilizing TIE as long as we have data to send. If we
20 * are done, we switch over to the transmission done interrupt (TEIE) and mark
21 * the message as completed (includes sending STOP) there.
23 * 3b) Read case: We switch over to receive interrupt (RIE). One dummy read is
24 * needed to start clocking, then we keep receiving until we are done. Note
25 * that we use the RDRFS mode all the time, i.e. we ACK/NACK every byte by
26 * writing to the ACKBT bit. I tried using the RDRFS mode only at the end of a
27 * message to create the final NACK as sketched in the datasheet. This caused
28 * some subtle races (when byte n was processed and byte n+1 was already
29 * waiting), though, and I started with the safe approach.
31 * 4) If we got a NACK somewhere, we flag the error and stop the transmission
34 * Also check the comments in the interrupt routines for some gory details.
37 #include <linux/clk.h>
38 #include <linux/completion.h>
39 #include <linux/err.h>
40 #include <linux/i2c.h>
41 #include <linux/interrupt.h>
43 #include <linux/module.h>
45 #include <linux/of_device.h>
46 #include <linux/platform_device.h>
47 #include <linux/pm_runtime.h>
48 #include <linux/reset.h>
50 #define RIIC_ICCR1 0x00
51 #define RIIC_ICCR2 0x04
52 #define RIIC_ICMR1 0x08
53 #define RIIC_ICMR3 0x10
54 #define RIIC_ICSER 0x18
55 #define RIIC_ICIER 0x1c
56 #define RIIC_ICSR2 0x24
57 #define RIIC_ICBRL 0x34
58 #define RIIC_ICBRH 0x38
59 #define RIIC_ICDRT 0x3c
60 #define RIIC_ICDRR 0x40
62 #define ICCR1_ICE 0x80
63 #define ICCR1_IICRST 0x40
64 #define ICCR1_SOWP 0x10
66 #define ICCR2_BBSY 0x80
71 #define ICMR1_CKS_MASK 0x70
72 #define ICMR1_BCWP 0x08
73 #define ICMR1_CKS(_x) ((((_x) << 4) & ICMR1_CKS_MASK) | ICMR1_BCWP)
75 #define ICMR3_RDRFS 0x20
76 #define ICMR3_ACKWP 0x10
77 #define ICMR3_ACKBT 0x08
79 #define ICIER_TIE 0x80
80 #define ICIER_TEIE 0x40
81 #define ICIER_RIE 0x20
82 #define ICIER_NAKIE 0x10
83 #define ICIER_SPIE 0x08
85 #define ICSR2_NACKF 0x10
87 #define ICBR_RESERVED 0xe0 /* Should be 1 on writes */
89 #define RIIC_INIT_MSG -1
103 struct completion msg_done;
104 struct i2c_adapter adapter;
108 struct riic_irq_desc {
114 static inline void riic_clear_set_bit(struct riic_dev *riic, u8 clear, u8 set, u8 reg)
116 writeb((readb(riic->base + reg) & ~clear) | set, riic->base + reg);
119 static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
121 struct riic_dev *riic = i2c_get_adapdata(adap);
122 unsigned long time_left;
126 pm_runtime_get_sync(adap->dev.parent);
128 if (readb(riic->base + RIIC_ICCR2) & ICCR2_BBSY) {
133 reinit_completion(&riic->msg_done);
136 writeb(0, riic->base + RIIC_ICSR2);
138 for (i = 0, start_bit = ICCR2_ST; i < num; i++) {
139 riic->bytes_left = RIIC_INIT_MSG;
140 riic->buf = msgs[i].buf;
141 riic->msg = &msgs[i];
142 riic->is_last = (i == num - 1);
144 writeb(ICIER_NAKIE | ICIER_TIE, riic->base + RIIC_ICIER);
146 writeb(start_bit, riic->base + RIIC_ICCR2);
148 time_left = wait_for_completion_timeout(&riic->msg_done, riic->adapter.timeout);
150 riic->err = -ETIMEDOUT;
155 start_bit = ICCR2_RS;
159 pm_runtime_put(adap->dev.parent);
161 return riic->err ?: num;
164 static irqreturn_t riic_tdre_isr(int irq, void *data)
166 struct riic_dev *riic = data;
169 if (!riic->bytes_left)
172 if (riic->bytes_left == RIIC_INIT_MSG) {
173 if (riic->msg->flags & I2C_M_RD)
174 /* On read, switch over to receive interrupt */
175 riic_clear_set_bit(riic, ICIER_TIE, ICIER_RIE, RIIC_ICIER);
177 /* On write, initialize length */
178 riic->bytes_left = riic->msg->len;
180 val = i2c_8bit_addr_from_msg(riic->msg);
188 * Switch to transmission ended interrupt when done. Do check here
189 * after bytes_left was initialized to support SMBUS_QUICK (new msg has
192 if (riic->bytes_left == 0)
193 riic_clear_set_bit(riic, ICIER_TIE, ICIER_TEIE, RIIC_ICIER);
196 * This acks the TIE interrupt. We get another TIE immediately if our
197 * value could be moved to the shadow shift register right away. So
198 * this must be after updates to ICIER (where we want to disable TIE)!
200 writeb(val, riic->base + RIIC_ICDRT);
205 static irqreturn_t riic_tend_isr(int irq, void *data)
207 struct riic_dev *riic = data;
209 if (readb(riic->base + RIIC_ICSR2) & ICSR2_NACKF) {
210 /* We got a NACKIE */
211 readb(riic->base + RIIC_ICDRR); /* dummy read */
212 riic_clear_set_bit(riic, ICSR2_NACKF, 0, RIIC_ICSR2);
214 } else if (riic->bytes_left) {
218 if (riic->is_last || riic->err) {
219 riic_clear_set_bit(riic, ICIER_TEIE, ICIER_SPIE, RIIC_ICIER);
220 writeb(ICCR2_SP, riic->base + RIIC_ICCR2);
222 /* Transfer is complete, but do not send STOP */
223 riic_clear_set_bit(riic, ICIER_TEIE, 0, RIIC_ICIER);
224 complete(&riic->msg_done);
230 static irqreturn_t riic_rdrf_isr(int irq, void *data)
232 struct riic_dev *riic = data;
234 if (!riic->bytes_left)
237 if (riic->bytes_left == RIIC_INIT_MSG) {
238 riic->bytes_left = riic->msg->len;
239 readb(riic->base + RIIC_ICDRR); /* dummy read */
243 if (riic->bytes_left == 1) {
244 /* STOP must come before we set ACKBT! */
246 riic_clear_set_bit(riic, 0, ICIER_SPIE, RIIC_ICIER);
247 writeb(ICCR2_SP, riic->base + RIIC_ICCR2);
250 riic_clear_set_bit(riic, 0, ICMR3_ACKBT, RIIC_ICMR3);
253 riic_clear_set_bit(riic, ICMR3_ACKBT, 0, RIIC_ICMR3);
256 /* Reading acks the RIE interrupt */
257 *riic->buf = readb(riic->base + RIIC_ICDRR);
264 static irqreturn_t riic_stop_isr(int irq, void *data)
266 struct riic_dev *riic = data;
268 /* read back registers to confirm writes have fully propagated */
269 writeb(0, riic->base + RIIC_ICSR2);
270 readb(riic->base + RIIC_ICSR2);
271 writeb(0, riic->base + RIIC_ICIER);
272 readb(riic->base + RIIC_ICIER);
274 complete(&riic->msg_done);
279 static u32 riic_func(struct i2c_adapter *adap)
281 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
284 static const struct i2c_algorithm riic_algo = {
285 .master_xfer = riic_xfer,
286 .functionality = riic_func,
289 static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t)
293 int total_ticks, cks, brl, brh;
295 pm_runtime_get_sync(riic->adapter.dev.parent);
297 if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) {
298 dev_err(&riic->adapter.dev,
299 "unsupported bus speed (%dHz). %d max\n",
300 t->bus_freq_hz, I2C_MAX_FAST_MODE_FREQ);
305 rate = clk_get_rate(riic->clk);
308 * Assume the default register settings:
309 * FER.SCLE = 1 (SCL sync circuit enabled, adds 2 or 3 cycles)
310 * FER.NFE = 1 (noise circuit enabled)
311 * MR3.NF = 0 (1 cycle of noise filtered out)
313 * Freq (CKS=000) = (I2CCLK + tr + tf)/ (BRH + 3 + 1) + (BRL + 3 + 1)
314 * Freq (CKS!=000) = (I2CCLK + tr + tf)/ (BRH + 2 + 1) + (BRL + 2 + 1)
318 * Determine reference clock rate. We must be able to get the desired
319 * frequency with only 62 clock ticks max (31 high, 31 low).
320 * Aim for a duty of 60% LOW, 40% HIGH.
322 total_ticks = DIV_ROUND_UP(rate, t->bus_freq_hz);
324 for (cks = 0; cks < 7; cks++) {
326 * 60% low time must be less than BRL + 2 + 1
327 * BRL max register value is 0x1F.
329 brl = ((total_ticks * 6) / 10);
330 if (brl <= (0x1F + 3))
337 if (brl > (0x1F + 3)) {
338 dev_err(&riic->adapter.dev, "invalid speed (%lu). Too slow.\n",
339 (unsigned long)t->bus_freq_hz);
344 brh = total_ticks - brl;
346 /* Remove automatic clock ticks for sync circuit and NF */
356 * Remove clock ticks for rise and fall times. Convert ns to clock
359 brl -= t->scl_fall_ns / (1000000000 / rate);
360 brh -= t->scl_rise_ns / (1000000000 / rate);
362 /* Adjust for min register values for when SCLE=1 and NFE=1 */
368 pr_debug("i2c-riic: freq=%lu, duty=%d, fall=%lu, rise=%lu, cks=%d, brl=%d, brh=%d\n",
369 rate / total_ticks, ((brl + 3) * 100) / (brl + brh + 6),
370 t->scl_fall_ns / (1000000000 / rate),
371 t->scl_rise_ns / (1000000000 / rate), cks, brl, brh);
373 /* Changing the order of accessing IICRST and ICE may break things! */
374 writeb(ICCR1_IICRST | ICCR1_SOWP, riic->base + RIIC_ICCR1);
375 riic_clear_set_bit(riic, 0, ICCR1_ICE, RIIC_ICCR1);
377 writeb(ICMR1_CKS(cks), riic->base + RIIC_ICMR1);
378 writeb(brh | ICBR_RESERVED, riic->base + RIIC_ICBRH);
379 writeb(brl | ICBR_RESERVED, riic->base + RIIC_ICBRL);
381 writeb(0, riic->base + RIIC_ICSER);
382 writeb(ICMR3_ACKWP | ICMR3_RDRFS, riic->base + RIIC_ICMR3);
384 riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1);
387 pm_runtime_put(riic->adapter.dev.parent);
391 static struct riic_irq_desc riic_irqs[] = {
392 { .res_num = 0, .isr = riic_tend_isr, .name = "riic-tend" },
393 { .res_num = 1, .isr = riic_rdrf_isr, .name = "riic-rdrf" },
394 { .res_num = 2, .isr = riic_tdre_isr, .name = "riic-tdre" },
395 { .res_num = 3, .isr = riic_stop_isr, .name = "riic-stop" },
396 { .res_num = 5, .isr = riic_tend_isr, .name = "riic-nack" },
399 static int riic_i2c_probe(struct platform_device *pdev)
401 struct riic_dev *riic;
402 struct i2c_adapter *adap;
403 struct resource *res;
404 struct i2c_timings i2c_t;
405 struct reset_control *rstc;
409 riic = devm_kzalloc(&pdev->dev, sizeof(*riic), GFP_KERNEL);
413 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
414 riic->base = devm_ioremap_resource(&pdev->dev, res);
415 if (IS_ERR(riic->base))
416 return PTR_ERR(riic->base);
418 riic->clk = devm_clk_get(&pdev->dev, NULL);
419 if (IS_ERR(riic->clk)) {
420 dev_err(&pdev->dev, "missing controller clock");
421 return PTR_ERR(riic->clk);
424 type = (enum riic_type)of_device_get_match_data(&pdev->dev);
425 if (type == RIIC_RZ_G2L) {
426 rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
428 dev_err(&pdev->dev, "Error: missing reset ctrl\n");
429 return PTR_ERR(rstc);
432 reset_control_deassert(rstc);
435 for (i = 0; i < ARRAY_SIZE(riic_irqs); i++) {
436 res = platform_get_resource(pdev, IORESOURCE_IRQ, riic_irqs[i].res_num);
440 ret = devm_request_irq(&pdev->dev, res->start, riic_irqs[i].isr,
441 0, riic_irqs[i].name, riic);
443 dev_err(&pdev->dev, "failed to request irq %s\n", riic_irqs[i].name);
448 adap = &riic->adapter;
449 i2c_set_adapdata(adap, riic);
450 strlcpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name));
451 adap->owner = THIS_MODULE;
452 adap->algo = &riic_algo;
453 adap->dev.parent = &pdev->dev;
454 adap->dev.of_node = pdev->dev.of_node;
456 init_completion(&riic->msg_done);
458 i2c_parse_fw_timings(&pdev->dev, &i2c_t, true);
460 pm_runtime_enable(&pdev->dev);
462 ret = riic_init_hw(riic, &i2c_t);
466 ret = i2c_add_adapter(adap);
470 platform_set_drvdata(pdev, riic);
472 dev_info(&pdev->dev, "registered with %dHz bus speed\n",
477 pm_runtime_disable(&pdev->dev);
481 static int riic_i2c_remove(struct platform_device *pdev)
483 struct riic_dev *riic = platform_get_drvdata(pdev);
485 pm_runtime_get_sync(&pdev->dev);
486 writeb(0, riic->base + RIIC_ICIER);
487 pm_runtime_put(&pdev->dev);
488 i2c_del_adapter(&riic->adapter);
489 pm_runtime_disable(&pdev->dev);
494 static const struct of_device_id riic_i2c_dt_ids[] = {
495 { .compatible = "renesas,riic-r9a07g044", .data = (void *)RIIC_RZ_G2L },
496 { .compatible = "renesas,riic-rz", .data = (void *)RIIC_RZ_A },
500 static struct platform_driver riic_i2c_driver = {
501 .probe = riic_i2c_probe,
502 .remove = riic_i2c_remove,
505 .of_match_table = riic_i2c_dt_ids,
509 module_platform_driver(riic_i2c_driver);
511 MODULE_DESCRIPTION("Renesas RIIC adapter");
512 MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>");
513 MODULE_LICENSE("GPL v2");
514 MODULE_DEVICE_TABLE(of, riic_i2c_dt_ids);