1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the Renesas R-Car I2C unit
5 * Copyright (C) 2014-19 Wolfram Sang <wsa@sang-engineering.com>
6 * Copyright (C) 2011-2019 Renesas Electronics Corporation
8 * Copyright (C) 2012-14 Renesas Solutions Corp.
9 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
11 * This file is based on the drivers/i2c/busses/i2c-sh7760.c
12 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
14 #include <linux/bitops.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/dmaengine.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
20 #include <linux/interrupt.h>
22 #include <linux/i2c.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/of_device.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/reset.h>
29 #include <linux/slab.h>
31 /* register offsets */
32 #define ICSCR 0x00 /* slave ctrl */
33 #define ICMCR 0x04 /* master ctrl */
34 #define ICSSR 0x08 /* slave status */
35 #define ICMSR 0x0C /* master status */
36 #define ICSIER 0x10 /* slave irq enable */
37 #define ICMIER 0x14 /* master irq enable */
38 #define ICCCR 0x18 /* clock dividers */
39 #define ICSAR 0x1C /* slave address */
40 #define ICMAR 0x20 /* master address */
41 #define ICRXTX 0x24 /* data port */
42 #define ICFBSCR 0x38 /* first bit setup cycle (Gen3) */
43 #define ICDMAER 0x3c /* DMA enable (Gen3) */
46 #define SDBS (1 << 3) /* slave data buffer select */
47 #define SIE (1 << 2) /* slave interface enable */
48 #define GCAE (1 << 1) /* general call address enable */
49 #define FNA (1 << 0) /* forced non acknowledgment */
52 #define MDBS (1 << 7) /* non-fifo mode switch */
53 #define FSCL (1 << 6) /* override SCL pin */
54 #define FSDA (1 << 5) /* override SDA pin */
55 #define OBPC (1 << 4) /* override pins */
56 #define MIE (1 << 3) /* master if enable */
58 #define FSB (1 << 1) /* force stop bit */
59 #define ESG (1 << 0) /* enable start bit gen */
61 /* ICSSR (also for ICSIER) */
62 #define GCAR (1 << 6) /* general call received */
63 #define STM (1 << 5) /* slave transmit mode */
64 #define SSR (1 << 4) /* stop received */
65 #define SDE (1 << 3) /* slave data empty */
66 #define SDT (1 << 2) /* slave data transmitted */
67 #define SDR (1 << 1) /* slave data received */
68 #define SAR (1 << 0) /* slave addr received */
70 /* ICMSR (also for ICMIE) */
71 #define MNR (1 << 6) /* nack received */
72 #define MAL (1 << 5) /* arbitration lost */
73 #define MST (1 << 4) /* sent a stop */
77 #define MAT (1 << 0) /* slave addr xfer done */
80 #define RSDMAE (1 << 3) /* DMA Slave Received Enable */
81 #define TSDMAE (1 << 2) /* DMA Slave Transmitted Enable */
82 #define RMDMAE (1 << 1) /* DMA Master Received Enable */
83 #define TMDMAE (1 << 0) /* DMA Master Transmitted Enable */
86 #define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */
88 #define RCAR_MIN_DMA_LEN 8
90 #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG)
91 #define RCAR_BUS_PHASE_DATA (MDBS | MIE)
92 #define RCAR_BUS_MASK_DATA (~(ESG | FSB) & 0xFF)
93 #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB)
95 #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE)
96 #define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR)
97 #define RCAR_IRQ_STOP (MST)
99 #define RCAR_IRQ_ACK_SEND (~(MAT | MDE) & 0x7F)
100 #define RCAR_IRQ_ACK_RECV (~(MAT | MDR) & 0x7F)
102 #define ID_LAST_MSG (1 << 0)
103 #define ID_FIRST_MSG (1 << 1)
104 #define ID_DONE (1 << 2)
105 #define ID_ARBLOST (1 << 3)
106 #define ID_NACK (1 << 4)
107 /* persistent flags */
108 #define ID_P_REP_AFTER_RD BIT(29)
109 #define ID_P_NO_RXDMA BIT(30) /* HW forbids RXDMA sometimes */
110 #define ID_P_PM_BLOCKED BIT(31)
111 #define ID_P_MASK GENMASK(31, 29)
119 struct rcar_i2c_priv {
121 struct i2c_adapter adap;
126 wait_queue_head_t wait;
131 u8 recovery_icmcr; /* protected by adapter lock */
132 enum rcar_i2c_type devtype;
133 struct i2c_client *slave;
135 struct resource *res;
136 struct dma_chan *dma_tx;
137 struct dma_chan *dma_rx;
138 struct scatterlist sg;
139 enum dma_data_direction dma_direction;
141 struct reset_control *rstc;
145 #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent)
146 #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD)
148 #define LOOP_TIMEOUT 1024
151 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val)
153 writel(val, priv->io + reg);
156 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg)
158 return readl(priv->io + reg);
161 static int rcar_i2c_get_scl(struct i2c_adapter *adap)
163 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
165 return !!(rcar_i2c_read(priv, ICMCR) & FSCL);
169 static void rcar_i2c_set_scl(struct i2c_adapter *adap, int val)
171 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
174 priv->recovery_icmcr |= FSCL;
176 priv->recovery_icmcr &= ~FSCL;
178 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr);
181 static void rcar_i2c_set_sda(struct i2c_adapter *adap, int val)
183 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
186 priv->recovery_icmcr |= FSDA;
188 priv->recovery_icmcr &= ~FSDA;
190 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr);
193 static int rcar_i2c_get_bus_free(struct i2c_adapter *adap)
195 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
197 return !(rcar_i2c_read(priv, ICMCR) & FSDA);
201 static struct i2c_bus_recovery_info rcar_i2c_bri = {
202 .get_scl = rcar_i2c_get_scl,
203 .set_scl = rcar_i2c_set_scl,
204 .set_sda = rcar_i2c_set_sda,
205 .get_bus_free = rcar_i2c_get_bus_free,
206 .recover_bus = i2c_generic_scl_recovery,
208 static void rcar_i2c_init(struct rcar_i2c_priv *priv)
210 /* reset master mode */
211 rcar_i2c_write(priv, ICMIER, 0);
212 rcar_i2c_write(priv, ICMCR, MDBS);
213 rcar_i2c_write(priv, ICMSR, 0);
215 rcar_i2c_write(priv, ICCCR, priv->icccr);
217 if (priv->devtype == I2C_RCAR_GEN3)
218 rcar_i2c_write(priv, ICFBSCR, TCYC17);
222 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
226 for (i = 0; i < LOOP_TIMEOUT; i++) {
227 /* make sure that bus is not busy */
228 if (!(rcar_i2c_read(priv, ICMCR) & FSDA))
233 /* Waiting did not help, try to recover */
234 priv->recovery_icmcr = MDBS | OBPC | FSDA | FSCL;
235 return i2c_recover_bus(&priv->adap);
238 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv)
240 u32 scgd, cdf, round, ick, sum, scl, cdf_width;
242 struct device *dev = rcar_i2c_priv_to_dev(priv);
243 struct i2c_timings t = {
244 .bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ,
247 .scl_int_delay_ns = 50,
250 /* Fall back to previously used values if not supplied */
251 i2c_parse_fw_timings(dev, &t, false);
253 switch (priv->devtype) {
262 dev_err(dev, "device type error\n");
267 * calculate SCL clock
271 * ick = clkp / (1 + CDF)
272 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
274 * ick : I2C internal clock < 20 MHz
275 * ticf : I2C SCL falling time
276 * tr : I2C SCL rising time
277 * intd : LSI internal delay
278 * clkp : peripheral_clk
279 * F[] : integer up-valuation
281 rate = clk_get_rate(priv->clk);
282 cdf = rate / 20000000;
283 if (cdf >= 1U << cdf_width) {
284 dev_err(dev, "Input clock %lu too high\n", rate);
287 ick = rate / (cdf + 1);
290 * it is impossible to calculate large scale
291 * number on u32. separate it
293 * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd)
294 * = F[sum * ick / 1000000000]
295 * = F[(ick / 1000000) * sum / 1000]
297 sum = t.scl_fall_ns + t.scl_rise_ns + t.scl_int_delay_ns;
298 round = (ick + 500000) / 1000000 * sum;
299 round = (round + 500) / 1000;
302 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
304 * Calculation result (= SCL) should be less than
305 * bus_speed for hardware safety
307 * We could use something along the lines of
308 * div = ick / (bus_speed + 1) + 1;
309 * scgd = (div - 20 - round + 7) / 8;
310 * scl = ick / (20 + (scgd * 8) + round);
311 * (not fully verified) but that would get pretty involved
313 for (scgd = 0; scgd < 0x40; scgd++) {
314 scl = ick / (20 + (scgd * 8) + round);
315 if (scl <= t.bus_freq_hz)
318 dev_err(dev, "it is impossible to calculate best SCL\n");
322 dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
323 scl, t.bus_freq_hz, rate, round, cdf, scgd);
325 /* keep icccr value */
326 priv->icccr = scgd << cdf_width | cdf;
331 static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
333 int read = !!rcar_i2c_is_recv(priv);
336 if (priv->msgs_left == 1)
337 priv->flags |= ID_LAST_MSG;
339 rcar_i2c_write(priv, ICMAR, i2c_8bit_addr_from_msg(priv->msg));
341 * We don't have a test case but the HW engineers say that the write order
342 * of ICMSR and ICMCR depends on whether we issue START or REP_START. Since
343 * it didn't cause a drawback for me, let's rather be safe than sorry.
345 if (priv->flags & ID_FIRST_MSG) {
346 rcar_i2c_write(priv, ICMSR, 0);
347 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
349 if (priv->flags & ID_P_REP_AFTER_RD)
350 priv->flags &= ~ID_P_REP_AFTER_RD;
352 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
353 rcar_i2c_write(priv, ICMSR, 0);
355 rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
358 static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv)
362 priv->flags &= ID_P_MASK;
363 rcar_i2c_prepare_msg(priv);
366 static void rcar_i2c_dma_unmap(struct rcar_i2c_priv *priv)
368 struct dma_chan *chan = priv->dma_direction == DMA_FROM_DEVICE
369 ? priv->dma_rx : priv->dma_tx;
371 dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg),
372 sg_dma_len(&priv->sg), priv->dma_direction);
374 /* Gen3 can only do one RXDMA per transfer and we just completed it */
375 if (priv->devtype == I2C_RCAR_GEN3 &&
376 priv->dma_direction == DMA_FROM_DEVICE)
377 priv->flags |= ID_P_NO_RXDMA;
379 priv->dma_direction = DMA_NONE;
381 /* Disable DMA Master Received/Transmitted, must be last! */
382 rcar_i2c_write(priv, ICDMAER, 0);
385 static void rcar_i2c_cleanup_dma(struct rcar_i2c_priv *priv)
387 if (priv->dma_direction == DMA_NONE)
389 else if (priv->dma_direction == DMA_FROM_DEVICE)
390 dmaengine_terminate_all(priv->dma_rx);
391 else if (priv->dma_direction == DMA_TO_DEVICE)
392 dmaengine_terminate_all(priv->dma_tx);
394 rcar_i2c_dma_unmap(priv);
397 static void rcar_i2c_dma_callback(void *data)
399 struct rcar_i2c_priv *priv = data;
401 priv->pos += sg_dma_len(&priv->sg);
403 rcar_i2c_dma_unmap(priv);
406 static bool rcar_i2c_dma(struct rcar_i2c_priv *priv)
408 struct device *dev = rcar_i2c_priv_to_dev(priv);
409 struct i2c_msg *msg = priv->msg;
410 bool read = msg->flags & I2C_M_RD;
411 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
412 struct dma_chan *chan = read ? priv->dma_rx : priv->dma_tx;
413 struct dma_async_tx_descriptor *txdesc;
419 /* Do various checks to see if DMA is feasible at all */
420 if (IS_ERR(chan) || msg->len < RCAR_MIN_DMA_LEN ||
421 !(msg->flags & I2C_M_DMA_SAFE) || (read && priv->flags & ID_P_NO_RXDMA))
426 * The last two bytes needs to be fetched using PIO in
427 * order for the STOP phase to work.
429 buf = priv->msg->buf;
430 len = priv->msg->len - 2;
433 * First byte in message was sent using PIO.
435 buf = priv->msg->buf + 1;
436 len = priv->msg->len - 1;
439 dma_addr = dma_map_single(chan->device->dev, buf, len, dir);
440 if (dma_mapping_error(chan->device->dev, dma_addr)) {
441 dev_dbg(dev, "dma map failed, using PIO\n");
445 sg_dma_len(&priv->sg) = len;
446 sg_dma_address(&priv->sg) = dma_addr;
448 priv->dma_direction = dir;
450 txdesc = dmaengine_prep_slave_sg(chan, &priv->sg, 1,
451 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV,
452 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
454 dev_dbg(dev, "dma prep slave sg failed, using PIO\n");
455 rcar_i2c_cleanup_dma(priv);
459 txdesc->callback = rcar_i2c_dma_callback;
460 txdesc->callback_param = priv;
462 cookie = dmaengine_submit(txdesc);
463 if (dma_submit_error(cookie)) {
464 dev_dbg(dev, "submitting dma failed, using PIO\n");
465 rcar_i2c_cleanup_dma(priv);
469 /* Enable DMA Master Received/Transmitted */
471 rcar_i2c_write(priv, ICDMAER, RMDMAE);
473 rcar_i2c_write(priv, ICDMAER, TMDMAE);
475 dma_async_issue_pending(chan);
479 static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
481 struct i2c_msg *msg = priv->msg;
483 /* FIXME: sometimes, unknown interrupt happened. Do nothing */
487 /* Check if DMA can be enabled and take over */
488 if (priv->pos == 1 && rcar_i2c_dma(priv))
491 if (priv->pos < msg->len) {
493 * Prepare next data to ICRXTX register.
494 * This data will go to _SHIFT_ register.
497 * [ICRXTX] -> [SHIFT] -> [I2C bus]
499 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
503 * The last data was pushed to ICRXTX on _PREV_ empty irq.
504 * It is on _SHIFT_ register, and will sent to I2C bus.
507 * [ICRXTX] -> [SHIFT] -> [I2C bus]
510 if (priv->flags & ID_LAST_MSG) {
512 * If current msg is the _LAST_ msg,
513 * prepare stop condition here.
514 * ID_DONE will be set on STOP irq.
516 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
518 rcar_i2c_next_msg(priv);
523 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND);
526 static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
528 struct i2c_msg *msg = priv->msg;
530 /* FIXME: sometimes, unknown interrupt happened. Do nothing */
536 * Address transfer phase finished, but no data at this point.
537 * Try to use DMA to receive data.
540 } else if (priv->pos < msg->len) {
541 /* get received data */
542 msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX);
546 /* If next received data is the _LAST_, go to new phase. */
547 if (priv->pos + 1 == msg->len) {
548 if (priv->flags & ID_LAST_MSG) {
549 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
551 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
552 priv->flags |= ID_P_REP_AFTER_RD;
556 if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG))
557 rcar_i2c_next_msg(priv);
559 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV);
562 static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv)
564 u32 ssr_raw, ssr_filtered;
567 ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff;
568 ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER);
573 /* address detected */
574 if (ssr_filtered & SAR) {
575 /* read or write request */
577 i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value);
578 rcar_i2c_write(priv, ICRXTX, value);
579 rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR);
581 i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value);
582 rcar_i2c_read(priv, ICRXTX); /* dummy read */
583 rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR);
586 /* Clear SSR, too, because of old STOPs to other clients than us */
587 rcar_i2c_write(priv, ICSSR, ~(SAR | SSR) & 0xff);
590 /* master sent stop */
591 if (ssr_filtered & SSR) {
592 i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value);
593 rcar_i2c_write(priv, ICSCR, SIE | SDBS); /* clear our NACK */
594 rcar_i2c_write(priv, ICSIER, SAR);
595 rcar_i2c_write(priv, ICSSR, ~SSR & 0xff);
598 /* master wants to write to us */
599 if (ssr_filtered & SDR) {
602 value = rcar_i2c_read(priv, ICRXTX);
603 ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value);
604 /* Send NACK in case of error */
605 rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0));
606 rcar_i2c_write(priv, ICSSR, ~SDR & 0xff);
609 /* master wants to read from us */
610 if (ssr_filtered & SDE) {
611 i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value);
612 rcar_i2c_write(priv, ICRXTX, value);
613 rcar_i2c_write(priv, ICSSR, ~SDE & 0xff);
620 * This driver has a lock-free design because there are IP cores (at least
621 * R-Car Gen2) which have an inherent race condition in their hardware design.
622 * There, we need to clear RCAR_BUS_MASK_DATA bits as soon as possible after
623 * the interrupt was generated, otherwise an unwanted repeated message gets
624 * generated. It turned out that taking a spinlock at the beginning of the ISR
625 * was already causing repeated messages. Thus, this driver was converted to
626 * the now lockless behaviour. Please keep this in mind when hacking the driver.
628 static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
630 struct rcar_i2c_priv *priv = ptr;
633 /* Clear START or STOP immediately, except for REPSTART after read */
634 if (likely(!(priv->flags & ID_P_REP_AFTER_RD))) {
635 val = rcar_i2c_read(priv, ICMCR);
636 rcar_i2c_write(priv, ICMCR, val & RCAR_BUS_MASK_DATA);
639 msr = rcar_i2c_read(priv, ICMSR);
641 /* Only handle interrupts that are currently enabled */
642 msr &= rcar_i2c_read(priv, ICMIER);
644 if (rcar_i2c_slave_irq(priv))
650 /* Arbitration lost */
652 priv->flags |= ID_DONE | ID_ARBLOST;
658 /* HW automatically sends STOP after received NACK */
659 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP);
660 priv->flags |= ID_NACK;
666 priv->msgs_left--; /* The last message also made it */
667 priv->flags |= ID_DONE;
671 if (rcar_i2c_is_recv(priv))
672 rcar_i2c_irq_recv(priv, msr);
674 rcar_i2c_irq_send(priv, msr);
677 if (priv->flags & ID_DONE) {
678 rcar_i2c_write(priv, ICMIER, 0);
679 rcar_i2c_write(priv, ICMSR, 0);
680 wake_up(&priv->wait);
686 static struct dma_chan *rcar_i2c_request_dma_chan(struct device *dev,
687 enum dma_transfer_direction dir,
688 dma_addr_t port_addr)
690 struct dma_chan *chan;
691 struct dma_slave_config cfg;
692 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx";
695 chan = dma_request_chan(dev, chan_name);
697 dev_dbg(dev, "request_channel failed for %s (%ld)\n",
698 chan_name, PTR_ERR(chan));
702 memset(&cfg, 0, sizeof(cfg));
704 if (dir == DMA_MEM_TO_DEV) {
705 cfg.dst_addr = port_addr;
706 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
708 cfg.src_addr = port_addr;
709 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
712 ret = dmaengine_slave_config(chan, &cfg);
714 dev_dbg(dev, "slave_config failed for %s (%d)\n",
716 dma_release_channel(chan);
720 dev_dbg(dev, "got DMA channel for %s\n", chan_name);
724 static void rcar_i2c_request_dma(struct rcar_i2c_priv *priv,
727 struct device *dev = rcar_i2c_priv_to_dev(priv);
729 struct dma_chan *chan;
730 enum dma_transfer_direction dir;
732 read = msg->flags & I2C_M_RD;
734 chan = read ? priv->dma_rx : priv->dma_tx;
735 if (PTR_ERR(chan) != -EPROBE_DEFER)
738 dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
739 chan = rcar_i2c_request_dma_chan(dev, dir, priv->res->start + ICRXTX);
747 static void rcar_i2c_release_dma(struct rcar_i2c_priv *priv)
749 if (!IS_ERR(priv->dma_tx)) {
750 dma_release_channel(priv->dma_tx);
751 priv->dma_tx = ERR_PTR(-EPROBE_DEFER);
754 if (!IS_ERR(priv->dma_rx)) {
755 dma_release_channel(priv->dma_rx);
756 priv->dma_rx = ERR_PTR(-EPROBE_DEFER);
760 /* I2C is a special case, we need to poll the status of a reset */
761 static int rcar_i2c_do_reset(struct rcar_i2c_priv *priv)
765 ret = reset_control_reset(priv->rstc);
769 for (i = 0; i < LOOP_TIMEOUT; i++) {
770 ret = reset_control_status(priv->rstc);
779 static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
780 struct i2c_msg *msgs,
783 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
784 struct device *dev = rcar_i2c_priv_to_dev(priv);
788 pm_runtime_get_sync(dev);
790 /* Check bus state before init otherwise bus busy info will be lost */
791 ret = rcar_i2c_bus_barrier(priv);
795 /* Gen3 needs a reset before allowing RXDMA once */
796 if (priv->devtype == I2C_RCAR_GEN3) {
797 priv->flags |= ID_P_NO_RXDMA;
798 if (!IS_ERR(priv->rstc)) {
799 ret = rcar_i2c_do_reset(priv);
801 priv->flags &= ~ID_P_NO_RXDMA;
807 for (i = 0; i < num; i++)
808 rcar_i2c_request_dma(priv, msgs + i);
810 /* init first message */
812 priv->msgs_left = num;
813 priv->flags = (priv->flags & ID_P_MASK) | ID_FIRST_MSG;
814 rcar_i2c_prepare_msg(priv);
816 time_left = wait_event_timeout(priv->wait, priv->flags & ID_DONE,
817 num * adap->timeout);
819 /* cleanup DMA if it couldn't complete properly due to an error */
820 if (priv->dma_direction != DMA_NONE)
821 rcar_i2c_cleanup_dma(priv);
826 } else if (priv->flags & ID_NACK) {
828 } else if (priv->flags & ID_ARBLOST) {
831 ret = num - priv->msgs_left; /* The number of transfer */
836 if (ret < 0 && ret != -ENXIO)
837 dev_err(dev, "error %d : %x\n", ret, priv->flags);
842 static int rcar_reg_slave(struct i2c_client *slave)
844 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
849 if (slave->flags & I2C_CLIENT_TEN)
850 return -EAFNOSUPPORT;
852 /* Keep device active for slave address detection logic */
853 pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv));
856 rcar_i2c_write(priv, ICSAR, slave->addr);
857 rcar_i2c_write(priv, ICSSR, 0);
858 rcar_i2c_write(priv, ICSIER, SAR);
859 rcar_i2c_write(priv, ICSCR, SIE | SDBS);
864 static int rcar_unreg_slave(struct i2c_client *slave)
866 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
868 WARN_ON(!priv->slave);
870 /* ensure no irq is running before clearing ptr */
871 disable_irq(priv->irq);
872 rcar_i2c_write(priv, ICSIER, 0);
873 rcar_i2c_write(priv, ICSSR, 0);
874 enable_irq(priv->irq);
875 rcar_i2c_write(priv, ICSCR, SDBS);
876 rcar_i2c_write(priv, ICSAR, 0); /* Gen2: must be 0 if not using slave */
880 pm_runtime_put(rcar_i2c_priv_to_dev(priv));
885 static u32 rcar_i2c_func(struct i2c_adapter *adap)
889 * I2C_SMBUS_QUICK (setting FSB during START didn't work)
890 * I2C_M_NOSTART (automatically sends address after START)
891 * I2C_M_IGNORE_NAK (automatically sends STOP after NAK)
893 return I2C_FUNC_I2C | I2C_FUNC_SLAVE |
894 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
897 static const struct i2c_algorithm rcar_i2c_algo = {
898 .master_xfer = rcar_i2c_master_xfer,
899 .functionality = rcar_i2c_func,
900 .reg_slave = rcar_reg_slave,
901 .unreg_slave = rcar_unreg_slave,
904 static const struct i2c_adapter_quirks rcar_i2c_quirks = {
905 .flags = I2C_AQ_NO_ZERO_LEN,
908 static const struct of_device_id rcar_i2c_dt_ids[] = {
909 { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 },
910 { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 },
911 { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 },
912 { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 },
913 { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 },
914 { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 },
915 { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 },
916 { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 },
917 { .compatible = "renesas,i2c-r8a7796", .data = (void *)I2C_RCAR_GEN3 },
918 { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 }, /* Deprecated */
919 { .compatible = "renesas,rcar-gen1-i2c", .data = (void *)I2C_RCAR_GEN1 },
920 { .compatible = "renesas,rcar-gen2-i2c", .data = (void *)I2C_RCAR_GEN2 },
921 { .compatible = "renesas,rcar-gen3-i2c", .data = (void *)I2C_RCAR_GEN3 },
924 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);
926 static int rcar_i2c_probe(struct platform_device *pdev)
928 struct rcar_i2c_priv *priv;
929 struct i2c_adapter *adap;
930 struct device *dev = &pdev->dev;
933 /* Otherwise logic will break because some bytes must always use PIO */
934 BUILD_BUG_ON_MSG(RCAR_MIN_DMA_LEN < 3, "Invalid min DMA length");
936 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
940 priv->clk = devm_clk_get(dev, NULL);
941 if (IS_ERR(priv->clk)) {
942 dev_err(dev, "cannot get clock\n");
943 return PTR_ERR(priv->clk);
946 priv->io = devm_platform_get_and_ioremap_resource(pdev, 0, &priv->res);
947 if (IS_ERR(priv->io))
948 return PTR_ERR(priv->io);
950 priv->devtype = (enum rcar_i2c_type)of_device_get_match_data(dev);
951 init_waitqueue_head(&priv->wait);
955 adap->algo = &rcar_i2c_algo;
956 adap->class = I2C_CLASS_DEPRECATED;
958 adap->dev.parent = dev;
959 adap->dev.of_node = dev->of_node;
960 adap->bus_recovery_info = &rcar_i2c_bri;
961 adap->quirks = &rcar_i2c_quirks;
962 i2c_set_adapdata(adap, priv);
963 strlcpy(adap->name, pdev->name, sizeof(adap->name));
966 sg_init_table(&priv->sg, 1);
967 priv->dma_direction = DMA_NONE;
968 priv->dma_rx = priv->dma_tx = ERR_PTR(-EPROBE_DEFER);
970 /* Activate device for clock calculation */
971 pm_runtime_enable(dev);
972 pm_runtime_get_sync(dev);
973 ret = rcar_i2c_clock_calculate(priv);
977 rcar_i2c_write(priv, ICSAR, 0); /* Gen2: must be 0 if not using slave */
979 if (priv->devtype == I2C_RCAR_GEN3) {
980 priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
981 if (!IS_ERR(priv->rstc)) {
982 ret = reset_control_status(priv->rstc);
984 priv->rstc = ERR_PTR(-ENOTSUPP);
988 /* Stay always active when multi-master to keep arbitration working */
989 if (of_property_read_bool(dev->of_node, "multi-master"))
990 priv->flags |= ID_P_PM_BLOCKED;
995 priv->irq = platform_get_irq(pdev, 0);
996 ret = devm_request_irq(dev, priv->irq, rcar_i2c_irq, 0, dev_name(dev), priv);
998 dev_err(dev, "cannot get irq %d\n", priv->irq);
1002 platform_set_drvdata(pdev, priv);
1004 ret = i2c_add_numbered_adapter(adap);
1006 goto out_pm_disable;
1008 dev_info(dev, "probed\n");
1013 pm_runtime_put(dev);
1015 pm_runtime_disable(dev);
1019 static int rcar_i2c_remove(struct platform_device *pdev)
1021 struct rcar_i2c_priv *priv = platform_get_drvdata(pdev);
1022 struct device *dev = &pdev->dev;
1024 i2c_del_adapter(&priv->adap);
1025 rcar_i2c_release_dma(priv);
1026 if (priv->flags & ID_P_PM_BLOCKED)
1027 pm_runtime_put(dev);
1028 pm_runtime_disable(dev);
1033 #ifdef CONFIG_PM_SLEEP
1034 static int rcar_i2c_suspend(struct device *dev)
1036 struct rcar_i2c_priv *priv = dev_get_drvdata(dev);
1038 i2c_mark_adapter_suspended(&priv->adap);
1042 static int rcar_i2c_resume(struct device *dev)
1044 struct rcar_i2c_priv *priv = dev_get_drvdata(dev);
1046 i2c_mark_adapter_resumed(&priv->adap);
1050 static const struct dev_pm_ops rcar_i2c_pm_ops = {
1051 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rcar_i2c_suspend, rcar_i2c_resume)
1054 #define DEV_PM_OPS (&rcar_i2c_pm_ops)
1056 #define DEV_PM_OPS NULL
1057 #endif /* CONFIG_PM_SLEEP */
1059 static struct platform_driver rcar_i2c_driver = {
1062 .of_match_table = rcar_i2c_dt_ids,
1065 .probe = rcar_i2c_probe,
1066 .remove = rcar_i2c_remove,
1069 module_platform_driver(rcar_i2c_driver);
1071 MODULE_LICENSE("GPL v2");
1072 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver");
1073 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");