drivers/i2c/busses/i2c-qcom-geni.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
   3
   4 #include <linux/acpi.h>
   5 #include <linux/clk.h>
   6 #include <linux/dma-mapping.h>
   7 #include <linux/err.h>
   8 #include <linux/i2c.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/io.h>
  11 #include <linux/module.h>
  12 #include <linux/of.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/qcom-geni-se.h>
  16 #include <linux/spinlock.h>
  17
  18 #define SE_I2C_TX_TRANS_LEN             0x26c
  19 #define SE_I2C_RX_TRANS_LEN             0x270
  20 #define SE_I2C_SCL_COUNTERS             0x278
  21
  22 #define SE_I2C_ERR  (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |\
  23                         M_GP_IRQ_1_EN | M_GP_IRQ_3_EN | M_GP_IRQ_4_EN)
  24 #define SE_I2C_ABORT            BIT(1)
  25
  26 /* M_CMD OP codes for I2C */
  27 #define I2C_WRITE               0x1
  28 #define I2C_READ                0x2
  29 #define I2C_WRITE_READ          0x3
  30 #define I2C_ADDR_ONLY           0x4
  31 #define I2C_BUS_CLEAR           0x6
  32 #define I2C_STOP_ON_BUS         0x7
  33 /* M_CMD params for I2C */
  34 #define PRE_CMD_DELAY           BIT(0)
  35 #define TIMESTAMP_BEFORE        BIT(1)
  36 #define STOP_STRETCH            BIT(2)
  37 #define TIMESTAMP_AFTER         BIT(3)
  38 #define POST_COMMAND_DELAY      BIT(4)
  39 #define IGNORE_ADD_NACK         BIT(6)
  40 #define READ_FINISHED_WITH_ACK  BIT(7)
  41 #define BYPASS_ADDR_PHASE       BIT(8)
  42 #define SLV_ADDR_MSK            GENMASK(15, 9)
  43 #define SLV_ADDR_SHFT           9
  44 /* I2C SCL COUNTER fields */
  45 #define HIGH_COUNTER_MSK        GENMASK(29, 20)
  46 #define HIGH_COUNTER_SHFT       20
  47 #define LOW_COUNTER_MSK         GENMASK(19, 10)
  48 #define LOW_COUNTER_SHFT        10
  49 #define CYCLE_COUNTER_MSK       GENMASK(9, 0)
  50
  51 enum geni_i2c_err_code {
  52         GP_IRQ0,
  53         NACK,
  54         GP_IRQ2,
  55         BUS_PROTO,
  56         ARB_LOST,
  57         GP_IRQ5,
  58         GENI_OVERRUN,
  59         GENI_ILLEGAL_CMD,
  60         GENI_ABORT_DONE,
  61         GENI_TIMEOUT,
  62 };
  63
  64 #define DM_I2C_CB_ERR           ((BIT(NACK) | BIT(BUS_PROTO) | BIT(ARB_LOST)) \
  65                                                                         << 5)
  66
  67 #define I2C_AUTO_SUSPEND_DELAY  250
  68 #define KHZ(freq)               (1000 * freq)
  69 #define PACKING_BYTES_PW        4
  70
  71 #define ABORT_TIMEOUT           HZ
  72 #define XFER_TIMEOUT            HZ
  73 #define RST_TIMEOUT             HZ
  74
  75 struct geni_i2c_dev {
  76         struct geni_se se;
  77         u32 tx_wm;
  78         int irq;
  79         int err;
  80         struct i2c_adapter adap;
  81         struct completion done;
  82         struct i2c_msg *cur;
  83         int cur_wr;
  84         int cur_rd;
  85         spinlock_t lock;
  86         u32 clk_freq_out;
  87         const struct geni_i2c_clk_fld *clk_fld;
  88         int suspended;
  89 };
  90
  91 struct geni_i2c_err_log {
  92         int err;
  93         const char *msg;
  94 };
  95
  96 static const struct geni_i2c_err_log gi2c_log[] = {
  97         [GP_IRQ0] = {-EIO, "Unknown I2C err GP_IRQ0"},
  98         [NACK] = {-ENXIO, "NACK: slv unresponsive, check its power/reset-ln"},
  99         [GP_IRQ2] = {-EIO, "Unknown I2C err GP IRQ2"},
 100         [BUS_PROTO] = {-EPROTO, "Bus proto err, noisy/unepxected start/stop"},
 101         [ARB_LOST] = {-EAGAIN, "Bus arbitration lost, clock line undriveable"},
 102         [GP_IRQ5] = {-EIO, "Unknown I2C err GP IRQ5"},
 103         [GENI_OVERRUN] = {-EIO, "Cmd overrun, check GENI cmd-state machine"},
 104         [GENI_ILLEGAL_CMD] = {-EIO, "Illegal cmd, check GENI cmd-state machine"},
 105         [GENI_ABORT_DONE] = {-ETIMEDOUT, "Abort after timeout successful"},
 106         [GENI_TIMEOUT] = {-ETIMEDOUT, "I2C TXN timed out"},
 107 };
 108
 109 struct geni_i2c_clk_fld {
 110         u32     clk_freq_out;
 111         u8      clk_div;
 112         u8      t_high_cnt;
 113         u8      t_low_cnt;
 114         u8      t_cycle_cnt;
 115 };
 116
 117 /*
 118  * Hardware uses the underlying formula to calculate time periods of
 119  * SCL clock cycle. Firmware uses some additional cycles excluded from the
 120  * below formula and it is confirmed that the time periods are within
 121  * specification limits.
 122  *
 123  * time of high period of SCL: t_high = (t_high_cnt * clk_div) / source_clock
 124  * time of low period of SCL: t_low = (t_low_cnt * clk_div) / source_clock
 125  * time of full period of SCL: t_cycle = (t_cycle_cnt * clk_div) / source_clock
 126  * clk_freq_out = t / t_cycle
 127  * source_clock = 19.2 MHz
 128  */
 129 static const struct geni_i2c_clk_fld geni_i2c_clk_map[] = {
 130         {KHZ(100), 7, 10, 11, 26},
 131         {KHZ(400), 2,  5, 12, 24},
 132         {KHZ(1000), 1, 3,  9, 18},
 133 };
 134
 135 static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c)
 136 {
 137         int i;
 138         const struct geni_i2c_clk_fld *itr = geni_i2c_clk_map;
 139
 140         for (i = 0; i < ARRAY_SIZE(geni_i2c_clk_map); i++, itr++) {
 141                 if (itr->clk_freq_out == gi2c->clk_freq_out) {
 142                         gi2c->clk_fld = itr;
 143                         return 0;
 144                 }
 145         }
 146         return -EINVAL;
 147 }
 148
 149 static void qcom_geni_i2c_conf(struct geni_i2c_dev *gi2c)
 150 {
 151         const struct geni_i2c_clk_fld *itr = gi2c->clk_fld;
 152         u32 val;
 153
 154         writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL);
 155
 156         val = (itr->clk_div << CLK_DIV_SHFT) | SER_CLK_EN;
 157         writel_relaxed(val, gi2c->se.base + GENI_SER_M_CLK_CFG);
 158
 159         val = itr->t_high_cnt << HIGH_COUNTER_SHFT;
 160         val |= itr->t_low_cnt << LOW_COUNTER_SHFT;
 161         val |= itr->t_cycle_cnt;
 162         writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS);
 163 }
 164
 165 static void geni_i2c_err_misc(struct geni_i2c_dev *gi2c)
 166 {
 167         u32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0);
 168         u32 m_stat = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS);
 169         u32 geni_s = readl_relaxed(gi2c->se.base + SE_GENI_STATUS);
 170         u32 geni_ios = readl_relaxed(gi2c->se.base + SE_GENI_IOS);
 171         u32 dma = readl_relaxed(gi2c->se.base + SE_GENI_DMA_MODE_EN);
 172         u32 rx_st, tx_st;
 173
 174         if (dma) {
 175                 rx_st = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT);
 176                 tx_st = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT);
 177         } else {
 178                 rx_st = readl_relaxed(gi2c->se.base + SE_GENI_RX_FIFO_STATUS);
 179                 tx_st = readl_relaxed(gi2c->se.base + SE_GENI_TX_FIFO_STATUS);
 180         }
 181         dev_dbg(gi2c->se.dev, "DMA:%d tx_stat:0x%x, rx_stat:0x%x, irq-stat:0x%x\n",
 182                 dma, tx_st, rx_st, m_stat);
 183         dev_dbg(gi2c->se.dev, "m_cmd:0x%x, geni_status:0x%x, geni_ios:0x%x\n",
 184                 m_cmd, geni_s, geni_ios);
 185 }
 186
 187 static void geni_i2c_err(struct geni_i2c_dev *gi2c, int err)
 188 {
 189         if (!gi2c->err)
 190                 gi2c->err = gi2c_log[err].err;
 191         if (gi2c->cur)
 192                 dev_dbg(gi2c->se.dev, "len:%d, slv-addr:0x%x, RD/WR:%d\n",
 193                         gi2c->cur->len, gi2c->cur->addr, gi2c->cur->flags);
 194
 195         if (err != NACK && err != GENI_ABORT_DONE) {
 196                 dev_err(gi2c->se.dev, "%s\n", gi2c_log[err].msg);
 197                 geni_i2c_err_misc(gi2c);
 198         }
 199 }
 200
 201 static irqreturn_t geni_i2c_irq(int irq, void *dev)
 202 {
 203         struct geni_i2c_dev *gi2c = dev;
 204         void __iomem *base = gi2c->se.base;
 205         int j, p;
 206         u32 m_stat;
 207         u32 rx_st;
 208         u32 dm_tx_st;
 209         u32 dm_rx_st;
 210         u32 dma;
 211         u32 val;
 212         struct i2c_msg *cur;
 213
 214         spin_lock(&gi2c->lock);
 215         m_stat = readl_relaxed(base + SE_GENI_M_IRQ_STATUS);
 216         rx_st = readl_relaxed(base + SE_GENI_RX_FIFO_STATUS);
 217         dm_tx_st = readl_relaxed(base + SE_DMA_TX_IRQ_STAT);
 218         dm_rx_st = readl_relaxed(base + SE_DMA_RX_IRQ_STAT);
 219         dma = readl_relaxed(base + SE_GENI_DMA_MODE_EN);
 220         cur = gi2c->cur;
 221
 222         if (!cur ||
 223             m_stat & (M_CMD_FAILURE_EN | M_CMD_ABORT_EN) ||
 224             dm_rx_st & (DM_I2C_CB_ERR)) {
 225                 if (m_stat & M_GP_IRQ_1_EN)
 226                         geni_i2c_err(gi2c, NACK);
 227                 if (m_stat & M_GP_IRQ_3_EN)
 228                         geni_i2c_err(gi2c, BUS_PROTO);
 229                 if (m_stat & M_GP_IRQ_4_EN)
 230                         geni_i2c_err(gi2c, ARB_LOST);
 231                 if (m_stat & M_CMD_OVERRUN_EN)
 232                         geni_i2c_err(gi2c, GENI_OVERRUN);
 233                 if (m_stat & M_ILLEGAL_CMD_EN)
 234                         geni_i2c_err(gi2c, GENI_ILLEGAL_CMD);
 235                 if (m_stat & M_CMD_ABORT_EN)
 236                         geni_i2c_err(gi2c, GENI_ABORT_DONE);
 237                 if (m_stat & M_GP_IRQ_0_EN)
 238                         geni_i2c_err(gi2c, GP_IRQ0);
 239
 240                 /* Disable the TX Watermark interrupt to stop TX */
 241                 if (!dma)
 242                         writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG);
 243         } else if (dma) {
 244                 dev_dbg(gi2c->se.dev, "i2c dma tx:0x%x, dma rx:0x%x\n",
 245                         dm_tx_st, dm_rx_st);
 246         } else if (cur->flags & I2C_M_RD &&
 247                    m_stat & (M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN)) {
 248                 u32 rxcnt = rx_st & RX_FIFO_WC_MSK;
 249
 250                 for (j = 0; j < rxcnt; j++) {
 251                         p = 0;
 252                         val = readl_relaxed(base + SE_GENI_RX_FIFOn);
 253                         while (gi2c->cur_rd < cur->len && p < sizeof(val)) {
 254                                 cur->buf[gi2c->cur_rd++] = val & 0xff;
 255                                 val >>= 8;
 256                                 p++;
 257                         }
 258                         if (gi2c->cur_rd == cur->len)
 259                                 break;
 260                 }
 261         } else if (!(cur->flags & I2C_M_RD) &&
 262                    m_stat & M_TX_FIFO_WATERMARK_EN) {
 263                 for (j = 0; j < gi2c->tx_wm; j++) {
 264                         u32 temp;
 265
 266                         val = 0;
 267                         p = 0;
 268                         while (gi2c->cur_wr < cur->len && p < sizeof(val)) {
 269                                 temp = cur->buf[gi2c->cur_wr++];
 270                                 val |= temp << (p * 8);
 271                                 p++;
 272                         }
 273                         writel_relaxed(val, base + SE_GENI_TX_FIFOn);
 274                         /* TX Complete, Disable the TX Watermark interrupt */
 275                         if (gi2c->cur_wr == cur->len) {
 276                                 writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG);
 277                                 break;
 278                         }
 279                 }
 280         }
 281
 282         if (m_stat)
 283                 writel_relaxed(m_stat, base + SE_GENI_M_IRQ_CLEAR);
 284
 285         if (dma && dm_tx_st)
 286                 writel_relaxed(dm_tx_st, base + SE_DMA_TX_IRQ_CLR);
 287         if (dma && dm_rx_st)
 288                 writel_relaxed(dm_rx_st, base + SE_DMA_RX_IRQ_CLR);
 289
 290         /* if this is err with done-bit not set, handle that through timeout. */
 291         if (m_stat & M_CMD_DONE_EN || m_stat & M_CMD_ABORT_EN ||
 292             dm_tx_st & TX_DMA_DONE || dm_tx_st & TX_RESET_DONE ||
 293             dm_rx_st & RX_DMA_DONE || dm_rx_st & RX_RESET_DONE)
 294                 complete(&gi2c->done);
 295
 296         spin_unlock(&gi2c->lock);
 297
 298         return IRQ_HANDLED;
 299 }
 300
 301 static void geni_i2c_abort_xfer(struct geni_i2c_dev *gi2c)
 302 {
 303         u32 val;
 304         unsigned long time_left = ABORT_TIMEOUT;
 305         unsigned long flags;
 306
 307         spin_lock_irqsave(&gi2c->lock, flags);
 308         geni_i2c_err(gi2c, GENI_TIMEOUT);
 309         gi2c->cur = NULL;
 310         geni_se_abort_m_cmd(&gi2c->se);
 311         spin_unlock_irqrestore(&gi2c->lock, flags);
 312         do {
 313                 time_left = wait_for_completion_timeout(&gi2c->done, time_left);
 314                 val = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS);
 315         } while (!(val & M_CMD_ABORT_EN) && time_left);
 316
 317         if (!(val & M_CMD_ABORT_EN))
 318                 dev_err(gi2c->se.dev, "Timeout abort_m_cmd\n");
 319 }
 320
 321 static void geni_i2c_rx_fsm_rst(struct geni_i2c_dev *gi2c)
 322 {
 323         u32 val;
 324         unsigned long time_left = RST_TIMEOUT;
 325
 326         writel_relaxed(1, gi2c->se.base + SE_DMA_RX_FSM_RST);
 327         do {
 328                 time_left = wait_for_completion_timeout(&gi2c->done, time_left);
 329                 val = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT);
 330         } while (!(val & RX_RESET_DONE) && time_left);
 331
 332         if (!(val & RX_RESET_DONE))
 333                 dev_err(gi2c->se.dev, "Timeout resetting RX_FSM\n");
 334 }
 335
 336 static void geni_i2c_tx_fsm_rst(struct geni_i2c_dev *gi2c)
 337 {
 338         u32 val;
 339         unsigned long time_left = RST_TIMEOUT;
 340
 341         writel_relaxed(1, gi2c->se.base + SE_DMA_TX_FSM_RST);
 342         do {
 343                 time_left = wait_for_completion_timeout(&gi2c->done, time_left);
 344                 val = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT);
 345         } while (!(val & TX_RESET_DONE) && time_left);
 346
 347         if (!(val & TX_RESET_DONE))
 348                 dev_err(gi2c->se.dev, "Timeout resetting TX_FSM\n");
 349 }
 350
 351 static int geni_i2c_rx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg,
 352                                 u32 m_param)
 353 {
 354         dma_addr_t rx_dma;
 355         unsigned long time_left;
 356         void *dma_buf = NULL;
 357         struct geni_se *se = &gi2c->se;
 358         size_t len = msg->len;
 359
 360         if (!of_machine_is_compatible("lenovo,yoga-c630"))
 361                 dma_buf = i2c_get_dma_safe_msg_buf(msg, 32);
 362
 363         if (dma_buf)
 364                 geni_se_select_mode(se, GENI_SE_DMA);
 365         else
 366                 geni_se_select_mode(se, GENI_SE_FIFO);
 367
 368         writel_relaxed(len, se->base + SE_I2C_RX_TRANS_LEN);
 369         geni_se_setup_m_cmd(se, I2C_READ, m_param);
 370
 371         if (dma_buf && geni_se_rx_dma_prep(se, dma_buf, len, &rx_dma)) {
 372                 geni_se_select_mode(se, GENI_SE_FIFO);
 373                 i2c_put_dma_safe_msg_buf(dma_buf, msg, false);
 374                 dma_buf = NULL;
 375         }
 376
 377         time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT);
 378         if (!time_left)
 379                 geni_i2c_abort_xfer(gi2c);
 380
 381         gi2c->cur_rd = 0;
 382         if (dma_buf) {
 383                 if (gi2c->err)
 384                         geni_i2c_rx_fsm_rst(gi2c);
 385                 geni_se_rx_dma_unprep(se, rx_dma, len);
 386                 i2c_put_dma_safe_msg_buf(dma_buf, msg, !gi2c->err);
 387         }
 388
 389         return gi2c->err;
 390 }
 391
 392 static int geni_i2c_tx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg,
 393                                 u32 m_param)
 394 {
 395         dma_addr_t tx_dma;
 396         unsigned long time_left;
 397         void *dma_buf = NULL;
 398         struct geni_se *se = &gi2c->se;
 399         size_t len = msg->len;
 400
 401         if (!of_machine_is_compatible("lenovo,yoga-c630"))
 402                 dma_buf = i2c_get_dma_safe_msg_buf(msg, 32);
 403
 404         if (dma_buf)
 405                 geni_se_select_mode(se, GENI_SE_DMA);
 406         else
 407                 geni_se_select_mode(se, GENI_SE_FIFO);
 408
 409         writel_relaxed(len, se->base + SE_I2C_TX_TRANS_LEN);
 410         geni_se_setup_m_cmd(se, I2C_WRITE, m_param);
 411
 412         if (dma_buf && geni_se_tx_dma_prep(se, dma_buf, len, &tx_dma)) {
 413                 geni_se_select_mode(se, GENI_SE_FIFO);
 414                 i2c_put_dma_safe_msg_buf(dma_buf, msg, false);
 415                 dma_buf = NULL;
 416         }
 417
 418         if (!dma_buf) /* Get FIFO IRQ */
 419                 writel_relaxed(1, se->base + SE_GENI_TX_WATERMARK_REG);
 420
 421         time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT);
 422         if (!time_left)
 423                 geni_i2c_abort_xfer(gi2c);
 424
 425         gi2c->cur_wr = 0;
 426         if (dma_buf) {
 427                 if (gi2c->err)
 428                         geni_i2c_tx_fsm_rst(gi2c);
 429                 geni_se_tx_dma_unprep(se, tx_dma, len);
 430                 i2c_put_dma_safe_msg_buf(dma_buf, msg, !gi2c->err);
 431         }
 432
 433         return gi2c->err;
 434 }
 435
 436 static int geni_i2c_xfer(struct i2c_adapter *adap,
 437                          struct i2c_msg msgs[],
 438                          int num)
 439 {
 440         struct geni_i2c_dev *gi2c = i2c_get_adapdata(adap);
 441         int i, ret;
 442
 443         gi2c->err = 0;
 444         reinit_completion(&gi2c->done);
 445         ret = pm_runtime_get_sync(gi2c->se.dev);
 446         if (ret < 0) {
 447                 dev_err(gi2c->se.dev, "error turning SE resources:%d\n", ret);
 448                 pm_runtime_put_noidle(gi2c->se.dev);
 449                 /* Set device in suspended since resume failed */
 450                 pm_runtime_set_suspended(gi2c->se.dev);
 451                 return ret;
 452         }
 453
 454         qcom_geni_i2c_conf(gi2c);
 455         for (i = 0; i < num; i++) {
 456                 u32 m_param = i < (num - 1) ? STOP_STRETCH : 0;
 457
 458                 m_param |= ((msgs[i].addr << SLV_ADDR_SHFT) & SLV_ADDR_MSK);
 459
 460                 gi2c->cur = &msgs[i];
 461                 if (msgs[i].flags & I2C_M_RD)
 462                         ret = geni_i2c_rx_one_msg(gi2c, &msgs[i], m_param);
 463                 else
 464                         ret = geni_i2c_tx_one_msg(gi2c, &msgs[i], m_param);
 465
 466                 if (ret)
 467                         break;
 468         }
 469         if (ret == 0)
 470                 ret = num;
 471
 472         pm_runtime_mark_last_busy(gi2c->se.dev);
 473         pm_runtime_put_autosuspend(gi2c->se.dev);
 474         gi2c->cur = NULL;
 475         gi2c->err = 0;
 476         return ret;
 477 }
 478
 479 static u32 geni_i2c_func(struct i2c_adapter *adap)
 480 {
 481         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 482 }
 483
 484 static const struct i2c_algorithm geni_i2c_algo = {
 485         .master_xfer    = geni_i2c_xfer,
 486         .functionality  = geni_i2c_func,
 487 };
 488
 489 #ifdef CONFIG_ACPI
 490 static const struct acpi_device_id geni_i2c_acpi_match[] = {
 491         { "QCOM0220"},
 492         { },
 493 };
 494 MODULE_DEVICE_TABLE(acpi, geni_i2c_acpi_match);
 495 #endif
 496
 497 static int geni_i2c_probe(struct platform_device *pdev)
 498 {
 499         struct geni_i2c_dev *gi2c;
 500         struct resource *res;
 501         u32 proto, tx_depth;
 502         int ret;
 503         struct device *dev = &pdev->dev;
 504
 505         gi2c = devm_kzalloc(dev, sizeof(*gi2c), GFP_KERNEL);
 506         if (!gi2c)
 507                 return -ENOMEM;
 508
 509         gi2c->se.dev = dev;
 510         gi2c->se.wrapper = dev_get_drvdata(dev->parent);
 511         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 512         gi2c->se.base = devm_ioremap_resource(dev, res);
 513         if (IS_ERR(gi2c->se.base))
 514                 return PTR_ERR(gi2c->se.base);
 515
 516         gi2c->se.clk = devm_clk_get(dev, "se");
 517         if (IS_ERR(gi2c->se.clk) && !has_acpi_companion(dev))
 518                 return PTR_ERR(gi2c->se.clk);
 519
 520         ret = device_property_read_u32(dev, "clock-frequency",
 521                                        &gi2c->clk_freq_out);
 522         if (ret) {
 523                 dev_info(dev, "Bus frequency not specified, default to 100kHz.\n");
 524                 gi2c->clk_freq_out = KHZ(100);
 525         }
 526
 527         if (has_acpi_companion(dev))
 528                 ACPI_COMPANION_SET(&gi2c->adap.dev, ACPI_COMPANION(dev));
 529
 530         gi2c->irq = platform_get_irq(pdev, 0);
 531         if (gi2c->irq < 0)
 532                 return gi2c->irq;
 533
 534         ret = geni_i2c_clk_map_idx(gi2c);
 535         if (ret) {
 536                 dev_err(dev, "Invalid clk frequency %d Hz: %d\n",
 537                         gi2c->clk_freq_out, ret);
 538                 return ret;
 539         }
 540
 541         gi2c->adap.algo = &geni_i2c_algo;
 542         init_completion(&gi2c->done);
 543         spin_lock_init(&gi2c->lock);
 544         platform_set_drvdata(pdev, gi2c);
 545         ret = devm_request_irq(dev, gi2c->irq, geni_i2c_irq, 0,
 546                                dev_name(dev), gi2c);
 547         if (ret) {
 548                 dev_err(dev, "Request_irq failed:%d: err:%d\n",
 549                         gi2c->irq, ret);
 550                 return ret;
 551         }
 552         /* Disable the interrupt so that the system can enter low-power mode */
 553         disable_irq(gi2c->irq);
 554         i2c_set_adapdata(&gi2c->adap, gi2c);
 555         gi2c->adap.dev.parent = dev;
 556         gi2c->adap.dev.of_node = dev->of_node;
 557         strlcpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name));
 558
 559         ret = geni_icc_get(&gi2c->se, "qup-memory");
 560         if (ret)
 561                 return ret;
 562         /*
 563          * Set the bus quota for core and cpu to a reasonable value for
 564          * register access.
 565          * Set quota for DDR based on bus speed.
 566          */
 567         gi2c->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
 568         gi2c->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
 569         gi2c->se.icc_paths[GENI_TO_DDR].avg_bw = Bps_to_icc(gi2c->clk_freq_out);
 570
 571         ret = geni_icc_set_bw(&gi2c->se);
 572         if (ret)
 573                 return ret;
 574
 575         ret = geni_se_resources_on(&gi2c->se);
 576         if (ret) {
 577                 dev_err(dev, "Error turning on resources %d\n", ret);
 578                 return ret;
 579         }
 580         proto = geni_se_read_proto(&gi2c->se);
 581         tx_depth = geni_se_get_tx_fifo_depth(&gi2c->se);
 582         if (proto != GENI_SE_I2C) {
 583                 dev_err(dev, "Invalid proto %d\n", proto);
 584                 geni_se_resources_off(&gi2c->se);
 585                 return -ENXIO;
 586         }
 587         gi2c->tx_wm = tx_depth - 1;
 588         geni_se_init(&gi2c->se, gi2c->tx_wm, tx_depth);
 589         geni_se_config_packing(&gi2c->se, BITS_PER_BYTE, PACKING_BYTES_PW,
 590                                                         true, true, true);
 591         ret = geni_se_resources_off(&gi2c->se);
 592         if (ret) {
 593                 dev_err(dev, "Error turning off resources %d\n", ret);
 594                 return ret;
 595         }
 596
 597         ret = geni_icc_disable(&gi2c->se);
 598         if (ret)
 599                 return ret;
 600
 601         dev_dbg(dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth);
 602
 603         gi2c->suspended = 1;
 604         pm_runtime_set_suspended(gi2c->se.dev);
 605         pm_runtime_set_autosuspend_delay(gi2c->se.dev, I2C_AUTO_SUSPEND_DELAY);
 606         pm_runtime_use_autosuspend(gi2c->se.dev);
 607         pm_runtime_enable(gi2c->se.dev);
 608
 609         ret = i2c_add_adapter(&gi2c->adap);
 610         if (ret) {
 611                 dev_err(dev, "Error adding i2c adapter %d\n", ret);
 612                 pm_runtime_disable(gi2c->se.dev);
 613                 return ret;
 614         }
 615
 616         dev_dbg(dev, "Geni-I2C adaptor successfully added\n");
 617
 618         return 0;
 619 }
 620
 621 static int geni_i2c_remove(struct platform_device *pdev)
 622 {
 623         struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev);
 624
 625         i2c_del_adapter(&gi2c->adap);
 626         pm_runtime_disable(gi2c->se.dev);
 627         return 0;
 628 }
 629
 630 static int __maybe_unused geni_i2c_runtime_suspend(struct device *dev)
 631 {
 632         int ret;
 633         struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
 634
 635         disable_irq(gi2c->irq);
 636         ret = geni_se_resources_off(&gi2c->se);
 637         if (ret) {
 638                 enable_irq(gi2c->irq);
 639                 return ret;
 640
 641         } else {
 642                 gi2c->suspended = 1;
 643         }
 644
 645         return geni_icc_disable(&gi2c->se);
 646 }
 647
 648 static int __maybe_unused geni_i2c_runtime_resume(struct device *dev)
 649 {
 650         int ret;
 651         struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
 652
 653         ret = geni_icc_enable(&gi2c->se);
 654         if (ret)
 655                 return ret;
 656
 657         ret = geni_se_resources_on(&gi2c->se);
 658         if (ret)
 659                 return ret;
 660
 661         enable_irq(gi2c->irq);
 662         gi2c->suspended = 0;
 663         return 0;
 664 }
 665
 666 static int __maybe_unused geni_i2c_suspend_noirq(struct device *dev)
 667 {
 668         struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
 669
 670         if (!gi2c->suspended) {
 671                 geni_i2c_runtime_suspend(dev);
 672                 pm_runtime_disable(dev);
 673                 pm_runtime_set_suspended(dev);
 674                 pm_runtime_enable(dev);
 675         }
 676         return 0;
 677 }
 678
 679 static const struct dev_pm_ops geni_i2c_pm_ops = {
 680         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(geni_i2c_suspend_noirq, NULL)
 681         SET_RUNTIME_PM_OPS(geni_i2c_runtime_suspend, geni_i2c_runtime_resume,
 682                                                                         NULL)
 683 };
 684
 685 static const struct of_device_id geni_i2c_dt_match[] = {
 686         { .compatible = "qcom,geni-i2c" },
 687         {}
 688 };
 689 MODULE_DEVICE_TABLE(of, geni_i2c_dt_match);
 690
 691 static struct platform_driver geni_i2c_driver = {
 692         .probe  = geni_i2c_probe,
 693         .remove = geni_i2c_remove,
 694         .driver = {
 695                 .name = "geni_i2c",
 696                 .pm = &geni_i2c_pm_ops,
 697                 .of_match_table = geni_i2c_dt_match,
 698                 .acpi_match_table = ACPI_PTR(geni_i2c_acpi_match),
 699         },
 700 };
 701
 702 module_platform_driver(geni_i2c_driver);
 703
 704 MODULE_DESCRIPTION("I2C Controller Driver for GENI based QUP cores");
 705 MODULE_LICENSE("GPL v2");