drivers/i2c/busses/i2c-pxa.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  i2c_adap_pxa.c
   4  *
   5  *  I2C adapter for the PXA I2C bus access.
   6  *
   7  *  Copyright (C) 2002 Intrinsyc Software Inc.
   8  *  Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
   9  *
  10  *  History:
  11  *    Apr 2002: Initial version [CS]
  12  *    Jun 2002: Properly separated algo/adap [FB]
  13  *    Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
  14  *    Jan 2003: added limited signal handling [Kai-Uwe Bloem]
  15  *    Sep 2004: Major rework to ensure efficient bus handling [RMK]
  16  *    Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
  17  *    Feb 2005: Rework slave mode handling [RMK]
  18  */
  19 #include <linux/clk.h>
  20 #include <linux/delay.h>
  21 #include <linux/err.h>
  22 #include <linux/errno.h>
  23 #include <linux/i2c.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/of.h>
  30 #include <linux/of_device.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/platform_data/i2c-pxa.h>
  33 #include <linux/slab.h>
  34
  35 /* I2C register field definitions */
  36 #define IBMR_SDAS       (1 << 0)
  37 #define IBMR_SCLS       (1 << 1)
  38
  39 #define ICR_START       (1 << 0)           /* start bit */
  40 #define ICR_STOP        (1 << 1)           /* stop bit */
  41 #define ICR_ACKNAK      (1 << 2)           /* send ACK(0) or NAK(1) */
  42 #define ICR_TB          (1 << 3)           /* transfer byte bit */
  43 #define ICR_MA          (1 << 4)           /* master abort */
  44 #define ICR_SCLE        (1 << 5)           /* master clock enable */
  45 #define ICR_IUE         (1 << 6)           /* unit enable */
  46 #define ICR_GCD         (1 << 7)           /* general call disable */
  47 #define ICR_ITEIE       (1 << 8)           /* enable tx interrupts */
  48 #define ICR_IRFIE       (1 << 9)           /* enable rx interrupts */
  49 #define ICR_BEIE        (1 << 10)          /* enable bus error ints */
  50 #define ICR_SSDIE       (1 << 11)          /* slave STOP detected int enable */
  51 #define ICR_ALDIE       (1 << 12)          /* enable arbitration interrupt */
  52 #define ICR_SADIE       (1 << 13)          /* slave address detected int enable */
  53 #define ICR_UR          (1 << 14)          /* unit reset */
  54 #define ICR_FM          (1 << 15)          /* fast mode */
  55 #define ICR_HS          (1 << 16)          /* High Speed mode */
  56 #define ICR_A3700_FM    (1 << 16)          /* fast mode for armada-3700 */
  57 #define ICR_A3700_HS    (1 << 17)          /* high speed mode for armada-3700 */
  58 #define ICR_GPIOEN      (1 << 19)          /* enable GPIO mode for SCL in HS */
  59
  60 #define ISR_RWM         (1 << 0)           /* read/write mode */
  61 #define ISR_ACKNAK      (1 << 1)           /* ack/nak status */
  62 #define ISR_UB          (1 << 2)           /* unit busy */
  63 #define ISR_IBB         (1 << 3)           /* bus busy */
  64 #define ISR_SSD         (1 << 4)           /* slave stop detected */
  65 #define ISR_ALD         (1 << 5)           /* arbitration loss detected */
  66 #define ISR_ITE         (1 << 6)           /* tx buffer empty */
  67 #define ISR_IRF         (1 << 7)           /* rx buffer full */
  68 #define ISR_GCAD        (1 << 8)           /* general call address detected */
  69 #define ISR_SAD         (1 << 9)           /* slave address detected */
  70 #define ISR_BED         (1 << 10)          /* bus error no ACK/NAK */
  71
  72 #define ILCR_SLV_SHIFT          0
  73 #define ILCR_SLV_MASK           (0x1FF << ILCR_SLV_SHIFT)
  74 #define ILCR_FLV_SHIFT          9
  75 #define ILCR_FLV_MASK           (0x1FF << ILCR_FLV_SHIFT)
  76 #define ILCR_HLVL_SHIFT         18
  77 #define ILCR_HLVL_MASK          (0x1FF << ILCR_HLVL_SHIFT)
  78 #define ILCR_HLVH_SHIFT         27
  79 #define ILCR_HLVH_MASK          (0x1F << ILCR_HLVH_SHIFT)
  80
  81 #define IWCR_CNT_SHIFT          0
  82 #define IWCR_CNT_MASK           (0x1F << IWCR_CNT_SHIFT)
  83 #define IWCR_HS_CNT1_SHIFT      5
  84 #define IWCR_HS_CNT1_MASK       (0x1F << IWCR_HS_CNT1_SHIFT)
  85 #define IWCR_HS_CNT2_SHIFT      10
  86 #define IWCR_HS_CNT2_MASK       (0x1F << IWCR_HS_CNT2_SHIFT)
  87
  88 /* need a longer timeout if we're dealing with the fact we may well be
  89  * looking at a multi-master environment
  90  */
  91 #define DEF_TIMEOUT             32
  92
  93 #define BUS_ERROR               (-EREMOTEIO)
  94 #define XFER_NAKED              (-ECONNREFUSED)
  95 #define I2C_RETRY               (-2000) /* an error has occurred retry transmit */
  96
  97 /* ICR initialize bit values
  98  *
  99  * 15 FM     0 (100 kHz operation)
 100  * 14 UR     0 (No unit reset)
 101  * 13 SADIE  0 (Disables the unit from interrupting on slave addresses
 102  *              matching its slave address)
 103  * 12 ALDIE  0 (Disables the unit from interrupt when it loses arbitration
 104  *              in master mode)
 105  * 11 SSDIE  0 (Disables interrupts from a slave stop detected, in slave mode)
 106  * 10 BEIE   1 (Enable interrupts from detected bus errors, no ACK sent)
 107  *  9 IRFIE  1 (Enable interrupts from full buffer received)
 108  *  8 ITEIE  1 (Enables the I2C unit to interrupt when transmit buffer empty)
 109  *  7 GCD    1 (Disables i2c unit response to general call messages as a slave)
 110  *  6 IUE    0 (Disable unit until we change settings)
 111  *  5 SCLE   1 (Enables the i2c clock output for master mode (drives SCL)
 112  *  4 MA     0 (Only send stop with the ICR stop bit)
 113  *  3 TB     0 (We are not transmitting a byte initially)
 114  *  2 ACKNAK 0 (Send an ACK after the unit receives a byte)
 115  *  1 STOP   0 (Do not send a STOP)
 116  *  0 START  0 (Do not send a START)
 117  */
 118 #define I2C_ICR_INIT    (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
 119
 120 /* I2C status register init values
 121  *
 122  * 10 BED    1 (Clear bus error detected)
 123  *  9 SAD    1 (Clear slave address detected)
 124  *  7 IRF    1 (Clear IDBR Receive Full)
 125  *  6 ITE    1 (Clear IDBR Transmit Empty)
 126  *  5 ALD    1 (Clear Arbitration Loss Detected)
 127  *  4 SSD    1 (Clear Slave Stop Detected)
 128  */
 129 #define I2C_ISR_INIT    0x7FF  /* status register init */
 130
 131 struct pxa_reg_layout {
 132         u32 ibmr;
 133         u32 idbr;
 134         u32 icr;
 135         u32 isr;
 136         u32 isar;
 137         u32 ilcr;
 138         u32 iwcr;
 139         u32 fm;
 140         u32 hs;
 141 };
 142
 143 enum pxa_i2c_types {
 144         REGS_PXA2XX,
 145         REGS_PXA3XX,
 146         REGS_CE4100,
 147         REGS_PXA910,
 148         REGS_A3700,
 149 };
 150
 151 /* I2C register layout definitions */
 152 static struct pxa_reg_layout pxa_reg_layout[] = {
 153         [REGS_PXA2XX] = {
 154                 .ibmr = 0x00,
 155                 .idbr = 0x08,
 156                 .icr =  0x10,
 157                 .isr =  0x18,
 158                 .isar = 0x20,
 159                 .fm = ICR_FM,
 160                 .hs = ICR_HS,
 161         },
 162         [REGS_PXA3XX] = {
 163                 .ibmr = 0x00,
 164                 .idbr = 0x04,
 165                 .icr =  0x08,
 166                 .isr =  0x0c,
 167                 .isar = 0x10,
 168                 .fm = ICR_FM,
 169                 .hs = ICR_HS,
 170         },
 171         [REGS_CE4100] = {
 172                 .ibmr = 0x14,
 173                 .idbr = 0x0c,
 174                 .icr =  0x00,
 175                 .isr =  0x04,
 176                 /* no isar register */
 177                 .fm = ICR_FM,
 178                 .hs = ICR_HS,
 179         },
 180         [REGS_PXA910] = {
 181                 .ibmr = 0x00,
 182                 .idbr = 0x08,
 183                 .icr =  0x10,
 184                 .isr =  0x18,
 185                 .isar = 0x20,
 186                 .ilcr = 0x28,
 187                 .iwcr = 0x30,
 188                 .fm = ICR_FM,
 189                 .hs = ICR_HS,
 190         },
 191         [REGS_A3700] = {
 192                 .ibmr = 0x00,
 193                 .idbr = 0x04,
 194                 .icr =  0x08,
 195                 .isr =  0x0c,
 196                 .isar = 0x10,
 197                 .fm = ICR_A3700_FM,
 198                 .hs = ICR_A3700_HS,
 199         },
 200 };
 201
 202 static const struct of_device_id i2c_pxa_dt_ids[] = {
 203         { .compatible = "mrvl,pxa-i2c", .data = (void *)REGS_PXA2XX },
 204         { .compatible = "mrvl,pwri2c", .data = (void *)REGS_PXA3XX },
 205         { .compatible = "mrvl,mmp-twsi", .data = (void *)REGS_PXA910 },
 206         { .compatible = "marvell,armada-3700-i2c", .data = (void *)REGS_A3700 },
 207         {}
 208 };
 209 MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids);
 210
 211 static const struct platform_device_id i2c_pxa_id_table[] = {
 212         { "pxa2xx-i2c",         REGS_PXA2XX },
 213         { "pxa3xx-pwri2c",      REGS_PXA3XX },
 214         { "ce4100-i2c",         REGS_CE4100 },
 215         { "pxa910-i2c",         REGS_PXA910 },
 216         { "armada-3700-i2c",    REGS_A3700  },
 217         { },
 218 };
 219 MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table);
 220
 221 struct pxa_i2c {
 222         spinlock_t              lock;
 223         wait_queue_head_t       wait;
 224         struct i2c_msg          *msg;
 225         unsigned int            msg_num;
 226         unsigned int            msg_idx;
 227         unsigned int            msg_ptr;
 228         unsigned int            slave_addr;
 229         unsigned int            req_slave_addr;
 230
 231         struct i2c_adapter      adap;
 232         struct clk              *clk;
 233 #ifdef CONFIG_I2C_PXA_SLAVE
 234         struct i2c_client       *slave;
 235 #endif
 236
 237         unsigned int            irqlogidx;
 238         u32                     isrlog[32];
 239         u32                     icrlog[32];
 240
 241         void __iomem            *reg_base;
 242         void __iomem            *reg_ibmr;
 243         void __iomem            *reg_idbr;
 244         void __iomem            *reg_icr;
 245         void __iomem            *reg_isr;
 246         void __iomem            *reg_isar;
 247         void __iomem            *reg_ilcr;
 248         void __iomem            *reg_iwcr;
 249
 250         unsigned long           iobase;
 251         unsigned long           iosize;
 252
 253         int                     irq;
 254         unsigned int            use_pio :1;
 255         unsigned int            fast_mode :1;
 256         unsigned int            high_mode:1;
 257         unsigned char           master_code;
 258         unsigned long           rate;
 259         bool                    highmode_enter;
 260         u32                     fm_mask;
 261         u32                     hs_mask;
 262 };
 263
 264 #define _IBMR(i2c)      ((i2c)->reg_ibmr)
 265 #define _IDBR(i2c)      ((i2c)->reg_idbr)
 266 #define _ICR(i2c)       ((i2c)->reg_icr)
 267 #define _ISR(i2c)       ((i2c)->reg_isr)
 268 #define _ISAR(i2c)      ((i2c)->reg_isar)
 269 #define _ILCR(i2c)      ((i2c)->reg_ilcr)
 270 #define _IWCR(i2c)      ((i2c)->reg_iwcr)
 271
 272 /*
 273  * I2C Slave mode address
 274  */
 275 #define I2C_PXA_SLAVE_ADDR      0x1
 276
 277 #ifdef DEBUG
 278
 279 struct bits {
 280         u32     mask;
 281         const char *set;
 282         const char *unset;
 283 };
 284 #define PXA_BIT(m, s, u)        { .mask = m, .set = s, .unset = u }
 285
 286 static inline void
 287 decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
 288 {
 289         printk("%s %08x:", prefix, val);
 290         while (num--) {
 291                 const char *str = val & bits->mask ? bits->set : bits->unset;
 292                 if (str)
 293                         pr_cont(" %s", str);
 294                 bits++;
 295         }
 296         pr_cont("\n");
 297 }
 298
 299 static const struct bits isr_bits[] = {
 300         PXA_BIT(ISR_RWM,        "RX",           "TX"),
 301         PXA_BIT(ISR_ACKNAK,     "NAK",          "ACK"),
 302         PXA_BIT(ISR_UB,         "Bsy",          "Rdy"),
 303         PXA_BIT(ISR_IBB,        "BusBsy",       "BusRdy"),
 304         PXA_BIT(ISR_SSD,        "SlaveStop",    NULL),
 305         PXA_BIT(ISR_ALD,        "ALD",          NULL),
 306         PXA_BIT(ISR_ITE,        "TxEmpty",      NULL),
 307         PXA_BIT(ISR_IRF,        "RxFull",       NULL),
 308         PXA_BIT(ISR_GCAD,       "GenCall",      NULL),
 309         PXA_BIT(ISR_SAD,        "SlaveAddr",    NULL),
 310         PXA_BIT(ISR_BED,        "BusErr",       NULL),
 311 };
 312
 313 static void decode_ISR(unsigned int val)
 314 {
 315         decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
 316 }
 317
 318 static const struct bits icr_bits[] = {
 319         PXA_BIT(ICR_START,  "START",    NULL),
 320         PXA_BIT(ICR_STOP,   "STOP",     NULL),
 321         PXA_BIT(ICR_ACKNAK, "ACKNAK",   NULL),
 322         PXA_BIT(ICR_TB,     "TB",       NULL),
 323         PXA_BIT(ICR_MA,     "MA",       NULL),
 324         PXA_BIT(ICR_SCLE,   "SCLE",     "scle"),
 325         PXA_BIT(ICR_IUE,    "IUE",      "iue"),
 326         PXA_BIT(ICR_GCD,    "GCD",      NULL),
 327         PXA_BIT(ICR_ITEIE,  "ITEIE",    NULL),
 328         PXA_BIT(ICR_IRFIE,  "IRFIE",    NULL),
 329         PXA_BIT(ICR_BEIE,   "BEIE",     NULL),
 330         PXA_BIT(ICR_SSDIE,  "SSDIE",    NULL),
 331         PXA_BIT(ICR_ALDIE,  "ALDIE",    NULL),
 332         PXA_BIT(ICR_SADIE,  "SADIE",    NULL),
 333         PXA_BIT(ICR_UR,     "UR",               "ur"),
 334 };
 335
 336 #ifdef CONFIG_I2C_PXA_SLAVE
 337 static void decode_ICR(unsigned int val)
 338 {
 339         decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
 340 }
 341 #endif
 342
 343 static unsigned int i2c_debug = DEBUG;
 344
 345 static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
 346 {
 347         dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno,
 348                 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
 349 }
 350
 351 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__)
 352
 353 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
 354 {
 355         unsigned int i;
 356         struct device *dev = &i2c->adap.dev;
 357
 358         dev_err(dev, "slave_0x%x error: %s\n",
 359                 i2c->req_slave_addr >> 1, why);
 360         dev_err(dev, "msg_num: %d msg_idx: %d msg_ptr: %d\n",
 361                 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
 362         dev_err(dev, "IBMR: %08x IDBR: %08x ICR: %08x ISR: %08x\n",
 363                 readl(_IBMR(i2c)), readl(_IDBR(i2c)), readl(_ICR(i2c)),
 364                 readl(_ISR(i2c)));
 365         dev_err(dev, "log:");
 366         for (i = 0; i < i2c->irqlogidx; i++)
 367                 pr_cont(" [%03x:%05x]", i2c->isrlog[i], i2c->icrlog[i]);
 368         pr_cont("\n");
 369 }
 370
 371 #else /* ifdef DEBUG */
 372
 373 #define i2c_debug       0
 374
 375 #define show_state(i2c) do { } while (0)
 376 #define decode_ISR(val) do { } while (0)
 377 #define decode_ICR(val) do { } while (0)
 378 #define i2c_pxa_scream_blue_murder(i2c, why) do { } while (0)
 379
 380 #endif /* ifdef DEBUG / else */
 381
 382 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
 383
 384 static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
 385 {
 386         return !(readl(_ICR(i2c)) & ICR_SCLE);
 387 }
 388
 389 static void i2c_pxa_abort(struct pxa_i2c *i2c)
 390 {
 391         int i = 250;
 392
 393         if (i2c_pxa_is_slavemode(i2c)) {
 394                 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
 395                 return;
 396         }
 397
 398         while ((i > 0) && (readl(_IBMR(i2c)) & IBMR_SDAS) == 0) {
 399                 unsigned long icr = readl(_ICR(i2c));
 400
 401                 icr &= ~ICR_START;
 402                 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
 403
 404                 writel(icr, _ICR(i2c));
 405
 406                 show_state(i2c);
 407
 408                 mdelay(1);
 409                 i --;
 410         }
 411
 412         writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP),
 413                _ICR(i2c));
 414 }
 415
 416 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
 417 {
 418         int timeout = DEF_TIMEOUT;
 419         u32 isr;
 420
 421         while (1) {
 422                 isr = readl(_ISR(i2c));
 423                 if (!(isr & (ISR_IBB | ISR_UB)))
 424                         return 0;
 425
 426                 if (isr & ISR_SAD)
 427                         timeout += 4;
 428
 429                 if (!timeout--)
 430                         break;
 431
 432                 msleep(2);
 433                 show_state(i2c);
 434         }
 435
 436         show_state(i2c);
 437
 438         return I2C_RETRY;
 439 }
 440
 441 static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
 442 {
 443         unsigned long timeout = jiffies + HZ*4;
 444
 445         while (time_before(jiffies, timeout)) {
 446                 if (i2c_debug > 1)
 447                         dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
 448                                 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
 449
 450                 if (readl(_ISR(i2c)) & ISR_SAD) {
 451                         if (i2c_debug > 0)
 452                                 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
 453                         goto out;
 454                 }
 455
 456                 /* wait for unit and bus being not busy, and we also do a
 457                  * quick check of the i2c lines themselves to ensure they've
 458                  * gone high...
 459                  */
 460                 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 &&
 461                     readl(_IBMR(i2c)) == (IBMR_SCLS | IBMR_SDAS)) {
 462                         if (i2c_debug > 0)
 463                                 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
 464                         return 1;
 465                 }
 466
 467                 msleep(1);
 468         }
 469
 470         if (i2c_debug > 0)
 471                 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
 472  out:
 473         return 0;
 474 }
 475
 476 static int i2c_pxa_set_master(struct pxa_i2c *i2c)
 477 {
 478         if (i2c_debug)
 479                 dev_dbg(&i2c->adap.dev, "setting to bus master\n");
 480
 481         if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) {
 482                 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
 483                 if (!i2c_pxa_wait_master(i2c)) {
 484                         dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
 485                         return I2C_RETRY;
 486                 }
 487         }
 488
 489         writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
 490         return 0;
 491 }
 492
 493 #ifdef CONFIG_I2C_PXA_SLAVE
 494 static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
 495 {
 496         unsigned long timeout = jiffies + HZ*1;
 497
 498         /* wait for stop */
 499
 500         show_state(i2c);
 501
 502         while (time_before(jiffies, timeout)) {
 503                 if (i2c_debug > 1)
 504                         dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
 505                                 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
 506
 507                 if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 ||
 508                     (readl(_ISR(i2c)) & ISR_SAD) != 0 ||
 509                     (readl(_ICR(i2c)) & ICR_SCLE) == 0) {
 510                         if (i2c_debug > 1)
 511                                 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
 512                         return 1;
 513                 }
 514
 515                 msleep(1);
 516         }
 517
 518         if (i2c_debug > 0)
 519                 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
 520         return 0;
 521 }
 522
 523 /*
 524  * clear the hold on the bus, and take of anything else
 525  * that has been configured
 526  */
 527 static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
 528 {
 529         show_state(i2c);
 530
 531         if (errcode < 0) {
 532                 udelay(100);   /* simple delay */
 533         } else {
 534                 /* we need to wait for the stop condition to end */
 535
 536                 /* if we where in stop, then clear... */
 537                 if (readl(_ICR(i2c)) & ICR_STOP) {
 538                         udelay(100);
 539                         writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c));
 540                 }
 541
 542                 if (!i2c_pxa_wait_slave(i2c)) {
 543                         dev_err(&i2c->adap.dev, "%s: wait timedout\n",
 544                                 __func__);
 545                         return;
 546                 }
 547         }
 548
 549         writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c));
 550         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
 551
 552         if (i2c_debug) {
 553                 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c)));
 554                 decode_ICR(readl(_ICR(i2c)));
 555         }
 556 }
 557 #else
 558 #define i2c_pxa_set_slave(i2c, err)     do { } while (0)
 559 #endif
 560
 561 static void i2c_pxa_reset(struct pxa_i2c *i2c)
 562 {
 563         pr_debug("Resetting I2C Controller Unit\n");
 564
 565         /* abort any transfer currently under way */
 566         i2c_pxa_abort(i2c);
 567
 568         /* reset according to 9.8 */
 569         writel(ICR_UR, _ICR(i2c));
 570         writel(I2C_ISR_INIT, _ISR(i2c));
 571         writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c));
 572
 573         if (i2c->reg_isar && IS_ENABLED(CONFIG_I2C_PXA_SLAVE))
 574                 writel(i2c->slave_addr, _ISAR(i2c));
 575
 576         /* set control register values */
 577         writel(I2C_ICR_INIT | (i2c->fast_mode ? i2c->fm_mask : 0), _ICR(i2c));
 578         writel(readl(_ICR(i2c)) | (i2c->high_mode ? i2c->hs_mask : 0), _ICR(i2c));
 579
 580 #ifdef CONFIG_I2C_PXA_SLAVE
 581         dev_info(&i2c->adap.dev, "Enabling slave mode\n");
 582         writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c));
 583 #endif
 584
 585         i2c_pxa_set_slave(i2c, 0);
 586
 587         /* enable unit */
 588         writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c));
 589         udelay(100);
 590 }
 591
 592
 593 #ifdef CONFIG_I2C_PXA_SLAVE
 594 /*
 595  * PXA I2C Slave mode
 596  */
 597
 598 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
 599 {
 600         if (isr & ISR_BED) {
 601                 /* what should we do here? */
 602         } else {
 603                 u8 byte = 0;
 604
 605                 if (i2c->slave != NULL)
 606                         i2c_slave_event(i2c->slave, I2C_SLAVE_READ_PROCESSED,
 607                                         &byte);
 608
 609                 writel(byte, _IDBR(i2c));
 610                 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));   /* allow next byte */
 611         }
 612 }
 613
 614 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
 615 {
 616         u8 byte = readl(_IDBR(i2c));
 617
 618         if (i2c->slave != NULL)
 619                 i2c_slave_event(i2c->slave, I2C_SLAVE_WRITE_RECEIVED, &byte);
 620
 621         writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
 622 }
 623
 624 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
 625 {
 626         int timeout;
 627
 628         if (i2c_debug > 0)
 629                 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
 630                        (isr & ISR_RWM) ? 'r' : 't');
 631
 632         if (i2c->slave != NULL) {
 633                 if (isr & ISR_RWM) {
 634                         u8 byte = 0;
 635
 636                         i2c_slave_event(i2c->slave, I2C_SLAVE_READ_REQUESTED,
 637                                         &byte);
 638                         writel(byte, _IDBR(i2c));
 639                 } else {
 640                         i2c_slave_event(i2c->slave, I2C_SLAVE_WRITE_REQUESTED,
 641                                         NULL);
 642                 }
 643         }
 644
 645         /*
 646          * slave could interrupt in the middle of us generating a
 647          * start condition... if this happens, we'd better back off
 648          * and stop holding the poor thing up
 649          */
 650         writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
 651         writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
 652
 653         timeout = 0x10000;
 654
 655         while (1) {
 656                 if ((readl(_IBMR(i2c)) & IBMR_SCLS) == IBMR_SCLS)
 657                         break;
 658
 659                 timeout--;
 660
 661                 if (timeout <= 0) {
 662                         dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
 663                         break;
 664                 }
 665         }
 666
 667         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
 668 }
 669
 670 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
 671 {
 672         if (i2c_debug > 2)
 673                 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
 674
 675         if (i2c->slave != NULL)
 676                 i2c_slave_event(i2c->slave, I2C_SLAVE_STOP, NULL);
 677
 678         if (i2c_debug > 2)
 679                 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
 680
 681         /*
 682          * If we have a master-mode message waiting,
 683          * kick it off now that the slave has completed.
 684          */
 685         if (i2c->msg)
 686                 i2c_pxa_master_complete(i2c, I2C_RETRY);
 687 }
 688
 689 static int i2c_pxa_slave_reg(struct i2c_client *slave)
 690 {
 691         struct pxa_i2c *i2c = slave->adapter->algo_data;
 692
 693         if (i2c->slave)
 694                 return -EBUSY;
 695
 696         if (!i2c->reg_isar)
 697                 return -EAFNOSUPPORT;
 698
 699         i2c->slave = slave;
 700         i2c->slave_addr = slave->addr;
 701
 702         writel(i2c->slave_addr, _ISAR(i2c));
 703
 704         return 0;
 705 }
 706
 707 static int i2c_pxa_slave_unreg(struct i2c_client *slave)
 708 {
 709         struct pxa_i2c *i2c = slave->adapter->algo_data;
 710
 711         WARN_ON(!i2c->slave);
 712
 713         i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
 714         writel(i2c->slave_addr, _ISAR(i2c));
 715
 716         i2c->slave = NULL;
 717
 718         return 0;
 719 }
 720 #else
 721 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
 722 {
 723         if (isr & ISR_BED) {
 724                 /* what should we do here? */
 725         } else {
 726                 writel(0, _IDBR(i2c));
 727                 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
 728         }
 729 }
 730
 731 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
 732 {
 733         writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
 734 }
 735
 736 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
 737 {
 738         int timeout;
 739
 740         /*
 741          * slave could interrupt in the middle of us generating a
 742          * start condition... if this happens, we'd better back off
 743          * and stop holding the poor thing up
 744          */
 745         writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
 746         writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
 747
 748         timeout = 0x10000;
 749
 750         while (1) {
 751                 if ((readl(_IBMR(i2c)) & IBMR_SCLS) == IBMR_SCLS)
 752                         break;
 753
 754                 timeout--;
 755
 756                 if (timeout <= 0) {
 757                         dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
 758                         break;
 759                 }
 760         }
 761
 762         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
 763 }
 764
 765 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
 766 {
 767         if (i2c->msg)
 768                 i2c_pxa_master_complete(i2c, I2C_RETRY);
 769 }
 770 #endif
 771
 772 /*
 773  * PXA I2C Master mode
 774  */
 775
 776 static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
 777 {
 778         u32 icr;
 779
 780         /*
 781          * Step 1: target slave address into IDBR
 782          */
 783         i2c->req_slave_addr = i2c_8bit_addr_from_msg(i2c->msg);
 784         writel(i2c->req_slave_addr, _IDBR(i2c));
 785
 786         /*
 787          * Step 2: initiate the write.
 788          */
 789         icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
 790         writel(icr | ICR_START | ICR_TB, _ICR(i2c));
 791 }
 792
 793 static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c)
 794 {
 795         u32 icr;
 796
 797         /*
 798          * Clear the STOP and ACK flags
 799          */
 800         icr = readl(_ICR(i2c));
 801         icr &= ~(ICR_STOP | ICR_ACKNAK);
 802         writel(icr, _ICR(i2c));
 803 }
 804
 805 /*
 806  * PXA I2C send master code
 807  * 1. Load master code to IDBR and send it.
 808  *    Note for HS mode, set ICR [GPIOEN].
 809  * 2. Wait until win arbitration.
 810  */
 811 static int i2c_pxa_send_mastercode(struct pxa_i2c *i2c)
 812 {
 813         u32 icr;
 814         long timeout;
 815
 816         spin_lock_irq(&i2c->lock);
 817         i2c->highmode_enter = true;
 818         writel(i2c->master_code, _IDBR(i2c));
 819
 820         icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
 821         icr |= ICR_GPIOEN | ICR_START | ICR_TB | ICR_ITEIE;
 822         writel(icr, _ICR(i2c));
 823
 824         spin_unlock_irq(&i2c->lock);
 825         timeout = wait_event_timeout(i2c->wait,
 826                         i2c->highmode_enter == false, HZ * 1);
 827
 828         i2c->highmode_enter = false;
 829
 830         return (timeout == 0) ? I2C_RETRY : 0;
 831 }
 832
 833 /*
 834  * i2c_pxa_master_complete - complete the message and wake up.
 835  */
 836 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
 837 {
 838         i2c->msg_ptr = 0;
 839         i2c->msg = NULL;
 840         i2c->msg_idx ++;
 841         i2c->msg_num = 0;
 842         if (ret)
 843                 i2c->msg_idx = ret;
 844         if (!i2c->use_pio)
 845                 wake_up(&i2c->wait);
 846 }
 847
 848 static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
 849 {
 850         u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
 851
 852  again:
 853         /*
 854          * If ISR_ALD is set, we lost arbitration.
 855          */
 856         if (isr & ISR_ALD) {
 857                 /*
 858                  * Do we need to do anything here?  The PXA docs
 859                  * are vague about what happens.
 860                  */
 861                 i2c_pxa_scream_blue_murder(i2c, "ALD set");
 862
 863                 /*
 864                  * We ignore this error.  We seem to see spurious ALDs
 865                  * for seemingly no reason.  If we handle them as I think
 866                  * they should, we end up causing an I2C error, which
 867                  * is painful for some systems.
 868                  */
 869                 return; /* ignore */
 870         }
 871
 872         if ((isr & ISR_BED) &&
 873                 (!((i2c->msg->flags & I2C_M_IGNORE_NAK) &&
 874                         (isr & ISR_ACKNAK)))) {
 875                 int ret = BUS_ERROR;
 876
 877                 /*
 878                  * I2C bus error - either the device NAK'd us, or
 879                  * something more serious happened.  If we were NAK'd
 880                  * on the initial address phase, we can retry.
 881                  */
 882                 if (isr & ISR_ACKNAK) {
 883                         if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
 884                                 ret = I2C_RETRY;
 885                         else
 886                                 ret = XFER_NAKED;
 887                 }
 888                 i2c_pxa_master_complete(i2c, ret);
 889         } else if (isr & ISR_RWM) {
 890                 /*
 891                  * Read mode.  We have just sent the address byte, and
 892                  * now we must initiate the transfer.
 893                  */
 894                 if (i2c->msg_ptr == i2c->msg->len - 1 &&
 895                     i2c->msg_idx == i2c->msg_num - 1)
 896                         icr |= ICR_STOP | ICR_ACKNAK;
 897
 898                 icr |= ICR_ALDIE | ICR_TB;
 899         } else if (i2c->msg_ptr < i2c->msg->len) {
 900                 /*
 901                  * Write mode.  Write the next data byte.
 902                  */
 903                 writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c));
 904
 905                 icr |= ICR_ALDIE | ICR_TB;
 906
 907                 /*
 908                  * If this is the last byte of the last message or last byte
 909                  * of any message with I2C_M_STOP (e.g. SCCB), send a STOP.
 910                  */
 911                 if ((i2c->msg_ptr == i2c->msg->len) &&
 912                         ((i2c->msg->flags & I2C_M_STOP) ||
 913                         (i2c->msg_idx == i2c->msg_num - 1)))
 914                                 icr |= ICR_STOP;
 915
 916         } else if (i2c->msg_idx < i2c->msg_num - 1) {
 917                 /*
 918                  * Next segment of the message.
 919                  */
 920                 i2c->msg_ptr = 0;
 921                 i2c->msg_idx ++;
 922                 i2c->msg++;
 923
 924                 /*
 925                  * If we aren't doing a repeated start and address,
 926                  * go back and try to send the next byte.  Note that
 927                  * we do not support switching the R/W direction here.
 928                  */
 929                 if (i2c->msg->flags & I2C_M_NOSTART)
 930                         goto again;
 931
 932                 /*
 933                  * Write the next address.
 934                  */
 935                 i2c->req_slave_addr = i2c_8bit_addr_from_msg(i2c->msg);
 936                 writel(i2c->req_slave_addr, _IDBR(i2c));
 937
 938                 /*
 939                  * And trigger a repeated start, and send the byte.
 940                  */
 941                 icr &= ~ICR_ALDIE;
 942                 icr |= ICR_START | ICR_TB;
 943         } else {
 944                 if (i2c->msg->len == 0) {
 945                         /*
 946                          * Device probes have a message length of zero
 947                          * and need the bus to be reset before it can
 948                          * be used again.
 949                          */
 950                         i2c_pxa_reset(i2c);
 951                 }
 952                 i2c_pxa_master_complete(i2c, 0);
 953         }
 954
 955         i2c->icrlog[i2c->irqlogidx-1] = icr;
 956
 957         writel(icr, _ICR(i2c));
 958         show_state(i2c);
 959 }
 960
 961 static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
 962 {
 963         u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
 964
 965         /*
 966          * Read the byte.
 967          */
 968         i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c));
 969
 970         if (i2c->msg_ptr < i2c->msg->len) {
 971                 /*
 972                  * If this is the last byte of the last
 973                  * message, send a STOP.
 974                  */
 975                 if (i2c->msg_ptr == i2c->msg->len - 1)
 976                         icr |= ICR_STOP | ICR_ACKNAK;
 977
 978                 icr |= ICR_ALDIE | ICR_TB;
 979         } else {
 980                 i2c_pxa_master_complete(i2c, 0);
 981         }
 982
 983         i2c->icrlog[i2c->irqlogidx-1] = icr;
 984
 985         writel(icr, _ICR(i2c));
 986 }
 987
 988 #define VALID_INT_SOURCE        (ISR_SSD | ISR_ALD | ISR_ITE | ISR_IRF | \
 989                                 ISR_SAD | ISR_BED)
 990 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
 991 {
 992         struct pxa_i2c *i2c = dev_id;
 993         u32 isr = readl(_ISR(i2c));
 994
 995         if (!(isr & VALID_INT_SOURCE))
 996                 return IRQ_NONE;
 997
 998         if (i2c_debug > 2 && 0) {
 999                 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
1000                         __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c)));
1001                 decode_ISR(isr);
1002         }
1003
1004         if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))
1005                 i2c->isrlog[i2c->irqlogidx++] = isr;
1006
1007         show_state(i2c);
1008
1009         /*
1010          * Always clear all pending IRQs.
1011          */
1012         writel(isr & VALID_INT_SOURCE, _ISR(i2c));
1013
1014         if (isr & ISR_SAD)
1015                 i2c_pxa_slave_start(i2c, isr);
1016         if (isr & ISR_SSD)
1017                 i2c_pxa_slave_stop(i2c);
1018
1019         if (i2c_pxa_is_slavemode(i2c)) {
1020                 if (isr & ISR_ITE)
1021                         i2c_pxa_slave_txempty(i2c, isr);
1022                 if (isr & ISR_IRF)
1023                         i2c_pxa_slave_rxfull(i2c, isr);
1024         } else if (i2c->msg && (!i2c->highmode_enter)) {
1025                 if (isr & ISR_ITE)
1026                         i2c_pxa_irq_txempty(i2c, isr);
1027                 if (isr & ISR_IRF)
1028                         i2c_pxa_irq_rxfull(i2c, isr);
1029         } else if ((isr & ISR_ITE) && i2c->highmode_enter) {
1030                 i2c->highmode_enter = false;
1031                 wake_up(&i2c->wait);
1032         } else {
1033                 i2c_pxa_scream_blue_murder(i2c, "spurious irq");
1034         }
1035
1036         return IRQ_HANDLED;
1037 }
1038
1039 /*
1040  * We are protected by the adapter bus mutex.
1041  */
1042 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
1043 {
1044         long timeout;
1045         int ret;
1046
1047         /*
1048          * Wait for the bus to become free.
1049          */
1050         ret = i2c_pxa_wait_bus_not_busy(i2c);
1051         if (ret) {
1052                 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
1053                 goto out;
1054         }
1055
1056         /*
1057          * Set master mode.
1058          */
1059         ret = i2c_pxa_set_master(i2c);
1060         if (ret) {
1061                 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
1062                 goto out;
1063         }
1064
1065         if (i2c->high_mode) {
1066                 ret = i2c_pxa_send_mastercode(i2c);
1067                 if (ret) {
1068                         dev_err(&i2c->adap.dev, "i2c_pxa_send_mastercode timeout\n");
1069                         goto out;
1070                         }
1071         }
1072
1073         spin_lock_irq(&i2c->lock);
1074
1075         i2c->msg = msg;
1076         i2c->msg_num = num;
1077         i2c->msg_idx = 0;
1078         i2c->msg_ptr = 0;
1079         i2c->irqlogidx = 0;
1080
1081         i2c_pxa_start_message(i2c);
1082
1083         spin_unlock_irq(&i2c->lock);
1084
1085         /*
1086          * The rest of the processing occurs in the interrupt handler.
1087          */
1088         timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
1089         i2c_pxa_stop_message(i2c);
1090
1091         /*
1092          * We place the return code in i2c->msg_idx.
1093          */
1094         ret = i2c->msg_idx;
1095
1096         if (!timeout && i2c->msg_num) {
1097                 i2c_pxa_scream_blue_murder(i2c, "timeout");
1098                 ret = I2C_RETRY;
1099         }
1100
1101  out:
1102         return ret;
1103 }
1104
1105 static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
1106 {
1107         struct pxa_i2c *i2c = adap->algo_data;
1108         int ret, i;
1109
1110         for (i = adap->retries; i >= 0; i--) {
1111                 ret = i2c_pxa_do_xfer(i2c, msgs, num);
1112                 if (ret != I2C_RETRY)
1113                         goto out;
1114
1115                 if (i2c_debug)
1116                         dev_dbg(&adap->dev, "Retrying transmission\n");
1117                 udelay(100);
1118         }
1119         i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
1120         ret = -EREMOTEIO;
1121  out:
1122         i2c_pxa_set_slave(i2c, ret);
1123         return ret;
1124 }
1125
1126 static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
1127 {
1128         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
1129                 I2C_FUNC_PROTOCOL_MANGLING | I2C_FUNC_NOSTART;
1130 }
1131
1132 static const struct i2c_algorithm i2c_pxa_algorithm = {
1133         .master_xfer    = i2c_pxa_xfer,
1134         .functionality  = i2c_pxa_functionality,
1135 #ifdef CONFIG_I2C_PXA_SLAVE
1136         .reg_slave      = i2c_pxa_slave_reg,
1137         .unreg_slave    = i2c_pxa_slave_unreg,
1138 #endif
1139 };
1140
1141 /* Non-interrupt mode support */
1142 static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c)
1143 {
1144         /* make timeout the same as for interrupt based functions */
1145         long timeout = 2 * DEF_TIMEOUT;
1146
1147         /*
1148          * Wait for the bus to become free.
1149          */
1150         while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
1151                 udelay(1000);
1152                 show_state(i2c);
1153         }
1154
1155         if (timeout < 0) {
1156                 show_state(i2c);
1157                 dev_err(&i2c->adap.dev,
1158                         "i2c_pxa: timeout waiting for bus free\n");
1159                 return I2C_RETRY;
1160         }
1161
1162         /*
1163          * Set master mode.
1164          */
1165         writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
1166
1167         return 0;
1168 }
1169
1170 static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c,
1171                                struct i2c_msg *msg, int num)
1172 {
1173         unsigned long timeout = 500000; /* 5 seconds */
1174         int ret = 0;
1175
1176         ret = i2c_pxa_pio_set_master(i2c);
1177         if (ret)
1178                 goto out;
1179
1180         i2c->msg = msg;
1181         i2c->msg_num = num;
1182         i2c->msg_idx = 0;
1183         i2c->msg_ptr = 0;
1184         i2c->irqlogidx = 0;
1185
1186         i2c_pxa_start_message(i2c);
1187
1188         while (i2c->msg_num > 0 && --timeout) {
1189                 i2c_pxa_handler(0, i2c);
1190                 udelay(10);
1191         }
1192
1193         i2c_pxa_stop_message(i2c);
1194
1195         /*
1196          * We place the return code in i2c->msg_idx.
1197          */
1198         ret = i2c->msg_idx;
1199
1200 out:
1201         if (timeout == 0) {
1202                 i2c_pxa_scream_blue_murder(i2c, "timeout");
1203                 ret = I2C_RETRY;
1204         }
1205
1206         return ret;
1207 }
1208
1209 static int i2c_pxa_pio_xfer(struct i2c_adapter *adap,
1210                             struct i2c_msg msgs[], int num)
1211 {
1212         struct pxa_i2c *i2c = adap->algo_data;
1213         int ret, i;
1214
1215         /* If the I2C controller is disabled we need to reset it
1216           (probably due to a suspend/resume destroying state). We do
1217           this here as we can then avoid worrying about resuming the
1218           controller before its users. */
1219         if (!(readl(_ICR(i2c)) & ICR_IUE))
1220                 i2c_pxa_reset(i2c);
1221
1222         for (i = adap->retries; i >= 0; i--) {
1223                 ret = i2c_pxa_do_pio_xfer(i2c, msgs, num);
1224                 if (ret != I2C_RETRY)
1225                         goto out;
1226
1227                 if (i2c_debug)
1228                         dev_dbg(&adap->dev, "Retrying transmission\n");
1229                 udelay(100);
1230         }
1231         i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
1232         ret = -EREMOTEIO;
1233  out:
1234         i2c_pxa_set_slave(i2c, ret);
1235         return ret;
1236 }
1237
1238 static const struct i2c_algorithm i2c_pxa_pio_algorithm = {
1239         .master_xfer    = i2c_pxa_pio_xfer,
1240         .functionality  = i2c_pxa_functionality,
1241 #ifdef CONFIG_I2C_PXA_SLAVE
1242         .reg_slave      = i2c_pxa_slave_reg,
1243         .unreg_slave    = i2c_pxa_slave_unreg,
1244 #endif
1245 };
1246
1247 static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c,
1248                             enum pxa_i2c_types *i2c_types)
1249 {
1250         struct device_node *np = pdev->dev.of_node;
1251         const struct of_device_id *of_id =
1252                         of_match_device(i2c_pxa_dt_ids, &pdev->dev);
1253
1254         if (!of_id)
1255                 return 1;
1256
1257         /* For device tree we always use the dynamic or alias-assigned ID */
1258         i2c->adap.nr = -1;
1259
1260         if (of_get_property(np, "mrvl,i2c-polling", NULL))
1261                 i2c->use_pio = 1;
1262         if (of_get_property(np, "mrvl,i2c-fast-mode", NULL))
1263                 i2c->fast_mode = 1;
1264
1265         *i2c_types = (enum pxa_i2c_types)(of_id->data);
1266
1267         return 0;
1268 }
1269
1270 static int i2c_pxa_probe_pdata(struct platform_device *pdev,
1271                                struct pxa_i2c *i2c,
1272                                enum pxa_i2c_types *i2c_types)
1273 {
1274         struct i2c_pxa_platform_data *plat = dev_get_platdata(&pdev->dev);
1275         const struct platform_device_id *id = platform_get_device_id(pdev);
1276
1277         *i2c_types = id->driver_data;
1278         if (plat) {
1279                 i2c->use_pio = plat->use_pio;
1280                 i2c->fast_mode = plat->fast_mode;
1281                 i2c->high_mode = plat->high_mode;
1282                 i2c->master_code = plat->master_code;
1283                 if (!i2c->master_code)
1284                         i2c->master_code = 0xe;
1285                 i2c->rate = plat->rate;
1286         }
1287         return 0;
1288 }
1289
1290 static int i2c_pxa_probe(struct platform_device *dev)
1291 {
1292         struct i2c_pxa_platform_data *plat = dev_get_platdata(&dev->dev);
1293         enum pxa_i2c_types i2c_type;
1294         struct pxa_i2c *i2c;
1295         struct resource *res = NULL;
1296         int ret, irq;
1297
1298         i2c = devm_kzalloc(&dev->dev, sizeof(struct pxa_i2c), GFP_KERNEL);
1299         if (!i2c)
1300                 return -ENOMEM;
1301
1302         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1303         i2c->reg_base = devm_ioremap_resource(&dev->dev, res);
1304         if (IS_ERR(i2c->reg_base))
1305                 return PTR_ERR(i2c->reg_base);
1306
1307         irq = platform_get_irq(dev, 0);
1308         if (irq < 0)
1309                 return irq;
1310
1311         /* Default adapter num to device id; i2c_pxa_probe_dt can override. */
1312         i2c->adap.nr = dev->id;
1313
1314         ret = i2c_pxa_probe_dt(dev, i2c, &i2c_type);
1315         if (ret > 0)
1316                 ret = i2c_pxa_probe_pdata(dev, i2c, &i2c_type);
1317         if (ret < 0)
1318                 return ret;
1319
1320         i2c->adap.owner   = THIS_MODULE;
1321         i2c->adap.retries = 5;
1322
1323         spin_lock_init(&i2c->lock);
1324         init_waitqueue_head(&i2c->wait);
1325
1326         strlcpy(i2c->adap.name, "pxa_i2c-i2c", sizeof(i2c->adap.name));
1327
1328         i2c->clk = devm_clk_get(&dev->dev, NULL);
1329         if (IS_ERR(i2c->clk)) {
1330                 dev_err(&dev->dev, "failed to get the clk: %ld\n", PTR_ERR(i2c->clk));
1331                 return PTR_ERR(i2c->clk);
1332         }
1333
1334         i2c->reg_ibmr = i2c->reg_base + pxa_reg_layout[i2c_type].ibmr;
1335         i2c->reg_idbr = i2c->reg_base + pxa_reg_layout[i2c_type].idbr;
1336         i2c->reg_icr = i2c->reg_base + pxa_reg_layout[i2c_type].icr;
1337         i2c->reg_isr = i2c->reg_base + pxa_reg_layout[i2c_type].isr;
1338         i2c->fm_mask = pxa_reg_layout[i2c_type].fm;
1339         i2c->hs_mask = pxa_reg_layout[i2c_type].hs;
1340
1341         if (i2c_type != REGS_CE4100)
1342                 i2c->reg_isar = i2c->reg_base + pxa_reg_layout[i2c_type].isar;
1343
1344         if (i2c_type == REGS_PXA910) {
1345                 i2c->reg_ilcr = i2c->reg_base + pxa_reg_layout[i2c_type].ilcr;
1346                 i2c->reg_iwcr = i2c->reg_base + pxa_reg_layout[i2c_type].iwcr;
1347         }
1348
1349         i2c->iobase = res->start;
1350         i2c->iosize = resource_size(res);
1351
1352         i2c->irq = irq;
1353
1354         i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
1355         i2c->highmode_enter = false;
1356
1357         if (plat) {
1358                 i2c->adap.class = plat->class;
1359         }
1360
1361         if (i2c->high_mode) {
1362                 if (i2c->rate) {
1363                         clk_set_rate(i2c->clk, i2c->rate);
1364                         pr_info("i2c: <%s> set rate to %ld\n",
1365                                 i2c->adap.name, clk_get_rate(i2c->clk));
1366                 } else
1367                         pr_warn("i2c: <%s> clock rate not set\n",
1368                                 i2c->adap.name);
1369         }
1370
1371         clk_prepare_enable(i2c->clk);
1372
1373         if (i2c->use_pio) {
1374                 i2c->adap.algo = &i2c_pxa_pio_algorithm;
1375         } else {
1376                 i2c->adap.algo = &i2c_pxa_algorithm;
1377                 ret = devm_request_irq(&dev->dev, irq, i2c_pxa_handler,
1378                                 IRQF_SHARED | IRQF_NO_SUSPEND,
1379                                 dev_name(&dev->dev), i2c);
1380                 if (ret) {
1381                         dev_err(&dev->dev, "failed to request irq: %d\n", ret);
1382                         goto ereqirq;
1383                 }
1384         }
1385
1386         i2c_pxa_reset(i2c);
1387
1388         i2c->adap.algo_data = i2c;
1389         i2c->adap.dev.parent = &dev->dev;
1390 #ifdef CONFIG_OF
1391         i2c->adap.dev.of_node = dev->dev.of_node;
1392 #endif
1393
1394         ret = i2c_add_numbered_adapter(&i2c->adap);
1395         if (ret < 0)
1396                 goto ereqirq;
1397
1398         platform_set_drvdata(dev, i2c);
1399
1400 #ifdef CONFIG_I2C_PXA_SLAVE
1401         dev_info(&i2c->adap.dev, " PXA I2C adapter, slave address %d\n",
1402                 i2c->slave_addr);
1403 #else
1404         dev_info(&i2c->adap.dev, " PXA I2C adapter\n");
1405 #endif
1406         return 0;
1407
1408 ereqirq:
1409         clk_disable_unprepare(i2c->clk);
1410         return ret;
1411 }
1412
1413 static int i2c_pxa_remove(struct platform_device *dev)
1414 {
1415         struct pxa_i2c *i2c = platform_get_drvdata(dev);
1416
1417         i2c_del_adapter(&i2c->adap);
1418
1419         clk_disable_unprepare(i2c->clk);
1420
1421         return 0;
1422 }
1423
1424 #ifdef CONFIG_PM
1425 static int i2c_pxa_suspend_noirq(struct device *dev)
1426 {
1427         struct pxa_i2c *i2c = dev_get_drvdata(dev);
1428
1429         clk_disable(i2c->clk);
1430
1431         return 0;
1432 }
1433
1434 static int i2c_pxa_resume_noirq(struct device *dev)
1435 {
1436         struct pxa_i2c *i2c = dev_get_drvdata(dev);
1437
1438         clk_enable(i2c->clk);
1439         i2c_pxa_reset(i2c);
1440
1441         return 0;
1442 }
1443
1444 static const struct dev_pm_ops i2c_pxa_dev_pm_ops = {
1445         .suspend_noirq = i2c_pxa_suspend_noirq,
1446         .resume_noirq = i2c_pxa_resume_noirq,
1447 };
1448
1449 #define I2C_PXA_DEV_PM_OPS (&i2c_pxa_dev_pm_ops)
1450 #else
1451 #define I2C_PXA_DEV_PM_OPS NULL
1452 #endif
1453
1454 static struct platform_driver i2c_pxa_driver = {
1455         .probe          = i2c_pxa_probe,
1456         .remove         = i2c_pxa_remove,
1457         .driver         = {
1458                 .name   = "pxa2xx-i2c",
1459                 .pm     = I2C_PXA_DEV_PM_OPS,
1460                 .of_match_table = i2c_pxa_dt_ids,
1461         },
1462         .id_table       = i2c_pxa_id_table,
1463 };
1464
1465 static int __init i2c_adap_pxa_init(void)
1466 {
1467         return platform_driver_register(&i2c_pxa_driver);
1468 }
1469
1470 static void __exit i2c_adap_pxa_exit(void)
1471 {
1472         platform_driver_unregister(&i2c_pxa_driver);
1473 }
1474
1475 MODULE_LICENSE("GPL");
1476 MODULE_ALIAS("platform:pxa2xx-i2c");
1477
1478 subsys_initcall(i2c_adap_pxa_init);
1479 module_exit(i2c_adap_pxa_exit);