1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Actions Semiconductor Owl SoC's I2C driver
5 * Copyright (c) 2014 Actions Semi Inc.
6 * Author: David Liu <liuwei@actions-semi.com>
8 * Copyright (c) 2018 Linaro Ltd.
9 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/i2c.h>
15 #include <linux/interrupt.h>
17 #include <linux/module.h>
18 #include <linux/of_device.h>
21 #define OWL_I2C_REG_CTL 0x0000
22 #define OWL_I2C_REG_CLKDIV 0x0004
23 #define OWL_I2C_REG_STAT 0x0008
24 #define OWL_I2C_REG_ADDR 0x000C
25 #define OWL_I2C_REG_TXDAT 0x0010
26 #define OWL_I2C_REG_RXDAT 0x0014
27 #define OWL_I2C_REG_CMD 0x0018
28 #define OWL_I2C_REG_FIFOCTL 0x001C
29 #define OWL_I2C_REG_FIFOSTAT 0x0020
30 #define OWL_I2C_REG_DATCNT 0x0024
31 #define OWL_I2C_REG_RCNT 0x0028
33 /* I2Cx_CTL Bit Mask */
34 #define OWL_I2C_CTL_RB BIT(1)
35 #define OWL_I2C_CTL_GBCC(x) (((x) & 0x3) << 2)
36 #define OWL_I2C_CTL_GBCC_NONE OWL_I2C_CTL_GBCC(0)
37 #define OWL_I2C_CTL_GBCC_START OWL_I2C_CTL_GBCC(1)
38 #define OWL_I2C_CTL_GBCC_STOP OWL_I2C_CTL_GBCC(2)
39 #define OWL_I2C_CTL_GBCC_RSTART OWL_I2C_CTL_GBCC(3)
40 #define OWL_I2C_CTL_IRQE BIT(5)
41 #define OWL_I2C_CTL_EN BIT(7)
42 #define OWL_I2C_CTL_AE BIT(8)
43 #define OWL_I2C_CTL_SHSM BIT(10)
45 #define OWL_I2C_DIV_FACTOR(x) ((x) & 0xff)
47 /* I2Cx_STAT Bit Mask */
48 #define OWL_I2C_STAT_RACK BIT(0)
49 #define OWL_I2C_STAT_BEB BIT(1)
50 #define OWL_I2C_STAT_IRQP BIT(2)
51 #define OWL_I2C_STAT_LAB BIT(3)
52 #define OWL_I2C_STAT_STPD BIT(4)
53 #define OWL_I2C_STAT_STAD BIT(5)
54 #define OWL_I2C_STAT_BBB BIT(6)
55 #define OWL_I2C_STAT_TCB BIT(7)
56 #define OWL_I2C_STAT_LBST BIT(8)
57 #define OWL_I2C_STAT_SAMB BIT(9)
58 #define OWL_I2C_STAT_SRGC BIT(10)
60 /* I2Cx_CMD Bit Mask */
61 #define OWL_I2C_CMD_SBE BIT(0)
62 #define OWL_I2C_CMD_RBE BIT(4)
63 #define OWL_I2C_CMD_DE BIT(8)
64 #define OWL_I2C_CMD_NS BIT(9)
65 #define OWL_I2C_CMD_SE BIT(10)
66 #define OWL_I2C_CMD_MSS BIT(11)
67 #define OWL_I2C_CMD_WRS BIT(12)
68 #define OWL_I2C_CMD_SECL BIT(15)
70 #define OWL_I2C_CMD_AS(x) (((x) & 0x7) << 1)
71 #define OWL_I2C_CMD_SAS(x) (((x) & 0x7) << 5)
73 /* I2Cx_FIFOCTL Bit Mask */
74 #define OWL_I2C_FIFOCTL_NIB BIT(0)
75 #define OWL_I2C_FIFOCTL_RFR BIT(1)
76 #define OWL_I2C_FIFOCTL_TFR BIT(2)
78 /* I2Cc_FIFOSTAT Bit Mask */
79 #define OWL_I2C_FIFOSTAT_RNB BIT(1)
80 #define OWL_I2C_FIFOSTAT_RFE BIT(2)
81 #define OWL_I2C_FIFOSTAT_TFF BIT(5)
82 #define OWL_I2C_FIFOSTAT_TFD GENMASK(23, 16)
83 #define OWL_I2C_FIFOSTAT_RFD GENMASK(15, 8)
86 #define OWL_I2C_TIMEOUT msecs_to_jiffies(4 * 1000)
88 #define OWL_I2C_MAX_RETRIES 50
91 struct i2c_adapter adap;
93 struct completion msg_complete;
97 unsigned long clk_rate;
103 static void owl_i2c_update_reg(void __iomem *reg, unsigned int val, bool state)
117 static void owl_i2c_reset(struct owl_i2c_dev *i2c_dev)
119 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
120 OWL_I2C_CTL_EN, false);
122 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
123 OWL_I2C_CTL_EN, true);
125 /* Clear status registers */
126 writel(0, i2c_dev->base + OWL_I2C_REG_STAT);
129 static int owl_i2c_reset_fifo(struct owl_i2c_dev *i2c_dev)
131 unsigned int val, timeout = 0;
134 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
135 OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR,
138 /* Wait 50ms for FIFO reset complete */
140 val = readl(i2c_dev->base + OWL_I2C_REG_FIFOCTL);
141 if (!(val & (OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR)))
143 usleep_range(500, 1000);
144 } while (timeout++ < OWL_I2C_MAX_RETRIES);
146 if (timeout > OWL_I2C_MAX_RETRIES) {
147 dev_err(&i2c_dev->adap.dev, "FIFO reset timeout\n");
154 static void owl_i2c_set_freq(struct owl_i2c_dev *i2c_dev)
158 val = DIV_ROUND_UP(i2c_dev->clk_rate, i2c_dev->bus_freq * 16);
160 /* Set clock divider factor */
161 writel(OWL_I2C_DIV_FACTOR(val), i2c_dev->base + OWL_I2C_REG_CLKDIV);
164 static irqreturn_t owl_i2c_interrupt(int irq, void *_dev)
166 struct owl_i2c_dev *i2c_dev = _dev;
167 struct i2c_msg *msg = i2c_dev->msg;
169 unsigned int stat, fifostat;
171 spin_lock_irqsave(&i2c_dev->lock, flags);
175 /* Handle NACK from slave */
176 fifostat = readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT);
177 if (fifostat & OWL_I2C_FIFOSTAT_RNB) {
178 i2c_dev->err = -ENXIO;
182 /* Handle bus error */
183 stat = readl(i2c_dev->base + OWL_I2C_REG_STAT);
184 if (stat & OWL_I2C_STAT_BEB) {
189 /* Handle FIFO read */
190 if (msg->flags & I2C_M_RD) {
191 while ((readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) &
192 OWL_I2C_FIFOSTAT_RFE) && i2c_dev->msg_ptr < msg->len) {
193 msg->buf[i2c_dev->msg_ptr++] = readl(i2c_dev->base +
197 /* Handle the remaining bytes which were not sent */
198 while (!(readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) &
199 OWL_I2C_FIFOSTAT_TFF) && i2c_dev->msg_ptr < msg->len) {
200 writel(msg->buf[i2c_dev->msg_ptr++],
201 i2c_dev->base + OWL_I2C_REG_TXDAT);
206 /* Clear pending interrupts */
207 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_STAT,
208 OWL_I2C_STAT_IRQP, true);
210 complete_all(&i2c_dev->msg_complete);
211 spin_unlock_irqrestore(&i2c_dev->lock, flags);
216 static u32 owl_i2c_func(struct i2c_adapter *adap)
218 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
221 static int owl_i2c_check_bus_busy(struct i2c_adapter *adap)
223 struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
224 unsigned long timeout;
226 /* Check for Bus busy */
227 timeout = jiffies + OWL_I2C_TIMEOUT;
228 while (readl(i2c_dev->base + OWL_I2C_REG_STAT) & OWL_I2C_STAT_BBB) {
229 if (time_after(jiffies, timeout)) {
230 dev_err(&adap->dev, "Bus busy timeout\n");
238 static int owl_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
241 struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
243 unsigned long time_left, flags;
244 unsigned int i2c_cmd, val;
248 spin_lock_irqsave(&i2c_dev->lock, flags);
250 /* Reset I2C controller */
251 owl_i2c_reset(i2c_dev);
253 /* Set bus frequency */
254 owl_i2c_set_freq(i2c_dev);
257 * Spinlock should be released before calling reset FIFO and
258 * bus busy check since those functions may sleep
260 spin_unlock_irqrestore(&i2c_dev->lock, flags);
263 ret = owl_i2c_reset_fifo(i2c_dev);
265 goto unlocked_err_exit;
267 /* Check for bus busy */
268 ret = owl_i2c_check_bus_busy(adap);
270 goto unlocked_err_exit;
272 spin_lock_irqsave(&i2c_dev->lock, flags);
274 /* Check for Arbitration lost */
275 val = readl(i2c_dev->base + OWL_I2C_REG_STAT);
276 if (val & OWL_I2C_STAT_LAB) {
277 val &= ~OWL_I2C_STAT_LAB;
278 writel(val, i2c_dev->base + OWL_I2C_REG_STAT);
283 reinit_completion(&i2c_dev->msg_complete);
285 /* Enable I2C controller interrupt */
286 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
287 OWL_I2C_CTL_IRQE, true);
290 * Select: FIFO enable, Master mode, Stop enable, Data count enable,
293 i2c_cmd = OWL_I2C_CMD_SECL | OWL_I2C_CMD_MSS | OWL_I2C_CMD_SE |
294 OWL_I2C_CMD_NS | OWL_I2C_CMD_DE | OWL_I2C_CMD_SBE;
296 /* Handle repeated start condition */
298 /* Set internal address length and enable repeated start */
299 i2c_cmd |= OWL_I2C_CMD_AS(msgs[0].len + 1) |
300 OWL_I2C_CMD_SAS(1) | OWL_I2C_CMD_RBE;
302 /* Write slave address */
303 addr = i2c_8bit_addr_from_msg(&msgs[0]);
304 writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT);
306 /* Write internal register address */
307 for (idx = 0; idx < msgs[0].len; idx++)
308 writel(msgs[0].buf[idx],
309 i2c_dev->base + OWL_I2C_REG_TXDAT);
313 /* Set address length */
314 i2c_cmd |= OWL_I2C_CMD_AS(1);
319 i2c_dev->msg_ptr = 0;
321 /* Set data count for the message */
322 writel(msg->len, i2c_dev->base + OWL_I2C_REG_DATCNT);
324 addr = i2c_8bit_addr_from_msg(msg);
325 writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT);
327 if (!(msg->flags & I2C_M_RD)) {
328 /* Write data to FIFO */
329 for (idx = 0; idx < msg->len; idx++) {
330 /* Check for FIFO full */
331 if (readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) &
332 OWL_I2C_FIFOSTAT_TFF)
335 writel(msg->buf[idx],
336 i2c_dev->base + OWL_I2C_REG_TXDAT);
339 i2c_dev->msg_ptr = idx;
342 /* Ignore the NACK if needed */
343 if (msg->flags & I2C_M_IGNORE_NAK)
344 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
345 OWL_I2C_FIFOCTL_NIB, true);
347 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
348 OWL_I2C_FIFOCTL_NIB, false);
350 /* Start the transfer */
351 writel(i2c_cmd, i2c_dev->base + OWL_I2C_REG_CMD);
353 spin_unlock_irqrestore(&i2c_dev->lock, flags);
355 time_left = wait_for_completion_timeout(&i2c_dev->msg_complete,
358 spin_lock_irqsave(&i2c_dev->lock, flags);
359 if (time_left == 0) {
360 dev_err(&adap->dev, "Transaction timed out\n");
361 /* Send stop condition and release the bus */
362 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
363 OWL_I2C_CTL_GBCC_STOP | OWL_I2C_CTL_RB,
369 ret = i2c_dev->err < 0 ? i2c_dev->err : num;
372 spin_unlock_irqrestore(&i2c_dev->lock, flags);
375 /* Disable I2C controller */
376 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
377 OWL_I2C_CTL_EN, false);
382 static const struct i2c_algorithm owl_i2c_algorithm = {
383 .master_xfer = owl_i2c_master_xfer,
384 .functionality = owl_i2c_func,
387 static const struct i2c_adapter_quirks owl_i2c_quirks = {
388 .flags = I2C_AQ_COMB | I2C_AQ_COMB_WRITE_FIRST,
390 .max_write_len = 240,
391 .max_comb_1st_msg_len = 6,
392 .max_comb_2nd_msg_len = 240,
395 static int owl_i2c_probe(struct platform_device *pdev)
397 struct device *dev = &pdev->dev;
398 struct owl_i2c_dev *i2c_dev;
399 struct resource *res;
402 i2c_dev = devm_kzalloc(dev, sizeof(*i2c_dev), GFP_KERNEL);
406 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
407 i2c_dev->base = devm_ioremap_resource(dev, res);
408 if (IS_ERR(i2c_dev->base))
409 return PTR_ERR(i2c_dev->base);
411 irq = platform_get_irq(pdev, 0);
413 dev_err(dev, "failed to get IRQ number\n");
417 if (of_property_read_u32(dev->of_node, "clock-frequency",
419 i2c_dev->bus_freq = I2C_MAX_STANDARD_MODE_FREQ;
421 /* We support only frequencies of 100k and 400k for now */
422 if (i2c_dev->bus_freq != I2C_MAX_STANDARD_MODE_FREQ &&
423 i2c_dev->bus_freq != I2C_MAX_FAST_MODE_FREQ) {
424 dev_err(dev, "invalid clock-frequency %d\n", i2c_dev->bus_freq);
428 i2c_dev->clk = devm_clk_get(dev, NULL);
429 if (IS_ERR(i2c_dev->clk)) {
430 dev_err(dev, "failed to get clock\n");
431 return PTR_ERR(i2c_dev->clk);
434 ret = clk_prepare_enable(i2c_dev->clk);
438 i2c_dev->clk_rate = clk_get_rate(i2c_dev->clk);
439 if (!i2c_dev->clk_rate) {
440 dev_err(dev, "input clock rate should not be zero\n");
445 init_completion(&i2c_dev->msg_complete);
446 spin_lock_init(&i2c_dev->lock);
447 i2c_dev->adap.owner = THIS_MODULE;
448 i2c_dev->adap.algo = &owl_i2c_algorithm;
449 i2c_dev->adap.timeout = OWL_I2C_TIMEOUT;
450 i2c_dev->adap.quirks = &owl_i2c_quirks;
451 i2c_dev->adap.dev.parent = dev;
452 i2c_dev->adap.dev.of_node = dev->of_node;
453 snprintf(i2c_dev->adap.name, sizeof(i2c_dev->adap.name),
454 "%s", "OWL I2C adapter");
455 i2c_set_adapdata(&i2c_dev->adap, i2c_dev);
457 platform_set_drvdata(pdev, i2c_dev);
459 ret = devm_request_irq(dev, irq, owl_i2c_interrupt, 0, pdev->name,
462 dev_err(dev, "failed to request irq %d\n", irq);
466 return i2c_add_adapter(&i2c_dev->adap);
469 clk_disable_unprepare(i2c_dev->clk);
474 static const struct of_device_id owl_i2c_of_match[] = {
475 { .compatible = "actions,s700-i2c" },
476 { .compatible = "actions,s900-i2c" },
479 MODULE_DEVICE_TABLE(of, owl_i2c_of_match);
481 static struct platform_driver owl_i2c_driver = {
482 .probe = owl_i2c_probe,
485 .of_match_table = of_match_ptr(owl_i2c_of_match),
488 module_platform_driver(owl_i2c_driver);
490 MODULE_AUTHOR("David Liu <liuwei@actions-semi.com>");
491 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
492 MODULE_DESCRIPTION("Actions Semiconductor Owl SoC's I2C driver");
493 MODULE_LICENSE("GPL");