1 // SPDX-License-Identifier: GPL-2.0
3 * i2c-ocores.c: I2C bus driver for OpenCores I2C controller
4 * (https://opencores.org/project/i2c/overview)
6 * Peter Korsgaard <peter@korsgaard.com>
8 * Support for the GRLIB port of the controller by
9 * Andreas Larsson <andreas@gaisler.com>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/err.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/errno.h>
18 #include <linux/platform_device.h>
19 #include <linux/i2c.h>
20 #include <linux/interrupt.h>
21 #include <linux/wait.h>
22 #include <linux/platform_data/i2c-ocores.h>
23 #include <linux/slab.h>
25 #include <linux/log2.h>
26 #include <linux/spinlock.h>
27 #include <linux/jiffies.h>
30 * 'process_lock' exists because ocores_process() and ocores_process_timeout()
31 * can't run in parallel.
38 wait_queue_head_t wait;
39 struct i2c_adapter adap;
43 int state; /* see STATE_ */
44 spinlock_t process_lock;
48 void (*setreg)(struct ocores_i2c *i2c, int reg, u8 value);
49 u8 (*getreg)(struct ocores_i2c *i2c, int reg);
53 #define OCI2C_PRELOW 0
54 #define OCI2C_PREHIGH 1
55 #define OCI2C_CONTROL 2
57 #define OCI2C_CMD 4 /* write only */
58 #define OCI2C_STATUS 4 /* read only, same address as OCI2C_CMD */
60 #define OCI2C_CTRL_IEN 0x40
61 #define OCI2C_CTRL_EN 0x80
63 #define OCI2C_CMD_START 0x91
64 #define OCI2C_CMD_STOP 0x41
65 #define OCI2C_CMD_READ 0x21
66 #define OCI2C_CMD_WRITE 0x11
67 #define OCI2C_CMD_READ_ACK 0x21
68 #define OCI2C_CMD_READ_NACK 0x29
69 #define OCI2C_CMD_IACK 0x01
71 #define OCI2C_STAT_IF 0x01
72 #define OCI2C_STAT_TIP 0x02
73 #define OCI2C_STAT_ARBLOST 0x20
74 #define OCI2C_STAT_BUSY 0x40
75 #define OCI2C_STAT_NACK 0x80
86 #define OCORES_FLAG_BROKEN_IRQ BIT(1) /* Broken IRQ for FU540-C000 SoC */
88 static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u8 value)
90 iowrite8(value, i2c->base + (reg << i2c->reg_shift));
93 static void oc_setreg_16(struct ocores_i2c *i2c, int reg, u8 value)
95 iowrite16(value, i2c->base + (reg << i2c->reg_shift));
98 static void oc_setreg_32(struct ocores_i2c *i2c, int reg, u8 value)
100 iowrite32(value, i2c->base + (reg << i2c->reg_shift));
103 static void oc_setreg_16be(struct ocores_i2c *i2c, int reg, u8 value)
105 iowrite16be(value, i2c->base + (reg << i2c->reg_shift));
108 static void oc_setreg_32be(struct ocores_i2c *i2c, int reg, u8 value)
110 iowrite32be(value, i2c->base + (reg << i2c->reg_shift));
113 static inline u8 oc_getreg_8(struct ocores_i2c *i2c, int reg)
115 return ioread8(i2c->base + (reg << i2c->reg_shift));
118 static inline u8 oc_getreg_16(struct ocores_i2c *i2c, int reg)
120 return ioread16(i2c->base + (reg << i2c->reg_shift));
123 static inline u8 oc_getreg_32(struct ocores_i2c *i2c, int reg)
125 return ioread32(i2c->base + (reg << i2c->reg_shift));
128 static inline u8 oc_getreg_16be(struct ocores_i2c *i2c, int reg)
130 return ioread16be(i2c->base + (reg << i2c->reg_shift));
133 static inline u8 oc_getreg_32be(struct ocores_i2c *i2c, int reg)
135 return ioread32be(i2c->base + (reg << i2c->reg_shift));
138 static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
140 i2c->setreg(i2c, reg, value);
143 static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
145 return i2c->getreg(i2c, reg);
148 static void ocores_process(struct ocores_i2c *i2c, u8 stat)
150 struct i2c_msg *msg = i2c->msg;
154 * If we spin here is because we are in timeout, so we are going
155 * to be in STATE_ERROR. See ocores_process_timeout()
157 spin_lock_irqsave(&i2c->process_lock, flags);
159 if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) {
160 /* stop has been sent */
161 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
167 if (stat & OCI2C_STAT_ARBLOST) {
168 i2c->state = STATE_ERROR;
169 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
173 if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) {
175 (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
177 if (stat & OCI2C_STAT_NACK) {
178 i2c->state = STATE_ERROR;
179 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
183 msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);
187 if (i2c->pos == msg->len) {
193 if (i2c->nmsgs) { /* end? */
195 if (!(msg->flags & I2C_M_NOSTART)) {
196 u8 addr = i2c_8bit_addr_from_msg(msg);
198 i2c->state = STATE_START;
200 oc_setreg(i2c, OCI2C_DATA, addr);
201 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
204 i2c->state = (msg->flags & I2C_M_RD)
205 ? STATE_READ : STATE_WRITE;
207 i2c->state = STATE_DONE;
208 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
213 if (i2c->state == STATE_READ) {
214 oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ?
215 OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK);
217 oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
218 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
222 spin_unlock_irqrestore(&i2c->process_lock, flags);
225 static irqreturn_t ocores_isr(int irq, void *dev_id)
227 struct ocores_i2c *i2c = dev_id;
228 u8 stat = oc_getreg(i2c, OCI2C_STATUS);
230 if (i2c->flags & OCORES_FLAG_BROKEN_IRQ) {
231 if ((stat & OCI2C_STAT_IF) && !(stat & OCI2C_STAT_BUSY))
233 } else if (!(stat & OCI2C_STAT_IF)) {
236 ocores_process(i2c, stat);
242 * ocores_process_timeout() - Process timeout event
243 * @i2c: ocores I2C device instance
245 static void ocores_process_timeout(struct ocores_i2c *i2c)
249 spin_lock_irqsave(&i2c->process_lock, flags);
250 i2c->state = STATE_ERROR;
251 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
252 spin_unlock_irqrestore(&i2c->process_lock, flags);
256 * ocores_wait() - Wait until something change in a given register
257 * @i2c: ocores I2C device instance
258 * @reg: register to query
259 * @mask: bitmask to apply on register value
260 * @val: expected result
261 * @timeout: timeout in jiffies
263 * Timeout is necessary to avoid to stay here forever when the chip
264 * does not answer correctly.
266 * Return: 0 on success, -ETIMEDOUT on timeout
268 static int ocores_wait(struct ocores_i2c *i2c,
269 int reg, u8 mask, u8 val,
270 const unsigned long timeout)
274 j = jiffies + timeout;
276 u8 status = oc_getreg(i2c, reg);
278 if ((status & mask) == val)
281 if (time_after(jiffies, j))
288 * ocores_poll_wait() - Wait until is possible to process some data
289 * @i2c: ocores I2C device instance
291 * Used when the device is in polling mode (interrupts disabled).
293 * Return: 0 on success, -ETIMEDOUT on timeout
295 static int ocores_poll_wait(struct ocores_i2c *i2c)
300 if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) {
301 /* transfer is over */
302 mask = OCI2C_STAT_BUSY;
304 /* on going transfer */
305 mask = OCI2C_STAT_TIP;
307 * We wait for the data to be transferred (8bit),
308 * then we start polling on the ACK/NACK bit
310 udelay((8 * 1000) / i2c->bus_clock_khz);
314 * once we are here we expect to get the expected result immediately
315 * so if after 1ms we timeout then something is broken.
317 err = ocores_wait(i2c, OCI2C_STATUS, mask, 0, msecs_to_jiffies(1));
319 dev_warn(i2c->adap.dev.parent,
320 "%s: STATUS timeout, bit 0x%x did not clear in 1ms\n",
326 * ocores_process_polling() - It handles an IRQ-less transfer
327 * @i2c: ocores I2C device instance
329 * Even if IRQ are disabled, the I2C OpenCore IP behavior is exactly the same
330 * (only that IRQ are not produced). This means that we can re-use entirely
331 * ocores_isr(), we just add our polling code around it.
333 * It can run in atomic context
335 * Return: 0 on success, -ETIMEDOUT on timeout
337 static int ocores_process_polling(struct ocores_i2c *i2c)
343 err = ocores_poll_wait(i2c);
347 ret = ocores_isr(-1, i2c);
349 break; /* all messages have been transferred */
351 if (i2c->flags & OCORES_FLAG_BROKEN_IRQ)
352 if (i2c->state == STATE_DONE)
360 static int ocores_xfer_core(struct ocores_i2c *i2c,
361 struct i2c_msg *msgs, int num,
367 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
369 oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~OCI2C_CTRL_IEN);
371 oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN);
376 i2c->state = STATE_START;
378 oc_setreg(i2c, OCI2C_DATA, i2c_8bit_addr_from_msg(i2c->msg));
379 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
382 ret = ocores_process_polling(i2c);
384 if (wait_event_timeout(i2c->wait,
385 (i2c->state == STATE_ERROR) ||
386 (i2c->state == STATE_DONE), HZ) == 0)
390 ocores_process_timeout(i2c);
394 return (i2c->state == STATE_DONE) ? num : -EIO;
397 static int ocores_xfer_polling(struct i2c_adapter *adap,
398 struct i2c_msg *msgs, int num)
400 return ocores_xfer_core(i2c_get_adapdata(adap), msgs, num, true);
403 static int ocores_xfer(struct i2c_adapter *adap,
404 struct i2c_msg *msgs, int num)
406 return ocores_xfer_core(i2c_get_adapdata(adap), msgs, num, false);
409 static int ocores_init(struct device *dev, struct ocores_i2c *i2c)
413 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
415 /* make sure the device is disabled */
416 ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN);
417 oc_setreg(i2c, OCI2C_CONTROL, ctrl);
419 prescale = (i2c->ip_clock_khz / (5 * i2c->bus_clock_khz)) - 1;
420 prescale = clamp(prescale, 0, 0xffff);
422 diff = i2c->ip_clock_khz / (5 * (prescale + 1)) - i2c->bus_clock_khz;
423 if (abs(diff) > i2c->bus_clock_khz / 10) {
425 "Unsupported clock settings: core: %d KHz, bus: %d KHz\n",
426 i2c->ip_clock_khz, i2c->bus_clock_khz);
430 oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff);
431 oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8);
433 /* Init the device */
434 oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_EN);
435 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
441 static u32 ocores_func(struct i2c_adapter *adap)
443 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
446 static struct i2c_algorithm ocores_algorithm = {
448 .xfer_atomic = ocores_xfer_polling,
449 .functionality = ocores_func,
452 static const struct i2c_adapter ocores_adapter = {
453 .owner = THIS_MODULE,
454 .name = "i2c-ocores",
455 .class = I2C_CLASS_DEPRECATED,
456 .algo = &ocores_algorithm,
459 static const struct of_device_id ocores_i2c_match[] = {
461 .compatible = "opencores,i2c-ocores",
462 .data = (void *)TYPE_OCORES,
465 .compatible = "aeroflexgaisler,i2cmst",
466 .data = (void *)TYPE_GRLIB,
469 .compatible = "sifive,fu540-c000-i2c",
472 .compatible = "sifive,i2c0",
476 MODULE_DEVICE_TABLE(of, ocores_i2c_match);
480 * Read and write functions for the GRLIB port of the controller. Registers are
481 * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one
482 * register. The subsequent registers have their offsets decreased accordingly.
484 static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg)
489 if (reg != OCI2C_PRELOW)
491 rd = ioread32be(i2c->base + (rreg << i2c->reg_shift));
492 if (reg == OCI2C_PREHIGH)
493 return (u8)(rd >> 8);
498 static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value)
503 if (reg != OCI2C_PRELOW)
505 if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) {
506 curr = ioread32be(i2c->base + (rreg << i2c->reg_shift));
507 if (reg == OCI2C_PRELOW)
508 wr = (curr & 0xff00) | value;
510 wr = (((u32)value) << 8) | (curr & 0xff);
514 iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift));
517 static int ocores_i2c_of_probe(struct platform_device *pdev,
518 struct ocores_i2c *i2c)
520 struct device_node *np = pdev->dev.of_node;
521 const struct of_device_id *match;
524 bool clock_frequency_present;
526 if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) {
527 /* no 'reg-shift', check for deprecated 'regstep' */
528 if (!of_property_read_u32(np, "regstep", &val)) {
529 if (!is_power_of_2(val)) {
530 dev_err(&pdev->dev, "invalid regstep %d\n",
534 i2c->reg_shift = ilog2(val);
536 "regstep property deprecated, use reg-shift\n");
540 clock_frequency_present = !of_property_read_u32(np, "clock-frequency",
542 i2c->bus_clock_khz = 100;
544 i2c->clk = devm_clk_get_optional_enabled(&pdev->dev, NULL);
545 if (IS_ERR(i2c->clk))
546 return dev_err_probe(&pdev->dev, PTR_ERR(i2c->clk),
547 "devm_clk_get_optional_enabled failed\n");
549 i2c->ip_clock_khz = clk_get_rate(i2c->clk) / 1000;
550 if (clock_frequency_present)
551 i2c->bus_clock_khz = clock_frequency / 1000;
552 if (i2c->ip_clock_khz == 0) {
553 if (of_property_read_u32(np, "opencores,ip-clock-frequency",
555 if (!clock_frequency_present) {
557 "Missing required parameter 'opencores,ip-clock-frequency'\n");
560 i2c->ip_clock_khz = clock_frequency / 1000;
562 "Deprecated usage of the 'clock-frequency' property, please update to 'opencores,ip-clock-frequency'\n");
564 i2c->ip_clock_khz = val / 1000;
565 if (clock_frequency_present)
566 i2c->bus_clock_khz = clock_frequency / 1000;
570 of_property_read_u32(pdev->dev.of_node, "reg-io-width",
573 match = of_match_node(ocores_i2c_match, pdev->dev.of_node);
574 if (match && (long)match->data == TYPE_GRLIB) {
575 dev_dbg(&pdev->dev, "GRLIB variant of i2c-ocores\n");
576 i2c->setreg = oc_setreg_grlib;
577 i2c->getreg = oc_getreg_grlib;
583 #define ocores_i2c_of_probe(pdev, i2c) -ENODEV
586 static int ocores_i2c_probe(struct platform_device *pdev)
588 struct ocores_i2c *i2c;
589 struct ocores_i2c_platform_data *pdata;
590 struct resource *res;
595 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
599 spin_lock_init(&i2c->process_lock);
601 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
603 i2c->base = devm_ioremap_resource(&pdev->dev, res);
604 if (IS_ERR(i2c->base))
605 return PTR_ERR(i2c->base);
607 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
610 if (!devm_request_region(&pdev->dev, res->start,
613 dev_err(&pdev->dev, "Can't get I/O resource.\n");
616 i2c->base = devm_ioport_map(&pdev->dev, res->start,
619 dev_err(&pdev->dev, "Can't map I/O resource.\n");
622 i2c->reg_io_width = 1;
625 pdata = dev_get_platdata(&pdev->dev);
627 i2c->reg_shift = pdata->reg_shift;
628 i2c->reg_io_width = pdata->reg_io_width;
629 i2c->ip_clock_khz = pdata->clock_khz;
631 i2c->bus_clock_khz = pdata->bus_khz;
633 i2c->bus_clock_khz = 100;
635 ret = ocores_i2c_of_probe(pdev, i2c);
640 if (i2c->reg_io_width == 0)
641 i2c->reg_io_width = 1; /* Set to default value */
643 if (!i2c->setreg || !i2c->getreg) {
644 bool be = pdata ? pdata->big_endian :
645 of_device_is_big_endian(pdev->dev.of_node);
647 switch (i2c->reg_io_width) {
649 i2c->setreg = oc_setreg_8;
650 i2c->getreg = oc_getreg_8;
654 i2c->setreg = be ? oc_setreg_16be : oc_setreg_16;
655 i2c->getreg = be ? oc_getreg_16be : oc_getreg_16;
659 i2c->setreg = be ? oc_setreg_32be : oc_setreg_32;
660 i2c->getreg = be ? oc_getreg_32be : oc_getreg_32;
664 dev_err(&pdev->dev, "Unsupported I/O width (%d)\n",
670 init_waitqueue_head(&i2c->wait);
672 irq = platform_get_irq_optional(pdev, 0);
674 * Since the SoC does have an interrupt, its DT has an interrupt
675 * property - But this should be bypassed as the IRQ logic in this
678 if (of_device_is_compatible(pdev->dev.of_node,
679 "sifive,fu540-c000-i2c")) {
680 i2c->flags |= OCORES_FLAG_BROKEN_IRQ;
685 ocores_algorithm.xfer = ocores_xfer_polling;
691 if (ocores_algorithm.xfer != ocores_xfer_polling) {
692 ret = devm_request_any_context_irq(&pdev->dev, irq,
696 dev_err(&pdev->dev, "Cannot claim IRQ\n");
701 ret = ocores_init(&pdev->dev, i2c);
705 /* hook up driver to tree */
706 platform_set_drvdata(pdev, i2c);
707 i2c->adap = ocores_adapter;
708 i2c_set_adapdata(&i2c->adap, i2c);
709 i2c->adap.dev.parent = &pdev->dev;
710 i2c->adap.dev.of_node = pdev->dev.of_node;
712 /* add i2c adapter to i2c tree */
713 ret = i2c_add_adapter(&i2c->adap);
717 /* add in known devices to the bus */
719 for (i = 0; i < pdata->num_devices; i++)
720 i2c_new_client_device(&i2c->adap, pdata->devices + i);
726 static void ocores_i2c_remove(struct platform_device *pdev)
728 struct ocores_i2c *i2c = platform_get_drvdata(pdev);
729 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
731 /* disable i2c logic */
732 ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN);
733 oc_setreg(i2c, OCI2C_CONTROL, ctrl);
735 /* remove adapter & data */
736 i2c_del_adapter(&i2c->adap);
739 static int ocores_i2c_suspend(struct device *dev)
741 struct ocores_i2c *i2c = dev_get_drvdata(dev);
742 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
744 /* make sure the device is disabled */
745 ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN);
746 oc_setreg(i2c, OCI2C_CONTROL, ctrl);
748 clk_disable_unprepare(i2c->clk);
752 static int ocores_i2c_resume(struct device *dev)
754 struct ocores_i2c *i2c = dev_get_drvdata(dev);
758 ret = clk_prepare_enable(i2c->clk);
760 return dev_err_probe(dev, ret, "clk_prepare_enable failed\n");
761 rate = clk_get_rate(i2c->clk) / 1000;
763 i2c->ip_clock_khz = rate;
764 return ocores_init(dev, i2c);
767 static DEFINE_NOIRQ_DEV_PM_OPS(ocores_i2c_pm,
768 ocores_i2c_suspend, ocores_i2c_resume);
770 static struct platform_driver ocores_i2c_driver = {
771 .probe = ocores_i2c_probe,
772 .remove_new = ocores_i2c_remove,
774 .name = "ocores-i2c",
775 .of_match_table = ocores_i2c_match,
776 .pm = pm_sleep_ptr(&ocores_i2c_pm),
780 module_platform_driver(ocores_i2c_driver);
782 MODULE_AUTHOR("Peter Korsgaard <peter@korsgaard.com>");
783 MODULE_DESCRIPTION("OpenCores I2C bus driver");
784 MODULE_LICENSE("GPL");
785 MODULE_ALIAS("platform:ocores-i2c");