1 // SPDX-License-Identifier: GPL-2.0
3 * i2c-ocores.c: I2C bus driver for OpenCores I2C controller
4 * (https://opencores.org/project/i2c/overview)
6 * Peter Korsgaard <peter@korsgaard.com>
8 * Support for the GRLIB port of the controller by
9 * Andreas Larsson <andreas@gaisler.com>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/err.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/errno.h>
18 #include <linux/platform_device.h>
19 #include <linux/i2c.h>
20 #include <linux/interrupt.h>
21 #include <linux/wait.h>
22 #include <linux/platform_data/i2c-ocores.h>
23 #include <linux/slab.h>
25 #include <linux/log2.h>
26 #include <linux/spinlock.h>
27 #include <linux/jiffies.h>
30 * 'process_lock' exists because ocores_process() and ocores_process_timeout()
31 * can't run in parallel.
39 wait_queue_head_t wait;
40 struct i2c_adapter adap;
44 int state; /* see STATE_ */
45 spinlock_t process_lock;
49 void (*setreg)(struct ocores_i2c *i2c, int reg, u8 value);
50 u8 (*getreg)(struct ocores_i2c *i2c, int reg);
54 #define OCI2C_PRELOW 0
55 #define OCI2C_PREHIGH 1
56 #define OCI2C_CONTROL 2
58 #define OCI2C_CMD 4 /* write only */
59 #define OCI2C_STATUS 4 /* read only, same address as OCI2C_CMD */
61 #define OCI2C_CTRL_IEN 0x40
62 #define OCI2C_CTRL_EN 0x80
64 #define OCI2C_CMD_START 0x91
65 #define OCI2C_CMD_STOP 0x41
66 #define OCI2C_CMD_READ 0x21
67 #define OCI2C_CMD_WRITE 0x11
68 #define OCI2C_CMD_READ_ACK 0x21
69 #define OCI2C_CMD_READ_NACK 0x29
70 #define OCI2C_CMD_IACK 0x01
72 #define OCI2C_STAT_IF 0x01
73 #define OCI2C_STAT_TIP 0x02
74 #define OCI2C_STAT_ARBLOST 0x20
75 #define OCI2C_STAT_BUSY 0x40
76 #define OCI2C_STAT_NACK 0x80
87 #define OCORES_FLAG_BROKEN_IRQ BIT(1) /* Broken IRQ for FU540-C000 SoC */
89 static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u8 value)
91 iowrite8(value, i2c->base + (reg << i2c->reg_shift));
94 static void oc_setreg_16(struct ocores_i2c *i2c, int reg, u8 value)
96 iowrite16(value, i2c->base + (reg << i2c->reg_shift));
99 static void oc_setreg_32(struct ocores_i2c *i2c, int reg, u8 value)
101 iowrite32(value, i2c->base + (reg << i2c->reg_shift));
104 static void oc_setreg_16be(struct ocores_i2c *i2c, int reg, u8 value)
106 iowrite16be(value, i2c->base + (reg << i2c->reg_shift));
109 static void oc_setreg_32be(struct ocores_i2c *i2c, int reg, u8 value)
111 iowrite32be(value, i2c->base + (reg << i2c->reg_shift));
114 static inline u8 oc_getreg_8(struct ocores_i2c *i2c, int reg)
116 return ioread8(i2c->base + (reg << i2c->reg_shift));
119 static inline u8 oc_getreg_16(struct ocores_i2c *i2c, int reg)
121 return ioread16(i2c->base + (reg << i2c->reg_shift));
124 static inline u8 oc_getreg_32(struct ocores_i2c *i2c, int reg)
126 return ioread32(i2c->base + (reg << i2c->reg_shift));
129 static inline u8 oc_getreg_16be(struct ocores_i2c *i2c, int reg)
131 return ioread16be(i2c->base + (reg << i2c->reg_shift));
134 static inline u8 oc_getreg_32be(struct ocores_i2c *i2c, int reg)
136 return ioread32be(i2c->base + (reg << i2c->reg_shift));
139 static void oc_setreg_io_8(struct ocores_i2c *i2c, int reg, u8 value)
141 outb(value, i2c->iobase + reg);
144 static inline u8 oc_getreg_io_8(struct ocores_i2c *i2c, int reg)
146 return inb(i2c->iobase + reg);
149 static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
151 i2c->setreg(i2c, reg, value);
154 static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
156 return i2c->getreg(i2c, reg);
159 static void ocores_process(struct ocores_i2c *i2c, u8 stat)
161 struct i2c_msg *msg = i2c->msg;
165 * If we spin here is because we are in timeout, so we are going
166 * to be in STATE_ERROR. See ocores_process_timeout()
168 spin_lock_irqsave(&i2c->process_lock, flags);
170 if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) {
171 /* stop has been sent */
172 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
178 if (stat & OCI2C_STAT_ARBLOST) {
179 i2c->state = STATE_ERROR;
180 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
184 if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) {
186 (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
188 if (stat & OCI2C_STAT_NACK) {
189 i2c->state = STATE_ERROR;
190 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
194 msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);
198 if (i2c->pos == msg->len) {
204 if (i2c->nmsgs) { /* end? */
206 if (!(msg->flags & I2C_M_NOSTART)) {
207 u8 addr = i2c_8bit_addr_from_msg(msg);
209 i2c->state = STATE_START;
211 oc_setreg(i2c, OCI2C_DATA, addr);
212 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
215 i2c->state = (msg->flags & I2C_M_RD)
216 ? STATE_READ : STATE_WRITE;
218 i2c->state = STATE_DONE;
219 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
224 if (i2c->state == STATE_READ) {
225 oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ?
226 OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK);
228 oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
229 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
233 spin_unlock_irqrestore(&i2c->process_lock, flags);
236 static irqreturn_t ocores_isr(int irq, void *dev_id)
238 struct ocores_i2c *i2c = dev_id;
239 u8 stat = oc_getreg(i2c, OCI2C_STATUS);
241 if (i2c->flags & OCORES_FLAG_BROKEN_IRQ) {
242 if ((stat & OCI2C_STAT_IF) && !(stat & OCI2C_STAT_BUSY))
244 } else if (!(stat & OCI2C_STAT_IF)) {
247 ocores_process(i2c, stat);
253 * ocores_process_timeout() - Process timeout event
254 * @i2c: ocores I2C device instance
256 static void ocores_process_timeout(struct ocores_i2c *i2c)
260 spin_lock_irqsave(&i2c->process_lock, flags);
261 i2c->state = STATE_ERROR;
262 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
263 spin_unlock_irqrestore(&i2c->process_lock, flags);
267 * ocores_wait() - Wait until something change in a given register
268 * @i2c: ocores I2C device instance
269 * @reg: register to query
270 * @mask: bitmask to apply on register value
271 * @val: expected result
272 * @timeout: timeout in jiffies
274 * Timeout is necessary to avoid to stay here forever when the chip
275 * does not answer correctly.
277 * Return: 0 on success, -ETIMEDOUT on timeout
279 static int ocores_wait(struct ocores_i2c *i2c,
280 int reg, u8 mask, u8 val,
281 const unsigned long timeout)
285 j = jiffies + timeout;
287 u8 status = oc_getreg(i2c, reg);
289 if ((status & mask) == val)
292 if (time_after(jiffies, j))
299 * ocores_poll_wait() - Wait until is possible to process some data
300 * @i2c: ocores I2C device instance
302 * Used when the device is in polling mode (interrupts disabled).
304 * Return: 0 on success, -ETIMEDOUT on timeout
306 static int ocores_poll_wait(struct ocores_i2c *i2c)
311 if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) {
312 /* transfer is over */
313 mask = OCI2C_STAT_BUSY;
315 /* on going transfer */
316 mask = OCI2C_STAT_TIP;
318 * We wait for the data to be transferred (8bit),
319 * then we start polling on the ACK/NACK bit
321 udelay((8 * 1000) / i2c->bus_clock_khz);
325 * once we are here we expect to get the expected result immediately
326 * so if after 1ms we timeout then something is broken.
328 err = ocores_wait(i2c, OCI2C_STATUS, mask, 0, msecs_to_jiffies(1));
330 dev_warn(i2c->adap.dev.parent,
331 "%s: STATUS timeout, bit 0x%x did not clear in 1ms\n",
337 * ocores_process_polling() - It handles an IRQ-less transfer
338 * @i2c: ocores I2C device instance
340 * Even if IRQ are disabled, the I2C OpenCore IP behavior is exactly the same
341 * (only that IRQ are not produced). This means that we can re-use entirely
342 * ocores_isr(), we just add our polling code around it.
344 * It can run in atomic context
346 static void ocores_process_polling(struct ocores_i2c *i2c)
352 err = ocores_poll_wait(i2c);
354 i2c->state = STATE_ERROR;
358 ret = ocores_isr(-1, i2c);
360 break; /* all messages have been transferred */
362 if (i2c->flags & OCORES_FLAG_BROKEN_IRQ)
363 if (i2c->state == STATE_DONE)
369 static int ocores_xfer_core(struct ocores_i2c *i2c,
370 struct i2c_msg *msgs, int num,
376 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
378 oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~OCI2C_CTRL_IEN);
380 oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN);
385 i2c->state = STATE_START;
387 oc_setreg(i2c, OCI2C_DATA, i2c_8bit_addr_from_msg(i2c->msg));
388 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
391 ocores_process_polling(i2c);
393 ret = wait_event_timeout(i2c->wait,
394 (i2c->state == STATE_ERROR) ||
395 (i2c->state == STATE_DONE), HZ);
397 ocores_process_timeout(i2c);
402 return (i2c->state == STATE_DONE) ? num : -EIO;
405 static int ocores_xfer_polling(struct i2c_adapter *adap,
406 struct i2c_msg *msgs, int num)
408 return ocores_xfer_core(i2c_get_adapdata(adap), msgs, num, true);
411 static int ocores_xfer(struct i2c_adapter *adap,
412 struct i2c_msg *msgs, int num)
414 return ocores_xfer_core(i2c_get_adapdata(adap), msgs, num, false);
417 static int ocores_init(struct device *dev, struct ocores_i2c *i2c)
421 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
423 /* make sure the device is disabled */
424 ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN);
425 oc_setreg(i2c, OCI2C_CONTROL, ctrl);
427 prescale = (i2c->ip_clock_khz / (5 * i2c->bus_clock_khz)) - 1;
428 prescale = clamp(prescale, 0, 0xffff);
430 diff = i2c->ip_clock_khz / (5 * (prescale + 1)) - i2c->bus_clock_khz;
431 if (abs(diff) > i2c->bus_clock_khz / 10) {
433 "Unsupported clock settings: core: %d KHz, bus: %d KHz\n",
434 i2c->ip_clock_khz, i2c->bus_clock_khz);
438 oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff);
439 oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8);
441 /* Init the device */
442 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
443 oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_EN);
449 static u32 ocores_func(struct i2c_adapter *adap)
451 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
454 static struct i2c_algorithm ocores_algorithm = {
455 .master_xfer = ocores_xfer,
456 .master_xfer_atomic = ocores_xfer_polling,
457 .functionality = ocores_func,
460 static const struct i2c_adapter ocores_adapter = {
461 .owner = THIS_MODULE,
462 .name = "i2c-ocores",
463 .class = I2C_CLASS_DEPRECATED,
464 .algo = &ocores_algorithm,
467 static const struct of_device_id ocores_i2c_match[] = {
469 .compatible = "opencores,i2c-ocores",
470 .data = (void *)TYPE_OCORES,
473 .compatible = "aeroflexgaisler,i2cmst",
474 .data = (void *)TYPE_GRLIB,
477 .compatible = "sifive,fu540-c000-i2c",
480 .compatible = "sifive,i2c0",
484 MODULE_DEVICE_TABLE(of, ocores_i2c_match);
488 * Read and write functions for the GRLIB port of the controller. Registers are
489 * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one
490 * register. The subsequent registers have their offsets decreased accordingly.
492 static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg)
497 if (reg != OCI2C_PRELOW)
499 rd = ioread32be(i2c->base + (rreg << i2c->reg_shift));
500 if (reg == OCI2C_PREHIGH)
501 return (u8)(rd >> 8);
506 static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value)
511 if (reg != OCI2C_PRELOW)
513 if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) {
514 curr = ioread32be(i2c->base + (rreg << i2c->reg_shift));
515 if (reg == OCI2C_PRELOW)
516 wr = (curr & 0xff00) | value;
518 wr = (((u32)value) << 8) | (curr & 0xff);
522 iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift));
525 static int ocores_i2c_of_probe(struct platform_device *pdev,
526 struct ocores_i2c *i2c)
528 struct device_node *np = pdev->dev.of_node;
529 const struct of_device_id *match;
532 bool clock_frequency_present;
534 if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) {
535 /* no 'reg-shift', check for deprecated 'regstep' */
536 if (!of_property_read_u32(np, "regstep", &val)) {
537 if (!is_power_of_2(val)) {
538 dev_err(&pdev->dev, "invalid regstep %d\n",
542 i2c->reg_shift = ilog2(val);
544 "regstep property deprecated, use reg-shift\n");
548 clock_frequency_present = !of_property_read_u32(np, "clock-frequency",
550 i2c->bus_clock_khz = 100;
552 i2c->clk = devm_clk_get(&pdev->dev, NULL);
554 if (!IS_ERR(i2c->clk)) {
555 int ret = clk_prepare_enable(i2c->clk);
559 "clk_prepare_enable failed: %d\n", ret);
562 i2c->ip_clock_khz = clk_get_rate(i2c->clk) / 1000;
563 if (clock_frequency_present)
564 i2c->bus_clock_khz = clock_frequency / 1000;
567 if (i2c->ip_clock_khz == 0) {
568 if (of_property_read_u32(np, "opencores,ip-clock-frequency",
570 if (!clock_frequency_present) {
572 "Missing required parameter 'opencores,ip-clock-frequency'\n");
573 clk_disable_unprepare(i2c->clk);
576 i2c->ip_clock_khz = clock_frequency / 1000;
578 "Deprecated usage of the 'clock-frequency' property, please update to 'opencores,ip-clock-frequency'\n");
580 i2c->ip_clock_khz = val / 1000;
581 if (clock_frequency_present)
582 i2c->bus_clock_khz = clock_frequency / 1000;
586 of_property_read_u32(pdev->dev.of_node, "reg-io-width",
589 match = of_match_node(ocores_i2c_match, pdev->dev.of_node);
590 if (match && (long)match->data == TYPE_GRLIB) {
591 dev_dbg(&pdev->dev, "GRLIB variant of i2c-ocores\n");
592 i2c->setreg = oc_setreg_grlib;
593 i2c->getreg = oc_getreg_grlib;
599 #define ocores_i2c_of_probe(pdev, i2c) -ENODEV
602 static int ocores_i2c_probe(struct platform_device *pdev)
604 struct ocores_i2c *i2c;
605 struct ocores_i2c_platform_data *pdata;
606 struct resource *res;
611 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
615 spin_lock_init(&i2c->process_lock);
617 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
619 i2c->base = devm_ioremap_resource(&pdev->dev, res);
620 if (IS_ERR(i2c->base))
621 return PTR_ERR(i2c->base);
623 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
626 i2c->iobase = res->start;
627 if (!devm_request_region(&pdev->dev, res->start,
630 dev_err(&pdev->dev, "Can't get I/O resource.\n");
633 i2c->setreg = oc_setreg_io_8;
634 i2c->getreg = oc_getreg_io_8;
637 pdata = dev_get_platdata(&pdev->dev);
639 i2c->reg_shift = pdata->reg_shift;
640 i2c->reg_io_width = pdata->reg_io_width;
641 i2c->ip_clock_khz = pdata->clock_khz;
643 i2c->bus_clock_khz = pdata->bus_khz;
645 i2c->bus_clock_khz = 100;
647 ret = ocores_i2c_of_probe(pdev, i2c);
652 if (i2c->reg_io_width == 0)
653 i2c->reg_io_width = 1; /* Set to default value */
655 if (!i2c->setreg || !i2c->getreg) {
656 bool be = pdata ? pdata->big_endian :
657 of_device_is_big_endian(pdev->dev.of_node);
659 switch (i2c->reg_io_width) {
661 i2c->setreg = oc_setreg_8;
662 i2c->getreg = oc_getreg_8;
666 i2c->setreg = be ? oc_setreg_16be : oc_setreg_16;
667 i2c->getreg = be ? oc_getreg_16be : oc_getreg_16;
671 i2c->setreg = be ? oc_setreg_32be : oc_setreg_32;
672 i2c->getreg = be ? oc_getreg_32be : oc_getreg_32;
676 dev_err(&pdev->dev, "Unsupported I/O width (%d)\n",
683 init_waitqueue_head(&i2c->wait);
685 irq = platform_get_irq_optional(pdev, 0);
687 * Since the SoC does have an interrupt, its DT has an interrupt
688 * property - But this should be bypassed as the IRQ logic in this
691 if (of_device_is_compatible(pdev->dev.of_node,
692 "sifive,fu540-c000-i2c")) {
693 i2c->flags |= OCORES_FLAG_BROKEN_IRQ;
698 ocores_algorithm.master_xfer = ocores_xfer_polling;
704 if (ocores_algorithm.master_xfer != ocores_xfer_polling) {
705 ret = devm_request_any_context_irq(&pdev->dev, irq,
709 dev_err(&pdev->dev, "Cannot claim IRQ\n");
714 ret = ocores_init(&pdev->dev, i2c);
718 /* hook up driver to tree */
719 platform_set_drvdata(pdev, i2c);
720 i2c->adap = ocores_adapter;
721 i2c_set_adapdata(&i2c->adap, i2c);
722 i2c->adap.dev.parent = &pdev->dev;
723 i2c->adap.dev.of_node = pdev->dev.of_node;
725 /* add i2c adapter to i2c tree */
726 ret = i2c_add_adapter(&i2c->adap);
730 /* add in known devices to the bus */
732 for (i = 0; i < pdata->num_devices; i++)
733 i2c_new_client_device(&i2c->adap, pdata->devices + i);
739 clk_disable_unprepare(i2c->clk);
743 static int ocores_i2c_remove(struct platform_device *pdev)
745 struct ocores_i2c *i2c = platform_get_drvdata(pdev);
746 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
748 /* disable i2c logic */
749 ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN);
750 oc_setreg(i2c, OCI2C_CONTROL, ctrl);
752 /* remove adapter & data */
753 i2c_del_adapter(&i2c->adap);
755 if (!IS_ERR(i2c->clk))
756 clk_disable_unprepare(i2c->clk);
761 #ifdef CONFIG_PM_SLEEP
762 static int ocores_i2c_suspend(struct device *dev)
764 struct ocores_i2c *i2c = dev_get_drvdata(dev);
765 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
767 /* make sure the device is disabled */
768 ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN);
769 oc_setreg(i2c, OCI2C_CONTROL, ctrl);
771 if (!IS_ERR(i2c->clk))
772 clk_disable_unprepare(i2c->clk);
776 static int ocores_i2c_resume(struct device *dev)
778 struct ocores_i2c *i2c = dev_get_drvdata(dev);
780 if (!IS_ERR(i2c->clk)) {
782 int ret = clk_prepare_enable(i2c->clk);
786 "clk_prepare_enable failed: %d\n", ret);
789 rate = clk_get_rate(i2c->clk) / 1000;
791 i2c->ip_clock_khz = rate;
793 return ocores_init(dev, i2c);
796 static SIMPLE_DEV_PM_OPS(ocores_i2c_pm, ocores_i2c_suspend, ocores_i2c_resume);
797 #define OCORES_I2C_PM (&ocores_i2c_pm)
799 #define OCORES_I2C_PM NULL
802 static struct platform_driver ocores_i2c_driver = {
803 .probe = ocores_i2c_probe,
804 .remove = ocores_i2c_remove,
806 .name = "ocores-i2c",
807 .of_match_table = ocores_i2c_match,
812 module_platform_driver(ocores_i2c_driver);
814 MODULE_AUTHOR("Peter Korsgaard <peter@korsgaard.com>");
815 MODULE_DESCRIPTION("OpenCores I2C bus driver");
816 MODULE_LICENSE("GPL");
817 MODULE_ALIAS("platform:ocores-i2c");