1 // SPDX-License-Identifier: GPL-2.0
3 * Nvidia GPU I2C controller Driver
5 * Copyright (C) 2018 NVIDIA Corporation. All rights reserved.
6 * Author: Ajay Gupta <ajayg@nvidia.com>
8 #include <linux/delay.h>
10 #include <linux/interrupt.h>
11 #include <linux/iopoll.h>
12 #include <linux/module.h>
13 #include <linux/pci.h>
14 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
18 #include <asm/unaligned.h>
21 #define I2C_MST_CNTL 0x00
22 #define I2C_MST_CNTL_GEN_START BIT(0)
23 #define I2C_MST_CNTL_GEN_STOP BIT(1)
24 #define I2C_MST_CNTL_CMD_READ (1 << 2)
25 #define I2C_MST_CNTL_CMD_WRITE (2 << 2)
26 #define I2C_MST_CNTL_BURST_SIZE_SHIFT 6
27 #define I2C_MST_CNTL_GEN_NACK BIT(28)
28 #define I2C_MST_CNTL_STATUS GENMASK(30, 29)
29 #define I2C_MST_CNTL_STATUS_OKAY (0 << 29)
30 #define I2C_MST_CNTL_STATUS_NO_ACK (1 << 29)
31 #define I2C_MST_CNTL_STATUS_TIMEOUT (2 << 29)
32 #define I2C_MST_CNTL_STATUS_BUS_BUSY (3 << 29)
33 #define I2C_MST_CNTL_CYCLE_TRIGGER BIT(31)
35 #define I2C_MST_ADDR 0x04
37 #define I2C_MST_I2C0_TIMING 0x08
38 #define I2C_MST_I2C0_TIMING_SCL_PERIOD_100KHZ 0x10e
39 #define I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT 16
40 #define I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT_MAX 255
41 #define I2C_MST_I2C0_TIMING_TIMEOUT_CHECK BIT(24)
43 #define I2C_MST_DATA 0x0c
45 #define I2C_MST_HYBRID_PADCTL 0x20
46 #define I2C_MST_HYBRID_PADCTL_MODE_I2C BIT(0)
47 #define I2C_MST_HYBRID_PADCTL_I2C_SCL_INPUT_RCV BIT(14)
48 #define I2C_MST_HYBRID_PADCTL_I2C_SDA_INPUT_RCV BIT(15)
53 struct i2c_adapter adapter;
54 struct i2c_board_info *gpu_ccgx_ucsi;
55 struct i2c_client *ccgx_client;
58 static void gpu_enable_i2c_bus(struct gpu_i2c_dev *i2cd)
63 val = readl(i2cd->regs + I2C_MST_HYBRID_PADCTL);
64 val |= I2C_MST_HYBRID_PADCTL_MODE_I2C |
65 I2C_MST_HYBRID_PADCTL_I2C_SCL_INPUT_RCV |
66 I2C_MST_HYBRID_PADCTL_I2C_SDA_INPUT_RCV;
67 writel(val, i2cd->regs + I2C_MST_HYBRID_PADCTL);
69 /* enable 100KHZ mode */
70 val = I2C_MST_I2C0_TIMING_SCL_PERIOD_100KHZ;
71 val |= (I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT_MAX
72 << I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT);
73 val |= I2C_MST_I2C0_TIMING_TIMEOUT_CHECK;
74 writel(val, i2cd->regs + I2C_MST_I2C0_TIMING);
77 static int gpu_i2c_check_status(struct gpu_i2c_dev *i2cd)
82 ret = readl_poll_timeout(i2cd->regs + I2C_MST_CNTL, val,
83 !(val & I2C_MST_CNTL_CYCLE_TRIGGER) ||
84 (val & I2C_MST_CNTL_STATUS) != I2C_MST_CNTL_STATUS_BUS_BUSY,
85 500, 1000 * USEC_PER_MSEC);
88 dev_err(i2cd->dev, "i2c timeout error %x\n", val);
92 val = readl(i2cd->regs + I2C_MST_CNTL);
93 switch (val & I2C_MST_CNTL_STATUS) {
94 case I2C_MST_CNTL_STATUS_OKAY:
96 case I2C_MST_CNTL_STATUS_NO_ACK:
98 case I2C_MST_CNTL_STATUS_TIMEOUT:
105 static int gpu_i2c_read(struct gpu_i2c_dev *i2cd, u8 *data, u16 len)
110 val = I2C_MST_CNTL_GEN_START | I2C_MST_CNTL_CMD_READ |
111 (len << I2C_MST_CNTL_BURST_SIZE_SHIFT) |
112 I2C_MST_CNTL_CYCLE_TRIGGER | I2C_MST_CNTL_GEN_NACK;
113 writel(val, i2cd->regs + I2C_MST_CNTL);
115 status = gpu_i2c_check_status(i2cd);
119 val = readl(i2cd->regs + I2C_MST_DATA);
125 put_unaligned_be16(val, data);
128 put_unaligned_be24(val, data);
131 put_unaligned_be32(val, data);
139 static int gpu_i2c_start(struct gpu_i2c_dev *i2cd)
141 writel(I2C_MST_CNTL_GEN_START, i2cd->regs + I2C_MST_CNTL);
142 return gpu_i2c_check_status(i2cd);
145 static int gpu_i2c_stop(struct gpu_i2c_dev *i2cd)
147 writel(I2C_MST_CNTL_GEN_STOP, i2cd->regs + I2C_MST_CNTL);
148 return gpu_i2c_check_status(i2cd);
151 static int gpu_i2c_write(struct gpu_i2c_dev *i2cd, u8 data)
155 writel(data, i2cd->regs + I2C_MST_DATA);
157 val = I2C_MST_CNTL_CMD_WRITE | (1 << I2C_MST_CNTL_BURST_SIZE_SHIFT);
158 writel(val, i2cd->regs + I2C_MST_CNTL);
160 return gpu_i2c_check_status(i2cd);
163 static int gpu_i2c_master_xfer(struct i2c_adapter *adap,
164 struct i2c_msg *msgs, int num)
166 struct gpu_i2c_dev *i2cd = i2c_get_adapdata(adap);
168 bool send_stop = true;
172 * The controller supports maximum 4 byte read due to known
173 * limitation of sending STOP after every read.
175 pm_runtime_get_sync(i2cd->dev);
176 for (i = 0; i < num; i++) {
177 if (msgs[i].flags & I2C_M_RD) {
178 /* program client address before starting read */
179 writel(msgs[i].addr, i2cd->regs + I2C_MST_ADDR);
180 /* gpu_i2c_read has implicit start */
181 status = gpu_i2c_read(i2cd, msgs[i].buf, msgs[i].len);
185 u8 addr = i2c_8bit_addr_from_msg(msgs + i);
187 status = gpu_i2c_start(i2cd);
194 status = gpu_i2c_write(i2cd, addr);
198 for (j = 0; j < msgs[i].len; j++) {
199 status = gpu_i2c_write(i2cd, msgs[i].buf[j]);
206 status = gpu_i2c_stop(i2cd);
213 status2 = gpu_i2c_stop(i2cd);
215 dev_err(i2cd->dev, "i2c stop failed %d\n", status2);
217 pm_runtime_mark_last_busy(i2cd->dev);
218 pm_runtime_put_autosuspend(i2cd->dev);
222 static const struct i2c_adapter_quirks gpu_i2c_quirks = {
224 .max_comb_2nd_msg_len = 4,
225 .flags = I2C_AQ_COMB_WRITE_THEN_READ,
228 static u32 gpu_i2c_functionality(struct i2c_adapter *adap)
230 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
233 static const struct i2c_algorithm gpu_i2c_algorithm = {
234 .master_xfer = gpu_i2c_master_xfer,
235 .functionality = gpu_i2c_functionality,
239 * This driver is for Nvidia GPU cards with USB Type-C interface.
240 * We want to identify the cards using vendor ID and class code only
241 * to avoid dependency of adding product id for any new card which
242 * requires this driver.
243 * Currently there is no class code defined for UCSI device over PCI
244 * so using UNKNOWN class for now and it will be updated when UCSI
245 * over PCI gets a class code.
246 * There is no other NVIDIA cards with UNKNOWN class code. Even if the
247 * driver gets loaded for an undesired card then eventually i2c_read()
248 * (initiated from UCSI i2c_client) will timeout or UCSI commands will
251 #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80
252 static const struct pci_device_id gpu_i2c_ids[] = {
253 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
254 PCI_CLASS_SERIAL_UNKNOWN << 8, 0xffffff00},
257 MODULE_DEVICE_TABLE(pci, gpu_i2c_ids);
259 static const struct property_entry ccgx_props[] = {
260 /* Use FW built for NVIDIA (nv) only */
261 PROPERTY_ENTRY_U16("ccgx,firmware-build", ('n' << 8) | 'v'),
265 static const struct software_node ccgx_node = {
266 .properties = ccgx_props,
269 static int gpu_populate_client(struct gpu_i2c_dev *i2cd, int irq)
271 i2cd->gpu_ccgx_ucsi = devm_kzalloc(i2cd->dev,
272 sizeof(*i2cd->gpu_ccgx_ucsi),
274 if (!i2cd->gpu_ccgx_ucsi)
277 strlcpy(i2cd->gpu_ccgx_ucsi->type, "ccgx-ucsi",
278 sizeof(i2cd->gpu_ccgx_ucsi->type));
279 i2cd->gpu_ccgx_ucsi->addr = 0x8;
280 i2cd->gpu_ccgx_ucsi->irq = irq;
281 i2cd->gpu_ccgx_ucsi->swnode = &ccgx_node;
282 i2cd->ccgx_client = i2c_new_client_device(&i2cd->adapter, i2cd->gpu_ccgx_ucsi);
283 return PTR_ERR_OR_ZERO(i2cd->ccgx_client);
286 static int gpu_i2c_probe(struct pci_dev *pdev, const struct pci_device_id *id)
288 struct gpu_i2c_dev *i2cd;
291 i2cd = devm_kzalloc(&pdev->dev, sizeof(*i2cd), GFP_KERNEL);
295 i2cd->dev = &pdev->dev;
296 dev_set_drvdata(&pdev->dev, i2cd);
298 status = pcim_enable_device(pdev);
300 dev_err(&pdev->dev, "pcim_enable_device failed %d\n", status);
304 pci_set_master(pdev);
306 i2cd->regs = pcim_iomap(pdev, 0, 0);
308 dev_err(&pdev->dev, "pcim_iomap failed\n");
312 status = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
314 dev_err(&pdev->dev, "pci_alloc_irq_vectors err %d\n", status);
318 gpu_enable_i2c_bus(i2cd);
320 i2c_set_adapdata(&i2cd->adapter, i2cd);
321 i2cd->adapter.owner = THIS_MODULE;
322 strlcpy(i2cd->adapter.name, "NVIDIA GPU I2C adapter",
323 sizeof(i2cd->adapter.name));
324 i2cd->adapter.algo = &gpu_i2c_algorithm;
325 i2cd->adapter.quirks = &gpu_i2c_quirks;
326 i2cd->adapter.dev.parent = &pdev->dev;
327 status = i2c_add_adapter(&i2cd->adapter);
329 goto free_irq_vectors;
331 status = gpu_populate_client(i2cd, pdev->irq);
333 dev_err(&pdev->dev, "gpu_populate_client failed %d\n", status);
337 pm_runtime_set_autosuspend_delay(&pdev->dev, 3000);
338 pm_runtime_use_autosuspend(&pdev->dev);
339 pm_runtime_put_autosuspend(&pdev->dev);
340 pm_runtime_allow(&pdev->dev);
345 i2c_del_adapter(&i2cd->adapter);
347 pci_free_irq_vectors(pdev);
351 static void gpu_i2c_remove(struct pci_dev *pdev)
353 struct gpu_i2c_dev *i2cd = dev_get_drvdata(&pdev->dev);
355 pm_runtime_get_noresume(i2cd->dev);
356 i2c_del_adapter(&i2cd->adapter);
357 pci_free_irq_vectors(pdev);
360 #define gpu_i2c_suspend NULL
362 static __maybe_unused int gpu_i2c_resume(struct device *dev)
364 struct gpu_i2c_dev *i2cd = dev_get_drvdata(dev);
366 gpu_enable_i2c_bus(i2cd);
368 * Runtime resume ccgx client so that it can see for any
369 * connector change event. Old ccg firmware has known
370 * issue of not triggering interrupt when a device is
371 * connected to runtime resume the controller.
373 pm_request_resume(&i2cd->ccgx_client->dev);
377 static UNIVERSAL_DEV_PM_OPS(gpu_i2c_driver_pm, gpu_i2c_suspend, gpu_i2c_resume,
380 static struct pci_driver gpu_i2c_driver = {
381 .name = "nvidia-gpu",
382 .id_table = gpu_i2c_ids,
383 .probe = gpu_i2c_probe,
384 .remove = gpu_i2c_remove,
386 .pm = &gpu_i2c_driver_pm,
390 module_pci_driver(gpu_i2c_driver);
392 MODULE_AUTHOR("Ajay Gupta <ajayg@nvidia.com>");
393 MODULE_DESCRIPTION("Nvidia GPU I2C controller Driver");
394 MODULE_LICENSE("GPL v2");