2 * Driver for the i2c controller on the Marvell line of host bridges
3 * (e.g, gt642[46]0, mv643[46]0, mv644[46]0, and Orion SoC family).
5 * Author: Mark A. Greer <mgreer@mvista.com>
7 * 2005 (c) MontaVista, Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
12 #include <linux/kernel.h>
13 #include <linux/slab.h>
14 #include <linux/module.h>
15 #include <linux/spinlock.h>
16 #include <linux/i2c.h>
17 #include <linux/interrupt.h>
18 #include <linux/mv643xx_i2c.h>
19 #include <linux/platform_device.h>
20 #include <linux/pinctrl/consumer.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/reset.h>
25 #include <linux/of_device.h>
26 #include <linux/of_irq.h>
27 #include <linux/clk.h>
28 #include <linux/err.h>
29 #include <linux/delay.h>
31 #define MV64XXX_I2C_ADDR_ADDR(val) ((val & 0x7f) << 1)
32 #define MV64XXX_I2C_BAUD_DIV_N(val) (val & 0x7)
33 #define MV64XXX_I2C_BAUD_DIV_M(val) ((val & 0xf) << 3)
35 #define MV64XXX_I2C_REG_CONTROL_ACK BIT(2)
36 #define MV64XXX_I2C_REG_CONTROL_IFLG BIT(3)
37 #define MV64XXX_I2C_REG_CONTROL_STOP BIT(4)
38 #define MV64XXX_I2C_REG_CONTROL_START BIT(5)
39 #define MV64XXX_I2C_REG_CONTROL_TWSIEN BIT(6)
40 #define MV64XXX_I2C_REG_CONTROL_INTEN BIT(7)
42 /* Ctlr status values */
43 #define MV64XXX_I2C_STATUS_BUS_ERR 0x00
44 #define MV64XXX_I2C_STATUS_MAST_START 0x08
45 #define MV64XXX_I2C_STATUS_MAST_REPEAT_START 0x10
46 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK 0x18
47 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20
48 #define MV64XXX_I2C_STATUS_MAST_WR_ACK 0x28
49 #define MV64XXX_I2C_STATUS_MAST_WR_NO_ACK 0x30
50 #define MV64XXX_I2C_STATUS_MAST_LOST_ARB 0x38
51 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK 0x40
52 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48
53 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK 0x50
54 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58
55 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0
56 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8
57 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0
58 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8
59 #define MV64XXX_I2C_STATUS_NO_STATUS 0xf8
61 /* Register defines (I2C bridge) */
62 #define MV64XXX_I2C_REG_TX_DATA_LO 0xc0
63 #define MV64XXX_I2C_REG_TX_DATA_HI 0xc4
64 #define MV64XXX_I2C_REG_RX_DATA_LO 0xc8
65 #define MV64XXX_I2C_REG_RX_DATA_HI 0xcc
66 #define MV64XXX_I2C_REG_BRIDGE_CONTROL 0xd0
67 #define MV64XXX_I2C_REG_BRIDGE_STATUS 0xd4
68 #define MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE 0xd8
69 #define MV64XXX_I2C_REG_BRIDGE_INTR_MASK 0xdC
70 #define MV64XXX_I2C_REG_BRIDGE_TIMING 0xe0
72 /* Bridge Control values */
73 #define MV64XXX_I2C_BRIDGE_CONTROL_WR BIT(0)
74 #define MV64XXX_I2C_BRIDGE_CONTROL_RD BIT(1)
75 #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT 2
76 #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT BIT(12)
77 #define MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT 13
78 #define MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT 16
79 #define MV64XXX_I2C_BRIDGE_CONTROL_ENABLE BIT(19)
80 #define MV64XXX_I2C_BRIDGE_CONTROL_REPEATED_START BIT(20)
82 /* Bridge Status values */
83 #define MV64XXX_I2C_BRIDGE_STATUS_ERROR BIT(0)
87 MV64XXX_I2C_STATE_INVALID,
88 MV64XXX_I2C_STATE_IDLE,
89 MV64XXX_I2C_STATE_WAITING_FOR_START_COND,
90 MV64XXX_I2C_STATE_WAITING_FOR_RESTART,
91 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK,
92 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK,
93 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK,
94 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA,
99 MV64XXX_I2C_ACTION_INVALID,
100 MV64XXX_I2C_ACTION_CONTINUE,
101 MV64XXX_I2C_ACTION_SEND_RESTART,
102 MV64XXX_I2C_ACTION_SEND_ADDR_1,
103 MV64XXX_I2C_ACTION_SEND_ADDR_2,
104 MV64XXX_I2C_ACTION_SEND_DATA,
105 MV64XXX_I2C_ACTION_RCV_DATA,
106 MV64XXX_I2C_ACTION_RCV_DATA_STOP,
107 MV64XXX_I2C_ACTION_SEND_STOP,
110 struct mv64xxx_i2c_regs {
120 struct mv64xxx_i2c_data {
121 struct i2c_msg *msgs;
128 void __iomem *reg_base;
129 struct mv64xxx_i2c_regs reg_offsets;
141 wait_queue_head_t waitq;
144 struct i2c_adapter adapter;
145 bool offload_enabled;
146 /* 5us delay in order to avoid repeated start timing violation */
148 struct reset_control *rstc;
149 bool irq_clear_inverted;
150 /* Clk div is 2 to the power n, not 2 to the power n + 1 */
152 struct i2c_bus_recovery_info rinfo;
155 static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_mv64xxx = {
165 static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_sun4i = {
176 mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
181 drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK |
182 MV64XXX_I2C_REG_CONTROL_INTEN | MV64XXX_I2C_REG_CONTROL_TWSIEN;
184 if (msg->flags & I2C_M_RD)
187 if (msg->flags & I2C_M_TEN) {
188 drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir;
189 drv_data->addr2 = (u32)msg->addr & 0xff;
191 drv_data->addr1 = MV64XXX_I2C_ADDR_ADDR((u32)msg->addr) | dir;
197 *****************************************************************************
199 * Finite State Machine & Interrupt Routines
201 *****************************************************************************
204 /* Reset hardware and initialize FSM */
206 mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data)
208 if (drv_data->offload_enabled) {
209 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
210 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_TIMING);
211 writel(0, drv_data->reg_base +
212 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
213 writel(0, drv_data->reg_base +
214 MV64XXX_I2C_REG_BRIDGE_INTR_MASK);
217 writel(0, drv_data->reg_base + drv_data->reg_offsets.soft_reset);
218 writel(MV64XXX_I2C_BAUD_DIV_M(drv_data->freq_m) | MV64XXX_I2C_BAUD_DIV_N(drv_data->freq_n),
219 drv_data->reg_base + drv_data->reg_offsets.clock);
220 writel(0, drv_data->reg_base + drv_data->reg_offsets.addr);
221 writel(0, drv_data->reg_base + drv_data->reg_offsets.ext_addr);
222 writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP,
223 drv_data->reg_base + drv_data->reg_offsets.control);
224 drv_data->state = MV64XXX_I2C_STATE_IDLE;
228 mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status)
231 * If state is idle, then this is likely the remnants of an old
232 * operation that driver has given up on or the user has killed.
233 * If so, issue the stop condition and go to idle.
235 if (drv_data->state == MV64XXX_I2C_STATE_IDLE) {
236 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
240 /* The status from the ctlr [mostly] tells us what to do next */
242 /* Start condition interrupt */
243 case MV64XXX_I2C_STATUS_MAST_START: /* 0x08 */
244 case MV64XXX_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */
245 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
246 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
249 /* Performing a write */
250 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */
251 if (drv_data->msg->flags & I2C_M_TEN) {
252 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
254 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
258 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */
259 case MV64XXX_I2C_STATUS_MAST_WR_ACK: /* 0x28 */
260 if ((drv_data->bytes_left == 0)
261 || (drv_data->aborting
262 && (drv_data->byte_posn != 0))) {
263 if (drv_data->send_stop || drv_data->aborting) {
264 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
265 drv_data->state = MV64XXX_I2C_STATE_IDLE;
268 MV64XXX_I2C_ACTION_SEND_RESTART;
270 MV64XXX_I2C_STATE_WAITING_FOR_RESTART;
273 drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
275 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK;
276 drv_data->bytes_left--;
280 /* Performing a read */
281 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */
282 if (drv_data->msg->flags & I2C_M_TEN) {
283 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
285 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
289 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */
290 if (drv_data->bytes_left == 0) {
291 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
292 drv_data->state = MV64XXX_I2C_STATE_IDLE;
296 case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */
297 if (status != MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK)
298 drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
300 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA;
301 drv_data->bytes_left--;
303 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;
305 if ((drv_data->bytes_left == 1) || drv_data->aborting)
306 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK;
309 case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */
310 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP;
311 drv_data->state = MV64XXX_I2C_STATE_IDLE;
314 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */
315 case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */
316 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */
317 /* Doesn't seem to be a device at other end */
318 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
319 drv_data->state = MV64XXX_I2C_STATE_IDLE;
320 drv_data->rc = -ENXIO;
324 dev_err(&drv_data->adapter.dev,
325 "mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, "
326 "status: 0x%x, addr: 0x%x, flags: 0x%x\n",
327 drv_data->state, status, drv_data->msg->addr,
328 drv_data->msg->flags);
329 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
330 mv64xxx_i2c_hw_init(drv_data);
331 i2c_recover_bus(&drv_data->adapter);
332 drv_data->rc = -EAGAIN;
336 static void mv64xxx_i2c_send_start(struct mv64xxx_i2c_data *drv_data)
338 drv_data->msg = drv_data->msgs;
339 drv_data->byte_posn = 0;
340 drv_data->bytes_left = drv_data->msg->len;
341 drv_data->aborting = 0;
344 mv64xxx_i2c_prepare_for_io(drv_data, drv_data->msgs);
345 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START,
346 drv_data->reg_base + drv_data->reg_offsets.control);
350 mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
352 switch(drv_data->action) {
353 case MV64XXX_I2C_ACTION_SEND_RESTART:
354 /* We should only get here if we have further messages */
355 BUG_ON(drv_data->num_msgs == 0);
358 drv_data->num_msgs--;
359 mv64xxx_i2c_send_start(drv_data);
361 if (drv_data->errata_delay)
365 * We're never at the start of the message here, and by this
366 * time it's already too late to do any protocol mangling.
367 * Thankfully, do not advertise support for that feature.
369 drv_data->send_stop = drv_data->num_msgs == 1;
372 case MV64XXX_I2C_ACTION_CONTINUE:
373 writel(drv_data->cntl_bits,
374 drv_data->reg_base + drv_data->reg_offsets.control);
377 case MV64XXX_I2C_ACTION_SEND_ADDR_1:
378 writel(drv_data->addr1,
379 drv_data->reg_base + drv_data->reg_offsets.data);
380 writel(drv_data->cntl_bits,
381 drv_data->reg_base + drv_data->reg_offsets.control);
384 case MV64XXX_I2C_ACTION_SEND_ADDR_2:
385 writel(drv_data->addr2,
386 drv_data->reg_base + drv_data->reg_offsets.data);
387 writel(drv_data->cntl_bits,
388 drv_data->reg_base + drv_data->reg_offsets.control);
391 case MV64XXX_I2C_ACTION_SEND_DATA:
392 writel(drv_data->msg->buf[drv_data->byte_posn++],
393 drv_data->reg_base + drv_data->reg_offsets.data);
394 writel(drv_data->cntl_bits,
395 drv_data->reg_base + drv_data->reg_offsets.control);
398 case MV64XXX_I2C_ACTION_RCV_DATA:
399 drv_data->msg->buf[drv_data->byte_posn++] =
400 readl(drv_data->reg_base + drv_data->reg_offsets.data);
401 writel(drv_data->cntl_bits,
402 drv_data->reg_base + drv_data->reg_offsets.control);
405 case MV64XXX_I2C_ACTION_RCV_DATA_STOP:
406 drv_data->msg->buf[drv_data->byte_posn++] =
407 readl(drv_data->reg_base + drv_data->reg_offsets.data);
408 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
409 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
410 drv_data->reg_base + drv_data->reg_offsets.control);
412 if (drv_data->errata_delay)
415 wake_up(&drv_data->waitq);
418 case MV64XXX_I2C_ACTION_INVALID:
420 dev_err(&drv_data->adapter.dev,
421 "mv64xxx_i2c_do_action: Invalid action: %d\n",
425 case MV64XXX_I2C_ACTION_SEND_STOP:
426 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
427 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
428 drv_data->reg_base + drv_data->reg_offsets.control);
430 wake_up(&drv_data->waitq);
436 mv64xxx_i2c_read_offload_rx_data(struct mv64xxx_i2c_data *drv_data,
441 buf[0] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_LO);
442 buf[1] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_HI);
444 memcpy(msg->buf, buf, msg->len);
448 mv64xxx_i2c_intr_offload(struct mv64xxx_i2c_data *drv_data)
452 cause = readl(drv_data->reg_base +
453 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
457 status = readl(drv_data->reg_base +
458 MV64XXX_I2C_REG_BRIDGE_STATUS);
460 if (status & MV64XXX_I2C_BRIDGE_STATUS_ERROR) {
468 * Transaction is a one message read transaction, read data
471 if (drv_data->num_msgs == 1 && drv_data->msgs[0].flags & I2C_M_RD) {
472 mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs);
474 drv_data->num_msgs--;
477 * Transaction is a two messages write/read transaction, read
478 * data for the second (read) message.
480 else if (drv_data->num_msgs == 2 &&
481 !(drv_data->msgs[0].flags & I2C_M_RD) &&
482 drv_data->msgs[1].flags & I2C_M_RD) {
483 mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs + 1);
485 drv_data->num_msgs -= 2;
489 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
490 writel(0, drv_data->reg_base +
491 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
494 wake_up(&drv_data->waitq);
500 mv64xxx_i2c_intr(int irq, void *dev_id)
502 struct mv64xxx_i2c_data *drv_data = dev_id;
504 irqreturn_t rc = IRQ_NONE;
506 spin_lock(&drv_data->lock);
508 if (drv_data->offload_enabled)
509 rc = mv64xxx_i2c_intr_offload(drv_data);
511 while (readl(drv_data->reg_base + drv_data->reg_offsets.control) &
512 MV64XXX_I2C_REG_CONTROL_IFLG) {
513 status = readl(drv_data->reg_base + drv_data->reg_offsets.status);
514 mv64xxx_i2c_fsm(drv_data, status);
515 mv64xxx_i2c_do_action(drv_data);
517 if (drv_data->irq_clear_inverted)
518 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_IFLG,
519 drv_data->reg_base + drv_data->reg_offsets.control);
523 spin_unlock(&drv_data->lock);
529 *****************************************************************************
531 * I2C Msg Execution Routines
533 *****************************************************************************
536 mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
542 time_left = wait_event_timeout(drv_data->waitq,
543 !drv_data->block, drv_data->adapter.timeout);
545 spin_lock_irqsave(&drv_data->lock, flags);
546 if (!time_left) { /* Timed out */
547 drv_data->rc = -ETIMEDOUT;
549 } else if (time_left < 0) { /* Interrupted/Error */
550 drv_data->rc = time_left; /* errno value */
554 if (abort && drv_data->block) {
555 drv_data->aborting = 1;
556 spin_unlock_irqrestore(&drv_data->lock, flags);
558 time_left = wait_event_timeout(drv_data->waitq,
559 !drv_data->block, drv_data->adapter.timeout);
561 if ((time_left <= 0) && drv_data->block) {
562 drv_data->state = MV64XXX_I2C_STATE_IDLE;
563 dev_err(&drv_data->adapter.dev,
564 "mv64xxx: I2C bus locked, block: %d, "
565 "time_left: %d\n", drv_data->block,
567 mv64xxx_i2c_hw_init(drv_data);
568 i2c_recover_bus(&drv_data->adapter);
571 spin_unlock_irqrestore(&drv_data->lock, flags);
575 mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg,
580 spin_lock_irqsave(&drv_data->lock, flags);
582 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
584 drv_data->send_stop = is_last;
586 mv64xxx_i2c_send_start(drv_data);
587 spin_unlock_irqrestore(&drv_data->lock, flags);
589 mv64xxx_i2c_wait_for_completion(drv_data);
594 mv64xxx_i2c_prepare_tx(struct mv64xxx_i2c_data *drv_data)
596 struct i2c_msg *msg = drv_data->msgs;
599 memcpy(buf, msg->buf, msg->len);
601 writel(buf[0], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_LO);
602 writel(buf[1], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_HI);
606 mv64xxx_i2c_offload_xfer(struct mv64xxx_i2c_data *drv_data)
608 struct i2c_msg *msgs = drv_data->msgs;
609 int num = drv_data->num_msgs;
610 unsigned long ctrl_reg;
613 spin_lock_irqsave(&drv_data->lock, flags);
615 /* Build transaction */
616 ctrl_reg = MV64XXX_I2C_BRIDGE_CONTROL_ENABLE |
617 (msgs[0].addr << MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT);
619 if (msgs[0].flags & I2C_M_TEN)
620 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT;
622 /* Single write message transaction */
623 if (num == 1 && !(msgs[0].flags & I2C_M_RD)) {
624 size_t len = msgs[0].len - 1;
626 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_WR |
627 (len << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT);
628 mv64xxx_i2c_prepare_tx(drv_data);
630 /* Single read message transaction */
631 else if (num == 1 && msgs[0].flags & I2C_M_RD) {
632 size_t len = msgs[0].len - 1;
634 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_RD |
635 (len << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT);
638 * Transaction with one write and one read message. This is
639 * guaranteed by the mv64xx_i2c_can_offload() checks.
642 size_t lentx = msgs[0].len - 1;
643 size_t lenrx = msgs[1].len - 1;
646 MV64XXX_I2C_BRIDGE_CONTROL_RD |
647 MV64XXX_I2C_BRIDGE_CONTROL_WR |
648 (lentx << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT) |
649 (lenrx << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT) |
650 MV64XXX_I2C_BRIDGE_CONTROL_REPEATED_START;
651 mv64xxx_i2c_prepare_tx(drv_data);
654 /* Execute transaction */
656 writel(ctrl_reg, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
657 spin_unlock_irqrestore(&drv_data->lock, flags);
659 mv64xxx_i2c_wait_for_completion(drv_data);
665 mv64xxx_i2c_valid_offload_sz(struct i2c_msg *msg)
667 return msg->len <= 8 && msg->len >= 1;
671 mv64xxx_i2c_can_offload(struct mv64xxx_i2c_data *drv_data)
673 struct i2c_msg *msgs = drv_data->msgs;
674 int num = drv_data->num_msgs;
676 if (!drv_data->offload_enabled)
680 * We can offload a transaction consisting of a single
681 * message, as long as the message has a length between 1 and
684 if (num == 1 && mv64xxx_i2c_valid_offload_sz(msgs))
688 * We can offload a transaction consisting of two messages, if
689 * the first is a write and a second is a read, and both have
690 * a length between 1 and 8 bytes.
693 mv64xxx_i2c_valid_offload_sz(msgs) &&
694 mv64xxx_i2c_valid_offload_sz(msgs + 1) &&
695 !(msgs[0].flags & I2C_M_RD) &&
696 msgs[1].flags & I2C_M_RD)
703 *****************************************************************************
705 * I2C Core Support Routines (Interface to higher level I2C code)
707 *****************************************************************************
710 mv64xxx_i2c_functionality(struct i2c_adapter *adap)
712 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL;
716 mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
718 struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
721 rc = pm_runtime_resume_and_get(&adap->dev);
725 BUG_ON(drv_data->msgs != NULL);
726 drv_data->msgs = msgs;
727 drv_data->num_msgs = num;
729 if (mv64xxx_i2c_can_offload(drv_data))
730 rc = mv64xxx_i2c_offload_xfer(drv_data);
732 rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[0], num == 1);
737 drv_data->num_msgs = 0;
738 drv_data->msgs = NULL;
740 pm_runtime_mark_last_busy(&adap->dev);
741 pm_runtime_put_autosuspend(&adap->dev);
746 static const struct i2c_algorithm mv64xxx_i2c_algo = {
747 .master_xfer = mv64xxx_i2c_xfer,
748 .functionality = mv64xxx_i2c_functionality,
752 *****************************************************************************
754 * Driver Interface & Early Init Routines
756 *****************************************************************************
758 static const struct of_device_id mv64xxx_i2c_of_match_table[] = {
759 { .compatible = "allwinner,sun4i-a10-i2c", .data = &mv64xxx_i2c_regs_sun4i},
760 { .compatible = "allwinner,sun6i-a31-i2c", .data = &mv64xxx_i2c_regs_sun4i},
761 { .compatible = "marvell,mv64xxx-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
762 { .compatible = "marvell,mv78230-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
763 { .compatible = "marvell,mv78230-a0-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
766 MODULE_DEVICE_TABLE(of, mv64xxx_i2c_of_match_table);
770 mv64xxx_calc_freq(struct mv64xxx_i2c_data *drv_data,
771 const int tclk, const int n, const int m)
773 if (drv_data->clk_n_base_0)
774 return tclk / (10 * (m + 1) * (1 << n));
776 return tclk / (10 * (m + 1) * (2 << n));
780 mv64xxx_find_baud_factors(struct mv64xxx_i2c_data *drv_data,
781 const u32 req_freq, const u32 tclk)
783 int freq, delta, best_delta = INT_MAX;
786 for (n = 0; n <= 7; n++)
787 for (m = 0; m <= 15; m++) {
788 freq = mv64xxx_calc_freq(drv_data, tclk, n, m);
789 delta = req_freq - freq;
790 if (delta >= 0 && delta < best_delta) {
791 drv_data->freq_m = m;
792 drv_data->freq_n = n;
798 if (best_delta == INT_MAX)
804 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
807 const struct of_device_id *device;
808 struct device_node *np = dev->of_node;
812 /* CLK is mandatory when using DT to describe the i2c bus. We
813 * need to know tclk in order to calculate bus clock
816 if (IS_ERR(drv_data->clk)) {
820 tclk = clk_get_rate(drv_data->clk);
822 if (of_property_read_u32(np, "clock-frequency", &bus_freq))
823 bus_freq = I2C_MAX_STANDARD_MODE_FREQ; /* 100kHz by default */
825 if (of_device_is_compatible(np, "allwinner,sun4i-a10-i2c") ||
826 of_device_is_compatible(np, "allwinner,sun6i-a31-i2c"))
827 drv_data->clk_n_base_0 = true;
829 if (!mv64xxx_find_baud_factors(drv_data, bus_freq, tclk)) {
834 drv_data->rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
835 if (IS_ERR(drv_data->rstc)) {
836 rc = PTR_ERR(drv_data->rstc);
840 /* Its not yet defined how timeouts will be specified in device tree.
841 * So hard code the value to 1 second.
843 drv_data->adapter.timeout = HZ;
845 device = of_match_device(mv64xxx_i2c_of_match_table, dev);
849 memcpy(&drv_data->reg_offsets, device->data, sizeof(drv_data->reg_offsets));
852 * For controllers embedded in new SoCs activate the
853 * Transaction Generator support and the errata fix.
855 if (of_device_is_compatible(np, "marvell,mv78230-i2c")) {
856 drv_data->offload_enabled = true;
857 /* The delay is only needed in standard mode (100kHz) */
858 if (bus_freq <= I2C_MAX_STANDARD_MODE_FREQ)
859 drv_data->errata_delay = true;
862 if (of_device_is_compatible(np, "marvell,mv78230-a0-i2c")) {
863 drv_data->offload_enabled = false;
864 /* The delay is only needed in standard mode (100kHz) */
865 if (bus_freq <= I2C_MAX_STANDARD_MODE_FREQ)
866 drv_data->errata_delay = true;
869 if (of_device_is_compatible(np, "allwinner,sun6i-a31-i2c"))
870 drv_data->irq_clear_inverted = true;
875 #else /* CONFIG_OF */
877 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
882 #endif /* CONFIG_OF */
884 static int mv64xxx_i2c_init_recovery_info(struct mv64xxx_i2c_data *drv_data,
887 struct i2c_bus_recovery_info *rinfo = &drv_data->rinfo;
889 rinfo->pinctrl = devm_pinctrl_get(dev);
890 if (IS_ERR(rinfo->pinctrl)) {
891 if (PTR_ERR(rinfo->pinctrl) == -EPROBE_DEFER)
892 return -EPROBE_DEFER;
893 dev_info(dev, "can't get pinctrl, bus recovery not supported\n");
894 return PTR_ERR(rinfo->pinctrl);
895 } else if (!rinfo->pinctrl) {
899 drv_data->adapter.bus_recovery_info = rinfo;
904 mv64xxx_i2c_runtime_suspend(struct device *dev)
906 struct mv64xxx_i2c_data *drv_data = dev_get_drvdata(dev);
908 reset_control_assert(drv_data->rstc);
909 clk_disable_unprepare(drv_data->reg_clk);
910 clk_disable_unprepare(drv_data->clk);
916 mv64xxx_i2c_runtime_resume(struct device *dev)
918 struct mv64xxx_i2c_data *drv_data = dev_get_drvdata(dev);
920 clk_prepare_enable(drv_data->clk);
921 clk_prepare_enable(drv_data->reg_clk);
922 reset_control_reset(drv_data->rstc);
924 mv64xxx_i2c_hw_init(drv_data);
930 mv64xxx_i2c_probe(struct platform_device *pd)
932 struct mv64xxx_i2c_data *drv_data;
933 struct mv64xxx_i2c_pdata *pdata = dev_get_platdata(&pd->dev);
936 if ((!pdata && !pd->dev.of_node))
939 drv_data = devm_kzalloc(&pd->dev, sizeof(struct mv64xxx_i2c_data),
944 drv_data->reg_base = devm_platform_ioremap_resource(pd, 0);
945 if (IS_ERR(drv_data->reg_base))
946 return PTR_ERR(drv_data->reg_base);
948 strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
949 sizeof(drv_data->adapter.name));
951 init_waitqueue_head(&drv_data->waitq);
952 spin_lock_init(&drv_data->lock);
954 /* Not all platforms have clocks */
955 drv_data->clk = devm_clk_get(&pd->dev, NULL);
956 if (IS_ERR(drv_data->clk)) {
957 if (PTR_ERR(drv_data->clk) == -EPROBE_DEFER)
958 return -EPROBE_DEFER;
959 drv_data->clk = NULL;
962 drv_data->reg_clk = devm_clk_get(&pd->dev, "reg");
963 if (IS_ERR(drv_data->reg_clk)) {
964 if (PTR_ERR(drv_data->reg_clk) == -EPROBE_DEFER)
965 return -EPROBE_DEFER;
966 drv_data->reg_clk = NULL;
969 drv_data->irq = platform_get_irq(pd, 0);
970 if (drv_data->irq < 0)
971 return drv_data->irq;
974 drv_data->freq_m = pdata->freq_m;
975 drv_data->freq_n = pdata->freq_n;
976 drv_data->adapter.timeout = msecs_to_jiffies(pdata->timeout);
977 drv_data->offload_enabled = false;
978 memcpy(&drv_data->reg_offsets, &mv64xxx_i2c_regs_mv64xxx, sizeof(drv_data->reg_offsets));
979 } else if (pd->dev.of_node) {
980 rc = mv64xxx_of_config(drv_data, &pd->dev);
985 rc = mv64xxx_i2c_init_recovery_info(drv_data, &pd->dev);
986 if (rc == -EPROBE_DEFER)
989 drv_data->adapter.dev.parent = &pd->dev;
990 drv_data->adapter.algo = &mv64xxx_i2c_algo;
991 drv_data->adapter.owner = THIS_MODULE;
992 drv_data->adapter.class = I2C_CLASS_DEPRECATED;
993 drv_data->adapter.nr = pd->id;
994 drv_data->adapter.dev.of_node = pd->dev.of_node;
995 platform_set_drvdata(pd, drv_data);
996 i2c_set_adapdata(&drv_data->adapter, drv_data);
998 pm_runtime_set_autosuspend_delay(&pd->dev, MSEC_PER_SEC);
999 pm_runtime_use_autosuspend(&pd->dev);
1000 pm_runtime_enable(&pd->dev);
1001 if (!pm_runtime_enabled(&pd->dev)) {
1002 rc = mv64xxx_i2c_runtime_resume(&pd->dev);
1004 goto exit_disable_pm;
1007 rc = request_irq(drv_data->irq, mv64xxx_i2c_intr, 0,
1008 MV64XXX_I2C_CTLR_NAME, drv_data);
1010 dev_err(&drv_data->adapter.dev,
1011 "mv64xxx: Can't register intr handler irq%d: %d\n",
1013 goto exit_disable_pm;
1014 } else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) {
1015 dev_err(&drv_data->adapter.dev,
1016 "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc);
1023 free_irq(drv_data->irq, drv_data);
1025 pm_runtime_disable(&pd->dev);
1026 if (!pm_runtime_status_suspended(&pd->dev))
1027 mv64xxx_i2c_runtime_suspend(&pd->dev);
1033 mv64xxx_i2c_remove(struct platform_device *pd)
1035 struct mv64xxx_i2c_data *drv_data = platform_get_drvdata(pd);
1037 i2c_del_adapter(&drv_data->adapter);
1038 free_irq(drv_data->irq, drv_data);
1039 pm_runtime_disable(&pd->dev);
1040 if (!pm_runtime_status_suspended(&pd->dev))
1041 mv64xxx_i2c_runtime_suspend(&pd->dev);
1047 mv64xxx_i2c_shutdown(struct platform_device *pd)
1049 pm_runtime_disable(&pd->dev);
1050 if (!pm_runtime_status_suspended(&pd->dev))
1051 mv64xxx_i2c_runtime_suspend(&pd->dev);
1054 static const struct dev_pm_ops mv64xxx_i2c_pm_ops = {
1055 SET_RUNTIME_PM_OPS(mv64xxx_i2c_runtime_suspend,
1056 mv64xxx_i2c_runtime_resume, NULL)
1057 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1058 pm_runtime_force_resume)
1061 static struct platform_driver mv64xxx_i2c_driver = {
1062 .probe = mv64xxx_i2c_probe,
1063 .remove = mv64xxx_i2c_remove,
1064 .shutdown = mv64xxx_i2c_shutdown,
1066 .name = MV64XXX_I2C_CTLR_NAME,
1067 .pm = &mv64xxx_i2c_pm_ops,
1068 .of_match_table = mv64xxx_i2c_of_match_table,
1072 module_platform_driver(mv64xxx_i2c_driver);
1074 MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
1075 MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver");
1076 MODULE_LICENSE("GPL");