2 * Driver for the i2c controller on the Marvell line of host bridges
3 * (e.g, gt642[46]0, mv643[46]0, mv644[46]0, and Orion SoC family).
5 * Author: Mark A. Greer <mgreer@mvista.com>
7 * 2005 (c) MontaVista, Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
12 #include <linux/kernel.h>
13 #include <linux/slab.h>
14 #include <linux/module.h>
15 #include <linux/spinlock.h>
16 #include <linux/i2c.h>
17 #include <linux/interrupt.h>
18 #include <linux/mv643xx_i2c.h>
19 #include <linux/platform_device.h>
20 #include <linux/pinctrl/consumer.h>
21 #include <linux/reset.h>
24 #include <linux/of_device.h>
25 #include <linux/of_irq.h>
26 #include <linux/clk.h>
27 #include <linux/err.h>
28 #include <linux/delay.h>
30 #define MV64XXX_I2C_ADDR_ADDR(val) ((val & 0x7f) << 1)
31 #define MV64XXX_I2C_BAUD_DIV_N(val) (val & 0x7)
32 #define MV64XXX_I2C_BAUD_DIV_M(val) ((val & 0xf) << 3)
34 #define MV64XXX_I2C_REG_CONTROL_ACK BIT(2)
35 #define MV64XXX_I2C_REG_CONTROL_IFLG BIT(3)
36 #define MV64XXX_I2C_REG_CONTROL_STOP BIT(4)
37 #define MV64XXX_I2C_REG_CONTROL_START BIT(5)
38 #define MV64XXX_I2C_REG_CONTROL_TWSIEN BIT(6)
39 #define MV64XXX_I2C_REG_CONTROL_INTEN BIT(7)
41 /* Ctlr status values */
42 #define MV64XXX_I2C_STATUS_BUS_ERR 0x00
43 #define MV64XXX_I2C_STATUS_MAST_START 0x08
44 #define MV64XXX_I2C_STATUS_MAST_REPEAT_START 0x10
45 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK 0x18
46 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20
47 #define MV64XXX_I2C_STATUS_MAST_WR_ACK 0x28
48 #define MV64XXX_I2C_STATUS_MAST_WR_NO_ACK 0x30
49 #define MV64XXX_I2C_STATUS_MAST_LOST_ARB 0x38
50 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK 0x40
51 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48
52 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK 0x50
53 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58
54 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0
55 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8
56 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0
57 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8
58 #define MV64XXX_I2C_STATUS_NO_STATUS 0xf8
60 /* Register defines (I2C bridge) */
61 #define MV64XXX_I2C_REG_TX_DATA_LO 0xc0
62 #define MV64XXX_I2C_REG_TX_DATA_HI 0xc4
63 #define MV64XXX_I2C_REG_RX_DATA_LO 0xc8
64 #define MV64XXX_I2C_REG_RX_DATA_HI 0xcc
65 #define MV64XXX_I2C_REG_BRIDGE_CONTROL 0xd0
66 #define MV64XXX_I2C_REG_BRIDGE_STATUS 0xd4
67 #define MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE 0xd8
68 #define MV64XXX_I2C_REG_BRIDGE_INTR_MASK 0xdC
69 #define MV64XXX_I2C_REG_BRIDGE_TIMING 0xe0
71 /* Bridge Control values */
72 #define MV64XXX_I2C_BRIDGE_CONTROL_WR BIT(0)
73 #define MV64XXX_I2C_BRIDGE_CONTROL_RD BIT(1)
74 #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT 2
75 #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT BIT(12)
76 #define MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT 13
77 #define MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT 16
78 #define MV64XXX_I2C_BRIDGE_CONTROL_ENABLE BIT(19)
79 #define MV64XXX_I2C_BRIDGE_CONTROL_REPEATED_START BIT(20)
81 /* Bridge Status values */
82 #define MV64XXX_I2C_BRIDGE_STATUS_ERROR BIT(0)
86 MV64XXX_I2C_STATE_INVALID,
87 MV64XXX_I2C_STATE_IDLE,
88 MV64XXX_I2C_STATE_WAITING_FOR_START_COND,
89 MV64XXX_I2C_STATE_WAITING_FOR_RESTART,
90 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK,
91 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK,
92 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK,
93 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA,
98 MV64XXX_I2C_ACTION_INVALID,
99 MV64XXX_I2C_ACTION_CONTINUE,
100 MV64XXX_I2C_ACTION_SEND_RESTART,
101 MV64XXX_I2C_ACTION_SEND_ADDR_1,
102 MV64XXX_I2C_ACTION_SEND_ADDR_2,
103 MV64XXX_I2C_ACTION_SEND_DATA,
104 MV64XXX_I2C_ACTION_RCV_DATA,
105 MV64XXX_I2C_ACTION_RCV_DATA_STOP,
106 MV64XXX_I2C_ACTION_SEND_STOP,
109 struct mv64xxx_i2c_regs {
119 struct mv64xxx_i2c_data {
120 struct i2c_msg *msgs;
127 void __iomem *reg_base;
128 struct mv64xxx_i2c_regs reg_offsets;
140 wait_queue_head_t waitq;
143 struct i2c_adapter adapter;
144 bool offload_enabled;
145 /* 5us delay in order to avoid repeated start timing violation */
147 struct reset_control *rstc;
148 bool irq_clear_inverted;
149 /* Clk div is 2 to the power n, not 2 to the power n + 1 */
151 struct i2c_bus_recovery_info rinfo;
154 static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_mv64xxx = {
164 static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_sun4i = {
175 mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
180 drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK |
181 MV64XXX_I2C_REG_CONTROL_INTEN | MV64XXX_I2C_REG_CONTROL_TWSIEN;
183 if (msg->flags & I2C_M_RD)
186 if (msg->flags & I2C_M_TEN) {
187 drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir;
188 drv_data->addr2 = (u32)msg->addr & 0xff;
190 drv_data->addr1 = MV64XXX_I2C_ADDR_ADDR((u32)msg->addr) | dir;
196 *****************************************************************************
198 * Finite State Machine & Interrupt Routines
200 *****************************************************************************
203 /* Reset hardware and initialize FSM */
205 mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data)
207 if (drv_data->offload_enabled) {
208 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
209 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_TIMING);
210 writel(0, drv_data->reg_base +
211 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
212 writel(0, drv_data->reg_base +
213 MV64XXX_I2C_REG_BRIDGE_INTR_MASK);
216 writel(0, drv_data->reg_base + drv_data->reg_offsets.soft_reset);
217 writel(MV64XXX_I2C_BAUD_DIV_M(drv_data->freq_m) | MV64XXX_I2C_BAUD_DIV_N(drv_data->freq_n),
218 drv_data->reg_base + drv_data->reg_offsets.clock);
219 writel(0, drv_data->reg_base + drv_data->reg_offsets.addr);
220 writel(0, drv_data->reg_base + drv_data->reg_offsets.ext_addr);
221 writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP,
222 drv_data->reg_base + drv_data->reg_offsets.control);
223 drv_data->state = MV64XXX_I2C_STATE_IDLE;
227 mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status)
230 * If state is idle, then this is likely the remnants of an old
231 * operation that driver has given up on or the user has killed.
232 * If so, issue the stop condition and go to idle.
234 if (drv_data->state == MV64XXX_I2C_STATE_IDLE) {
235 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
239 /* The status from the ctlr [mostly] tells us what to do next */
241 /* Start condition interrupt */
242 case MV64XXX_I2C_STATUS_MAST_START: /* 0x08 */
243 case MV64XXX_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */
244 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
245 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
248 /* Performing a write */
249 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */
250 if (drv_data->msg->flags & I2C_M_TEN) {
251 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
253 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
257 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */
258 case MV64XXX_I2C_STATUS_MAST_WR_ACK: /* 0x28 */
259 if ((drv_data->bytes_left == 0)
260 || (drv_data->aborting
261 && (drv_data->byte_posn != 0))) {
262 if (drv_data->send_stop || drv_data->aborting) {
263 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
264 drv_data->state = MV64XXX_I2C_STATE_IDLE;
267 MV64XXX_I2C_ACTION_SEND_RESTART;
269 MV64XXX_I2C_STATE_WAITING_FOR_RESTART;
272 drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
274 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK;
275 drv_data->bytes_left--;
279 /* Performing a read */
280 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */
281 if (drv_data->msg->flags & I2C_M_TEN) {
282 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
284 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
288 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */
289 if (drv_data->bytes_left == 0) {
290 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
291 drv_data->state = MV64XXX_I2C_STATE_IDLE;
295 case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */
296 if (status != MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK)
297 drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
299 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA;
300 drv_data->bytes_left--;
302 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;
304 if ((drv_data->bytes_left == 1) || drv_data->aborting)
305 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK;
308 case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */
309 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP;
310 drv_data->state = MV64XXX_I2C_STATE_IDLE;
313 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */
314 case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */
315 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */
316 /* Doesn't seem to be a device at other end */
317 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
318 drv_data->state = MV64XXX_I2C_STATE_IDLE;
319 drv_data->rc = -ENXIO;
323 dev_err(&drv_data->adapter.dev,
324 "mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, "
325 "status: 0x%x, addr: 0x%x, flags: 0x%x\n",
326 drv_data->state, status, drv_data->msg->addr,
327 drv_data->msg->flags);
328 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
329 mv64xxx_i2c_hw_init(drv_data);
330 i2c_recover_bus(&drv_data->adapter);
331 drv_data->rc = -EAGAIN;
335 static void mv64xxx_i2c_send_start(struct mv64xxx_i2c_data *drv_data)
337 drv_data->msg = drv_data->msgs;
338 drv_data->byte_posn = 0;
339 drv_data->bytes_left = drv_data->msg->len;
340 drv_data->aborting = 0;
343 mv64xxx_i2c_prepare_for_io(drv_data, drv_data->msgs);
344 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START,
345 drv_data->reg_base + drv_data->reg_offsets.control);
349 mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
351 switch(drv_data->action) {
352 case MV64XXX_I2C_ACTION_SEND_RESTART:
353 /* We should only get here if we have further messages */
354 BUG_ON(drv_data->num_msgs == 0);
357 drv_data->num_msgs--;
358 mv64xxx_i2c_send_start(drv_data);
360 if (drv_data->errata_delay)
364 * We're never at the start of the message here, and by this
365 * time it's already too late to do any protocol mangling.
366 * Thankfully, do not advertise support for that feature.
368 drv_data->send_stop = drv_data->num_msgs == 1;
371 case MV64XXX_I2C_ACTION_CONTINUE:
372 writel(drv_data->cntl_bits,
373 drv_data->reg_base + drv_data->reg_offsets.control);
376 case MV64XXX_I2C_ACTION_SEND_ADDR_1:
377 writel(drv_data->addr1,
378 drv_data->reg_base + drv_data->reg_offsets.data);
379 writel(drv_data->cntl_bits,
380 drv_data->reg_base + drv_data->reg_offsets.control);
383 case MV64XXX_I2C_ACTION_SEND_ADDR_2:
384 writel(drv_data->addr2,
385 drv_data->reg_base + drv_data->reg_offsets.data);
386 writel(drv_data->cntl_bits,
387 drv_data->reg_base + drv_data->reg_offsets.control);
390 case MV64XXX_I2C_ACTION_SEND_DATA:
391 writel(drv_data->msg->buf[drv_data->byte_posn++],
392 drv_data->reg_base + drv_data->reg_offsets.data);
393 writel(drv_data->cntl_bits,
394 drv_data->reg_base + drv_data->reg_offsets.control);
397 case MV64XXX_I2C_ACTION_RCV_DATA:
398 drv_data->msg->buf[drv_data->byte_posn++] =
399 readl(drv_data->reg_base + drv_data->reg_offsets.data);
400 writel(drv_data->cntl_bits,
401 drv_data->reg_base + drv_data->reg_offsets.control);
404 case MV64XXX_I2C_ACTION_RCV_DATA_STOP:
405 drv_data->msg->buf[drv_data->byte_posn++] =
406 readl(drv_data->reg_base + drv_data->reg_offsets.data);
407 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
408 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
409 drv_data->reg_base + drv_data->reg_offsets.control);
411 if (drv_data->errata_delay)
414 wake_up(&drv_data->waitq);
417 case MV64XXX_I2C_ACTION_INVALID:
419 dev_err(&drv_data->adapter.dev,
420 "mv64xxx_i2c_do_action: Invalid action: %d\n",
424 case MV64XXX_I2C_ACTION_SEND_STOP:
425 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
426 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
427 drv_data->reg_base + drv_data->reg_offsets.control);
429 wake_up(&drv_data->waitq);
435 mv64xxx_i2c_read_offload_rx_data(struct mv64xxx_i2c_data *drv_data,
440 buf[0] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_LO);
441 buf[1] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_HI);
443 memcpy(msg->buf, buf, msg->len);
447 mv64xxx_i2c_intr_offload(struct mv64xxx_i2c_data *drv_data)
451 cause = readl(drv_data->reg_base +
452 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
456 status = readl(drv_data->reg_base +
457 MV64XXX_I2C_REG_BRIDGE_STATUS);
459 if (status & MV64XXX_I2C_BRIDGE_STATUS_ERROR) {
467 * Transaction is a one message read transaction, read data
470 if (drv_data->num_msgs == 1 && drv_data->msgs[0].flags & I2C_M_RD) {
471 mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs);
473 drv_data->num_msgs--;
476 * Transaction is a two messages write/read transaction, read
477 * data for the second (read) message.
479 else if (drv_data->num_msgs == 2 &&
480 !(drv_data->msgs[0].flags & I2C_M_RD) &&
481 drv_data->msgs[1].flags & I2C_M_RD) {
482 mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs + 1);
484 drv_data->num_msgs -= 2;
488 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
489 writel(0, drv_data->reg_base +
490 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
493 wake_up(&drv_data->waitq);
499 mv64xxx_i2c_intr(int irq, void *dev_id)
501 struct mv64xxx_i2c_data *drv_data = dev_id;
503 irqreturn_t rc = IRQ_NONE;
505 spin_lock(&drv_data->lock);
507 if (drv_data->offload_enabled)
508 rc = mv64xxx_i2c_intr_offload(drv_data);
510 while (readl(drv_data->reg_base + drv_data->reg_offsets.control) &
511 MV64XXX_I2C_REG_CONTROL_IFLG) {
512 status = readl(drv_data->reg_base + drv_data->reg_offsets.status);
513 mv64xxx_i2c_fsm(drv_data, status);
514 mv64xxx_i2c_do_action(drv_data);
516 if (drv_data->irq_clear_inverted)
517 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_IFLG,
518 drv_data->reg_base + drv_data->reg_offsets.control);
522 spin_unlock(&drv_data->lock);
528 *****************************************************************************
530 * I2C Msg Execution Routines
532 *****************************************************************************
535 mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
541 time_left = wait_event_timeout(drv_data->waitq,
542 !drv_data->block, drv_data->adapter.timeout);
544 spin_lock_irqsave(&drv_data->lock, flags);
545 if (!time_left) { /* Timed out */
546 drv_data->rc = -ETIMEDOUT;
548 } else if (time_left < 0) { /* Interrupted/Error */
549 drv_data->rc = time_left; /* errno value */
553 if (abort && drv_data->block) {
554 drv_data->aborting = 1;
555 spin_unlock_irqrestore(&drv_data->lock, flags);
557 time_left = wait_event_timeout(drv_data->waitq,
558 !drv_data->block, drv_data->adapter.timeout);
560 if ((time_left <= 0) && drv_data->block) {
561 drv_data->state = MV64XXX_I2C_STATE_IDLE;
562 dev_err(&drv_data->adapter.dev,
563 "mv64xxx: I2C bus locked, block: %d, "
564 "time_left: %d\n", drv_data->block,
566 mv64xxx_i2c_hw_init(drv_data);
567 i2c_recover_bus(&drv_data->adapter);
570 spin_unlock_irqrestore(&drv_data->lock, flags);
574 mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg,
579 spin_lock_irqsave(&drv_data->lock, flags);
581 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
583 drv_data->send_stop = is_last;
585 mv64xxx_i2c_send_start(drv_data);
586 spin_unlock_irqrestore(&drv_data->lock, flags);
588 mv64xxx_i2c_wait_for_completion(drv_data);
593 mv64xxx_i2c_prepare_tx(struct mv64xxx_i2c_data *drv_data)
595 struct i2c_msg *msg = drv_data->msgs;
598 memcpy(buf, msg->buf, msg->len);
600 writel(buf[0], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_LO);
601 writel(buf[1], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_HI);
605 mv64xxx_i2c_offload_xfer(struct mv64xxx_i2c_data *drv_data)
607 struct i2c_msg *msgs = drv_data->msgs;
608 int num = drv_data->num_msgs;
609 unsigned long ctrl_reg;
612 spin_lock_irqsave(&drv_data->lock, flags);
614 /* Build transaction */
615 ctrl_reg = MV64XXX_I2C_BRIDGE_CONTROL_ENABLE |
616 (msgs[0].addr << MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT);
618 if (msgs[0].flags & I2C_M_TEN)
619 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT;
621 /* Single write message transaction */
622 if (num == 1 && !(msgs[0].flags & I2C_M_RD)) {
623 size_t len = msgs[0].len - 1;
625 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_WR |
626 (len << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT);
627 mv64xxx_i2c_prepare_tx(drv_data);
629 /* Single read message transaction */
630 else if (num == 1 && msgs[0].flags & I2C_M_RD) {
631 size_t len = msgs[0].len - 1;
633 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_RD |
634 (len << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT);
637 * Transaction with one write and one read message. This is
638 * guaranteed by the mv64xx_i2c_can_offload() checks.
641 size_t lentx = msgs[0].len - 1;
642 size_t lenrx = msgs[1].len - 1;
645 MV64XXX_I2C_BRIDGE_CONTROL_RD |
646 MV64XXX_I2C_BRIDGE_CONTROL_WR |
647 (lentx << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT) |
648 (lenrx << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT) |
649 MV64XXX_I2C_BRIDGE_CONTROL_REPEATED_START;
650 mv64xxx_i2c_prepare_tx(drv_data);
653 /* Execute transaction */
655 writel(ctrl_reg, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
656 spin_unlock_irqrestore(&drv_data->lock, flags);
658 mv64xxx_i2c_wait_for_completion(drv_data);
664 mv64xxx_i2c_valid_offload_sz(struct i2c_msg *msg)
666 return msg->len <= 8 && msg->len >= 1;
670 mv64xxx_i2c_can_offload(struct mv64xxx_i2c_data *drv_data)
672 struct i2c_msg *msgs = drv_data->msgs;
673 int num = drv_data->num_msgs;
675 if (!drv_data->offload_enabled)
679 * We can offload a transaction consisting of a single
680 * message, as long as the message has a length between 1 and
683 if (num == 1 && mv64xxx_i2c_valid_offload_sz(msgs))
687 * We can offload a transaction consisting of two messages, if
688 * the first is a write and a second is a read, and both have
689 * a length between 1 and 8 bytes.
692 mv64xxx_i2c_valid_offload_sz(msgs) &&
693 mv64xxx_i2c_valid_offload_sz(msgs + 1) &&
694 !(msgs[0].flags & I2C_M_RD) &&
695 msgs[1].flags & I2C_M_RD)
702 *****************************************************************************
704 * I2C Core Support Routines (Interface to higher level I2C code)
706 *****************************************************************************
709 mv64xxx_i2c_functionality(struct i2c_adapter *adap)
711 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL;
715 mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
717 struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
720 BUG_ON(drv_data->msgs != NULL);
721 drv_data->msgs = msgs;
722 drv_data->num_msgs = num;
724 if (mv64xxx_i2c_can_offload(drv_data))
725 rc = mv64xxx_i2c_offload_xfer(drv_data);
727 rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[0], num == 1);
732 drv_data->num_msgs = 0;
733 drv_data->msgs = NULL;
738 static const struct i2c_algorithm mv64xxx_i2c_algo = {
739 .master_xfer = mv64xxx_i2c_xfer,
740 .functionality = mv64xxx_i2c_functionality,
744 *****************************************************************************
746 * Driver Interface & Early Init Routines
748 *****************************************************************************
750 static const struct of_device_id mv64xxx_i2c_of_match_table[] = {
751 { .compatible = "allwinner,sun4i-a10-i2c", .data = &mv64xxx_i2c_regs_sun4i},
752 { .compatible = "allwinner,sun6i-a31-i2c", .data = &mv64xxx_i2c_regs_sun4i},
753 { .compatible = "marvell,mv64xxx-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
754 { .compatible = "marvell,mv78230-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
755 { .compatible = "marvell,mv78230-a0-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
758 MODULE_DEVICE_TABLE(of, mv64xxx_i2c_of_match_table);
762 mv64xxx_calc_freq(struct mv64xxx_i2c_data *drv_data,
763 const int tclk, const int n, const int m)
765 if (drv_data->clk_n_base_0)
766 return tclk / (10 * (m + 1) * (1 << n));
768 return tclk / (10 * (m + 1) * (2 << n));
772 mv64xxx_find_baud_factors(struct mv64xxx_i2c_data *drv_data,
773 const u32 req_freq, const u32 tclk)
775 int freq, delta, best_delta = INT_MAX;
778 for (n = 0; n <= 7; n++)
779 for (m = 0; m <= 15; m++) {
780 freq = mv64xxx_calc_freq(drv_data, tclk, n, m);
781 delta = req_freq - freq;
782 if (delta >= 0 && delta < best_delta) {
783 drv_data->freq_m = m;
784 drv_data->freq_n = n;
790 if (best_delta == INT_MAX)
796 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
799 const struct of_device_id *device;
800 struct device_node *np = dev->of_node;
804 /* CLK is mandatory when using DT to describe the i2c bus. We
805 * need to know tclk in order to calculate bus clock
808 if (IS_ERR(drv_data->clk)) {
812 tclk = clk_get_rate(drv_data->clk);
814 if (of_property_read_u32(np, "clock-frequency", &bus_freq))
815 bus_freq = I2C_MAX_STANDARD_MODE_FREQ; /* 100kHz by default */
817 if (of_device_is_compatible(np, "allwinner,sun4i-a10-i2c") ||
818 of_device_is_compatible(np, "allwinner,sun6i-a31-i2c"))
819 drv_data->clk_n_base_0 = true;
821 if (!mv64xxx_find_baud_factors(drv_data, bus_freq, tclk)) {
826 drv_data->rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
827 if (IS_ERR(drv_data->rstc)) {
828 rc = PTR_ERR(drv_data->rstc);
831 reset_control_deassert(drv_data->rstc);
833 /* Its not yet defined how timeouts will be specified in device tree.
834 * So hard code the value to 1 second.
836 drv_data->adapter.timeout = HZ;
838 device = of_match_device(mv64xxx_i2c_of_match_table, dev);
842 memcpy(&drv_data->reg_offsets, device->data, sizeof(drv_data->reg_offsets));
845 * For controllers embedded in new SoCs activate the
846 * Transaction Generator support and the errata fix.
848 if (of_device_is_compatible(np, "marvell,mv78230-i2c")) {
849 drv_data->offload_enabled = true;
850 /* The delay is only needed in standard mode (100kHz) */
851 if (bus_freq <= I2C_MAX_STANDARD_MODE_FREQ)
852 drv_data->errata_delay = true;
855 if (of_device_is_compatible(np, "marvell,mv78230-a0-i2c")) {
856 drv_data->offload_enabled = false;
857 /* The delay is only needed in standard mode (100kHz) */
858 if (bus_freq <= I2C_MAX_STANDARD_MODE_FREQ)
859 drv_data->errata_delay = true;
862 if (of_device_is_compatible(np, "allwinner,sun6i-a31-i2c"))
863 drv_data->irq_clear_inverted = true;
868 #else /* CONFIG_OF */
870 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
875 #endif /* CONFIG_OF */
877 static int mv64xxx_i2c_init_recovery_info(struct mv64xxx_i2c_data *drv_data,
880 struct i2c_bus_recovery_info *rinfo = &drv_data->rinfo;
882 rinfo->pinctrl = devm_pinctrl_get(dev);
883 if (IS_ERR(rinfo->pinctrl)) {
884 if (PTR_ERR(rinfo->pinctrl) == -EPROBE_DEFER)
885 return -EPROBE_DEFER;
886 dev_info(dev, "can't get pinctrl, bus recovery not supported\n");
887 return PTR_ERR(rinfo->pinctrl);
888 } else if (!rinfo->pinctrl) {
892 drv_data->adapter.bus_recovery_info = rinfo;
897 mv64xxx_i2c_probe(struct platform_device *pd)
899 struct mv64xxx_i2c_data *drv_data;
900 struct mv64xxx_i2c_pdata *pdata = dev_get_platdata(&pd->dev);
903 if ((!pdata && !pd->dev.of_node))
906 drv_data = devm_kzalloc(&pd->dev, sizeof(struct mv64xxx_i2c_data),
911 drv_data->reg_base = devm_platform_ioremap_resource(pd, 0);
912 if (IS_ERR(drv_data->reg_base))
913 return PTR_ERR(drv_data->reg_base);
915 strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
916 sizeof(drv_data->adapter.name));
918 init_waitqueue_head(&drv_data->waitq);
919 spin_lock_init(&drv_data->lock);
921 /* Not all platforms have clocks */
922 drv_data->clk = devm_clk_get(&pd->dev, NULL);
923 if (PTR_ERR(drv_data->clk) == -EPROBE_DEFER)
924 return -EPROBE_DEFER;
925 if (!IS_ERR(drv_data->clk))
926 clk_prepare_enable(drv_data->clk);
928 drv_data->reg_clk = devm_clk_get(&pd->dev, "reg");
929 if (PTR_ERR(drv_data->reg_clk) == -EPROBE_DEFER)
930 return -EPROBE_DEFER;
931 if (!IS_ERR(drv_data->reg_clk))
932 clk_prepare_enable(drv_data->reg_clk);
934 drv_data->irq = platform_get_irq(pd, 0);
937 drv_data->freq_m = pdata->freq_m;
938 drv_data->freq_n = pdata->freq_n;
939 drv_data->adapter.timeout = msecs_to_jiffies(pdata->timeout);
940 drv_data->offload_enabled = false;
941 memcpy(&drv_data->reg_offsets, &mv64xxx_i2c_regs_mv64xxx, sizeof(drv_data->reg_offsets));
942 } else if (pd->dev.of_node) {
943 rc = mv64xxx_of_config(drv_data, &pd->dev);
947 if (drv_data->irq < 0) {
952 rc = mv64xxx_i2c_init_recovery_info(drv_data, &pd->dev);
953 if (rc == -EPROBE_DEFER)
956 drv_data->adapter.dev.parent = &pd->dev;
957 drv_data->adapter.algo = &mv64xxx_i2c_algo;
958 drv_data->adapter.owner = THIS_MODULE;
959 drv_data->adapter.class = I2C_CLASS_DEPRECATED;
960 drv_data->adapter.nr = pd->id;
961 drv_data->adapter.dev.of_node = pd->dev.of_node;
962 platform_set_drvdata(pd, drv_data);
963 i2c_set_adapdata(&drv_data->adapter, drv_data);
965 mv64xxx_i2c_hw_init(drv_data);
967 rc = request_irq(drv_data->irq, mv64xxx_i2c_intr, 0,
968 MV64XXX_I2C_CTLR_NAME, drv_data);
970 dev_err(&drv_data->adapter.dev,
971 "mv64xxx: Can't register intr handler irq%d: %d\n",
974 } else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) {
975 dev_err(&drv_data->adapter.dev,
976 "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc);
983 free_irq(drv_data->irq, drv_data);
985 reset_control_assert(drv_data->rstc);
987 clk_disable_unprepare(drv_data->reg_clk);
988 clk_disable_unprepare(drv_data->clk);
994 mv64xxx_i2c_remove(struct platform_device *dev)
996 struct mv64xxx_i2c_data *drv_data = platform_get_drvdata(dev);
998 i2c_del_adapter(&drv_data->adapter);
999 free_irq(drv_data->irq, drv_data);
1000 reset_control_assert(drv_data->rstc);
1001 clk_disable_unprepare(drv_data->reg_clk);
1002 clk_disable_unprepare(drv_data->clk);
1008 static int mv64xxx_i2c_resume(struct device *dev)
1010 struct mv64xxx_i2c_data *drv_data = dev_get_drvdata(dev);
1012 mv64xxx_i2c_hw_init(drv_data);
1017 static const struct dev_pm_ops mv64xxx_i2c_pm = {
1018 .resume = mv64xxx_i2c_resume,
1021 #define mv64xxx_i2c_pm_ops (&mv64xxx_i2c_pm)
1023 #define mv64xxx_i2c_pm_ops NULL
1026 static struct platform_driver mv64xxx_i2c_driver = {
1027 .probe = mv64xxx_i2c_probe,
1028 .remove = mv64xxx_i2c_remove,
1030 .name = MV64XXX_I2C_CTLR_NAME,
1031 .pm = mv64xxx_i2c_pm_ops,
1032 .of_match_table = mv64xxx_i2c_of_match_table,
1036 module_platform_driver(mv64xxx_i2c_driver);
1038 MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
1039 MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver");
1040 MODULE_LICENSE("GPL");