drivers/i2c/busses/i2c-mt7621.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * drivers/i2c/busses/i2c-mt7621.c
   4  *
   5  * Copyright (C) 2013 Steven Liu <steven_liu@mediatek.com>
   6  * Copyright (C) 2016 Michael Lee <igvtee@gmail.com>
   7  * Copyright (C) 2018 Jan Breuer <jan.breuer@jaybee.cz>
   8  *
   9  * Improve driver for i2cdetect from i2c-tools to detect i2c devices on the bus.
  10  * (C) 2014 Sittisak <sittisaks@hotmail.com>
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/delay.h>
  15 #include <linux/i2c.h>
  16 #include <linux/io.h>
  17 #include <linux/iopoll.h>
  18 #include <linux/module.h>
  19 #include <linux/of_platform.h>
  20 #include <linux/reset.h>
  21
  22 #define REG_SM0CFG2_REG         0x28
  23 #define REG_SM0CTL0_REG         0x40
  24 #define REG_SM0CTL1_REG         0x44
  25 #define REG_SM0D0_REG           0x50
  26 #define REG_SM0D1_REG           0x54
  27 #define REG_PINTEN_REG          0x5c
  28 #define REG_PINTST_REG          0x60
  29 #define REG_PINTCL_REG          0x64
  30
  31 /* REG_SM0CFG2_REG */
  32 #define SM0CFG2_IS_AUTOMODE     BIT(0)
  33
  34 /* REG_SM0CTL0_REG */
  35 #define SM0CTL0_ODRAIN          BIT(31)
  36 #define SM0CTL0_CLK_DIV_MASK    (0x7ff << 16)
  37 #define SM0CTL0_CLK_DIV_MAX     0x7ff
  38 #define SM0CTL0_CS_STATUS       BIT(4)
  39 #define SM0CTL0_SCL_STATE       BIT(3)
  40 #define SM0CTL0_SDA_STATE       BIT(2)
  41 #define SM0CTL0_EN              BIT(1)
  42 #define SM0CTL0_SCL_STRETCH     BIT(0)
  43
  44 /* REG_SM0CTL1_REG */
  45 #define SM0CTL1_ACK_MASK        (0xff << 16)
  46 #define SM0CTL1_PGLEN_MASK      (0x7 << 8)
  47 #define SM0CTL1_PGLEN(x)        ((((x) - 1) << 8) & SM0CTL1_PGLEN_MASK)
  48 #define SM0CTL1_READ            (5 << 4)
  49 #define SM0CTL1_READ_LAST       (4 << 4)
  50 #define SM0CTL1_STOP            (3 << 4)
  51 #define SM0CTL1_WRITE           (2 << 4)
  52 #define SM0CTL1_START           (1 << 4)
  53 #define SM0CTL1_MODE_MASK       (0x7 << 4)
  54 #define SM0CTL1_TRI             BIT(0)
  55
  56 /* timeout waiting for I2C devices to respond */
  57 #define TIMEOUT_MS              1000
  58
  59 struct mtk_i2c {
  60         void __iomem *base;
  61         struct device *dev;
  62         struct i2c_adapter adap;
  63         u32 bus_freq;
  64         u32 clk_div;
  65         u32 flags;
  66         struct clk *clk;
  67 };
  68
  69 static int mtk_i2c_wait_idle(struct mtk_i2c *i2c)
  70 {
  71         int ret;
  72         u32 val;
  73
  74         ret = readl_relaxed_poll_timeout(i2c->base + REG_SM0CTL1_REG,
  75                                          val, !(val & SM0CTL1_TRI),
  76                                          10, TIMEOUT_MS * 1000);
  77         if (ret)
  78                 dev_dbg(i2c->dev, "idle err(%d)\n", ret);
  79
  80         return ret;
  81 }
  82
  83 static void mtk_i2c_reset(struct mtk_i2c *i2c)
  84 {
  85         int ret;
  86
  87         ret = device_reset(i2c->adap.dev.parent);
  88         if (ret)
  89                 dev_err(i2c->dev, "I2C reset failed!\n");
  90
  91         /*
  92          * Don't set SM0CTL0_ODRAIN as its bit meaning is inverted. To
  93          * configure open-drain mode, this bit needs to be cleared.
  94          */
  95         iowrite32(((i2c->clk_div << 16) & SM0CTL0_CLK_DIV_MASK) | SM0CTL0_EN |
  96                   SM0CTL0_SCL_STRETCH, i2c->base + REG_SM0CTL0_REG);
  97         iowrite32(0, i2c->base + REG_SM0CFG2_REG);
  98 }
  99
 100 static void mtk_i2c_dump_reg(struct mtk_i2c *i2c)
 101 {
 102         dev_dbg(i2c->dev,
 103                 "SM0CFG2 %08x, SM0CTL0 %08x, SM0CTL1 %08x, SM0D0 %08x, SM0D1 %08x\n",
 104                 ioread32(i2c->base + REG_SM0CFG2_REG),
 105                 ioread32(i2c->base + REG_SM0CTL0_REG),
 106                 ioread32(i2c->base + REG_SM0CTL1_REG),
 107                 ioread32(i2c->base + REG_SM0D0_REG),
 108                 ioread32(i2c->base + REG_SM0D1_REG));
 109 }
 110
 111 static int mtk_i2c_check_ack(struct mtk_i2c *i2c, u32 expected)
 112 {
 113         u32 ack = readl_relaxed(i2c->base + REG_SM0CTL1_REG);
 114         u32 ack_expected = (expected << 16) & SM0CTL1_ACK_MASK;
 115
 116         return ((ack & ack_expected) == ack_expected) ? 0 : -ENXIO;
 117 }
 118
 119 static int mtk_i2c_master_start(struct mtk_i2c *i2c)
 120 {
 121         iowrite32(SM0CTL1_START | SM0CTL1_TRI, i2c->base + REG_SM0CTL1_REG);
 122         return mtk_i2c_wait_idle(i2c);
 123 }
 124
 125 static int mtk_i2c_master_stop(struct mtk_i2c *i2c)
 126 {
 127         iowrite32(SM0CTL1_STOP | SM0CTL1_TRI, i2c->base + REG_SM0CTL1_REG);
 128         return mtk_i2c_wait_idle(i2c);
 129 }
 130
 131 static int mtk_i2c_master_cmd(struct mtk_i2c *i2c, u32 cmd, int page_len)
 132 {
 133         iowrite32(cmd | SM0CTL1_TRI | SM0CTL1_PGLEN(page_len),
 134                   i2c->base + REG_SM0CTL1_REG);
 135         return mtk_i2c_wait_idle(i2c);
 136 }
 137
 138 static int mtk_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
 139                                int num)
 140 {
 141         struct mtk_i2c *i2c;
 142         struct i2c_msg *pmsg;
 143         u16 addr;
 144         int i, j, ret, len, page_len;
 145         u32 cmd;
 146         u32 data[2];
 147
 148         i2c = i2c_get_adapdata(adap);
 149
 150         for (i = 0; i < num; i++) {
 151                 pmsg = &msgs[i];
 152
 153                 /* wait hardware idle */
 154                 ret = mtk_i2c_wait_idle(i2c);
 155                 if (ret)
 156                         goto err_timeout;
 157
 158                 /* start sequence */
 159                 ret = mtk_i2c_master_start(i2c);
 160                 if (ret)
 161                         goto err_timeout;
 162
 163                 /* write address */
 164                 if (pmsg->flags & I2C_M_TEN) {
 165                         /* 10 bits address */
 166                         addr = 0xf0 | ((pmsg->addr >> 7) & 0x06);
 167                         addr |= (pmsg->addr & 0xff) << 8;
 168                         if (pmsg->flags & I2C_M_RD)
 169                                 addr |= 1;
 170                         iowrite32(addr, i2c->base + REG_SM0D0_REG);
 171                         ret = mtk_i2c_master_cmd(i2c, SM0CTL1_WRITE, 2);
 172                         if (ret)
 173                                 goto err_timeout;
 174                 } else {
 175                         /* 7 bits address */
 176                         addr = i2c_8bit_addr_from_msg(pmsg);
 177                         iowrite32(addr, i2c->base + REG_SM0D0_REG);
 178                         ret = mtk_i2c_master_cmd(i2c, SM0CTL1_WRITE, 1);
 179                         if (ret)
 180                                 goto err_timeout;
 181                 }
 182
 183                 /* check address ACK */
 184                 if (!(pmsg->flags & I2C_M_IGNORE_NAK)) {
 185                         ret = mtk_i2c_check_ack(i2c, BIT(0));
 186                         if (ret)
 187                                 goto err_ack;
 188                 }
 189
 190                 /* transfer data */
 191                 for (len = pmsg->len, j = 0; len > 0; len -= 8, j += 8) {
 192                         page_len = (len >= 8) ? 8 : len;
 193
 194                         if (pmsg->flags & I2C_M_RD) {
 195                                 cmd = (len > 8) ?
 196                                         SM0CTL1_READ : SM0CTL1_READ_LAST;
 197                         } else {
 198                                 memcpy(data, &pmsg->buf[j], page_len);
 199                                 iowrite32(data[0], i2c->base + REG_SM0D0_REG);
 200                                 iowrite32(data[1], i2c->base + REG_SM0D1_REG);
 201                                 cmd = SM0CTL1_WRITE;
 202                         }
 203
 204                         ret = mtk_i2c_master_cmd(i2c, cmd, page_len);
 205                         if (ret)
 206                                 goto err_timeout;
 207
 208                         if (pmsg->flags & I2C_M_RD) {
 209                                 data[0] = ioread32(i2c->base + REG_SM0D0_REG);
 210                                 data[1] = ioread32(i2c->base + REG_SM0D1_REG);
 211                                 memcpy(&pmsg->buf[j], data, page_len);
 212                         } else {
 213                                 if (!(pmsg->flags & I2C_M_IGNORE_NAK)) {
 214                                         ret = mtk_i2c_check_ack(i2c,
 215                                                                 (1 << page_len)
 216                                                                 - 1);
 217                                         if (ret)
 218                                                 goto err_ack;
 219                                 }
 220                         }
 221                 }
 222         }
 223
 224         ret = mtk_i2c_master_stop(i2c);
 225         if (ret)
 226                 goto err_timeout;
 227
 228         /* the return value is number of executed messages */
 229         return i;
 230
 231 err_ack:
 232         ret = mtk_i2c_master_stop(i2c);
 233         if (ret)
 234                 goto err_timeout;
 235         return -ENXIO;
 236
 237 err_timeout:
 238         mtk_i2c_dump_reg(i2c);
 239         mtk_i2c_reset(i2c);
 240         return ret;
 241 }
 242
 243 static u32 mtk_i2c_func(struct i2c_adapter *a)
 244 {
 245         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
 246 }
 247
 248 static const struct i2c_algorithm mtk_i2c_algo = {
 249         .master_xfer    = mtk_i2c_master_xfer,
 250         .functionality  = mtk_i2c_func,
 251 };
 252
 253 static const struct of_device_id i2c_mtk_dt_ids[] = {
 254         { .compatible = "mediatek,mt7621-i2c" },
 255         { /* sentinel */ }
 256 };
 257
 258 MODULE_DEVICE_TABLE(of, i2c_mtk_dt_ids);
 259
 260 static void mtk_i2c_init(struct mtk_i2c *i2c)
 261 {
 262         i2c->clk_div = clk_get_rate(i2c->clk) / i2c->bus_freq - 1;
 263         if (i2c->clk_div < 99)
 264                 i2c->clk_div = 99;
 265         if (i2c->clk_div > SM0CTL0_CLK_DIV_MAX)
 266                 i2c->clk_div = SM0CTL0_CLK_DIV_MAX;
 267
 268         mtk_i2c_reset(i2c);
 269 }
 270
 271 static int mtk_i2c_probe(struct platform_device *pdev)
 272 {
 273         struct resource *res;
 274         struct mtk_i2c *i2c;
 275         struct i2c_adapter *adap;
 276         int ret;
 277
 278         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 279
 280         i2c = devm_kzalloc(&pdev->dev, sizeof(struct mtk_i2c), GFP_KERNEL);
 281         if (!i2c)
 282                 return -ENOMEM;
 283
 284         i2c->base = devm_ioremap_resource(&pdev->dev, res);
 285         if (IS_ERR(i2c->base))
 286                 return PTR_ERR(i2c->base);
 287
 288         i2c->clk = devm_clk_get(&pdev->dev, NULL);
 289         if (IS_ERR(i2c->clk)) {
 290                 dev_err(&pdev->dev, "no clock defined\n");
 291                 return PTR_ERR(i2c->clk);
 292         }
 293         ret = clk_prepare_enable(i2c->clk);
 294         if (ret) {
 295                 dev_err(&pdev->dev, "Unable to enable clock\n");
 296                 return ret;
 297         }
 298
 299         i2c->dev = &pdev->dev;
 300
 301         if (of_property_read_u32(pdev->dev.of_node, "clock-frequency",
 302                                  &i2c->bus_freq))
 303                 i2c->bus_freq = I2C_MAX_STANDARD_MODE_FREQ;
 304
 305         if (i2c->bus_freq == 0) {
 306                 dev_warn(i2c->dev, "clock-frequency 0 not supported\n");
 307                 return -EINVAL;
 308         }
 309
 310         adap = &i2c->adap;
 311         adap->owner = THIS_MODULE;
 312         adap->algo = &mtk_i2c_algo;
 313         adap->retries = 3;
 314         adap->dev.parent = &pdev->dev;
 315         i2c_set_adapdata(adap, i2c);
 316         adap->dev.of_node = pdev->dev.of_node;
 317         strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));
 318
 319         platform_set_drvdata(pdev, i2c);
 320
 321         mtk_i2c_init(i2c);
 322
 323         ret = i2c_add_adapter(adap);
 324         if (ret < 0)
 325                 return ret;
 326
 327         dev_info(&pdev->dev, "clock %u kHz\n", i2c->bus_freq / 1000);
 328
 329         return ret;
 330 }
 331
 332 static int mtk_i2c_remove(struct platform_device *pdev)
 333 {
 334         struct mtk_i2c *i2c = platform_get_drvdata(pdev);
 335
 336         clk_disable_unprepare(i2c->clk);
 337         i2c_del_adapter(&i2c->adap);
 338
 339         return 0;
 340 }
 341
 342 static struct platform_driver mtk_i2c_driver = {
 343         .probe          = mtk_i2c_probe,
 344         .remove         = mtk_i2c_remove,
 345         .driver         = {
 346                 .name   = "i2c-mt7621",
 347                 .of_match_table = i2c_mtk_dt_ids,
 348         },
 349 };
 350
 351 module_platform_driver(mtk_i2c_driver);
 352
 353 MODULE_AUTHOR("Steven Liu");
 354 MODULE_DESCRIPTION("MT7621 I2C host driver");
 355 MODULE_LICENSE("GPL v2");
 356 MODULE_ALIAS("platform:MT7621-I2C");