drivers/i2c/busses/i2c-mt65xx.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014 MediaTek Inc.
   4  * Author: Xudong Chen <xudong.chen@mediatek.com>
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/completion.h>
   9 #include <linux/delay.h>
  10 #include <linux/device.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/err.h>
  13 #include <linux/errno.h>
  14 #include <linux/i2c.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/kernel.h>
  19 #include <linux/mm.h>
  20 #include <linux/module.h>
  21 #include <linux/of_address.h>
  22 #include <linux/of_device.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/scatterlist.h>
  26 #include <linux/sched.h>
  27 #include <linux/slab.h>
  28
  29 #define I2C_RS_TRANSFER                 (1 << 4)
  30 #define I2C_ARB_LOST                    (1 << 3)
  31 #define I2C_HS_NACKERR                  (1 << 2)
  32 #define I2C_ACKERR                      (1 << 1)
  33 #define I2C_TRANSAC_COMP                (1 << 0)
  34 #define I2C_TRANSAC_START               (1 << 0)
  35 #define I2C_RS_MUL_CNFG                 (1 << 15)
  36 #define I2C_RS_MUL_TRIG                 (1 << 14)
  37 #define I2C_DCM_DISABLE                 0x0000
  38 #define I2C_IO_CONFIG_OPEN_DRAIN        0x0003
  39 #define I2C_IO_CONFIG_PUSH_PULL         0x0000
  40 #define I2C_SOFT_RST                    0x0001
  41 #define I2C_HANDSHAKE_RST               0x0020
  42 #define I2C_FIFO_ADDR_CLR               0x0001
  43 #define I2C_DELAY_LEN                   0x0002
  44 #define I2C_TIME_CLR_VALUE              0x0000
  45 #define I2C_TIME_DEFAULT_VALUE          0x0003
  46 #define I2C_WRRD_TRANAC_VALUE           0x0002
  47 #define I2C_RD_TRANAC_VALUE             0x0001
  48 #define I2C_SCL_MIS_COMP_VALUE          0x0000
  49 #define I2C_CHN_CLR_FLAG                0x0000
  50
  51 #define I2C_DMA_CON_TX                  0x0000
  52 #define I2C_DMA_CON_RX                  0x0001
  53 #define I2C_DMA_ASYNC_MODE              0x0004
  54 #define I2C_DMA_SKIP_CONFIG             0x0010
  55 #define I2C_DMA_DIR_CHANGE              0x0200
  56 #define I2C_DMA_START_EN                0x0001
  57 #define I2C_DMA_INT_FLAG_NONE           0x0000
  58 #define I2C_DMA_CLR_FLAG                0x0000
  59 #define I2C_DMA_WARM_RST                0x0001
  60 #define I2C_DMA_HARD_RST                0x0002
  61 #define I2C_DMA_HANDSHAKE_RST           0x0004
  62
  63 #define MAX_SAMPLE_CNT_DIV              8
  64 #define MAX_STEP_CNT_DIV                64
  65 #define MAX_CLOCK_DIV                   256
  66 #define MAX_HS_STEP_CNT_DIV             8
  67 #define I2C_STANDARD_MODE_BUFFER        (1000 / 2)
  68 #define I2C_FAST_MODE_BUFFER            (300 / 2)
  69 #define I2C_FAST_MODE_PLUS_BUFFER       (20 / 2)
  70
  71 #define I2C_CONTROL_RS                  (0x1 << 1)
  72 #define I2C_CONTROL_DMA_EN              (0x1 << 2)
  73 #define I2C_CONTROL_CLK_EXT_EN          (0x1 << 3)
  74 #define I2C_CONTROL_DIR_CHANGE          (0x1 << 4)
  75 #define I2C_CONTROL_ACKERR_DET_EN       (0x1 << 5)
  76 #define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6)
  77 #define I2C_CONTROL_DMAACK_EN           (0x1 << 8)
  78 #define I2C_CONTROL_ASYNC_MODE          (0x1 << 9)
  79 #define I2C_CONTROL_WRAPPER             (0x1 << 0)
  80
  81 #define I2C_DRV_NAME            "i2c-mt65xx"
  82
  83 enum DMA_REGS_OFFSET {
  84         OFFSET_INT_FLAG = 0x0,
  85         OFFSET_INT_EN = 0x04,
  86         OFFSET_EN = 0x08,
  87         OFFSET_RST = 0x0c,
  88         OFFSET_CON = 0x18,
  89         OFFSET_TX_MEM_ADDR = 0x1c,
  90         OFFSET_RX_MEM_ADDR = 0x20,
  91         OFFSET_TX_LEN = 0x24,
  92         OFFSET_RX_LEN = 0x28,
  93         OFFSET_TX_4G_MODE = 0x54,
  94         OFFSET_RX_4G_MODE = 0x58,
  95 };
  96
  97 enum i2c_trans_st_rs {
  98         I2C_TRANS_STOP = 0,
  99         I2C_TRANS_REPEATED_START,
 100 };
 101
 102 enum mtk_trans_op {
 103         I2C_MASTER_WR = 1,
 104         I2C_MASTER_RD,
 105         I2C_MASTER_WRRD,
 106 };
 107
 108 enum I2C_REGS_OFFSET {
 109         OFFSET_DATA_PORT,
 110         OFFSET_SLAVE_ADDR,
 111         OFFSET_INTR_MASK,
 112         OFFSET_INTR_STAT,
 113         OFFSET_CONTROL,
 114         OFFSET_TRANSFER_LEN,
 115         OFFSET_TRANSAC_LEN,
 116         OFFSET_DELAY_LEN,
 117         OFFSET_TIMING,
 118         OFFSET_START,
 119         OFFSET_EXT_CONF,
 120         OFFSET_FIFO_STAT,
 121         OFFSET_FIFO_THRESH,
 122         OFFSET_FIFO_ADDR_CLR,
 123         OFFSET_IO_CONFIG,
 124         OFFSET_RSV_DEBUG,
 125         OFFSET_HS,
 126         OFFSET_SOFTRESET,
 127         OFFSET_DCM_EN,
 128         OFFSET_PATH_DIR,
 129         OFFSET_DEBUGSTAT,
 130         OFFSET_DEBUGCTRL,
 131         OFFSET_TRANSFER_LEN_AUX,
 132         OFFSET_CLOCK_DIV,
 133         OFFSET_LTIMING,
 134         OFFSET_SCL_HIGH_LOW_RATIO,
 135         OFFSET_HS_SCL_HIGH_LOW_RATIO,
 136         OFFSET_SCL_MIS_COMP_POINT,
 137         OFFSET_STA_STO_AC_TIMING,
 138         OFFSET_HS_STA_STO_AC_TIMING,
 139         OFFSET_SDA_TIMING,
 140 };
 141
 142 static const u16 mt_i2c_regs_v1[] = {
 143         [OFFSET_DATA_PORT] = 0x0,
 144         [OFFSET_SLAVE_ADDR] = 0x4,
 145         [OFFSET_INTR_MASK] = 0x8,
 146         [OFFSET_INTR_STAT] = 0xc,
 147         [OFFSET_CONTROL] = 0x10,
 148         [OFFSET_TRANSFER_LEN] = 0x14,
 149         [OFFSET_TRANSAC_LEN] = 0x18,
 150         [OFFSET_DELAY_LEN] = 0x1c,
 151         [OFFSET_TIMING] = 0x20,
 152         [OFFSET_START] = 0x24,
 153         [OFFSET_EXT_CONF] = 0x28,
 154         [OFFSET_FIFO_STAT] = 0x30,
 155         [OFFSET_FIFO_THRESH] = 0x34,
 156         [OFFSET_FIFO_ADDR_CLR] = 0x38,
 157         [OFFSET_IO_CONFIG] = 0x40,
 158         [OFFSET_RSV_DEBUG] = 0x44,
 159         [OFFSET_HS] = 0x48,
 160         [OFFSET_SOFTRESET] = 0x50,
 161         [OFFSET_DCM_EN] = 0x54,
 162         [OFFSET_PATH_DIR] = 0x60,
 163         [OFFSET_DEBUGSTAT] = 0x64,
 164         [OFFSET_DEBUGCTRL] = 0x68,
 165         [OFFSET_TRANSFER_LEN_AUX] = 0x6c,
 166         [OFFSET_CLOCK_DIV] = 0x70,
 167         [OFFSET_SCL_HIGH_LOW_RATIO] = 0x74,
 168         [OFFSET_HS_SCL_HIGH_LOW_RATIO] = 0x78,
 169         [OFFSET_SCL_MIS_COMP_POINT] = 0x7C,
 170         [OFFSET_STA_STO_AC_TIMING] = 0x80,
 171         [OFFSET_HS_STA_STO_AC_TIMING] = 0x84,
 172         [OFFSET_SDA_TIMING] = 0x88,
 173 };
 174
 175 static const u16 mt_i2c_regs_v2[] = {
 176         [OFFSET_DATA_PORT] = 0x0,
 177         [OFFSET_SLAVE_ADDR] = 0x4,
 178         [OFFSET_INTR_MASK] = 0x8,
 179         [OFFSET_INTR_STAT] = 0xc,
 180         [OFFSET_CONTROL] = 0x10,
 181         [OFFSET_TRANSFER_LEN] = 0x14,
 182         [OFFSET_TRANSAC_LEN] = 0x18,
 183         [OFFSET_DELAY_LEN] = 0x1c,
 184         [OFFSET_TIMING] = 0x20,
 185         [OFFSET_START] = 0x24,
 186         [OFFSET_EXT_CONF] = 0x28,
 187         [OFFSET_LTIMING] = 0x2c,
 188         [OFFSET_HS] = 0x30,
 189         [OFFSET_IO_CONFIG] = 0x34,
 190         [OFFSET_FIFO_ADDR_CLR] = 0x38,
 191         [OFFSET_SDA_TIMING] = 0x3c,
 192         [OFFSET_TRANSFER_LEN_AUX] = 0x44,
 193         [OFFSET_CLOCK_DIV] = 0x48,
 194         [OFFSET_SOFTRESET] = 0x50,
 195         [OFFSET_SCL_MIS_COMP_POINT] = 0x90,
 196         [OFFSET_DEBUGSTAT] = 0xe0,
 197         [OFFSET_DEBUGCTRL] = 0xe8,
 198         [OFFSET_FIFO_STAT] = 0xf4,
 199         [OFFSET_FIFO_THRESH] = 0xf8,
 200         [OFFSET_DCM_EN] = 0xf88,
 201 };
 202
 203 struct mtk_i2c_compatible {
 204         const struct i2c_adapter_quirks *quirks;
 205         const u16 *regs;
 206         unsigned char pmic_i2c: 1;
 207         unsigned char dcm: 1;
 208         unsigned char auto_restart: 1;
 209         unsigned char aux_len_reg: 1;
 210         unsigned char timing_adjust: 1;
 211         unsigned char dma_sync: 1;
 212         unsigned char ltiming_adjust: 1;
 213         unsigned char apdma_sync: 1;
 214         unsigned char max_dma_support;
 215 };
 216
 217 struct mtk_i2c_ac_timing {
 218         u16 htiming;
 219         u16 ltiming;
 220         u16 hs;
 221         u16 ext;
 222         u16 inter_clk_div;
 223         u16 scl_hl_ratio;
 224         u16 hs_scl_hl_ratio;
 225         u16 sta_stop;
 226         u16 hs_sta_stop;
 227         u16 sda_timing;
 228 };
 229
 230 struct mtk_i2c {
 231         struct i2c_adapter adap;        /* i2c host adapter */
 232         struct device *dev;
 233         struct completion msg_complete;
 234         struct i2c_timings timing_info;
 235
 236         /* set in i2c probe */
 237         void __iomem *base;             /* i2c base addr */
 238         void __iomem *pdmabase;         /* dma base address*/
 239         struct clk *clk_main;           /* main clock for i2c bus */
 240         struct clk *clk_dma;            /* DMA clock for i2c via DMA */
 241         struct clk *clk_pmic;           /* PMIC clock for i2c from PMIC */
 242         struct clk *clk_arb;            /* Arbitrator clock for i2c */
 243         bool have_pmic;                 /* can use i2c pins from PMIC */
 244         bool use_push_pull;             /* IO config push-pull mode */
 245
 246         u16 irq_stat;                   /* interrupt status */
 247         unsigned int clk_src_div;
 248         unsigned int speed_hz;          /* The speed in transfer */
 249         enum mtk_trans_op op;
 250         u16 timing_reg;
 251         u16 high_speed_reg;
 252         u16 ltiming_reg;
 253         unsigned char auto_restart;
 254         bool ignore_restart_irq;
 255         struct mtk_i2c_ac_timing ac_timing;
 256         const struct mtk_i2c_compatible *dev_comp;
 257 };
 258
 259 /**
 260  * struct i2c_spec_values:
 261  * @min_low_ns: min LOW period of the SCL clock
 262  * @min_su_sta_ns: min set-up time for a repeated START condition
 263  * @max_hd_dat_ns: max data hold time
 264  * @min_su_dat_ns: min data set-up time
 265  */
 266 struct i2c_spec_values {
 267         unsigned int min_low_ns;
 268         unsigned int min_su_sta_ns;
 269         unsigned int max_hd_dat_ns;
 270         unsigned int min_su_dat_ns;
 271 };
 272
 273 static const struct i2c_spec_values standard_mode_spec = {
 274         .min_low_ns = 4700 + I2C_STANDARD_MODE_BUFFER,
 275         .min_su_sta_ns = 4700 + I2C_STANDARD_MODE_BUFFER,
 276         .max_hd_dat_ns = 3450 - I2C_STANDARD_MODE_BUFFER,
 277         .min_su_dat_ns = 250 + I2C_STANDARD_MODE_BUFFER,
 278 };
 279
 280 static const struct i2c_spec_values fast_mode_spec = {
 281         .min_low_ns = 1300 + I2C_FAST_MODE_BUFFER,
 282         .min_su_sta_ns = 600 + I2C_FAST_MODE_BUFFER,
 283         .max_hd_dat_ns = 900 - I2C_FAST_MODE_BUFFER,
 284         .min_su_dat_ns = 100 + I2C_FAST_MODE_BUFFER,
 285 };
 286
 287 static const struct i2c_spec_values fast_mode_plus_spec = {
 288         .min_low_ns = 500 + I2C_FAST_MODE_PLUS_BUFFER,
 289         .min_su_sta_ns = 260 + I2C_FAST_MODE_PLUS_BUFFER,
 290         .max_hd_dat_ns = 400 - I2C_FAST_MODE_PLUS_BUFFER,
 291         .min_su_dat_ns = 50 + I2C_FAST_MODE_PLUS_BUFFER,
 292 };
 293
 294 static const struct i2c_adapter_quirks mt6577_i2c_quirks = {
 295         .flags = I2C_AQ_COMB_WRITE_THEN_READ,
 296         .max_num_msgs = 1,
 297         .max_write_len = 255,
 298         .max_read_len = 255,
 299         .max_comb_1st_msg_len = 255,
 300         .max_comb_2nd_msg_len = 31,
 301 };
 302
 303 static const struct i2c_adapter_quirks mt7622_i2c_quirks = {
 304         .max_num_msgs = 255,
 305 };
 306
 307 static const struct i2c_adapter_quirks mt8183_i2c_quirks = {
 308         .flags = I2C_AQ_NO_ZERO_LEN,
 309 };
 310
 311 static const struct mtk_i2c_compatible mt2712_compat = {
 312         .regs = mt_i2c_regs_v1,
 313         .pmic_i2c = 0,
 314         .dcm = 1,
 315         .auto_restart = 1,
 316         .aux_len_reg = 1,
 317         .timing_adjust = 1,
 318         .dma_sync = 0,
 319         .ltiming_adjust = 0,
 320         .apdma_sync = 0,
 321         .max_dma_support = 33,
 322 };
 323
 324 static const struct mtk_i2c_compatible mt6577_compat = {
 325         .quirks = &mt6577_i2c_quirks,
 326         .regs = mt_i2c_regs_v1,
 327         .pmic_i2c = 0,
 328         .dcm = 1,
 329         .auto_restart = 0,
 330         .aux_len_reg = 0,
 331         .timing_adjust = 0,
 332         .dma_sync = 0,
 333         .ltiming_adjust = 0,
 334         .apdma_sync = 0,
 335         .max_dma_support = 32,
 336 };
 337
 338 static const struct mtk_i2c_compatible mt6589_compat = {
 339         .quirks = &mt6577_i2c_quirks,
 340         .regs = mt_i2c_regs_v1,
 341         .pmic_i2c = 1,
 342         .dcm = 0,
 343         .auto_restart = 0,
 344         .aux_len_reg = 0,
 345         .timing_adjust = 0,
 346         .dma_sync = 0,
 347         .ltiming_adjust = 0,
 348         .apdma_sync = 0,
 349         .max_dma_support = 32,
 350 };
 351
 352 static const struct mtk_i2c_compatible mt7622_compat = {
 353         .quirks = &mt7622_i2c_quirks,
 354         .regs = mt_i2c_regs_v1,
 355         .pmic_i2c = 0,
 356         .dcm = 1,
 357         .auto_restart = 1,
 358         .aux_len_reg = 1,
 359         .timing_adjust = 0,
 360         .dma_sync = 0,
 361         .ltiming_adjust = 0,
 362         .apdma_sync = 0,
 363         .max_dma_support = 32,
 364 };
 365
 366 static const struct mtk_i2c_compatible mt8173_compat = {
 367         .regs = mt_i2c_regs_v1,
 368         .pmic_i2c = 0,
 369         .dcm = 1,
 370         .auto_restart = 1,
 371         .aux_len_reg = 1,
 372         .timing_adjust = 0,
 373         .dma_sync = 0,
 374         .ltiming_adjust = 0,
 375         .apdma_sync = 0,
 376         .max_dma_support = 33,
 377 };
 378
 379 static const struct mtk_i2c_compatible mt8183_compat = {
 380         .quirks = &mt8183_i2c_quirks,
 381         .regs = mt_i2c_regs_v2,
 382         .pmic_i2c = 0,
 383         .dcm = 0,
 384         .auto_restart = 1,
 385         .aux_len_reg = 1,
 386         .timing_adjust = 1,
 387         .dma_sync = 1,
 388         .ltiming_adjust = 1,
 389         .apdma_sync = 0,
 390         .max_dma_support = 33,
 391 };
 392
 393 static const struct mtk_i2c_compatible mt8192_compat = {
 394         .quirks = &mt8183_i2c_quirks,
 395         .regs = mt_i2c_regs_v2,
 396         .pmic_i2c = 0,
 397         .dcm = 0,
 398         .auto_restart = 1,
 399         .aux_len_reg = 1,
 400         .timing_adjust = 1,
 401         .dma_sync = 1,
 402         .ltiming_adjust = 1,
 403         .apdma_sync = 1,
 404         .max_dma_support = 36,
 405 };
 406
 407 static const struct of_device_id mtk_i2c_of_match[] = {
 408         { .compatible = "mediatek,mt2712-i2c", .data = &mt2712_compat },
 409         { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
 410         { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
 411         { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
 412         { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
 413         { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
 414         { .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat },
 415         {}
 416 };
 417 MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);
 418
 419 static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg)
 420 {
 421         return readw(i2c->base + i2c->dev_comp->regs[reg]);
 422 }
 423
 424 static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val,
 425                            enum I2C_REGS_OFFSET reg)
 426 {
 427         writew(val, i2c->base + i2c->dev_comp->regs[reg]);
 428 }
 429
 430 static int mtk_i2c_clock_enable(struct mtk_i2c *i2c)
 431 {
 432         int ret;
 433
 434         ret = clk_prepare_enable(i2c->clk_dma);
 435         if (ret)
 436                 return ret;
 437
 438         ret = clk_prepare_enable(i2c->clk_main);
 439         if (ret)
 440                 goto err_main;
 441
 442         if (i2c->have_pmic) {
 443                 ret = clk_prepare_enable(i2c->clk_pmic);
 444                 if (ret)
 445                         goto err_pmic;
 446         }
 447
 448         if (i2c->clk_arb) {
 449                 ret = clk_prepare_enable(i2c->clk_arb);
 450                 if (ret)
 451                         goto err_arb;
 452         }
 453
 454         return 0;
 455
 456 err_arb:
 457         if (i2c->have_pmic)
 458                 clk_disable_unprepare(i2c->clk_pmic);
 459 err_pmic:
 460         clk_disable_unprepare(i2c->clk_main);
 461 err_main:
 462         clk_disable_unprepare(i2c->clk_dma);
 463
 464         return ret;
 465 }
 466
 467 static void mtk_i2c_clock_disable(struct mtk_i2c *i2c)
 468 {
 469         if (i2c->clk_arb)
 470                 clk_disable_unprepare(i2c->clk_arb);
 471
 472         if (i2c->have_pmic)
 473                 clk_disable_unprepare(i2c->clk_pmic);
 474
 475         clk_disable_unprepare(i2c->clk_main);
 476         clk_disable_unprepare(i2c->clk_dma);
 477 }
 478
 479 static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
 480 {
 481         u16 control_reg;
 482         u16 intr_stat_reg;
 483
 484         mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_START);
 485         intr_stat_reg = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);
 486         mtk_i2c_writew(i2c, intr_stat_reg, OFFSET_INTR_STAT);
 487
 488         if (i2c->dev_comp->apdma_sync) {
 489                 writel(I2C_DMA_WARM_RST, i2c->pdmabase + OFFSET_RST);
 490                 udelay(10);
 491                 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
 492                 udelay(10);
 493                 writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_HARD_RST,
 494                        i2c->pdmabase + OFFSET_RST);
 495                 mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST | I2C_SOFT_RST,
 496                                OFFSET_SOFTRESET);
 497                 udelay(10);
 498                 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
 499                 mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET);
 500         } else {
 501                 writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
 502                 udelay(50);
 503                 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
 504                 mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET);
 505         }
 506
 507         /* Set ioconfig */
 508         if (i2c->use_push_pull)
 509                 mtk_i2c_writew(i2c, I2C_IO_CONFIG_PUSH_PULL, OFFSET_IO_CONFIG);
 510         else
 511                 mtk_i2c_writew(i2c, I2C_IO_CONFIG_OPEN_DRAIN, OFFSET_IO_CONFIG);
 512
 513         if (i2c->dev_comp->dcm)
 514                 mtk_i2c_writew(i2c, I2C_DCM_DISABLE, OFFSET_DCM_EN);
 515
 516         mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING);
 517         mtk_i2c_writew(i2c, i2c->high_speed_reg, OFFSET_HS);
 518         if (i2c->dev_comp->ltiming_adjust)
 519                 mtk_i2c_writew(i2c, i2c->ltiming_reg, OFFSET_LTIMING);
 520
 521         if (i2c->dev_comp->timing_adjust) {
 522                 mtk_i2c_writew(i2c, i2c->ac_timing.ext, OFFSET_EXT_CONF);
 523                 mtk_i2c_writew(i2c, i2c->ac_timing.inter_clk_div,
 524                                OFFSET_CLOCK_DIV);
 525                 mtk_i2c_writew(i2c, I2C_SCL_MIS_COMP_VALUE,
 526                                OFFSET_SCL_MIS_COMP_POINT);
 527                 mtk_i2c_writew(i2c, i2c->ac_timing.sda_timing,
 528                                OFFSET_SDA_TIMING);
 529
 530                 if (i2c->dev_comp->ltiming_adjust) {
 531                         mtk_i2c_writew(i2c, i2c->ac_timing.htiming,
 532                                        OFFSET_TIMING);
 533                         mtk_i2c_writew(i2c, i2c->ac_timing.hs, OFFSET_HS);
 534                         mtk_i2c_writew(i2c, i2c->ac_timing.ltiming,
 535                                        OFFSET_LTIMING);
 536                 } else {
 537                         mtk_i2c_writew(i2c, i2c->ac_timing.scl_hl_ratio,
 538                                        OFFSET_SCL_HIGH_LOW_RATIO);
 539                         mtk_i2c_writew(i2c, i2c->ac_timing.hs_scl_hl_ratio,
 540                                        OFFSET_HS_SCL_HIGH_LOW_RATIO);
 541                         mtk_i2c_writew(i2c, i2c->ac_timing.sta_stop,
 542                                        OFFSET_STA_STO_AC_TIMING);
 543                         mtk_i2c_writew(i2c, i2c->ac_timing.hs_sta_stop,
 544                                        OFFSET_HS_STA_STO_AC_TIMING);
 545                 }
 546         }
 547
 548         /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */
 549         if (i2c->have_pmic)
 550                 mtk_i2c_writew(i2c, I2C_CONTROL_WRAPPER, OFFSET_PATH_DIR);
 551
 552         control_reg = I2C_CONTROL_ACKERR_DET_EN |
 553                       I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN;
 554         if (i2c->dev_comp->dma_sync)
 555                 control_reg |= I2C_CONTROL_DMAACK_EN | I2C_CONTROL_ASYNC_MODE;
 556
 557         mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
 558         mtk_i2c_writew(i2c, I2C_DELAY_LEN, OFFSET_DELAY_LEN);
 559 }
 560
 561 static const struct i2c_spec_values *mtk_i2c_get_spec(unsigned int speed)
 562 {
 563         if (speed <= I2C_MAX_STANDARD_MODE_FREQ)
 564                 return &standard_mode_spec;
 565         else if (speed <= I2C_MAX_FAST_MODE_FREQ)
 566                 return &fast_mode_spec;
 567         else
 568                 return &fast_mode_plus_spec;
 569 }
 570
 571 static int mtk_i2c_max_step_cnt(unsigned int target_speed)
 572 {
 573         if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ)
 574                 return MAX_HS_STEP_CNT_DIV;
 575         else
 576                 return MAX_STEP_CNT_DIV;
 577 }
 578
 579 /*
 580  * Check and Calculate i2c ac-timing
 581  *
 582  * Hardware design:
 583  * sample_ns = (1000000000 * (sample_cnt + 1)) / clk_src
 584  * xxx_cnt_div =  spec->min_xxx_ns / sample_ns
 585  *
 586  * Sample_ns is rounded down for xxx_cnt_div would be greater
 587  * than the smallest spec.
 588  * The sda_timing is chosen as the middle value between
 589  * the largest and smallest.
 590  */
 591 static int mtk_i2c_check_ac_timing(struct mtk_i2c *i2c,
 592                                    unsigned int clk_src,
 593                                    unsigned int check_speed,
 594                                    unsigned int step_cnt,
 595                                    unsigned int sample_cnt)
 596 {
 597         const struct i2c_spec_values *spec;
 598         unsigned int su_sta_cnt, low_cnt, high_cnt, max_step_cnt;
 599         unsigned int sda_max, sda_min, clk_ns, max_sta_cnt = 0x3f;
 600         unsigned int sample_ns = div_u64(1000000000ULL * (sample_cnt + 1),
 601                                          clk_src);
 602
 603         if (!i2c->dev_comp->timing_adjust)
 604                 return 0;
 605
 606         if (i2c->dev_comp->ltiming_adjust)
 607                 max_sta_cnt = 0x100;
 608
 609         spec = mtk_i2c_get_spec(check_speed);
 610
 611         if (i2c->dev_comp->ltiming_adjust)
 612                 clk_ns = 1000000000 / clk_src;
 613         else
 614                 clk_ns = sample_ns / 2;
 615
 616         su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns +
 617                                   i2c->timing_info.scl_int_delay_ns, clk_ns);
 618         if (su_sta_cnt > max_sta_cnt)
 619                 return -1;
 620
 621         low_cnt = DIV_ROUND_UP(spec->min_low_ns, sample_ns);
 622         max_step_cnt = mtk_i2c_max_step_cnt(check_speed);
 623         if ((2 * step_cnt) > low_cnt && low_cnt < max_step_cnt) {
 624                 if (low_cnt > step_cnt) {
 625                         high_cnt = 2 * step_cnt - low_cnt;
 626                 } else {
 627                         high_cnt = step_cnt;
 628                         low_cnt = step_cnt;
 629                 }
 630         } else {
 631                 return -2;
 632         }
 633
 634         sda_max = spec->max_hd_dat_ns / sample_ns;
 635         if (sda_max > low_cnt)
 636                 sda_max = 0;
 637
 638         sda_min = DIV_ROUND_UP(spec->min_su_dat_ns, sample_ns);
 639         if (sda_min < low_cnt)
 640                 sda_min = 0;
 641
 642         if (sda_min > sda_max)
 643                 return -3;
 644
 645         if (check_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) {
 646                 if (i2c->dev_comp->ltiming_adjust) {
 647                         i2c->ac_timing.hs = I2C_TIME_DEFAULT_VALUE |
 648                                 (sample_cnt << 12) | (high_cnt << 8);
 649                         i2c->ac_timing.ltiming &= ~GENMASK(15, 9);
 650                         i2c->ac_timing.ltiming |= (sample_cnt << 12) |
 651                                 (low_cnt << 9);
 652                         i2c->ac_timing.ext &= ~GENMASK(7, 1);
 653                         i2c->ac_timing.ext |= (su_sta_cnt << 1) | (1 << 0);
 654                 } else {
 655                         i2c->ac_timing.hs_scl_hl_ratio = (1 << 12) |
 656                                 (high_cnt << 6) | low_cnt;
 657                         i2c->ac_timing.hs_sta_stop = (su_sta_cnt << 8) |
 658                                 su_sta_cnt;
 659                 }
 660                 i2c->ac_timing.sda_timing &= ~GENMASK(11, 6);
 661                 i2c->ac_timing.sda_timing |= (1 << 12) |
 662                         ((sda_max + sda_min) / 2) << 6;
 663         } else {
 664                 if (i2c->dev_comp->ltiming_adjust) {
 665                         i2c->ac_timing.htiming = (sample_cnt << 8) | (high_cnt);
 666                         i2c->ac_timing.ltiming = (sample_cnt << 6) | (low_cnt);
 667                         i2c->ac_timing.ext = (su_sta_cnt << 8) | (1 << 0);
 668                 } else {
 669                         i2c->ac_timing.scl_hl_ratio = (1 << 12) |
 670                                 (high_cnt << 6) | low_cnt;
 671                         i2c->ac_timing.sta_stop = (su_sta_cnt << 8) |
 672                                 su_sta_cnt;
 673                 }
 674
 675                 i2c->ac_timing.sda_timing = (1 << 12) |
 676                         (sda_max + sda_min) / 2;
 677         }
 678
 679         return 0;
 680 }
 681
 682 /*
 683  * Calculate i2c port speed
 684  *
 685  * Hardware design:
 686  * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt)
 687  * clock_div: fixed in hardware, but may be various in different SoCs
 688  *
 689  * The calculation want to pick the highest bus frequency that is still
 690  * less than or equal to i2c->speed_hz. The calculation try to get
 691  * sample_cnt and step_cn
 692  */
 693 static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src,
 694                                    unsigned int target_speed,
 695                                    unsigned int *timing_step_cnt,
 696                                    unsigned int *timing_sample_cnt)
 697 {
 698         unsigned int step_cnt;
 699         unsigned int sample_cnt;
 700         unsigned int max_step_cnt;
 701         unsigned int base_sample_cnt = MAX_SAMPLE_CNT_DIV;
 702         unsigned int base_step_cnt;
 703         unsigned int opt_div;
 704         unsigned int best_mul;
 705         unsigned int cnt_mul;
 706         int ret = -EINVAL;
 707
 708         if (target_speed > I2C_MAX_HIGH_SPEED_MODE_FREQ)
 709                 target_speed = I2C_MAX_HIGH_SPEED_MODE_FREQ;
 710
 711         max_step_cnt = mtk_i2c_max_step_cnt(target_speed);
 712         base_step_cnt = max_step_cnt;
 713         /* Find the best combination */
 714         opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed);
 715         best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt;
 716
 717         /* Search for the best pair (sample_cnt, step_cnt) with
 718          * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV
 719          * 0 < step_cnt < max_step_cnt
 720          * sample_cnt * step_cnt >= opt_div
 721          * optimizing for sample_cnt * step_cnt being minimal
 722          */
 723         for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) {
 724                 step_cnt = DIV_ROUND_UP(opt_div, sample_cnt);
 725                 cnt_mul = step_cnt * sample_cnt;
 726                 if (step_cnt > max_step_cnt)
 727                         continue;
 728
 729                 if (cnt_mul < best_mul) {
 730                         ret = mtk_i2c_check_ac_timing(i2c, clk_src,
 731                                 target_speed, step_cnt - 1, sample_cnt - 1);
 732                         if (ret)
 733                                 continue;
 734
 735                         best_mul = cnt_mul;
 736                         base_sample_cnt = sample_cnt;
 737                         base_step_cnt = step_cnt;
 738                         if (best_mul == opt_div)
 739                                 break;
 740                 }
 741         }
 742
 743         if (ret)
 744                 return -EINVAL;
 745
 746         sample_cnt = base_sample_cnt;
 747         step_cnt = base_step_cnt;
 748
 749         if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) {
 750                 /* In this case, hardware can't support such
 751                  * low i2c_bus_freq
 752                  */
 753                 dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n", target_speed);
 754                 return -EINVAL;
 755         }
 756
 757         *timing_step_cnt = step_cnt - 1;
 758         *timing_sample_cnt = sample_cnt - 1;
 759
 760         return 0;
 761 }
 762
 763 static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)
 764 {
 765         unsigned int clk_src;
 766         unsigned int step_cnt;
 767         unsigned int sample_cnt;
 768         unsigned int l_step_cnt;
 769         unsigned int l_sample_cnt;
 770         unsigned int target_speed;
 771         unsigned int clk_div;
 772         unsigned int max_clk_div;
 773         int ret;
 774
 775         target_speed = i2c->speed_hz;
 776         parent_clk /= i2c->clk_src_div;
 777
 778         if (i2c->dev_comp->timing_adjust)
 779                 max_clk_div = MAX_CLOCK_DIV;
 780         else
 781                 max_clk_div = 1;
 782
 783         for (clk_div = 1; clk_div <= max_clk_div; clk_div++) {
 784                 clk_src = parent_clk / clk_div;
 785
 786                 if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) {
 787                         /* Set master code speed register */
 788                         ret = mtk_i2c_calculate_speed(i2c, clk_src,
 789                                                       I2C_MAX_FAST_MODE_FREQ,
 790                                                       &l_step_cnt,
 791                                                       &l_sample_cnt);
 792                         if (ret < 0)
 793                                 continue;
 794
 795                         i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt;
 796
 797                         /* Set the high speed mode register */
 798                         ret = mtk_i2c_calculate_speed(i2c, clk_src,
 799                                                       target_speed, &step_cnt,
 800                                                       &sample_cnt);
 801                         if (ret < 0)
 802                                 continue;
 803
 804                         i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE |
 805                                         (sample_cnt << 12) | (step_cnt << 8);
 806
 807                         if (i2c->dev_comp->ltiming_adjust)
 808                                 i2c->ltiming_reg =
 809                                         (l_sample_cnt << 6) | l_step_cnt |
 810                                         (sample_cnt << 12) | (step_cnt << 9);
 811                 } else {
 812                         ret = mtk_i2c_calculate_speed(i2c, clk_src,
 813                                                       target_speed, &l_step_cnt,
 814                                                       &l_sample_cnt);
 815                         if (ret < 0)
 816                                 continue;
 817
 818                         i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt;
 819
 820                         /* Disable the high speed transaction */
 821                         i2c->high_speed_reg = I2C_TIME_CLR_VALUE;
 822
 823                         if (i2c->dev_comp->ltiming_adjust)
 824                                 i2c->ltiming_reg =
 825                                         (l_sample_cnt << 6) | l_step_cnt;
 826                 }
 827
 828                 break;
 829         }
 830
 831         i2c->ac_timing.inter_clk_div = clk_div - 1;
 832
 833         return 0;
 834 }
 835
 836 static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
 837                                int num, int left_num)
 838 {
 839         u16 addr_reg;
 840         u16 start_reg;
 841         u16 control_reg;
 842         u16 restart_flag = 0;
 843         u16 dma_sync = 0;
 844         u32 reg_4g_mode;
 845         u8 *dma_rd_buf = NULL;
 846         u8 *dma_wr_buf = NULL;
 847         dma_addr_t rpaddr = 0;
 848         dma_addr_t wpaddr = 0;
 849         int ret;
 850
 851         i2c->irq_stat = 0;
 852
 853         if (i2c->auto_restart)
 854                 restart_flag = I2C_RS_TRANSFER;
 855
 856         reinit_completion(&i2c->msg_complete);
 857
 858         control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) &
 859                         ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
 860         if ((i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) || (left_num >= 1))
 861                 control_reg |= I2C_CONTROL_RS;
 862
 863         if (i2c->op == I2C_MASTER_WRRD)
 864                 control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS;
 865
 866         mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
 867
 868         addr_reg = i2c_8bit_addr_from_msg(msgs);
 869         mtk_i2c_writew(i2c, addr_reg, OFFSET_SLAVE_ADDR);
 870
 871         /* Clear interrupt status */
 872         mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
 873                             I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_STAT);
 874
 875         mtk_i2c_writew(i2c, I2C_FIFO_ADDR_CLR, OFFSET_FIFO_ADDR_CLR);
 876
 877         /* Enable interrupt */
 878         mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
 879                             I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_MASK);
 880
 881         /* Set transfer and transaction len */
 882         if (i2c->op == I2C_MASTER_WRRD) {
 883                 if (i2c->dev_comp->aux_len_reg) {
 884                         mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN);
 885                         mtk_i2c_writew(i2c, (msgs + 1)->len,
 886                                             OFFSET_TRANSFER_LEN_AUX);
 887                 } else {
 888                         mtk_i2c_writew(i2c, msgs->len | ((msgs + 1)->len) << 8,
 889                                             OFFSET_TRANSFER_LEN);
 890                 }
 891                 mtk_i2c_writew(i2c, I2C_WRRD_TRANAC_VALUE, OFFSET_TRANSAC_LEN);
 892         } else {
 893                 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN);
 894                 mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN);
 895         }
 896
 897         if (i2c->dev_comp->apdma_sync) {
 898                 dma_sync = I2C_DMA_SKIP_CONFIG | I2C_DMA_ASYNC_MODE;
 899                 if (i2c->op == I2C_MASTER_WRRD)
 900                         dma_sync |= I2C_DMA_DIR_CHANGE;
 901         }
 902
 903         /* Prepare buffer data to start transfer */
 904         if (i2c->op == I2C_MASTER_RD) {
 905                 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
 906                 writel(I2C_DMA_CON_RX | dma_sync, i2c->pdmabase + OFFSET_CON);
 907
 908                 dma_rd_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
 909                 if (!dma_rd_buf)
 910                         return -ENOMEM;
 911
 912                 rpaddr = dma_map_single(i2c->dev, dma_rd_buf,
 913                                         msgs->len, DMA_FROM_DEVICE);
 914                 if (dma_mapping_error(i2c->dev, rpaddr)) {
 915                         i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, false);
 916
 917                         return -ENOMEM;
 918                 }
 919
 920                 if (i2c->dev_comp->max_dma_support > 32) {
 921                         reg_4g_mode = upper_32_bits(rpaddr);
 922                         writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
 923                 }
 924
 925                 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
 926                 writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN);
 927         } else if (i2c->op == I2C_MASTER_WR) {
 928                 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
 929                 writel(I2C_DMA_CON_TX | dma_sync, i2c->pdmabase + OFFSET_CON);
 930
 931                 dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
 932                 if (!dma_wr_buf)
 933                         return -ENOMEM;
 934
 935                 wpaddr = dma_map_single(i2c->dev, dma_wr_buf,
 936                                         msgs->len, DMA_TO_DEVICE);
 937                 if (dma_mapping_error(i2c->dev, wpaddr)) {
 938                         i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
 939
 940                         return -ENOMEM;
 941                 }
 942
 943                 if (i2c->dev_comp->max_dma_support > 32) {
 944                         reg_4g_mode = upper_32_bits(wpaddr);
 945                         writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
 946                 }
 947
 948                 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
 949                 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
 950         } else {
 951                 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG);
 952                 writel(I2C_DMA_CLR_FLAG | dma_sync, i2c->pdmabase + OFFSET_CON);
 953
 954                 dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
 955                 if (!dma_wr_buf)
 956                         return -ENOMEM;
 957
 958                 wpaddr = dma_map_single(i2c->dev, dma_wr_buf,
 959                                         msgs->len, DMA_TO_DEVICE);
 960                 if (dma_mapping_error(i2c->dev, wpaddr)) {
 961                         i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
 962
 963                         return -ENOMEM;
 964                 }
 965
 966                 dma_rd_buf = i2c_get_dma_safe_msg_buf((msgs + 1), 1);
 967                 if (!dma_rd_buf) {
 968                         dma_unmap_single(i2c->dev, wpaddr,
 969                                          msgs->len, DMA_TO_DEVICE);
 970
 971                         i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
 972
 973                         return -ENOMEM;
 974                 }
 975
 976                 rpaddr = dma_map_single(i2c->dev, dma_rd_buf,
 977                                         (msgs + 1)->len,
 978                                         DMA_FROM_DEVICE);
 979                 if (dma_mapping_error(i2c->dev, rpaddr)) {
 980                         dma_unmap_single(i2c->dev, wpaddr,
 981                                          msgs->len, DMA_TO_DEVICE);
 982
 983                         i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
 984                         i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), false);
 985
 986                         return -ENOMEM;
 987                 }
 988
 989                 if (i2c->dev_comp->max_dma_support > 32) {
 990                         reg_4g_mode = upper_32_bits(wpaddr);
 991                         writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
 992
 993                         reg_4g_mode = upper_32_bits(rpaddr);
 994                         writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
 995                 }
 996
 997                 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
 998                 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
 999                 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
1000                 writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN);
1001         }
1002
1003         writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN);
1004
1005         if (!i2c->auto_restart) {
1006                 start_reg = I2C_TRANSAC_START;
1007         } else {
1008                 start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG;
1009                 if (left_num >= 1)
1010                         start_reg |= I2C_RS_MUL_CNFG;
1011         }
1012         mtk_i2c_writew(i2c, start_reg, OFFSET_START);
1013
1014         ret = wait_for_completion_timeout(&i2c->msg_complete,
1015                                           i2c->adap.timeout);
1016
1017         /* Clear interrupt mask */
1018         mtk_i2c_writew(i2c, ~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
1019                             I2C_ARB_LOST | I2C_TRANSAC_COMP), OFFSET_INTR_MASK);
1020
1021         if (i2c->op == I2C_MASTER_WR) {
1022                 dma_unmap_single(i2c->dev, wpaddr,
1023                                  msgs->len, DMA_TO_DEVICE);
1024
1025                 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true);
1026         } else if (i2c->op == I2C_MASTER_RD) {
1027                 dma_unmap_single(i2c->dev, rpaddr,
1028                                  msgs->len, DMA_FROM_DEVICE);
1029
1030                 i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, true);
1031         } else {
1032                 dma_unmap_single(i2c->dev, wpaddr, msgs->len,
1033                                  DMA_TO_DEVICE);
1034                 dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len,
1035                                  DMA_FROM_DEVICE);
1036
1037                 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true);
1038                 i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), true);
1039         }
1040
1041         if (ret == 0) {
1042                 dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr);
1043                 mtk_i2c_init_hw(i2c);
1044                 return -ETIMEDOUT;
1045         }
1046
1047         if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) {
1048                 dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr);
1049                 mtk_i2c_init_hw(i2c);
1050                 return -ENXIO;
1051         }
1052
1053         return 0;
1054 }
1055
1056 static int mtk_i2c_transfer(struct i2c_adapter *adap,
1057                             struct i2c_msg msgs[], int num)
1058 {
1059         int ret;
1060         int left_num = num;
1061         struct mtk_i2c *i2c = i2c_get_adapdata(adap);
1062
1063         ret = mtk_i2c_clock_enable(i2c);
1064         if (ret)
1065                 return ret;
1066
1067         i2c->auto_restart = i2c->dev_comp->auto_restart;
1068
1069         /* checking if we can skip restart and optimize using WRRD mode */
1070         if (i2c->auto_restart && num == 2) {
1071                 if (!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD) &&
1072                     msgs[0].addr == msgs[1].addr) {
1073                         i2c->auto_restart = 0;
1074                 }
1075         }
1076
1077         if (i2c->auto_restart && num >= 2 &&
1078                 i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ)
1079                 /* ignore the first restart irq after the master code,
1080                  * otherwise the first transfer will be discarded.
1081                  */
1082                 i2c->ignore_restart_irq = true;
1083         else
1084                 i2c->ignore_restart_irq = false;
1085
1086         while (left_num--) {
1087                 if (!msgs->buf) {
1088                         dev_dbg(i2c->dev, "data buffer is NULL.\n");
1089                         ret = -EINVAL;
1090                         goto err_exit;
1091                 }
1092
1093                 if (msgs->flags & I2C_M_RD)
1094                         i2c->op = I2C_MASTER_RD;
1095                 else
1096                         i2c->op = I2C_MASTER_WR;
1097
1098                 if (!i2c->auto_restart) {
1099                         if (num > 1) {
1100                                 /* combined two messages into one transaction */
1101                                 i2c->op = I2C_MASTER_WRRD;
1102                                 left_num--;
1103                         }
1104                 }
1105
1106                 /* always use DMA mode. */
1107                 ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num);
1108                 if (ret < 0)
1109                         goto err_exit;
1110
1111                 msgs++;
1112         }
1113         /* the return value is number of executed messages */
1114         ret = num;
1115
1116 err_exit:
1117         mtk_i2c_clock_disable(i2c);
1118         return ret;
1119 }
1120
1121 static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id)
1122 {
1123         struct mtk_i2c *i2c = dev_id;
1124         u16 restart_flag = 0;
1125         u16 intr_stat;
1126
1127         if (i2c->auto_restart)
1128                 restart_flag = I2C_RS_TRANSFER;
1129
1130         intr_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);
1131         mtk_i2c_writew(i2c, intr_stat, OFFSET_INTR_STAT);
1132
1133         /*
1134          * when occurs ack error, i2c controller generate two interrupts
1135          * first is the ack error interrupt, then the complete interrupt
1136          * i2c->irq_stat need keep the two interrupt value.
1137          */
1138         i2c->irq_stat |= intr_stat;
1139
1140         if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) {
1141                 i2c->ignore_restart_irq = false;
1142                 i2c->irq_stat = 0;
1143                 mtk_i2c_writew(i2c, I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG |
1144                                     I2C_TRANSAC_START, OFFSET_START);
1145         } else {
1146                 if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag))
1147                         complete(&i2c->msg_complete);
1148         }
1149
1150         return IRQ_HANDLED;
1151 }
1152
1153 static u32 mtk_i2c_functionality(struct i2c_adapter *adap)
1154 {
1155         if (i2c_check_quirks(adap, I2C_AQ_NO_ZERO_LEN))
1156                 return I2C_FUNC_I2C |
1157                         (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
1158         else
1159                 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1160 }
1161
1162 static const struct i2c_algorithm mtk_i2c_algorithm = {
1163         .master_xfer = mtk_i2c_transfer,
1164         .functionality = mtk_i2c_functionality,
1165 };
1166
1167 static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c)
1168 {
1169         int ret;
1170
1171         ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz);
1172         if (ret < 0)
1173                 i2c->speed_hz = I2C_MAX_STANDARD_MODE_FREQ;
1174
1175         ret = of_property_read_u32(np, "clock-div", &i2c->clk_src_div);
1176         if (ret < 0)
1177                 return ret;
1178
1179         if (i2c->clk_src_div == 0)
1180                 return -EINVAL;
1181
1182         i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic");
1183         i2c->use_push_pull =
1184                 of_property_read_bool(np, "mediatek,use-push-pull");
1185
1186         i2c_parse_fw_timings(i2c->dev, &i2c->timing_info, true);
1187
1188         return 0;
1189 }
1190
1191 static int mtk_i2c_probe(struct platform_device *pdev)
1192 {
1193         int ret = 0;
1194         struct mtk_i2c *i2c;
1195         struct clk *clk;
1196         struct resource *res;
1197         int irq;
1198
1199         i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
1200         if (!i2c)
1201                 return -ENOMEM;
1202
1203         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1204         i2c->base = devm_ioremap_resource(&pdev->dev, res);
1205         if (IS_ERR(i2c->base))
1206                 return PTR_ERR(i2c->base);
1207
1208         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1209         i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res);
1210         if (IS_ERR(i2c->pdmabase))
1211                 return PTR_ERR(i2c->pdmabase);
1212
1213         irq = platform_get_irq(pdev, 0);
1214         if (irq <= 0)
1215                 return irq;
1216
1217         init_completion(&i2c->msg_complete);
1218
1219         i2c->dev_comp = of_device_get_match_data(&pdev->dev);
1220         i2c->adap.dev.of_node = pdev->dev.of_node;
1221         i2c->dev = &pdev->dev;
1222         i2c->adap.dev.parent = &pdev->dev;
1223         i2c->adap.owner = THIS_MODULE;
1224         i2c->adap.algo = &mtk_i2c_algorithm;
1225         i2c->adap.quirks = i2c->dev_comp->quirks;
1226         i2c->adap.timeout = 2 * HZ;
1227         i2c->adap.retries = 1;
1228
1229         ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c);
1230         if (ret)
1231                 return -EINVAL;
1232
1233         if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c)
1234                 return -EINVAL;
1235
1236         i2c->clk_main = devm_clk_get(&pdev->dev, "main");
1237         if (IS_ERR(i2c->clk_main)) {
1238                 dev_err(&pdev->dev, "cannot get main clock\n");
1239                 return PTR_ERR(i2c->clk_main);
1240         }
1241
1242         i2c->clk_dma = devm_clk_get(&pdev->dev, "dma");
1243         if (IS_ERR(i2c->clk_dma)) {
1244                 dev_err(&pdev->dev, "cannot get dma clock\n");
1245                 return PTR_ERR(i2c->clk_dma);
1246         }
1247
1248         i2c->clk_arb = devm_clk_get(&pdev->dev, "arb");
1249         if (IS_ERR(i2c->clk_arb))
1250                 i2c->clk_arb = NULL;
1251
1252         clk = i2c->clk_main;
1253         if (i2c->have_pmic) {
1254                 i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic");
1255                 if (IS_ERR(i2c->clk_pmic)) {
1256                         dev_err(&pdev->dev, "cannot get pmic clock\n");
1257                         return PTR_ERR(i2c->clk_pmic);
1258                 }
1259                 clk = i2c->clk_pmic;
1260         }
1261
1262         strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name));
1263
1264         ret = mtk_i2c_set_speed(i2c, clk_get_rate(clk));
1265         if (ret) {
1266                 dev_err(&pdev->dev, "Failed to set the speed.\n");
1267                 return -EINVAL;
1268         }
1269
1270         if (i2c->dev_comp->max_dma_support > 32) {
1271                 ret = dma_set_mask(&pdev->dev,
1272                                 DMA_BIT_MASK(i2c->dev_comp->max_dma_support));
1273                 if (ret) {
1274                         dev_err(&pdev->dev, "dma_set_mask return error.\n");
1275                         return ret;
1276                 }
1277         }
1278
1279         ret = mtk_i2c_clock_enable(i2c);
1280         if (ret) {
1281                 dev_err(&pdev->dev, "clock enable failed!\n");
1282                 return ret;
1283         }
1284         mtk_i2c_init_hw(i2c);
1285         mtk_i2c_clock_disable(i2c);
1286
1287         ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq,
1288                                IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE,
1289                                I2C_DRV_NAME, i2c);
1290         if (ret < 0) {
1291                 dev_err(&pdev->dev,
1292                         "Request I2C IRQ %d fail\n", irq);
1293                 return ret;
1294         }
1295
1296         i2c_set_adapdata(&i2c->adap, i2c);
1297         ret = i2c_add_adapter(&i2c->adap);
1298         if (ret)
1299                 return ret;
1300
1301         platform_set_drvdata(pdev, i2c);
1302
1303         return 0;
1304 }
1305
1306 static int mtk_i2c_remove(struct platform_device *pdev)
1307 {
1308         struct mtk_i2c *i2c = platform_get_drvdata(pdev);
1309
1310         i2c_del_adapter(&i2c->adap);
1311
1312         return 0;
1313 }
1314
1315 #ifdef CONFIG_PM_SLEEP
1316 static int mtk_i2c_suspend_noirq(struct device *dev)
1317 {
1318         struct mtk_i2c *i2c = dev_get_drvdata(dev);
1319
1320         i2c_mark_adapter_suspended(&i2c->adap);
1321
1322         return 0;
1323 }
1324
1325 static int mtk_i2c_resume_noirq(struct device *dev)
1326 {
1327         int ret;
1328         struct mtk_i2c *i2c = dev_get_drvdata(dev);
1329
1330         ret = mtk_i2c_clock_enable(i2c);
1331         if (ret) {
1332                 dev_err(dev, "clock enable failed!\n");
1333                 return ret;
1334         }
1335
1336         mtk_i2c_init_hw(i2c);
1337
1338         mtk_i2c_clock_disable(i2c);
1339
1340         i2c_mark_adapter_resumed(&i2c->adap);
1341
1342         return 0;
1343 }
1344 #endif
1345
1346 static const struct dev_pm_ops mtk_i2c_pm = {
1347         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_i2c_suspend_noirq,
1348                                       mtk_i2c_resume_noirq)
1349 };
1350
1351 static struct platform_driver mtk_i2c_driver = {
1352         .probe = mtk_i2c_probe,
1353         .remove = mtk_i2c_remove,
1354         .driver = {
1355                 .name = I2C_DRV_NAME,
1356                 .pm = &mtk_i2c_pm,
1357                 .of_match_table = of_match_ptr(mtk_i2c_of_match),
1358         },
1359 };
1360
1361 module_platform_driver(mtk_i2c_driver);
1362
1363 MODULE_LICENSE("GPL v2");
1364 MODULE_DESCRIPTION("MediaTek I2C Bus Driver");
1365 MODULE_AUTHOR("Xudong Chen <xudong.chen@mediatek.com>");