drivers/i2c/busses/i2c-mpc.c

   1 /*
   2  * (C) Copyright 2003-2004
   3  * Humboldt Solutions Ltd, adrian@humboldt.co.uk.
   4
   5  * This is a combined i2c adapter and algorithm driver for the
   6  * MPC107/Tsi107 PowerPC northbridge and processors that include
   7  * the same I2C unit (8240, 8245, 85xx).
   8  *
   9  * Release 0.8
  10  *
  11  * This file is licensed under the terms of the GNU General Public
  12  * License version 2. This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/sched/signal.h>
  19 #include <linux/of_address.h>
  20 #include <linux/of_irq.h>
  21 #include <linux/of_platform.h>
  22 #include <linux/slab.h>
  23
  24 #include <linux/clk.h>
  25 #include <linux/io.h>
  26 #include <linux/fsl_devices.h>
  27 #include <linux/i2c.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/delay.h>
  30
  31 #include <asm/mpc52xx.h>
  32 #include <asm/mpc85xx.h>
  33 #include <sysdev/fsl_soc.h>
  34
  35 #define DRV_NAME "mpc-i2c"
  36
  37 #define MPC_I2C_CLOCK_LEGACY   0
  38 #define MPC_I2C_CLOCK_PRESERVE (~0U)
  39
  40 #define MPC_I2C_FDR   0x04
  41 #define MPC_I2C_CR    0x08
  42 #define MPC_I2C_SR    0x0c
  43 #define MPC_I2C_DR    0x10
  44 #define MPC_I2C_DFSRR 0x14
  45
  46 #define CCR_MEN  0x80
  47 #define CCR_MIEN 0x40
  48 #define CCR_MSTA 0x20
  49 #define CCR_MTX  0x10
  50 #define CCR_TXAK 0x08
  51 #define CCR_RSTA 0x04
  52
  53 #define CSR_MCF  0x80
  54 #define CSR_MAAS 0x40
  55 #define CSR_MBB  0x20
  56 #define CSR_MAL  0x10
  57 #define CSR_SRW  0x04
  58 #define CSR_MIF  0x02
  59 #define CSR_RXAK 0x01
  60
  61 struct mpc_i2c {
  62         struct device *dev;
  63         void __iomem *base;
  64         u32 interrupt;
  65         wait_queue_head_t queue;
  66         struct i2c_adapter adap;
  67         int irq;
  68         u32 real_clk;
  69 #ifdef CONFIG_PM_SLEEP
  70         u8 fdr, dfsrr;
  71 #endif
  72         struct clk *clk_per;
  73 };
  74
  75 struct mpc_i2c_divider {
  76         u16 divider;
  77         u16 fdr;        /* including dfsrr */
  78 };
  79
  80 struct mpc_i2c_data {
  81         void (*setup)(struct device_node *node, struct mpc_i2c *i2c,
  82                       u32 clock, u32 prescaler);
  83         u32 prescaler;
  84 };
  85
  86 static inline void writeccr(struct mpc_i2c *i2c, u32 x)
  87 {
  88         writeb(x, i2c->base + MPC_I2C_CR);
  89 }
  90
  91 static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
  92 {
  93         struct mpc_i2c *i2c = dev_id;
  94         if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) {
  95                 /* Read again to allow register to stabilise */
  96                 i2c->interrupt = readb(i2c->base + MPC_I2C_SR);
  97                 writeb(0, i2c->base + MPC_I2C_SR);
  98                 wake_up(&i2c->queue);
  99                 return IRQ_HANDLED;
 100         }
 101         return IRQ_NONE;
 102 }
 103
 104 /* Sometimes 9th clock pulse isn't generated, and slave doesn't release
 105  * the bus, because it wants to send ACK.
 106  * Following sequence of enabling/disabling and sending start/stop generates
 107  * the 9 pulses, so it's all OK.
 108  */
 109 static void mpc_i2c_fixup(struct mpc_i2c *i2c)
 110 {
 111         int k;
 112         u32 delay_val = 1000000 / i2c->real_clk + 1;
 113
 114         if (delay_val < 2)
 115                 delay_val = 2;
 116
 117         for (k = 9; k; k--) {
 118                 writeccr(i2c, 0);
 119                 writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN);
 120                 readb(i2c->base + MPC_I2C_DR);
 121                 writeccr(i2c, CCR_MEN);
 122                 udelay(delay_val << 1);
 123         }
 124 }
 125
 126 static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
 127 {
 128         unsigned long orig_jiffies = jiffies;
 129         u32 cmd_err;
 130         int result = 0;
 131
 132         if (!i2c->irq) {
 133                 while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) {
 134                         schedule();
 135                         if (time_after(jiffies, orig_jiffies + timeout)) {
 136                                 dev_dbg(i2c->dev, "timeout\n");
 137                                 writeccr(i2c, 0);
 138                                 result = -ETIMEDOUT;
 139                                 break;
 140                         }
 141                 }
 142                 cmd_err = readb(i2c->base + MPC_I2C_SR);
 143                 writeb(0, i2c->base + MPC_I2C_SR);
 144         } else {
 145                 /* Interrupt mode */
 146                 result = wait_event_timeout(i2c->queue,
 147                         (i2c->interrupt & CSR_MIF), timeout);
 148
 149                 if (unlikely(!(i2c->interrupt & CSR_MIF))) {
 150                         dev_dbg(i2c->dev, "wait timeout\n");
 151                         writeccr(i2c, 0);
 152                         result = -ETIMEDOUT;
 153                 }
 154
 155                 cmd_err = i2c->interrupt;
 156                 i2c->interrupt = 0;
 157         }
 158
 159         if (result < 0)
 160                 return result;
 161
 162         if (!(cmd_err & CSR_MCF)) {
 163                 dev_dbg(i2c->dev, "unfinished\n");
 164                 return -EIO;
 165         }
 166
 167         if (cmd_err & CSR_MAL) {
 168                 dev_dbg(i2c->dev, "MAL\n");
 169                 return -EAGAIN;
 170         }
 171
 172         if (writing && (cmd_err & CSR_RXAK)) {
 173                 dev_dbg(i2c->dev, "No RXAK\n");
 174                 /* generate stop */
 175                 writeccr(i2c, CCR_MEN);
 176                 return -ENXIO;
 177         }
 178         return 0;
 179 }
 180
 181 #if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x)
 182 static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
 183         {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
 184         {28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
 185         {36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28},
 186         {52, 0x63}, {56, 0x29}, {60, 0x41}, {64, 0x2a},
 187         {68, 0x07}, {72, 0x2b}, {80, 0x2c}, {88, 0x09},
 188         {96, 0x2d}, {104, 0x0a}, {112, 0x2e}, {120, 0x81},
 189         {128, 0x2f}, {136, 0x47}, {144, 0x0c}, {160, 0x30},
 190         {176, 0x49}, {192, 0x31}, {208, 0x4a}, {224, 0x32},
 191         {240, 0x0f}, {256, 0x33}, {272, 0x87}, {288, 0x10},
 192         {320, 0x34}, {352, 0x89}, {384, 0x35}, {416, 0x8a},
 193         {448, 0x36}, {480, 0x13}, {512, 0x37}, {576, 0x14},
 194         {640, 0x38}, {768, 0x39}, {896, 0x3a}, {960, 0x17},
 195         {1024, 0x3b}, {1152, 0x18}, {1280, 0x3c}, {1536, 0x3d},
 196         {1792, 0x3e}, {1920, 0x1b}, {2048, 0x3f}, {2304, 0x1c},
 197         {2560, 0x1d}, {3072, 0x1e}, {3584, 0x7e}, {3840, 0x1f},
 198         {4096, 0x7f}, {4608, 0x5c}, {5120, 0x5d}, {6144, 0x5e},
 199         {7168, 0xbe}, {7680, 0x5f}, {8192, 0xbf}, {9216, 0x9c},
 200         {10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f}
 201 };
 202
 203 static int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock,
 204                                           int prescaler, u32 *real_clk)
 205 {
 206         const struct mpc_i2c_divider *div = NULL;
 207         unsigned int pvr = mfspr(SPRN_PVR);
 208         u32 divider;
 209         int i;
 210
 211         if (clock == MPC_I2C_CLOCK_LEGACY) {
 212                 /* see below - default fdr = 0x3f -> div = 2048 */
 213                 *real_clk = mpc5xxx_get_bus_frequency(node) / 2048;
 214                 return -EINVAL;
 215         }
 216
 217         /* Determine divider value */
 218         divider = mpc5xxx_get_bus_frequency(node) / clock;
 219
 220         /*
 221          * We want to choose an FDR/DFSR that generates an I2C bus speed that
 222          * is equal to or lower than the requested speed.
 223          */
 224         for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_52xx); i++) {
 225                 div = &mpc_i2c_dividers_52xx[i];
 226                 /* Old MPC5200 rev A CPUs do not support the high bits */
 227                 if (div->fdr & 0xc0 && pvr == 0x80822011)
 228                         continue;
 229                 if (div->divider >= divider)
 230                         break;
 231         }
 232
 233         *real_clk = mpc5xxx_get_bus_frequency(node) / div->divider;
 234         return (int)div->fdr;
 235 }
 236
 237 static void mpc_i2c_setup_52xx(struct device_node *node,
 238                                          struct mpc_i2c *i2c,
 239                                          u32 clock, u32 prescaler)
 240 {
 241         int ret, fdr;
 242
 243         if (clock == MPC_I2C_CLOCK_PRESERVE) {
 244                 dev_dbg(i2c->dev, "using fdr %d\n",
 245                         readb(i2c->base + MPC_I2C_FDR));
 246                 return;
 247         }
 248
 249         ret = mpc_i2c_get_fdr_52xx(node, clock, prescaler, &i2c->real_clk);
 250         fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */
 251
 252         writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
 253
 254         if (ret >= 0)
 255                 dev_info(i2c->dev, "clock %u Hz (fdr=%d)\n", i2c->real_clk,
 256                          fdr);
 257 }
 258 #else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */
 259 static void mpc_i2c_setup_52xx(struct device_node *node,
 260                                          struct mpc_i2c *i2c,
 261                                          u32 clock, u32 prescaler)
 262 {
 263 }
 264 #endif /* CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x */
 265
 266 #ifdef CONFIG_PPC_MPC512x
 267 static void mpc_i2c_setup_512x(struct device_node *node,
 268                                          struct mpc_i2c *i2c,
 269                                          u32 clock, u32 prescaler)
 270 {
 271         struct device_node *node_ctrl;
 272         void __iomem *ctrl;
 273         const u32 *pval;
 274         u32 idx;
 275
 276         /* Enable I2C interrupts for mpc5121 */
 277         node_ctrl = of_find_compatible_node(NULL, NULL,
 278                                             "fsl,mpc5121-i2c-ctrl");
 279         if (node_ctrl) {
 280                 ctrl = of_iomap(node_ctrl, 0);
 281                 if (ctrl) {
 282                         /* Interrupt enable bits for i2c-0/1/2: bit 24/26/28 */
 283                         pval = of_get_property(node, "reg", NULL);
 284                         idx = (*pval & 0xff) / 0x20;
 285                         setbits32(ctrl, 1 << (24 + idx * 2));
 286                         iounmap(ctrl);
 287                 }
 288                 of_node_put(node_ctrl);
 289         }
 290
 291         /* The clock setup for the 52xx works also fine for the 512x */
 292         mpc_i2c_setup_52xx(node, i2c, clock, prescaler);
 293 }
 294 #else /* CONFIG_PPC_MPC512x */
 295 static void mpc_i2c_setup_512x(struct device_node *node,
 296                                          struct mpc_i2c *i2c,
 297                                          u32 clock, u32 prescaler)
 298 {
 299 }
 300 #endif /* CONFIG_PPC_MPC512x */
 301
 302 #ifdef CONFIG_FSL_SOC
 303 static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = {
 304         {160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123},
 305         {288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102},
 306         {416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127},
 307         {544, 0x0b03}, {576, 0x0104}, {608, 0x1603}, {640, 0x0105},
 308         {672, 0x2003}, {704, 0x0b05}, {736, 0x2b03}, {768, 0x0106},
 309         {800, 0x3603}, {832, 0x0b06}, {896, 0x012a}, {960, 0x0107},
 310         {1024, 0x012b}, {1088, 0x1607}, {1152, 0x0108}, {1216, 0x2b07},
 311         {1280, 0x0109}, {1408, 0x1609}, {1536, 0x010a}, {1664, 0x160a},
 312         {1792, 0x012e}, {1920, 0x010b}, {2048, 0x012f}, {2176, 0x2b0b},
 313         {2304, 0x010c}, {2560, 0x010d}, {2816, 0x2b0d}, {3072, 0x010e},
 314         {3328, 0x2b0e}, {3584, 0x0132}, {3840, 0x010f}, {4096, 0x0133},
 315         {4608, 0x0110}, {5120, 0x0111}, {6144, 0x0112}, {7168, 0x0136},
 316         {7680, 0x0113}, {8192, 0x0137}, {9216, 0x0114}, {10240, 0x0115},
 317         {12288, 0x0116}, {14336, 0x013a}, {15360, 0x0117}, {16384, 0x013b},
 318         {18432, 0x0118}, {20480, 0x0119}, {24576, 0x011a}, {28672, 0x013e},
 319         {30720, 0x011b}, {32768, 0x013f}, {36864, 0x011c}, {40960, 0x011d},
 320         {49152, 0x011e}, {61440, 0x011f}
 321 };
 322
 323 static u32 mpc_i2c_get_sec_cfg_8xxx(void)
 324 {
 325         struct device_node *node;
 326         u32 __iomem *reg;
 327         u32 val = 0;
 328
 329         node = of_find_node_by_name(NULL, "global-utilities");
 330         if (node) {
 331                 const u32 *prop = of_get_property(node, "reg", NULL);
 332                 if (prop) {
 333                         /*
 334                          * Map and check POR Device Status Register 2
 335                          * (PORDEVSR2) at 0xE0014. Note than while MPC8533
 336                          * and MPC8544 indicate SEC frequency ratio
 337                          * configuration as bit 26 in PORDEVSR2, other MPC8xxx
 338                          * parts may store it differently or may not have it
 339                          * at all.
 340                          */
 341                         reg = ioremap(get_immrbase() + *prop + 0x14, 0x4);
 342                         if (!reg)
 343                                 printk(KERN_ERR
 344                                        "Error: couldn't map PORDEVSR2\n");
 345                         else
 346                                 val = in_be32(reg) & 0x00000020; /* sec-cfg */
 347                         iounmap(reg);
 348                 }
 349         }
 350         of_node_put(node);
 351
 352         return val;
 353 }
 354
 355 static u32 mpc_i2c_get_prescaler_8xxx(void)
 356 {
 357         /*
 358          * According to the AN2919 all MPC824x have prescaler 1, while MPC83xx
 359          * may have prescaler 1, 2, or 3, depending on the power-on
 360          * configuration.
 361          */
 362         u32 prescaler = 1;
 363
 364         /* mpc85xx */
 365         if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2)
 366                 || pvr_version_is(PVR_VER_E500MC)
 367                 || pvr_version_is(PVR_VER_E5500)
 368                 || pvr_version_is(PVR_VER_E6500)) {
 369                 unsigned int svr = mfspr(SPRN_SVR);
 370
 371                 if ((SVR_SOC_VER(svr) == SVR_8540)
 372                         || (SVR_SOC_VER(svr) == SVR_8541)
 373                         || (SVR_SOC_VER(svr) == SVR_8560)
 374                         || (SVR_SOC_VER(svr) == SVR_8555)
 375                         || (SVR_SOC_VER(svr) == SVR_8610))
 376                         /* the above 85xx SoCs have prescaler 1 */
 377                         prescaler = 1;
 378                 else if ((SVR_SOC_VER(svr) == SVR_8533)
 379                         || (SVR_SOC_VER(svr) == SVR_8544))
 380                         /* the above 85xx SoCs have prescaler 3 or 2 */
 381                         prescaler = mpc_i2c_get_sec_cfg_8xxx() ? 3 : 2;
 382                 else
 383                         /* all the other 85xx have prescaler 2 */
 384                         prescaler = 2;
 385         }
 386
 387         return prescaler;
 388 }
 389
 390 static int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock,
 391                                           u32 prescaler, u32 *real_clk)
 392 {
 393         const struct mpc_i2c_divider *div = NULL;
 394         u32 divider;
 395         int i;
 396
 397         /* Determine proper divider value */
 398         if (!prescaler)
 399                 prescaler = mpc_i2c_get_prescaler_8xxx();
 400
 401         if (clock == MPC_I2C_CLOCK_LEGACY) {
 402                 /* see below - default fdr = 0x1031 -> div = 16 * 3072 */
 403                 *real_clk = fsl_get_sys_freq() / prescaler / (16 * 3072);
 404                 return -EINVAL;
 405         }
 406
 407         divider = fsl_get_sys_freq() / clock / prescaler;
 408
 409         pr_debug("I2C: src_clock=%d clock=%d divider=%d\n",
 410                  fsl_get_sys_freq(), clock, divider);
 411
 412         /*
 413          * We want to choose an FDR/DFSR that generates an I2C bus speed that
 414          * is equal to or lower than the requested speed.
 415          */
 416         for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_8xxx); i++) {
 417                 div = &mpc_i2c_dividers_8xxx[i];
 418                 if (div->divider >= divider)
 419                         break;
 420         }
 421
 422         *real_clk = fsl_get_sys_freq() / prescaler / div->divider;
 423         return div ? (int)div->fdr : -EINVAL;
 424 }
 425
 426 static void mpc_i2c_setup_8xxx(struct device_node *node,
 427                                          struct mpc_i2c *i2c,
 428                                          u32 clock, u32 prescaler)
 429 {
 430         int ret, fdr;
 431
 432         if (clock == MPC_I2C_CLOCK_PRESERVE) {
 433                 dev_dbg(i2c->dev, "using dfsrr %d, fdr %d\n",
 434                         readb(i2c->base + MPC_I2C_DFSRR),
 435                         readb(i2c->base + MPC_I2C_FDR));
 436                 return;
 437         }
 438
 439         ret = mpc_i2c_get_fdr_8xxx(node, clock, prescaler, &i2c->real_clk);
 440         fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */
 441
 442         writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
 443         writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR);
 444
 445         if (ret >= 0)
 446                 dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n",
 447                          i2c->real_clk, fdr >> 8, fdr & 0xff);
 448 }
 449
 450 #else /* !CONFIG_FSL_SOC */
 451 static void mpc_i2c_setup_8xxx(struct device_node *node,
 452                                          struct mpc_i2c *i2c,
 453                                          u32 clock, u32 prescaler)
 454 {
 455 }
 456 #endif /* CONFIG_FSL_SOC */
 457
 458 static void mpc_i2c_start(struct mpc_i2c *i2c)
 459 {
 460         /* Clear arbitration */
 461         writeb(0, i2c->base + MPC_I2C_SR);
 462         /* Start with MEN */
 463         writeccr(i2c, CCR_MEN);
 464 }
 465
 466 static void mpc_i2c_stop(struct mpc_i2c *i2c)
 467 {
 468         writeccr(i2c, CCR_MEN);
 469 }
 470
 471 static int mpc_write(struct mpc_i2c *i2c, int target,
 472                      const u8 *data, int length, int restart)
 473 {
 474         int i, result;
 475         unsigned timeout = i2c->adap.timeout;
 476         u32 flags = restart ? CCR_RSTA : 0;
 477
 478         /* Start as master */
 479         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
 480         /* Write target byte */
 481         writeb((target << 1), i2c->base + MPC_I2C_DR);
 482
 483         result = i2c_wait(i2c, timeout, 1);
 484         if (result < 0)
 485                 return result;
 486
 487         for (i = 0; i < length; i++) {
 488                 /* Write data byte */
 489                 writeb(data[i], i2c->base + MPC_I2C_DR);
 490
 491                 result = i2c_wait(i2c, timeout, 1);
 492                 if (result < 0)
 493                         return result;
 494         }
 495
 496         return 0;
 497 }
 498
 499 static int mpc_read(struct mpc_i2c *i2c, int target,
 500                     u8 *data, int length, int restart, bool recv_len)
 501 {
 502         unsigned timeout = i2c->adap.timeout;
 503         int i, result;
 504         u32 flags = restart ? CCR_RSTA : 0;
 505
 506         /* Switch to read - restart */
 507         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
 508         /* Write target address byte - this time with the read flag set */
 509         writeb((target << 1) | 1, i2c->base + MPC_I2C_DR);
 510
 511         result = i2c_wait(i2c, timeout, 1);
 512         if (result < 0)
 513                 return result;
 514
 515         if (length) {
 516                 if (length == 1 && !recv_len)
 517                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
 518                 else
 519                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA);
 520                 /* Dummy read */
 521                 readb(i2c->base + MPC_I2C_DR);
 522         }
 523
 524         for (i = 0; i < length; i++) {
 525                 u8 byte;
 526
 527                 result = i2c_wait(i2c, timeout, 0);
 528                 if (result < 0)
 529                         return result;
 530
 531                 /*
 532                  * For block reads, we have to know the total length (1st byte)
 533                  * before we can determine if we are done.
 534                  */
 535                 if (i || !recv_len) {
 536                         /* Generate txack on next to last byte */
 537                         if (i == length - 2)
 538                                 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
 539                                          | CCR_TXAK);
 540                         /* Do not generate stop on last byte */
 541                         if (i == length - 1)
 542                                 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
 543                                          | CCR_MTX);
 544                 }
 545
 546                 byte = readb(i2c->base + MPC_I2C_DR);
 547
 548                 /*
 549                  * Adjust length if first received byte is length.
 550                  * The length is 1 length byte plus actually data length
 551                  */
 552                 if (i == 0 && recv_len) {
 553                         if (byte == 0 || byte > I2C_SMBUS_BLOCK_MAX)
 554                                 return -EPROTO;
 555                         length += byte;
 556                         /*
 557                          * For block reads, generate txack here if data length
 558                          * is 1 byte (total length is 2 bytes).
 559                          */
 560                         if (length == 2)
 561                                 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
 562                                          | CCR_TXAK);
 563                 }
 564                 data[i] = byte;
 565         }
 566
 567         return length;
 568 }
 569
 570 static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
 571 {
 572         struct i2c_msg *pmsg;
 573         int i;
 574         int ret = 0;
 575         unsigned long orig_jiffies = jiffies;
 576         struct mpc_i2c *i2c = i2c_get_adapdata(adap);
 577
 578         mpc_i2c_start(i2c);
 579
 580         /* Allow bus up to 1s to become not busy */
 581         while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
 582                 if (signal_pending(current)) {
 583                         dev_dbg(i2c->dev, "Interrupted\n");
 584                         writeccr(i2c, 0);
 585                         return -EINTR;
 586                 }
 587                 if (time_after(jiffies, orig_jiffies + HZ)) {
 588                         u8 status = readb(i2c->base + MPC_I2C_SR);
 589
 590                         dev_dbg(i2c->dev, "timeout\n");
 591                         if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {
 592                                 writeb(status & ~CSR_MAL,
 593                                        i2c->base + MPC_I2C_SR);
 594                                 mpc_i2c_fixup(i2c);
 595                         }
 596                         return -EIO;
 597                 }
 598                 schedule();
 599         }
 600
 601         for (i = 0; ret >= 0 && i < num; i++) {
 602                 pmsg = &msgs[i];
 603                 dev_dbg(i2c->dev,
 604                         "Doing %s %d bytes to 0x%02x - %d of %d messages\n",
 605                         pmsg->flags & I2C_M_RD ? "read" : "write",
 606                         pmsg->len, pmsg->addr, i + 1, num);
 607                 if (pmsg->flags & I2C_M_RD) {
 608                         bool recv_len = pmsg->flags & I2C_M_RECV_LEN;
 609
 610                         ret = mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i,
 611                                        recv_len);
 612                         if (recv_len && ret > 0)
 613                                 pmsg->len = ret;
 614                 } else {
 615                         ret =
 616                             mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
 617                 }
 618         }
 619         mpc_i2c_stop(i2c); /* Initiate STOP */
 620         orig_jiffies = jiffies;
 621         /* Wait until STOP is seen, allow up to 1 s */
 622         while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
 623                 if (time_after(jiffies, orig_jiffies + HZ)) {
 624                         u8 status = readb(i2c->base + MPC_I2C_SR);
 625
 626                         dev_dbg(i2c->dev, "timeout\n");
 627                         if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {
 628                                 writeb(status & ~CSR_MAL,
 629                                        i2c->base + MPC_I2C_SR);
 630                                 mpc_i2c_fixup(i2c);
 631                         }
 632                         return -EIO;
 633                 }
 634                 cond_resched();
 635         }
 636         return (ret < 0) ? ret : num;
 637 }
 638
 639 static u32 mpc_functionality(struct i2c_adapter *adap)
 640 {
 641         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
 642           | I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL;
 643 }
 644
 645 static const struct i2c_algorithm mpc_algo = {
 646         .master_xfer = mpc_xfer,
 647         .functionality = mpc_functionality,
 648 };
 649
 650 static struct i2c_adapter mpc_ops = {
 651         .owner = THIS_MODULE,
 652         .algo = &mpc_algo,
 653         .timeout = HZ,
 654 };
 655
 656 static const struct of_device_id mpc_i2c_of_match[];
 657 static int fsl_i2c_probe(struct platform_device *op)
 658 {
 659         const struct of_device_id *match;
 660         struct mpc_i2c *i2c;
 661         const u32 *prop;
 662         u32 clock = MPC_I2C_CLOCK_LEGACY;
 663         int result = 0;
 664         int plen;
 665         struct resource res;
 666         struct clk *clk;
 667         int err;
 668
 669         match = of_match_device(mpc_i2c_of_match, &op->dev);
 670         if (!match)
 671                 return -EINVAL;
 672
 673         i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
 674         if (!i2c)
 675                 return -ENOMEM;
 676
 677         i2c->dev = &op->dev; /* for debug and error output */
 678
 679         init_waitqueue_head(&i2c->queue);
 680
 681         i2c->base = of_iomap(op->dev.of_node, 0);
 682         if (!i2c->base) {
 683                 dev_err(i2c->dev, "failed to map controller\n");
 684                 result = -ENOMEM;
 685                 goto fail_map;
 686         }
 687
 688         i2c->irq = irq_of_parse_and_map(op->dev.of_node, 0);
 689         if (i2c->irq) { /* no i2c->irq implies polling */
 690                 result = request_irq(i2c->irq, mpc_i2c_isr,
 691                                      IRQF_SHARED, "i2c-mpc", i2c);
 692                 if (result < 0) {
 693                         dev_err(i2c->dev, "failed to attach interrupt\n");
 694                         goto fail_request;
 695                 }
 696         }
 697
 698         /*
 699          * enable clock for the I2C peripheral (non fatal),
 700          * keep a reference upon successful allocation
 701          */
 702         clk = devm_clk_get(&op->dev, NULL);
 703         if (!IS_ERR(clk)) {
 704                 err = clk_prepare_enable(clk);
 705                 if (err) {
 706                         dev_err(&op->dev, "failed to enable clock\n");
 707                         goto fail_request;
 708                 } else {
 709                         i2c->clk_per = clk;
 710                 }
 711         }
 712
 713         if (of_property_read_bool(op->dev.of_node, "fsl,preserve-clocking")) {
 714                 clock = MPC_I2C_CLOCK_PRESERVE;
 715         } else {
 716                 prop = of_get_property(op->dev.of_node, "clock-frequency",
 717                                         &plen);
 718                 if (prop && plen == sizeof(u32))
 719                         clock = *prop;
 720         }
 721
 722         if (match->data) {
 723                 const struct mpc_i2c_data *data = match->data;
 724                 data->setup(op->dev.of_node, i2c, clock, data->prescaler);
 725         } else {
 726                 /* Backwards compatibility */
 727                 if (of_get_property(op->dev.of_node, "dfsrr", NULL))
 728                         mpc_i2c_setup_8xxx(op->dev.of_node, i2c, clock, 0);
 729         }
 730
 731         prop = of_get_property(op->dev.of_node, "fsl,timeout", &plen);
 732         if (prop && plen == sizeof(u32)) {
 733                 mpc_ops.timeout = *prop * HZ / 1000000;
 734                 if (mpc_ops.timeout < 5)
 735                         mpc_ops.timeout = 5;
 736         }
 737         dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 / HZ);
 738
 739         platform_set_drvdata(op, i2c);
 740
 741         i2c->adap = mpc_ops;
 742         of_address_to_resource(op->dev.of_node, 0, &res);
 743         scnprintf(i2c->adap.name, sizeof(i2c->adap.name),
 744                   "MPC adapter at 0x%llx", (unsigned long long)res.start);
 745         i2c_set_adapdata(&i2c->adap, i2c);
 746         i2c->adap.dev.parent = &op->dev;
 747         i2c->adap.dev.of_node = of_node_get(op->dev.of_node);
 748
 749         result = i2c_add_adapter(&i2c->adap);
 750         if (result < 0)
 751                 goto fail_add;
 752
 753         return result;
 754
 755  fail_add:
 756         if (i2c->clk_per)
 757                 clk_disable_unprepare(i2c->clk_per);
 758         free_irq(i2c->irq, i2c);
 759  fail_request:
 760         irq_dispose_mapping(i2c->irq);
 761         iounmap(i2c->base);
 762  fail_map:
 763         kfree(i2c);
 764         return result;
 765 };
 766
 767 static int fsl_i2c_remove(struct platform_device *op)
 768 {
 769         struct mpc_i2c *i2c = platform_get_drvdata(op);
 770
 771         i2c_del_adapter(&i2c->adap);
 772
 773         if (i2c->clk_per)
 774                 clk_disable_unprepare(i2c->clk_per);
 775
 776         if (i2c->irq)
 777                 free_irq(i2c->irq, i2c);
 778
 779         irq_dispose_mapping(i2c->irq);
 780         iounmap(i2c->base);
 781         kfree(i2c);
 782         return 0;
 783 };
 784
 785 #ifdef CONFIG_PM_SLEEP
 786 static int mpc_i2c_suspend(struct device *dev)
 787 {
 788         struct mpc_i2c *i2c = dev_get_drvdata(dev);
 789
 790         i2c->fdr = readb(i2c->base + MPC_I2C_FDR);
 791         i2c->dfsrr = readb(i2c->base + MPC_I2C_DFSRR);
 792
 793         return 0;
 794 }
 795
 796 static int mpc_i2c_resume(struct device *dev)
 797 {
 798         struct mpc_i2c *i2c = dev_get_drvdata(dev);
 799
 800         writeb(i2c->fdr, i2c->base + MPC_I2C_FDR);
 801         writeb(i2c->dfsrr, i2c->base + MPC_I2C_DFSRR);
 802
 803         return 0;
 804 }
 805
 806 static SIMPLE_DEV_PM_OPS(mpc_i2c_pm_ops, mpc_i2c_suspend, mpc_i2c_resume);
 807 #define MPC_I2C_PM_OPS  (&mpc_i2c_pm_ops)
 808 #else
 809 #define MPC_I2C_PM_OPS  NULL
 810 #endif
 811
 812 static const struct mpc_i2c_data mpc_i2c_data_512x = {
 813         .setup = mpc_i2c_setup_512x,
 814 };
 815
 816 static const struct mpc_i2c_data mpc_i2c_data_52xx = {
 817         .setup = mpc_i2c_setup_52xx,
 818 };
 819
 820 static const struct mpc_i2c_data mpc_i2c_data_8313 = {
 821         .setup = mpc_i2c_setup_8xxx,
 822 };
 823
 824 static const struct mpc_i2c_data mpc_i2c_data_8543 = {
 825         .setup = mpc_i2c_setup_8xxx,
 826         .prescaler = 2,
 827 };
 828
 829 static const struct mpc_i2c_data mpc_i2c_data_8544 = {
 830         .setup = mpc_i2c_setup_8xxx,
 831         .prescaler = 3,
 832 };
 833
 834 static const struct of_device_id mpc_i2c_of_match[] = {
 835         {.compatible = "mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
 836         {.compatible = "fsl,mpc5200b-i2c", .data = &mpc_i2c_data_52xx, },
 837         {.compatible = "fsl,mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
 838         {.compatible = "fsl,mpc5121-i2c", .data = &mpc_i2c_data_512x, },
 839         {.compatible = "fsl,mpc8313-i2c", .data = &mpc_i2c_data_8313, },
 840         {.compatible = "fsl,mpc8543-i2c", .data = &mpc_i2c_data_8543, },
 841         {.compatible = "fsl,mpc8544-i2c", .data = &mpc_i2c_data_8544, },
 842         /* Backward compatibility */
 843         {.compatible = "fsl-i2c", },
 844         {},
 845 };
 846 MODULE_DEVICE_TABLE(of, mpc_i2c_of_match);
 847
 848 /* Structure for a device driver */
 849 static struct platform_driver mpc_i2c_driver = {
 850         .probe          = fsl_i2c_probe,
 851         .remove         = fsl_i2c_remove,
 852         .driver = {
 853                 .name = DRV_NAME,
 854                 .of_match_table = mpc_i2c_of_match,
 855                 .pm = MPC_I2C_PM_OPS,
 856         },
 857 };
 858
 859 module_platform_driver(mpc_i2c_driver);
 860
 861 MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
 862 MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and "
 863                    "MPC824x/83xx/85xx/86xx/512x/52xx processors");
 864 MODULE_LICENSE("GPL");