1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Ingenic JZ4780 I2C bus driver
5 * Copyright (C) 2006 - 2009 Ingenic Semiconductor Inc.
6 * Copyright (C) 2015 Imagination Technologies
7 * Copyright (C) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
10 #include <linux/bitops.h>
11 #include <linux/clk.h>
12 #include <linux/completion.h>
13 #include <linux/delay.h>
14 #include <linux/errno.h>
15 #include <linux/i2c.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/of_device.h>
22 #include <linux/platform_device.h>
23 #include <linux/sched.h>
24 #include <linux/slab.h>
25 #include <linux/time.h>
27 #define JZ4780_I2C_CTRL 0x00
28 #define JZ4780_I2C_TAR 0x04
29 #define JZ4780_I2C_SAR 0x08
30 #define JZ4780_I2C_DC 0x10
31 #define JZ4780_I2C_SHCNT 0x14
32 #define JZ4780_I2C_SLCNT 0x18
33 #define JZ4780_I2C_FHCNT 0x1C
34 #define JZ4780_I2C_FLCNT 0x20
35 #define JZ4780_I2C_INTST 0x2C
36 #define JZ4780_I2C_INTM 0x30
37 #define JZ4780_I2C_RXTL 0x38
38 #define JZ4780_I2C_TXTL 0x3C
39 #define JZ4780_I2C_CINTR 0x40
40 #define JZ4780_I2C_CRXUF 0x44
41 #define JZ4780_I2C_CRXOF 0x48
42 #define JZ4780_I2C_CTXOF 0x4C
43 #define JZ4780_I2C_CRXREQ 0x50
44 #define JZ4780_I2C_CTXABRT 0x54
45 #define JZ4780_I2C_CRXDONE 0x58
46 #define JZ4780_I2C_CACT 0x5C
47 #define JZ4780_I2C_CSTP 0x60
48 #define JZ4780_I2C_CSTT 0x64
49 #define JZ4780_I2C_CGC 0x68
50 #define JZ4780_I2C_ENB 0x6C
51 #define JZ4780_I2C_STA 0x70
52 #define JZ4780_I2C_TXABRT 0x80
53 #define JZ4780_I2C_DMACR 0x88
54 #define JZ4780_I2C_DMATDLR 0x8C
55 #define JZ4780_I2C_DMARDLR 0x90
56 #define JZ4780_I2C_SDASU 0x94
57 #define JZ4780_I2C_ACKGC 0x98
58 #define JZ4780_I2C_ENSTA 0x9C
59 #define JZ4780_I2C_SDAHD 0xD0
60 #define X1000_I2C_SDAHD 0x7C
62 #define JZ4780_I2C_CTRL_STPHLD BIT(7)
63 #define JZ4780_I2C_CTRL_SLVDIS BIT(6)
64 #define JZ4780_I2C_CTRL_REST BIT(5)
65 #define JZ4780_I2C_CTRL_MATP BIT(4)
66 #define JZ4780_I2C_CTRL_SATP BIT(3)
67 #define JZ4780_I2C_CTRL_SPDF BIT(2)
68 #define JZ4780_I2C_CTRL_SPDS BIT(1)
69 #define JZ4780_I2C_CTRL_MD BIT(0)
71 #define JZ4780_I2C_STA_SLVACT BIT(6)
72 #define JZ4780_I2C_STA_MSTACT BIT(5)
73 #define JZ4780_I2C_STA_RFF BIT(4)
74 #define JZ4780_I2C_STA_RFNE BIT(3)
75 #define JZ4780_I2C_STA_TFE BIT(2)
76 #define JZ4780_I2C_STA_TFNF BIT(1)
77 #define JZ4780_I2C_STA_ACT BIT(0)
79 #define X1000_I2C_DC_STOP BIT(9)
81 #define JZ4780_I2C_INTST_IGC BIT(11)
82 #define JZ4780_I2C_INTST_ISTT BIT(10)
83 #define JZ4780_I2C_INTST_ISTP BIT(9)
84 #define JZ4780_I2C_INTST_IACT BIT(8)
85 #define JZ4780_I2C_INTST_RXDN BIT(7)
86 #define JZ4780_I2C_INTST_TXABT BIT(6)
87 #define JZ4780_I2C_INTST_RDREQ BIT(5)
88 #define JZ4780_I2C_INTST_TXEMP BIT(4)
89 #define JZ4780_I2C_INTST_TXOF BIT(3)
90 #define JZ4780_I2C_INTST_RXFL BIT(2)
91 #define JZ4780_I2C_INTST_RXOF BIT(1)
92 #define JZ4780_I2C_INTST_RXUF BIT(0)
94 #define JZ4780_I2C_INTM_MIGC BIT(11)
95 #define JZ4780_I2C_INTM_MISTT BIT(10)
96 #define JZ4780_I2C_INTM_MISTP BIT(9)
97 #define JZ4780_I2C_INTM_MIACT BIT(8)
98 #define JZ4780_I2C_INTM_MRXDN BIT(7)
99 #define JZ4780_I2C_INTM_MTXABT BIT(6)
100 #define JZ4780_I2C_INTM_MRDREQ BIT(5)
101 #define JZ4780_I2C_INTM_MTXEMP BIT(4)
102 #define JZ4780_I2C_INTM_MTXOF BIT(3)
103 #define JZ4780_I2C_INTM_MRXFL BIT(2)
104 #define JZ4780_I2C_INTM_MRXOF BIT(1)
105 #define JZ4780_I2C_INTM_MRXUF BIT(0)
107 #define JZ4780_I2C_DC_READ BIT(8)
109 #define JZ4780_I2C_SDAHD_HDENB BIT(8)
111 #define JZ4780_I2C_ENB_I2C BIT(0)
113 #define JZ4780_I2CSHCNT_ADJUST(n) (((n) - 8) < 6 ? 6 : ((n) - 8))
114 #define JZ4780_I2CSLCNT_ADJUST(n) (((n) - 1) < 8 ? 8 : ((n) - 1))
115 #define JZ4780_I2CFHCNT_ADJUST(n) (((n) - 8) < 6 ? 6 : ((n) - 8))
116 #define JZ4780_I2CFLCNT_ADJUST(n) (((n) - 1) < 8 ? 8 : ((n) - 1))
118 #define JZ4780_I2C_FIFO_LEN 16
120 #define X1000_I2C_FIFO_LEN 64
122 #define JZ4780_I2C_TIMEOUT 300
126 enum ingenic_i2c_version {
131 /* ingenic_i2c_config: SoC specific config data. */
132 struct ingenic_i2c_config {
133 enum ingenic_i2c_version version;
144 struct i2c_adapter adap;
145 const struct ingenic_i2c_config *cdata;
147 /* lock to protect rbuf and wbuf between xfer_rd/wr and irq handler */
150 /* beginning of lock scope */
163 int data_buf[BUFSIZE];
164 int cmd_buf[BUFSIZE];
167 /* end of lock scope */
168 struct completion trans_waitq;
171 static inline unsigned short jz4780_i2c_readw(struct jz4780_i2c *i2c,
172 unsigned long offset)
174 return readw(i2c->iomem + offset);
177 static inline void jz4780_i2c_writew(struct jz4780_i2c *i2c,
178 unsigned long offset, unsigned short val)
180 writew(val, i2c->iomem + offset);
183 static int jz4780_i2c_disable(struct jz4780_i2c *i2c)
185 unsigned short regval;
186 unsigned long loops = 5;
188 jz4780_i2c_writew(i2c, JZ4780_I2C_ENB, 0);
191 regval = jz4780_i2c_readw(i2c, JZ4780_I2C_ENSTA);
192 if (!(regval & JZ4780_I2C_ENB_I2C))
195 usleep_range(5000, 15000);
198 dev_err(&i2c->adap.dev, "disable failed: ENSTA=0x%04x\n", regval);
202 static int jz4780_i2c_enable(struct jz4780_i2c *i2c)
204 unsigned short regval;
205 unsigned long loops = 5;
207 jz4780_i2c_writew(i2c, JZ4780_I2C_ENB, 1);
210 regval = jz4780_i2c_readw(i2c, JZ4780_I2C_ENSTA);
211 if (regval & JZ4780_I2C_ENB_I2C)
214 usleep_range(5000, 15000);
217 dev_err(&i2c->adap.dev, "enable failed: ENSTA=0x%04x\n", regval);
221 static int jz4780_i2c_set_target(struct jz4780_i2c *i2c, unsigned char address)
223 unsigned short regval;
224 unsigned long loops = 5;
227 regval = jz4780_i2c_readw(i2c, JZ4780_I2C_STA);
228 if ((regval & JZ4780_I2C_STA_TFE) &&
229 !(regval & JZ4780_I2C_STA_MSTACT))
232 usleep_range(5000, 15000);
236 jz4780_i2c_writew(i2c, JZ4780_I2C_TAR, address);
240 dev_err(&i2c->adap.dev,
241 "set device to address 0x%02x failed, STA=0x%04x\n",
247 static int jz4780_i2c_set_speed(struct jz4780_i2c *i2c)
249 int dev_clk_khz = clk_get_rate(i2c->clk) / 1000;
250 int cnt_high = 0; /* HIGH period count of the SCL clock */
251 int cnt_low = 0; /* LOW period count of the SCL clock */
252 int cnt_period = 0; /* period count of the SCL clock */
255 unsigned short tmp = 0;
256 int i2c_clk = i2c->speed;
258 if (jz4780_i2c_disable(i2c))
259 dev_dbg(&i2c->adap.dev, "i2c not disabled\n");
262 * 1 JZ4780_I2C cycle equals to cnt_period PCLK(i2c_clk)
263 * standard mode, min LOW and HIGH period are 4700 ns and 4000 ns
264 * fast mode, min LOW and HIGH period are 1300 ns and 600 ns
266 cnt_period = dev_clk_khz / i2c_clk;
269 cnt_high = (cnt_period * 4000) / (4700 + 4000);
271 cnt_high = (cnt_period * 600) / (1300 + 600);
273 cnt_low = cnt_period - cnt_high;
276 * NOTE: JZ4780_I2C_CTRL_REST can't set when i2c enabled, because
277 * normal read are 2 messages, we cannot disable i2c controller
278 * between these two messages, this means that we must always set
279 * JZ4780_I2C_CTRL_REST when init JZ4780_I2C_CTRL
282 if (i2c_clk <= 100) {
283 tmp = JZ4780_I2C_CTRL_SPDS | JZ4780_I2C_CTRL_REST
284 | JZ4780_I2C_CTRL_SLVDIS | JZ4780_I2C_CTRL_MD;
285 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
287 jz4780_i2c_writew(i2c, JZ4780_I2C_SHCNT,
288 JZ4780_I2CSHCNT_ADJUST(cnt_high));
289 jz4780_i2c_writew(i2c, JZ4780_I2C_SLCNT,
290 JZ4780_I2CSLCNT_ADJUST(cnt_low));
292 tmp = JZ4780_I2C_CTRL_SPDF | JZ4780_I2C_CTRL_REST
293 | JZ4780_I2C_CTRL_SLVDIS | JZ4780_I2C_CTRL_MD;
294 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
296 jz4780_i2c_writew(i2c, JZ4780_I2C_FHCNT,
297 JZ4780_I2CFHCNT_ADJUST(cnt_high));
298 jz4780_i2c_writew(i2c, JZ4780_I2C_FLCNT,
299 JZ4780_I2CFLCNT_ADJUST(cnt_low));
303 * a i2c device must internally provide a hold time at least 300ns
305 * Standard Mode: min=300ns, max=3450ns
306 * Fast Mode: min=0ns, max=900ns
308 * Standard Mode: min=250ns, max=infinite
309 * Fast Mode: min=100(250ns is recommended), max=infinite
311 * 1i2c_clk = 10^6 / dev_clk_khz
312 * on FPGA, dev_clk_khz = 12000, so 1i2c_clk = 1000/12 = 83ns
313 * on Pisces(1008M), dev_clk_khz=126000, so 1i2c_clk = 1000 / 126 = 8ns
315 * The actual hold time is (SDAHD + 1) * (i2c_clk period).
317 * Length of setup time calculated using (SDASU - 1) * (ic_clk_period)
320 if (i2c_clk <= 100) { /* standard mode */
328 hold_time = ((hold_time * dev_clk_khz) / 1000000) - 1;
329 setup_time = ((setup_time * dev_clk_khz) / 1000000) + 1;
331 if (setup_time > 255)
337 jz4780_i2c_writew(i2c, JZ4780_I2C_SDASU, setup_time);
342 if (hold_time >= 0) {
343 /*i2c hold time enable */
344 if (i2c->cdata->version >= ID_X1000) {
345 jz4780_i2c_writew(i2c, X1000_I2C_SDAHD, hold_time);
347 hold_time |= JZ4780_I2C_SDAHD_HDENB;
348 jz4780_i2c_writew(i2c, JZ4780_I2C_SDAHD, hold_time);
351 /* disable hold time */
352 if (i2c->cdata->version >= ID_X1000)
353 jz4780_i2c_writew(i2c, X1000_I2C_SDAHD, 0);
355 jz4780_i2c_writew(i2c, JZ4780_I2C_SDAHD, 0);
361 static int jz4780_i2c_cleanup(struct jz4780_i2c *i2c)
367 spin_lock_irqsave(&i2c->lock, flags);
369 /* can send stop now if need */
370 if (i2c->cdata->version < ID_X1000) {
371 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
372 tmp &= ~JZ4780_I2C_CTRL_STPHLD;
373 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
376 /* disable all interrupts first */
377 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, 0);
379 /* then clear all interrupts */
380 jz4780_i2c_readw(i2c, JZ4780_I2C_CTXABRT);
381 jz4780_i2c_readw(i2c, JZ4780_I2C_CINTR);
383 /* then disable the controller */
384 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
385 tmp &= ~JZ4780_I2C_ENB_I2C;
386 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
388 tmp |= JZ4780_I2C_ENB_I2C;
389 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
391 spin_unlock_irqrestore(&i2c->lock, flags);
393 ret = jz4780_i2c_disable(i2c);
395 dev_err(&i2c->adap.dev,
396 "unable to disable device during cleanup!\n");
398 if (unlikely(jz4780_i2c_readw(i2c, JZ4780_I2C_INTM)
399 & jz4780_i2c_readw(i2c, JZ4780_I2C_INTST)))
400 dev_err(&i2c->adap.dev,
401 "device has interrupts after a complete cleanup!\n");
406 static int jz4780_i2c_prepare(struct jz4780_i2c *i2c)
408 jz4780_i2c_set_speed(i2c);
409 return jz4780_i2c_enable(i2c);
412 static void jz4780_i2c_send_rcmd(struct jz4780_i2c *i2c,
418 for (i = 0; i < cmd_count - 1; i++)
419 jz4780_i2c_writew(i2c, JZ4780_I2C_DC, JZ4780_I2C_DC_READ);
421 if ((cmd_left == 0) && (i2c->cdata->version >= ID_X1000))
422 jz4780_i2c_writew(i2c, JZ4780_I2C_DC,
423 JZ4780_I2C_DC_READ | X1000_I2C_DC_STOP);
425 jz4780_i2c_writew(i2c, JZ4780_I2C_DC, JZ4780_I2C_DC_READ);
428 static void jz4780_i2c_trans_done(struct jz4780_i2c *i2c)
430 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, 0);
431 complete(&i2c->trans_waitq);
434 static irqreturn_t jz4780_i2c_irq(int irqno, void *dev_id)
437 unsigned short intst;
438 unsigned short intmsk;
439 struct jz4780_i2c *i2c = dev_id;
442 spin_lock_irqsave(&i2c->lock, flags);
443 intmsk = jz4780_i2c_readw(i2c, JZ4780_I2C_INTM);
444 intst = jz4780_i2c_readw(i2c, JZ4780_I2C_INTST);
448 if (intst & JZ4780_I2C_INTST_TXABT) {
449 jz4780_i2c_trans_done(i2c);
453 if (intst & JZ4780_I2C_INTST_RXOF) {
454 dev_dbg(&i2c->adap.dev, "received fifo overflow!\n");
455 jz4780_i2c_trans_done(i2c);
460 * When reading, always drain RX FIFO before we send more Read
461 * Commands to avoid fifo overrun
463 if (i2c->is_write == 0) {
466 while ((jz4780_i2c_readw(i2c, JZ4780_I2C_STA)
467 & JZ4780_I2C_STA_RFNE)) {
468 *(i2c->rbuf++) = jz4780_i2c_readw(i2c, JZ4780_I2C_DC)
470 i2c->rd_data_xfered++;
471 if (i2c->rd_data_xfered == i2c->rd_total_len) {
472 jz4780_i2c_trans_done(i2c);
477 rd_left = i2c->rd_total_len - i2c->rd_data_xfered;
479 if (rd_left <= i2c->cdata->fifosize)
480 jz4780_i2c_writew(i2c, JZ4780_I2C_RXTL, rd_left - 1);
483 if (intst & JZ4780_I2C_INTST_TXEMP) {
484 if (i2c->is_write == 0) {
485 int cmd_left = i2c->rd_total_len - i2c->rd_cmd_xfered;
486 int max_send = (i2c->cdata->fifosize - 1)
487 - (i2c->rd_cmd_xfered
488 - i2c->rd_data_xfered);
489 int cmd_to_send = min(cmd_left, max_send);
491 if (i2c->rd_cmd_xfered != 0)
492 cmd_to_send = min(cmd_to_send,
494 - i2c->cdata->tx_level - 1);
497 i2c->rd_cmd_xfered += cmd_to_send;
498 cmd_left = i2c->rd_total_len -
500 jz4780_i2c_send_rcmd(i2c,
501 cmd_to_send, cmd_left);
506 intmsk = jz4780_i2c_readw(i2c, JZ4780_I2C_INTM);
507 intmsk &= ~JZ4780_I2C_INTM_MTXEMP;
508 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, intmsk);
510 if (i2c->cdata->version < ID_X1000) {
511 tmp = jz4780_i2c_readw(i2c,
513 tmp &= ~JZ4780_I2C_CTRL_STPHLD;
514 jz4780_i2c_writew(i2c,
515 JZ4780_I2C_CTRL, tmp);
520 unsigned short i2c_sta;
522 i2c_sta = jz4780_i2c_readw(i2c, JZ4780_I2C_STA);
524 while ((i2c_sta & JZ4780_I2C_STA_TFNF) &&
526 i2c_sta = jz4780_i2c_readw(i2c, JZ4780_I2C_STA);
528 data &= ~JZ4780_I2C_DC_READ;
529 if ((!i2c->stop_hold) && (i2c->cdata->version >=
531 data |= X1000_I2C_DC_STOP;
532 jz4780_i2c_writew(i2c, JZ4780_I2C_DC, data);
537 if (i2c->wt_len == 0) {
538 if ((!i2c->stop_hold) && (i2c->cdata->version <
540 tmp = jz4780_i2c_readw(i2c,
542 tmp &= ~JZ4780_I2C_CTRL_STPHLD;
543 jz4780_i2c_writew(i2c,
544 JZ4780_I2C_CTRL, tmp);
547 jz4780_i2c_trans_done(i2c);
554 spin_unlock_irqrestore(&i2c->lock, flags);
558 static void jz4780_i2c_txabrt(struct jz4780_i2c *i2c, int src)
560 dev_dbg(&i2c->adap.dev, "txabrt: 0x%08x, cmd: %d, send: %d, recv: %d\n",
561 src, i2c->cmd, i2c->cmd_buf[i2c->cmd], i2c->data_buf[i2c->cmd]);
564 static inline int jz4780_i2c_xfer_read(struct jz4780_i2c *i2c,
565 unsigned char *buf, int len, int cnt,
570 int wait_time = JZ4780_I2C_TIMEOUT * (len + 5);
576 spin_lock_irqsave(&i2c->lock, flags);
581 i2c->rd_total_len = len;
582 i2c->rd_data_xfered = 0;
583 i2c->rd_cmd_xfered = 0;
585 if (len <= i2c->cdata->fifosize)
586 jz4780_i2c_writew(i2c, JZ4780_I2C_RXTL, len - 1);
588 jz4780_i2c_writew(i2c, JZ4780_I2C_RXTL, i2c->cdata->rx_level);
590 jz4780_i2c_writew(i2c, JZ4780_I2C_TXTL, i2c->cdata->tx_level);
592 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM,
593 JZ4780_I2C_INTM_MRXFL | JZ4780_I2C_INTM_MTXEMP
594 | JZ4780_I2C_INTM_MTXABT | JZ4780_I2C_INTM_MRXOF);
596 if (i2c->cdata->version < ID_X1000) {
597 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
598 tmp |= JZ4780_I2C_CTRL_STPHLD;
599 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
602 spin_unlock_irqrestore(&i2c->lock, flags);
604 timeout = wait_for_completion_timeout(&i2c->trans_waitq,
605 msecs_to_jiffies(wait_time));
608 dev_err(&i2c->adap.dev, "irq read timeout\n");
609 dev_dbg(&i2c->adap.dev, "send cmd count:%d %d\n",
610 i2c->cmd, i2c->cmd_buf[i2c->cmd]);
611 dev_dbg(&i2c->adap.dev, "receive data count:%d %d\n",
612 i2c->cmd, i2c->data_buf[i2c->cmd]);
616 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_TXABRT);
618 jz4780_i2c_txabrt(i2c, tmp);
625 static inline int jz4780_i2c_xfer_write(struct jz4780_i2c *i2c,
626 unsigned char *buf, int len,
630 int wait_time = JZ4780_I2C_TIMEOUT * (len + 5);
635 spin_lock_irqsave(&i2c->lock, flags);
646 jz4780_i2c_writew(i2c, JZ4780_I2C_TXTL, i2c->cdata->tx_level);
648 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, JZ4780_I2C_INTM_MTXEMP
649 | JZ4780_I2C_INTM_MTXABT);
651 if (i2c->cdata->version < ID_X1000) {
652 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
653 tmp |= JZ4780_I2C_CTRL_STPHLD;
654 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
657 spin_unlock_irqrestore(&i2c->lock, flags);
659 timeout = wait_for_completion_timeout(&i2c->trans_waitq,
660 msecs_to_jiffies(wait_time));
661 if (timeout && !i2c->stop_hold) {
662 unsigned short i2c_sta;
663 int write_in_process;
665 timeout = JZ4780_I2C_TIMEOUT * 100;
666 for (; timeout > 0; timeout--) {
667 i2c_sta = jz4780_i2c_readw(i2c, JZ4780_I2C_STA);
669 write_in_process = (i2c_sta & JZ4780_I2C_STA_MSTACT) ||
670 !(i2c_sta & JZ4780_I2C_STA_TFE);
671 if (!write_in_process)
678 dev_err(&i2c->adap.dev, "write wait timeout\n");
682 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_TXABRT);
684 jz4780_i2c_txabrt(i2c, tmp);
691 static int jz4780_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msg,
696 struct jz4780_i2c *i2c = adap->algo_data;
698 ret = jz4780_i2c_prepare(i2c);
700 dev_err(&i2c->adap.dev, "I2C prepare failed\n");
704 if (msg->addr != jz4780_i2c_readw(i2c, JZ4780_I2C_TAR)) {
705 ret = jz4780_i2c_set_target(i2c, msg->addr);
709 for (i = 0; i < count; i++, msg++) {
710 if (msg->flags & I2C_M_RD)
711 ret = jz4780_i2c_xfer_read(i2c, msg->buf, msg->len,
714 ret = jz4780_i2c_xfer_write(i2c, msg->buf, msg->len,
724 jz4780_i2c_cleanup(i2c);
728 static u32 jz4780_i2c_functionality(struct i2c_adapter *adap)
730 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
733 static const struct i2c_algorithm jz4780_i2c_algorithm = {
734 .master_xfer = jz4780_i2c_xfer,
735 .functionality = jz4780_i2c_functionality,
738 static const struct ingenic_i2c_config jz4780_i2c_config = {
739 .version = ID_JZ4780,
741 .fifosize = JZ4780_I2C_FIFO_LEN,
742 .tx_level = JZ4780_I2C_FIFO_LEN / 2,
743 .rx_level = JZ4780_I2C_FIFO_LEN / 2 - 1,
746 static const struct ingenic_i2c_config x1000_i2c_config = {
749 .fifosize = X1000_I2C_FIFO_LEN,
750 .tx_level = X1000_I2C_FIFO_LEN / 2,
751 .rx_level = X1000_I2C_FIFO_LEN / 2 - 1,
754 static const struct of_device_id jz4780_i2c_of_matches[] = {
755 { .compatible = "ingenic,jz4770-i2c", .data = &jz4780_i2c_config },
756 { .compatible = "ingenic,jz4780-i2c", .data = &jz4780_i2c_config },
757 { .compatible = "ingenic,x1000-i2c", .data = &x1000_i2c_config },
760 MODULE_DEVICE_TABLE(of, jz4780_i2c_of_matches);
762 static int jz4780_i2c_probe(struct platform_device *pdev)
765 unsigned int clk_freq = 0;
767 struct jz4780_i2c *i2c;
769 i2c = devm_kzalloc(&pdev->dev, sizeof(struct jz4780_i2c), GFP_KERNEL);
773 i2c->cdata = device_get_match_data(&pdev->dev);
775 dev_err(&pdev->dev, "Error: No device match found\n");
779 i2c->adap.owner = THIS_MODULE;
780 i2c->adap.algo = &jz4780_i2c_algorithm;
781 i2c->adap.algo_data = i2c;
782 i2c->adap.retries = 5;
783 i2c->adap.dev.parent = &pdev->dev;
784 i2c->adap.dev.of_node = pdev->dev.of_node;
785 sprintf(i2c->adap.name, "%s", pdev->name);
787 init_completion(&i2c->trans_waitq);
788 spin_lock_init(&i2c->lock);
790 i2c->iomem = devm_platform_ioremap_resource(pdev, 0);
791 if (IS_ERR(i2c->iomem))
792 return PTR_ERR(i2c->iomem);
794 platform_set_drvdata(pdev, i2c);
796 i2c->clk = devm_clk_get(&pdev->dev, NULL);
797 if (IS_ERR(i2c->clk))
798 return PTR_ERR(i2c->clk);
800 ret = clk_prepare_enable(i2c->clk);
804 ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
807 dev_err(&pdev->dev, "clock-frequency not specified in DT\n");
811 i2c->speed = clk_freq / 1000;
812 if (i2c->speed == 0) {
814 dev_err(&pdev->dev, "clock-frequency minimum is 1000\n");
817 jz4780_i2c_set_speed(i2c);
819 dev_info(&pdev->dev, "Bus frequency is %d KHz\n", i2c->speed);
821 if (i2c->cdata->version < ID_X1000) {
822 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
823 tmp &= ~JZ4780_I2C_CTRL_STPHLD;
824 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
827 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, 0x0);
829 i2c->irq = platform_get_irq(pdev, 0);
830 ret = devm_request_irq(&pdev->dev, i2c->irq, jz4780_i2c_irq, 0,
831 dev_name(&pdev->dev), i2c);
835 ret = i2c_add_adapter(&i2c->adap);
842 clk_disable_unprepare(i2c->clk);
846 static int jz4780_i2c_remove(struct platform_device *pdev)
848 struct jz4780_i2c *i2c = platform_get_drvdata(pdev);
850 clk_disable_unprepare(i2c->clk);
851 i2c_del_adapter(&i2c->adap);
855 static struct platform_driver jz4780_i2c_driver = {
856 .probe = jz4780_i2c_probe,
857 .remove = jz4780_i2c_remove,
859 .name = "jz4780-i2c",
860 .of_match_table = jz4780_i2c_of_matches,
864 module_platform_driver(jz4780_i2c_driver);
866 MODULE_LICENSE("GPL");
867 MODULE_AUTHOR("ztyan<ztyan@ingenic.cn>");
868 MODULE_DESCRIPTION("i2c driver for JZ4780 SoCs");