drivers/i2c/busses/i2c-ismt.c

   1 /*
   2  * This file is provided under a dual BSD/GPLv2 license.  When using or
   3  * redistributing this file, you may do so under either license.
   4  *
   5  * Copyright(c) 2012 Intel Corporation. All rights reserved.
   6  *
   7  * GPL LICENSE SUMMARY
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of version 2 of the GNU General Public License as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  * The full GNU General Public License is included in this distribution
  18  * in the file called LICENSE.GPL.
  19  *
  20  * BSD LICENSE
  21  *
  22  * Redistribution and use in source and binary forms, with or without
  23  * modification, are permitted provided that the following conditions
  24  * are met:
  25  *
  26  *   * Redistributions of source code must retain the above copyright
  27  *     notice, this list of conditions and the following disclaimer.
  28  *   * Redistributions in binary form must reproduce the above copyright
  29  *     notice, this list of conditions and the following disclaimer in
  30  *     the documentation and/or other materials provided with the
  31  *     distribution.
  32  *   * Neither the name of Intel Corporation nor the names of its
  33  *     contributors may be used to endorse or promote products derived
  34  *     from this software without specific prior written permission.
  35  *
  36  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  37  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  38  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  39  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  40  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  41  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  42  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  43  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  44  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  45  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  46  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  47  */
  48
  49 /*
  50  *  Supports the SMBus Message Transport (SMT) in the Intel Atom Processor
  51  *  S12xx Product Family.
  52  *
  53  *  Features supported by this driver:
  54  *  Hardware PEC                     yes
  55  *  Block buffer                     yes
  56  *  Block process call transaction   yes
  57  *  Slave mode                       no
  58  */
  59
  60 #include <linux/module.h>
  61 #include <linux/pci.h>
  62 #include <linux/kernel.h>
  63 #include <linux/stddef.h>
  64 #include <linux/completion.h>
  65 #include <linux/dma-mapping.h>
  66 #include <linux/i2c.h>
  67 #include <linux/acpi.h>
  68 #include <linux/interrupt.h>
  69
  70 #include <linux/io-64-nonatomic-lo-hi.h>
  71
  72 /* PCI Address Constants */
  73 #define SMBBAR          0
  74
  75 /* PCI DIDs for the Intel SMBus Message Transport (SMT) Devices */
  76 #define PCI_DEVICE_ID_INTEL_S1200_SMT0  0x0c59
  77 #define PCI_DEVICE_ID_INTEL_S1200_SMT1  0x0c5a
  78 #define PCI_DEVICE_ID_INTEL_CDF_SMT     0x18ac
  79 #define PCI_DEVICE_ID_INTEL_DNV_SMT     0x19ac
  80 #define PCI_DEVICE_ID_INTEL_EBG_SMT     0x1bff
  81 #define PCI_DEVICE_ID_INTEL_AVOTON_SMT  0x1f15
  82
  83 #define ISMT_DESC_ENTRIES       2       /* number of descriptor entries */
  84 #define ISMT_MAX_RETRIES        3       /* number of SMBus retries to attempt */
  85
  86 /* Hardware Descriptor Constants - Control Field */
  87 #define ISMT_DESC_CWRL  0x01    /* Command/Write Length */
  88 #define ISMT_DESC_BLK   0X04    /* Perform Block Transaction */
  89 #define ISMT_DESC_FAIR  0x08    /* Set fairness flag upon successful arbit. */
  90 #define ISMT_DESC_PEC   0x10    /* Packet Error Code */
  91 #define ISMT_DESC_I2C   0x20    /* I2C Enable */
  92 #define ISMT_DESC_INT   0x40    /* Interrupt */
  93 #define ISMT_DESC_SOE   0x80    /* Stop On Error */
  94
  95 /* Hardware Descriptor Constants - Status Field */
  96 #define ISMT_DESC_SCS   0x01    /* Success */
  97 #define ISMT_DESC_DLTO  0x04    /* Data Low Time Out */
  98 #define ISMT_DESC_NAK   0x08    /* NAK Received */
  99 #define ISMT_DESC_CRC   0x10    /* CRC Error */
 100 #define ISMT_DESC_CLTO  0x20    /* Clock Low Time Out */
 101 #define ISMT_DESC_COL   0x40    /* Collisions */
 102 #define ISMT_DESC_LPR   0x80    /* Large Packet Received */
 103
 104 /* Macros */
 105 #define ISMT_DESC_ADDR_RW(addr, rw) (((addr) << 1) | (rw))
 106
 107 /* iSMT General Register address offsets (SMBBAR + <addr>) */
 108 #define ISMT_GR_GCTRL           0x000   /* General Control */
 109 #define ISMT_GR_SMTICL          0x008   /* SMT Interrupt Cause Location */
 110 #define ISMT_GR_ERRINTMSK       0x010   /* Error Interrupt Mask */
 111 #define ISMT_GR_ERRAERMSK       0x014   /* Error AER Mask */
 112 #define ISMT_GR_ERRSTS          0x018   /* Error Status */
 113 #define ISMT_GR_ERRINFO         0x01c   /* Error Information */
 114
 115 /* iSMT Master Registers */
 116 #define ISMT_MSTR_MDBA          0x100   /* Master Descriptor Base Address */
 117 #define ISMT_MSTR_MCTRL         0x108   /* Master Control */
 118 #define ISMT_MSTR_MSTS          0x10c   /* Master Status */
 119 #define ISMT_MSTR_MDS           0x110   /* Master Descriptor Size */
 120 #define ISMT_MSTR_RPOLICY       0x114   /* Retry Policy */
 121
 122 /* iSMT Miscellaneous Registers */
 123 #define ISMT_SPGT       0x300   /* SMBus PHY Global Timing */
 124
 125 /* General Control Register (GCTRL) bit definitions */
 126 #define ISMT_GCTRL_TRST 0x04    /* Target Reset */
 127 #define ISMT_GCTRL_KILL 0x08    /* Kill */
 128 #define ISMT_GCTRL_SRST 0x40    /* Soft Reset */
 129
 130 /* Master Control Register (MCTRL) bit definitions */
 131 #define ISMT_MCTRL_SS   0x01            /* Start/Stop */
 132 #define ISMT_MCTRL_MEIE 0x10            /* Master Error Interrupt Enable */
 133 #define ISMT_MCTRL_FMHP 0x00ff0000      /* Firmware Master Head Ptr (FMHP) */
 134
 135 /* Master Status Register (MSTS) bit definitions */
 136 #define ISMT_MSTS_HMTP  0xff0000        /* HW Master Tail Pointer (HMTP) */
 137 #define ISMT_MSTS_MIS   0x20            /* Master Interrupt Status (MIS) */
 138 #define ISMT_MSTS_MEIS  0x10            /* Master Error Int Status (MEIS) */
 139 #define ISMT_MSTS_IP    0x01            /* In Progress */
 140
 141 /* Master Descriptor Size (MDS) bit definitions */
 142 #define ISMT_MDS_MASK   0xff    /* Master Descriptor Size mask (MDS) */
 143
 144 /* SMBus PHY Global Timing Register (SPGT) bit definitions */
 145 #define ISMT_SPGT_SPD_MASK      0xc0000000      /* SMBus Speed mask */
 146 #define ISMT_SPGT_SPD_80K       0x00            /* 80 kHz */
 147 #define ISMT_SPGT_SPD_100K      (0x1 << 30)     /* 100 kHz */
 148 #define ISMT_SPGT_SPD_400K      (0x2 << 30)     /* 400 kHz */
 149 #define ISMT_SPGT_SPD_1M        (0x3 << 30)     /* 1 MHz */
 150
 151
 152 /* MSI Control Register (MSICTL) bit definitions */
 153 #define ISMT_MSICTL_MSIE        0x01    /* MSI Enable */
 154
 155 /* iSMT Hardware Descriptor */
 156 struct ismt_desc {
 157         u8 tgtaddr_rw;  /* target address & r/w bit */
 158         u8 wr_len_cmd;  /* write length in bytes or a command */
 159         u8 rd_len;      /* read length */
 160         u8 control;     /* control bits */
 161         u8 status;      /* status bits */
 162         u8 retry;       /* collision retry and retry count */
 163         u8 rxbytes;     /* received bytes */
 164         u8 txbytes;     /* transmitted bytes */
 165         u32 dptr_low;   /* lower 32 bit of the data pointer */
 166         u32 dptr_high;  /* upper 32 bit of the data pointer */
 167 } __packed;
 168
 169 struct ismt_priv {
 170         struct i2c_adapter adapter;
 171         void __iomem *smba;                     /* PCI BAR */
 172         struct pci_dev *pci_dev;
 173         struct ismt_desc *hw;                   /* descriptor virt base addr */
 174         dma_addr_t io_rng_dma;                  /* descriptor HW base addr */
 175         u8 head;                                /* ring buffer head pointer */
 176         struct completion cmp;                  /* interrupt completion */
 177         u8 buffer[I2C_SMBUS_BLOCK_MAX + 16];    /* temp R/W data buffer */
 178 };
 179
 180 static const struct pci_device_id ismt_ids[] = {
 181         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT0) },
 182         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT1) },
 183         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMT) },
 184         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMT) },
 185         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EBG_SMT) },
 186         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMT) },
 187         { 0, }
 188 };
 189
 190 MODULE_DEVICE_TABLE(pci, ismt_ids);
 191
 192 /* Bus speed control bits for slow debuggers - refer to the docs for usage */
 193 static unsigned int bus_speed;
 194 module_param(bus_speed, uint, S_IRUGO);
 195 MODULE_PARM_DESC(bus_speed, "Bus Speed in kHz (0 = BIOS default)");
 196
 197 /**
 198  * __ismt_desc_dump() - dump the contents of a specific descriptor
 199  * @dev: the iSMT device
 200  * @desc: the iSMT hardware descriptor
 201  */
 202 static void __ismt_desc_dump(struct device *dev, const struct ismt_desc *desc)
 203 {
 204
 205         dev_dbg(dev, "Descriptor struct:  %p\n", desc);
 206         dev_dbg(dev, "\ttgtaddr_rw=0x%02X\n", desc->tgtaddr_rw);
 207         dev_dbg(dev, "\twr_len_cmd=0x%02X\n", desc->wr_len_cmd);
 208         dev_dbg(dev, "\trd_len=    0x%02X\n", desc->rd_len);
 209         dev_dbg(dev, "\tcontrol=   0x%02X\n", desc->control);
 210         dev_dbg(dev, "\tstatus=    0x%02X\n", desc->status);
 211         dev_dbg(dev, "\tretry=     0x%02X\n", desc->retry);
 212         dev_dbg(dev, "\trxbytes=   0x%02X\n", desc->rxbytes);
 213         dev_dbg(dev, "\ttxbytes=   0x%02X\n", desc->txbytes);
 214         dev_dbg(dev, "\tdptr_low=  0x%08X\n", desc->dptr_low);
 215         dev_dbg(dev, "\tdptr_high= 0x%08X\n", desc->dptr_high);
 216 }
 217 /**
 218  * ismt_desc_dump() - dump the contents of a descriptor for debug purposes
 219  * @priv: iSMT private data
 220  */
 221 static void ismt_desc_dump(struct ismt_priv *priv)
 222 {
 223         struct device *dev = &priv->pci_dev->dev;
 224         struct ismt_desc *desc = &priv->hw[priv->head];
 225
 226         dev_dbg(dev, "Dump of the descriptor struct:  0x%X\n", priv->head);
 227         __ismt_desc_dump(dev, desc);
 228 }
 229
 230 /**
 231  * ismt_gen_reg_dump() - dump the iSMT General Registers
 232  * @priv: iSMT private data
 233  */
 234 static void ismt_gen_reg_dump(struct ismt_priv *priv)
 235 {
 236         struct device *dev = &priv->pci_dev->dev;
 237
 238         dev_dbg(dev, "Dump of the iSMT General Registers\n");
 239         dev_dbg(dev, "  GCTRL.... : (0x%p)=0x%X\n",
 240                 priv->smba + ISMT_GR_GCTRL,
 241                 readl(priv->smba + ISMT_GR_GCTRL));
 242         dev_dbg(dev, "  SMTICL... : (0x%p)=0x%016llX\n",
 243                 priv->smba + ISMT_GR_SMTICL,
 244                 (long long unsigned int)readq(priv->smba + ISMT_GR_SMTICL));
 245         dev_dbg(dev, "  ERRINTMSK : (0x%p)=0x%X\n",
 246                 priv->smba + ISMT_GR_ERRINTMSK,
 247                 readl(priv->smba + ISMT_GR_ERRINTMSK));
 248         dev_dbg(dev, "  ERRAERMSK : (0x%p)=0x%X\n",
 249                 priv->smba + ISMT_GR_ERRAERMSK,
 250                 readl(priv->smba + ISMT_GR_ERRAERMSK));
 251         dev_dbg(dev, "  ERRSTS... : (0x%p)=0x%X\n",
 252                 priv->smba + ISMT_GR_ERRSTS,
 253                 readl(priv->smba + ISMT_GR_ERRSTS));
 254         dev_dbg(dev, "  ERRINFO.. : (0x%p)=0x%X\n",
 255                 priv->smba + ISMT_GR_ERRINFO,
 256                 readl(priv->smba + ISMT_GR_ERRINFO));
 257 }
 258
 259 /**
 260  * ismt_mstr_reg_dump() - dump the iSMT Master Registers
 261  * @priv: iSMT private data
 262  */
 263 static void ismt_mstr_reg_dump(struct ismt_priv *priv)
 264 {
 265         struct device *dev = &priv->pci_dev->dev;
 266
 267         dev_dbg(dev, "Dump of the iSMT Master Registers\n");
 268         dev_dbg(dev, "  MDBA..... : (0x%p)=0x%016llX\n",
 269                 priv->smba + ISMT_MSTR_MDBA,
 270                 (long long unsigned int)readq(priv->smba + ISMT_MSTR_MDBA));
 271         dev_dbg(dev, "  MCTRL.... : (0x%p)=0x%X\n",
 272                 priv->smba + ISMT_MSTR_MCTRL,
 273                 readl(priv->smba + ISMT_MSTR_MCTRL));
 274         dev_dbg(dev, "  MSTS..... : (0x%p)=0x%X\n",
 275                 priv->smba + ISMT_MSTR_MSTS,
 276                 readl(priv->smba + ISMT_MSTR_MSTS));
 277         dev_dbg(dev, "  MDS...... : (0x%p)=0x%X\n",
 278                 priv->smba + ISMT_MSTR_MDS,
 279                 readl(priv->smba + ISMT_MSTR_MDS));
 280         dev_dbg(dev, "  RPOLICY.. : (0x%p)=0x%X\n",
 281                 priv->smba + ISMT_MSTR_RPOLICY,
 282                 readl(priv->smba + ISMT_MSTR_RPOLICY));
 283         dev_dbg(dev, "  SPGT..... : (0x%p)=0x%X\n",
 284                 priv->smba + ISMT_SPGT,
 285                 readl(priv->smba + ISMT_SPGT));
 286 }
 287
 288 /**
 289  * ismt_submit_desc() - add a descriptor to the ring
 290  * @priv: iSMT private data
 291  */
 292 static void ismt_submit_desc(struct ismt_priv *priv)
 293 {
 294         uint fmhp;
 295         uint val;
 296
 297         ismt_desc_dump(priv);
 298         ismt_gen_reg_dump(priv);
 299         ismt_mstr_reg_dump(priv);
 300
 301         /* Set the FMHP (Firmware Master Head Pointer)*/
 302         fmhp = ((priv->head + 1) % ISMT_DESC_ENTRIES) << 16;
 303         val = readl(priv->smba + ISMT_MSTR_MCTRL);
 304         writel((val & ~ISMT_MCTRL_FMHP) | fmhp,
 305                priv->smba + ISMT_MSTR_MCTRL);
 306
 307         /* Set the start bit */
 308         val = readl(priv->smba + ISMT_MSTR_MCTRL);
 309         writel(val | ISMT_MCTRL_SS,
 310                priv->smba + ISMT_MSTR_MCTRL);
 311 }
 312
 313 /**
 314  * ismt_process_desc() - handle the completion of the descriptor
 315  * @desc: the iSMT hardware descriptor
 316  * @data: data buffer from the upper layer
 317  * @priv: ismt_priv struct holding our dma buffer
 318  * @size: SMBus transaction type
 319  * @read_write: flag to indicate if this is a read or write
 320  */
 321 static int ismt_process_desc(const struct ismt_desc *desc,
 322                              union i2c_smbus_data *data,
 323                              struct ismt_priv *priv, int size,
 324                              char read_write)
 325 {
 326         u8 *dma_buffer = PTR_ALIGN(&priv->buffer[0], 16);
 327
 328         dev_dbg(&priv->pci_dev->dev, "Processing completed descriptor\n");
 329         __ismt_desc_dump(&priv->pci_dev->dev, desc);
 330         ismt_gen_reg_dump(priv);
 331         ismt_mstr_reg_dump(priv);
 332
 333         if (desc->status & ISMT_DESC_SCS) {
 334                 if (read_write == I2C_SMBUS_WRITE &&
 335                     size != I2C_SMBUS_PROC_CALL &&
 336                     size != I2C_SMBUS_BLOCK_PROC_CALL)
 337                         return 0;
 338
 339                 switch (size) {
 340                 case I2C_SMBUS_BYTE:
 341                 case I2C_SMBUS_BYTE_DATA:
 342                         data->byte = dma_buffer[0];
 343                         break;
 344                 case I2C_SMBUS_WORD_DATA:
 345                 case I2C_SMBUS_PROC_CALL:
 346                         data->word = dma_buffer[0] | (dma_buffer[1] << 8);
 347                         break;
 348                 case I2C_SMBUS_BLOCK_DATA:
 349                 case I2C_SMBUS_BLOCK_PROC_CALL:
 350                         if (desc->rxbytes != dma_buffer[0] + 1)
 351                                 return -EMSGSIZE;
 352
 353                         memcpy(data->block, dma_buffer, desc->rxbytes);
 354                         break;
 355                 case I2C_SMBUS_I2C_BLOCK_DATA:
 356                         memcpy(&data->block[1], dma_buffer, desc->rxbytes);
 357                         data->block[0] = desc->rxbytes;
 358                         break;
 359                 }
 360                 return 0;
 361         }
 362
 363         if (likely(desc->status & ISMT_DESC_NAK))
 364                 return -ENXIO;
 365
 366         if (desc->status & ISMT_DESC_CRC)
 367                 return -EBADMSG;
 368
 369         if (desc->status & ISMT_DESC_COL)
 370                 return -EAGAIN;
 371
 372         if (desc->status & ISMT_DESC_LPR)
 373                 return -EPROTO;
 374
 375         if (desc->status & (ISMT_DESC_DLTO | ISMT_DESC_CLTO))
 376                 return -ETIMEDOUT;
 377
 378         return -EIO;
 379 }
 380
 381 /**
 382  * ismt_access() - process an SMBus command
 383  * @adap: the i2c host adapter
 384  * @addr: address of the i2c/SMBus target
 385  * @flags: command options
 386  * @read_write: read from or write to device
 387  * @command: the i2c/SMBus command to issue
 388  * @size: SMBus transaction type
 389  * @data: read/write data buffer
 390  */
 391 static int ismt_access(struct i2c_adapter *adap, u16 addr,
 392                        unsigned short flags, char read_write, u8 command,
 393                        int size, union i2c_smbus_data *data)
 394 {
 395         int ret;
 396         unsigned long time_left;
 397         dma_addr_t dma_addr = 0; /* address of the data buffer */
 398         u8 dma_size = 0;
 399         enum dma_data_direction dma_direction = 0;
 400         struct ismt_desc *desc;
 401         struct ismt_priv *priv = i2c_get_adapdata(adap);
 402         struct device *dev = &priv->pci_dev->dev;
 403         u8 *dma_buffer = PTR_ALIGN(&priv->buffer[0], 16);
 404
 405         desc = &priv->hw[priv->head];
 406
 407         /* Initialize the DMA buffer */
 408         memset(priv->buffer, 0, sizeof(priv->buffer));
 409
 410         /* Initialize the descriptor */
 411         memset(desc, 0, sizeof(struct ismt_desc));
 412         desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, read_write);
 413
 414         /* Initialize common control bits */
 415         if (likely(pci_dev_msi_enabled(priv->pci_dev)))
 416                 desc->control = ISMT_DESC_INT | ISMT_DESC_FAIR;
 417         else
 418                 desc->control = ISMT_DESC_FAIR;
 419
 420         if ((flags & I2C_CLIENT_PEC) && (size != I2C_SMBUS_QUICK)
 421             && (size != I2C_SMBUS_I2C_BLOCK_DATA))
 422                 desc->control |= ISMT_DESC_PEC;
 423
 424         switch (size) {
 425         case I2C_SMBUS_QUICK:
 426                 dev_dbg(dev, "I2C_SMBUS_QUICK\n");
 427                 break;
 428
 429         case I2C_SMBUS_BYTE:
 430                 if (read_write == I2C_SMBUS_WRITE) {
 431                         /*
 432                          * Send Byte
 433                          * The command field contains the write data
 434                          */
 435                         dev_dbg(dev, "I2C_SMBUS_BYTE:  WRITE\n");
 436                         desc->control |= ISMT_DESC_CWRL;
 437                         desc->wr_len_cmd = command;
 438                 } else {
 439                         /* Receive Byte */
 440                         dev_dbg(dev, "I2C_SMBUS_BYTE:  READ\n");
 441                         dma_size = 1;
 442                         dma_direction = DMA_FROM_DEVICE;
 443                         desc->rd_len = 1;
 444                 }
 445                 break;
 446
 447         case I2C_SMBUS_BYTE_DATA:
 448                 if (read_write == I2C_SMBUS_WRITE) {
 449                         /*
 450                          * Write Byte
 451                          * Command plus 1 data byte
 452                          */
 453                         dev_dbg(dev, "I2C_SMBUS_BYTE_DATA:  WRITE\n");
 454                         desc->wr_len_cmd = 2;
 455                         dma_size = 2;
 456                         dma_direction = DMA_TO_DEVICE;
 457                         dma_buffer[0] = command;
 458                         dma_buffer[1] = data->byte;
 459                 } else {
 460                         /* Read Byte */
 461                         dev_dbg(dev, "I2C_SMBUS_BYTE_DATA:  READ\n");
 462                         desc->control |= ISMT_DESC_CWRL;
 463                         desc->wr_len_cmd = command;
 464                         desc->rd_len = 1;
 465                         dma_size = 1;
 466                         dma_direction = DMA_FROM_DEVICE;
 467                 }
 468                 break;
 469
 470         case I2C_SMBUS_WORD_DATA:
 471                 if (read_write == I2C_SMBUS_WRITE) {
 472                         /* Write Word */
 473                         dev_dbg(dev, "I2C_SMBUS_WORD_DATA:  WRITE\n");
 474                         desc->wr_len_cmd = 3;
 475                         dma_size = 3;
 476                         dma_direction = DMA_TO_DEVICE;
 477                         dma_buffer[0] = command;
 478                         dma_buffer[1] = data->word & 0xff;
 479                         dma_buffer[2] = data->word >> 8;
 480                 } else {
 481                         /* Read Word */
 482                         dev_dbg(dev, "I2C_SMBUS_WORD_DATA:  READ\n");
 483                         desc->wr_len_cmd = command;
 484                         desc->control |= ISMT_DESC_CWRL;
 485                         desc->rd_len = 2;
 486                         dma_size = 2;
 487                         dma_direction = DMA_FROM_DEVICE;
 488                 }
 489                 break;
 490
 491         case I2C_SMBUS_PROC_CALL:
 492                 dev_dbg(dev, "I2C_SMBUS_PROC_CALL\n");
 493                 desc->wr_len_cmd = 3;
 494                 desc->rd_len = 2;
 495                 dma_size = 3;
 496                 dma_direction = DMA_BIDIRECTIONAL;
 497                 dma_buffer[0] = command;
 498                 dma_buffer[1] = data->word & 0xff;
 499                 dma_buffer[2] = data->word >> 8;
 500                 break;
 501
 502         case I2C_SMBUS_BLOCK_DATA:
 503                 if (read_write == I2C_SMBUS_WRITE) {
 504                         /* Block Write */
 505                         dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA:  WRITE\n");
 506                         dma_size = data->block[0] + 1;
 507                         dma_direction = DMA_TO_DEVICE;
 508                         desc->wr_len_cmd = dma_size;
 509                         desc->control |= ISMT_DESC_BLK;
 510                         dma_buffer[0] = command;
 511                         memcpy(&dma_buffer[1], &data->block[1], dma_size - 1);
 512                 } else {
 513                         /* Block Read */
 514                         dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA:  READ\n");
 515                         dma_size = I2C_SMBUS_BLOCK_MAX;
 516                         dma_direction = DMA_FROM_DEVICE;
 517                         desc->rd_len = dma_size;
 518                         desc->wr_len_cmd = command;
 519                         desc->control |= (ISMT_DESC_BLK | ISMT_DESC_CWRL);
 520                 }
 521                 break;
 522
 523         case I2C_SMBUS_BLOCK_PROC_CALL:
 524                 dev_dbg(dev, "I2C_SMBUS_BLOCK_PROC_CALL\n");
 525                 dma_size = I2C_SMBUS_BLOCK_MAX;
 526                 desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, 1);
 527                 desc->wr_len_cmd = data->block[0] + 1;
 528                 desc->rd_len = dma_size;
 529                 desc->control |= ISMT_DESC_BLK;
 530                 dma_direction = DMA_BIDIRECTIONAL;
 531                 dma_buffer[0] = command;
 532                 memcpy(&dma_buffer[1], &data->block[1], data->block[0]);
 533                 break;
 534
 535         case I2C_SMBUS_I2C_BLOCK_DATA:
 536                 /* Make sure the length is valid */
 537                 if (data->block[0] < 1)
 538                         data->block[0] = 1;
 539
 540                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
 541                         data->block[0] = I2C_SMBUS_BLOCK_MAX;
 542
 543                 if (read_write == I2C_SMBUS_WRITE) {
 544                         /* i2c Block Write */
 545                         dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA:  WRITE\n");
 546                         dma_size = data->block[0] + 1;
 547                         dma_direction = DMA_TO_DEVICE;
 548                         desc->wr_len_cmd = dma_size;
 549                         desc->control |= ISMT_DESC_I2C;
 550                         dma_buffer[0] = command;
 551                         memcpy(&dma_buffer[1], &data->block[1], dma_size - 1);
 552                 } else {
 553                         /* i2c Block Read */
 554                         dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA:  READ\n");
 555                         dma_size = data->block[0];
 556                         dma_direction = DMA_FROM_DEVICE;
 557                         desc->rd_len = dma_size;
 558                         desc->wr_len_cmd = command;
 559                         desc->control |= (ISMT_DESC_I2C | ISMT_DESC_CWRL);
 560                         /*
 561                          * Per the "Table 15-15. I2C Commands",
 562                          * in the External Design Specification (EDS),
 563                          * (Document Number: 508084, Revision: 2.0),
 564                          * the _rw bit must be 0
 565                          */
 566                         desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, 0);
 567                 }
 568                 break;
 569
 570         default:
 571                 dev_err(dev, "Unsupported transaction %d\n",
 572                         size);
 573                 return -EOPNOTSUPP;
 574         }
 575
 576         /* map the data buffer */
 577         if (dma_size != 0) {
 578                 dev_dbg(dev, " dev=%p\n", dev);
 579                 dev_dbg(dev, " data=%p\n", data);
 580                 dev_dbg(dev, " dma_buffer=%p\n", dma_buffer);
 581                 dev_dbg(dev, " dma_size=%d\n", dma_size);
 582                 dev_dbg(dev, " dma_direction=%d\n", dma_direction);
 583
 584                 dma_addr = dma_map_single(dev,
 585                                       dma_buffer,
 586                                       dma_size,
 587                                       dma_direction);
 588
 589                 if (dma_mapping_error(dev, dma_addr)) {
 590                         dev_err(dev, "Error in mapping dma buffer %p\n",
 591                                 dma_buffer);
 592                         return -EIO;
 593                 }
 594
 595                 dev_dbg(dev, " dma_addr = %pad\n", &dma_addr);
 596
 597                 desc->dptr_low = lower_32_bits(dma_addr);
 598                 desc->dptr_high = upper_32_bits(dma_addr);
 599         }
 600
 601         reinit_completion(&priv->cmp);
 602
 603         /* Add the descriptor */
 604         ismt_submit_desc(priv);
 605
 606         /* Now we wait for interrupt completion, 1s */
 607         time_left = wait_for_completion_timeout(&priv->cmp, HZ*1);
 608
 609         /* unmap the data buffer */
 610         if (dma_size != 0)
 611                 dma_unmap_single(dev, dma_addr, dma_size, dma_direction);
 612
 613         if (unlikely(!time_left)) {
 614                 dev_err(dev, "completion wait timed out\n");
 615                 ret = -ETIMEDOUT;
 616                 goto out;
 617         }
 618
 619         /* do any post processing of the descriptor here */
 620         ret = ismt_process_desc(desc, data, priv, size, read_write);
 621
 622 out:
 623         /* Update the ring pointer */
 624         priv->head++;
 625         priv->head %= ISMT_DESC_ENTRIES;
 626
 627         return ret;
 628 }
 629
 630 /**
 631  * ismt_func() - report which i2c commands are supported by this adapter
 632  * @adap: the i2c host adapter
 633  */
 634 static u32 ismt_func(struct i2c_adapter *adap)
 635 {
 636         return I2C_FUNC_SMBUS_QUICK             |
 637                I2C_FUNC_SMBUS_BYTE              |
 638                I2C_FUNC_SMBUS_BYTE_DATA         |
 639                I2C_FUNC_SMBUS_WORD_DATA         |
 640                I2C_FUNC_SMBUS_PROC_CALL         |
 641                I2C_FUNC_SMBUS_BLOCK_PROC_CALL   |
 642                I2C_FUNC_SMBUS_BLOCK_DATA        |
 643                I2C_FUNC_SMBUS_I2C_BLOCK         |
 644                I2C_FUNC_SMBUS_PEC;
 645 }
 646
 647 static const struct i2c_algorithm smbus_algorithm = {
 648         .smbus_xfer     = ismt_access,
 649         .functionality  = ismt_func,
 650 };
 651
 652 /**
 653  * ismt_handle_isr() - interrupt handler bottom half
 654  * @priv: iSMT private data
 655  */
 656 static irqreturn_t ismt_handle_isr(struct ismt_priv *priv)
 657 {
 658         complete(&priv->cmp);
 659
 660         return IRQ_HANDLED;
 661 }
 662
 663
 664 /**
 665  * ismt_do_interrupt() - IRQ interrupt handler
 666  * @vec: interrupt vector
 667  * @data: iSMT private data
 668  */
 669 static irqreturn_t ismt_do_interrupt(int vec, void *data)
 670 {
 671         u32 val;
 672         struct ismt_priv *priv = data;
 673
 674         /*
 675          * check to see it's our interrupt, return IRQ_NONE if not ours
 676          * since we are sharing interrupt
 677          */
 678         val = readl(priv->smba + ISMT_MSTR_MSTS);
 679
 680         if (!(val & (ISMT_MSTS_MIS | ISMT_MSTS_MEIS)))
 681                 return IRQ_NONE;
 682         else
 683                 writel(val | ISMT_MSTS_MIS | ISMT_MSTS_MEIS,
 684                        priv->smba + ISMT_MSTR_MSTS);
 685
 686         return ismt_handle_isr(priv);
 687 }
 688
 689 /**
 690  * ismt_do_msi_interrupt() - MSI interrupt handler
 691  * @vec: interrupt vector
 692  * @data: iSMT private data
 693  */
 694 static irqreturn_t ismt_do_msi_interrupt(int vec, void *data)
 695 {
 696         return ismt_handle_isr(data);
 697 }
 698
 699 /**
 700  * ismt_hw_init() - initialize the iSMT hardware
 701  * @priv: iSMT private data
 702  */
 703 static void ismt_hw_init(struct ismt_priv *priv)
 704 {
 705         u32 val;
 706         struct device *dev = &priv->pci_dev->dev;
 707
 708         /* initialize the Master Descriptor Base Address (MDBA) */
 709         writeq(priv->io_rng_dma, priv->smba + ISMT_MSTR_MDBA);
 710
 711         /* initialize the Master Control Register (MCTRL) */
 712         writel(ISMT_MCTRL_MEIE, priv->smba + ISMT_MSTR_MCTRL);
 713
 714         /* initialize the Master Status Register (MSTS) */
 715         writel(0, priv->smba + ISMT_MSTR_MSTS);
 716
 717         /* initialize the Master Descriptor Size (MDS) */
 718         val = readl(priv->smba + ISMT_MSTR_MDS);
 719         writel((val & ~ISMT_MDS_MASK) | (ISMT_DESC_ENTRIES - 1),
 720                 priv->smba + ISMT_MSTR_MDS);
 721
 722         /*
 723          * Set the SMBus speed (could use this for slow HW debuggers)
 724          */
 725
 726         val = readl(priv->smba + ISMT_SPGT);
 727
 728         switch (bus_speed) {
 729         case 0:
 730                 break;
 731
 732         case 80:
 733                 dev_dbg(dev, "Setting SMBus clock to 80 kHz\n");
 734                 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_80K),
 735                         priv->smba + ISMT_SPGT);
 736                 break;
 737
 738         case 100:
 739                 dev_dbg(dev, "Setting SMBus clock to 100 kHz\n");
 740                 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_100K),
 741                         priv->smba + ISMT_SPGT);
 742                 break;
 743
 744         case 400:
 745                 dev_dbg(dev, "Setting SMBus clock to 400 kHz\n");
 746                 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_400K),
 747                         priv->smba + ISMT_SPGT);
 748                 break;
 749
 750         case 1000:
 751                 dev_dbg(dev, "Setting SMBus clock to 1000 kHz\n");
 752                 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_1M),
 753                         priv->smba + ISMT_SPGT);
 754                 break;
 755
 756         default:
 757                 dev_warn(dev, "Invalid SMBus clock speed, only 0, 80, 100, 400, and 1000 are valid\n");
 758                 break;
 759         }
 760
 761         val = readl(priv->smba + ISMT_SPGT);
 762
 763         switch (val & ISMT_SPGT_SPD_MASK) {
 764         case ISMT_SPGT_SPD_80K:
 765                 bus_speed = 80;
 766                 break;
 767         case ISMT_SPGT_SPD_100K:
 768                 bus_speed = 100;
 769                 break;
 770         case ISMT_SPGT_SPD_400K:
 771                 bus_speed = 400;
 772                 break;
 773         case ISMT_SPGT_SPD_1M:
 774                 bus_speed = 1000;
 775                 break;
 776         }
 777         dev_dbg(dev, "SMBus clock is running at %d kHz\n", bus_speed);
 778 }
 779
 780 /**
 781  * ismt_dev_init() - initialize the iSMT data structures
 782  * @priv: iSMT private data
 783  */
 784 static int ismt_dev_init(struct ismt_priv *priv)
 785 {
 786         /* allocate memory for the descriptor */
 787         priv->hw = dmam_alloc_coherent(&priv->pci_dev->dev,
 788                                        (ISMT_DESC_ENTRIES
 789                                                * sizeof(struct ismt_desc)),
 790                                        &priv->io_rng_dma,
 791                                        GFP_KERNEL);
 792         if (!priv->hw)
 793                 return -ENOMEM;
 794
 795         priv->head = 0;
 796         init_completion(&priv->cmp);
 797
 798         return 0;
 799 }
 800
 801 /**
 802  * ismt_int_init() - initialize interrupts
 803  * @priv: iSMT private data
 804  */
 805 static int ismt_int_init(struct ismt_priv *priv)
 806 {
 807         int err;
 808
 809         /* Try using MSI interrupts */
 810         err = pci_enable_msi(priv->pci_dev);
 811         if (err)
 812                 goto intx;
 813
 814         err = devm_request_irq(&priv->pci_dev->dev,
 815                                priv->pci_dev->irq,
 816                                ismt_do_msi_interrupt,
 817                                0,
 818                                "ismt-msi",
 819                                priv);
 820         if (err) {
 821                 pci_disable_msi(priv->pci_dev);
 822                 goto intx;
 823         }
 824
 825         return 0;
 826
 827         /* Try using legacy interrupts */
 828 intx:
 829         dev_warn(&priv->pci_dev->dev,
 830                  "Unable to use MSI interrupts, falling back to legacy\n");
 831
 832         err = devm_request_irq(&priv->pci_dev->dev,
 833                                priv->pci_dev->irq,
 834                                ismt_do_interrupt,
 835                                IRQF_SHARED,
 836                                "ismt-intx",
 837                                priv);
 838         if (err) {
 839                 dev_err(&priv->pci_dev->dev, "no usable interrupts\n");
 840                 return err;
 841         }
 842
 843         return 0;
 844 }
 845
 846 static struct pci_driver ismt_driver;
 847
 848 /**
 849  * ismt_probe() - probe for iSMT devices
 850  * @pdev: PCI-Express device
 851  * @id: PCI-Express device ID
 852  */
 853 static int
 854 ismt_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 855 {
 856         int err;
 857         struct ismt_priv *priv;
 858         unsigned long start, len;
 859
 860         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 861         if (!priv)
 862                 return -ENOMEM;
 863
 864         pci_set_drvdata(pdev, priv);
 865
 866         i2c_set_adapdata(&priv->adapter, priv);
 867         priv->adapter.owner = THIS_MODULE;
 868         priv->adapter.class = I2C_CLASS_HWMON;
 869         priv->adapter.algo = &smbus_algorithm;
 870         priv->adapter.dev.parent = &pdev->dev;
 871         ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&pdev->dev));
 872         priv->adapter.retries = ISMT_MAX_RETRIES;
 873
 874         priv->pci_dev = pdev;
 875
 876         err = pcim_enable_device(pdev);
 877         if (err) {
 878                 dev_err(&pdev->dev, "Failed to enable SMBus PCI device (%d)\n",
 879                         err);
 880                 return err;
 881         }
 882
 883         /* enable bus mastering */
 884         pci_set_master(pdev);
 885
 886         /* Determine the address of the SMBus area */
 887         start = pci_resource_start(pdev, SMBBAR);
 888         len = pci_resource_len(pdev, SMBBAR);
 889         if (!start || !len) {
 890                 dev_err(&pdev->dev,
 891                         "SMBus base address uninitialized, upgrade BIOS\n");
 892                 return -ENODEV;
 893         }
 894
 895         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
 896                  "SMBus iSMT adapter at %lx", start);
 897
 898         dev_dbg(&priv->pci_dev->dev, " start=0x%lX\n", start);
 899         dev_dbg(&priv->pci_dev->dev, " len=0x%lX\n", len);
 900
 901         err = acpi_check_resource_conflict(&pdev->resource[SMBBAR]);
 902         if (err) {
 903                 dev_err(&pdev->dev, "ACPI resource conflict!\n");
 904                 return err;
 905         }
 906
 907         err = pci_request_region(pdev, SMBBAR, ismt_driver.name);
 908         if (err) {
 909                 dev_err(&pdev->dev,
 910                         "Failed to request SMBus region 0x%lx-0x%lx\n",
 911                         start, start + len);
 912                 return err;
 913         }
 914
 915         priv->smba = pcim_iomap(pdev, SMBBAR, len);
 916         if (!priv->smba) {
 917                 dev_err(&pdev->dev, "Unable to ioremap SMBus BAR\n");
 918                 return -ENODEV;
 919         }
 920
 921         if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) ||
 922             (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) {
 923                 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
 924                     (pci_set_consistent_dma_mask(pdev,
 925                                                  DMA_BIT_MASK(32)) != 0)) {
 926                         dev_err(&pdev->dev, "pci_set_dma_mask fail %p\n",
 927                                 pdev);
 928                         return -ENODEV;
 929                 }
 930         }
 931
 932         err = ismt_dev_init(priv);
 933         if (err)
 934                 return err;
 935
 936         ismt_hw_init(priv);
 937
 938         err = ismt_int_init(priv);
 939         if (err)
 940                 return err;
 941
 942         err = i2c_add_adapter(&priv->adapter);
 943         if (err)
 944                 return -ENODEV;
 945         return 0;
 946 }
 947
 948 /**
 949  * ismt_remove() - release driver resources
 950  * @pdev: PCI-Express device
 951  */
 952 static void ismt_remove(struct pci_dev *pdev)
 953 {
 954         struct ismt_priv *priv = pci_get_drvdata(pdev);
 955
 956         i2c_del_adapter(&priv->adapter);
 957 }
 958
 959 static struct pci_driver ismt_driver = {
 960         .name = "ismt_smbus",
 961         .id_table = ismt_ids,
 962         .probe = ismt_probe,
 963         .remove = ismt_remove,
 964 };
 965
 966 module_pci_driver(ismt_driver);
 967
 968 MODULE_LICENSE("Dual BSD/GPL");
 969 MODULE_AUTHOR("Bill E. Brown <bill.e.brown@intel.com>");
 970 MODULE_DESCRIPTION("Intel SMBus Message Transport (iSMT) driver");