drivers/i2c/busses/i2c-imx.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *      Copyright (C) 2002 Motorola GSG-China
   4  *
   5  * Author:
   6  *      Darius Augulis, Teltonika Inc.
   7  *
   8  * Desc.:
   9  *      Implementation of I2C Adapter/Algorithm Driver
  10  *      for I2C Bus integrated in Freescale i.MX/MXC processors
  11  *
  12  *      Derived from Motorola GSG China I2C example driver
  13  *
  14  *      Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
  15  *      Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
  16  *      Copyright (C) 2007 RightHand Technologies, Inc.
  17  *      Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
  18  *
  19  *      Copyright 2013 Freescale Semiconductor, Inc.
  20  *
  21  */
  22
  23 #include <linux/acpi.h>
  24 #include <linux/clk.h>
  25 #include <linux/completion.h>
  26 #include <linux/delay.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/dmaengine.h>
  29 #include <linux/dmapool.h>
  30 #include <linux/err.h>
  31 #include <linux/errno.h>
  32 #include <linux/gpio/consumer.h>
  33 #include <linux/i2c.h>
  34 #include <linux/init.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/io.h>
  37 #include <linux/iopoll.h>
  38 #include <linux/kernel.h>
  39 #include <linux/module.h>
  40 #include <linux/of.h>
  41 #include <linux/of_device.h>
  42 #include <linux/of_dma.h>
  43 #include <linux/pinctrl/consumer.h>
  44 #include <linux/platform_data/i2c-imx.h>
  45 #include <linux/platform_device.h>
  46 #include <linux/pm_runtime.h>
  47 #include <linux/sched.h>
  48 #include <linux/slab.h>
  49
  50 /* This will be the driver name the kernel reports */
  51 #define DRIVER_NAME "imx-i2c"
  52
  53 /*
  54  * Enable DMA if transfer byte size is bigger than this threshold.
  55  * As the hardware request, it must bigger than 4 bytes.\
  56  * I have set '16' here, maybe it's not the best but I think it's
  57  * the appropriate.
  58  */
  59 #define DMA_THRESHOLD   16
  60 #define DMA_TIMEOUT     1000
  61
  62 /* IMX I2C registers:
  63  * the I2C register offset is different between SoCs,
  64  * to provid support for all these chips, split the
  65  * register offset into a fixed base address and a
  66  * variable shift value, then the full register offset
  67  * will be calculated by
  68  * reg_off = ( reg_base_addr << reg_shift)
  69  */
  70 #define IMX_I2C_IADR    0x00    /* i2c slave address */
  71 #define IMX_I2C_IFDR    0x01    /* i2c frequency divider */
  72 #define IMX_I2C_I2CR    0x02    /* i2c control */
  73 #define IMX_I2C_I2SR    0x03    /* i2c status */
  74 #define IMX_I2C_I2DR    0x04    /* i2c transfer data */
  75
  76 #define IMX_I2C_REGSHIFT        2
  77 #define VF610_I2C_REGSHIFT      0
  78
  79 /* Bits of IMX I2C registers */
  80 #define I2SR_RXAK       0x01
  81 #define I2SR_IIF        0x02
  82 #define I2SR_SRW        0x04
  83 #define I2SR_IAL        0x10
  84 #define I2SR_IBB        0x20
  85 #define I2SR_IAAS       0x40
  86 #define I2SR_ICF        0x80
  87 #define I2CR_DMAEN      0x02
  88 #define I2CR_RSTA       0x04
  89 #define I2CR_TXAK       0x08
  90 #define I2CR_MTX        0x10
  91 #define I2CR_MSTA       0x20
  92 #define I2CR_IIEN       0x40
  93 #define I2CR_IEN        0x80
  94
  95 /* register bits different operating codes definition:
  96  * 1) I2SR: Interrupt flags clear operation differ between SoCs:
  97  * - write zero to clear(w0c) INT flag on i.MX,
  98  * - but write one to clear(w1c) INT flag on Vybrid.
  99  * 2) I2CR: I2C module enable operation also differ between SoCs:
 100  * - set I2CR_IEN bit enable the module on i.MX,
 101  * - but clear I2CR_IEN bit enable the module on Vybrid.
 102  */
 103 #define I2SR_CLR_OPCODE_W0C     0x0
 104 #define I2SR_CLR_OPCODE_W1C     (I2SR_IAL | I2SR_IIF)
 105 #define I2CR_IEN_OPCODE_0       0x0
 106 #define I2CR_IEN_OPCODE_1       I2CR_IEN
 107
 108 #define I2C_PM_TIMEOUT          10 /* ms */
 109
 110 /*
 111  * sorted list of clock divider, register value pairs
 112  * taken from table 26-5, p.26-9, Freescale i.MX
 113  * Integrated Portable System Processor Reference Manual
 114  * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
 115  *
 116  * Duplicated divider values removed from list
 117  */
 118 struct imx_i2c_clk_pair {
 119         u16     div;
 120         u16     val;
 121 };
 122
 123 static struct imx_i2c_clk_pair imx_i2c_clk_div[] = {
 124         { 22,   0x20 }, { 24,   0x21 }, { 26,   0x22 }, { 28,   0x23 },
 125         { 30,   0x00 }, { 32,   0x24 }, { 36,   0x25 }, { 40,   0x26 },
 126         { 42,   0x03 }, { 44,   0x27 }, { 48,   0x28 }, { 52,   0x05 },
 127         { 56,   0x29 }, { 60,   0x06 }, { 64,   0x2A }, { 72,   0x2B },
 128         { 80,   0x2C }, { 88,   0x09 }, { 96,   0x2D }, { 104,  0x0A },
 129         { 112,  0x2E }, { 128,  0x2F }, { 144,  0x0C }, { 160,  0x30 },
 130         { 192,  0x31 }, { 224,  0x32 }, { 240,  0x0F }, { 256,  0x33 },
 131         { 288,  0x10 }, { 320,  0x34 }, { 384,  0x35 }, { 448,  0x36 },
 132         { 480,  0x13 }, { 512,  0x37 }, { 576,  0x14 }, { 640,  0x38 },
 133         { 768,  0x39 }, { 896,  0x3A }, { 960,  0x17 }, { 1024, 0x3B },
 134         { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
 135         { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
 136         { 3072, 0x1E }, { 3840, 0x1F }
 137 };
 138
 139 /* Vybrid VF610 clock divider, register value pairs */
 140 static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = {
 141         { 20,   0x00 }, { 22,   0x01 }, { 24,   0x02 }, { 26,   0x03 },
 142         { 28,   0x04 }, { 30,   0x05 }, { 32,   0x09 }, { 34,   0x06 },
 143         { 36,   0x0A }, { 40,   0x07 }, { 44,   0x0C }, { 48,   0x0D },
 144         { 52,   0x43 }, { 56,   0x0E }, { 60,   0x45 }, { 64,   0x12 },
 145         { 68,   0x0F }, { 72,   0x13 }, { 80,   0x14 }, { 88,   0x15 },
 146         { 96,   0x19 }, { 104,  0x16 }, { 112,  0x1A }, { 128,  0x17 },
 147         { 136,  0x4F }, { 144,  0x1C }, { 160,  0x1D }, { 176,  0x55 },
 148         { 192,  0x1E }, { 208,  0x56 }, { 224,  0x22 }, { 228,  0x24 },
 149         { 240,  0x1F }, { 256,  0x23 }, { 288,  0x5C }, { 320,  0x25 },
 150         { 384,  0x26 }, { 448,  0x2A }, { 480,  0x27 }, { 512,  0x2B },
 151         { 576,  0x2C }, { 640,  0x2D }, { 768,  0x31 }, { 896,  0x32 },
 152         { 960,  0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
 153         { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
 154         { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
 155         { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
 156 };
 157
 158 enum imx_i2c_type {
 159         IMX1_I2C,
 160         IMX21_I2C,
 161         VF610_I2C,
 162 };
 163
 164 struct imx_i2c_hwdata {
 165         enum imx_i2c_type       devtype;
 166         unsigned                regshift;
 167         struct imx_i2c_clk_pair *clk_div;
 168         unsigned                ndivs;
 169         unsigned                i2sr_clr_opcode;
 170         unsigned                i2cr_ien_opcode;
 171 };
 172
 173 struct imx_i2c_dma {
 174         struct dma_chan         *chan_tx;
 175         struct dma_chan         *chan_rx;
 176         struct dma_chan         *chan_using;
 177         struct completion       cmd_complete;
 178         dma_addr_t              dma_buf;
 179         unsigned int            dma_len;
 180         enum dma_transfer_direction dma_transfer_dir;
 181         enum dma_data_direction dma_data_dir;
 182 };
 183
 184 struct imx_i2c_struct {
 185         struct i2c_adapter      adapter;
 186         struct clk              *clk;
 187         struct notifier_block   clk_change_nb;
 188         void __iomem            *base;
 189         wait_queue_head_t       queue;
 190         unsigned long           i2csr;
 191         unsigned int            disable_delay;
 192         int                     stopped;
 193         unsigned int            ifdr; /* IMX_I2C_IFDR */
 194         unsigned int            cur_clk;
 195         unsigned int            bitrate;
 196         const struct imx_i2c_hwdata     *hwdata;
 197         struct i2c_bus_recovery_info rinfo;
 198
 199         struct pinctrl *pinctrl;
 200         struct pinctrl_state *pinctrl_pins_default;
 201         struct pinctrl_state *pinctrl_pins_gpio;
 202
 203         struct imx_i2c_dma      *dma;
 204 };
 205
 206 static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
 207         .devtype                = IMX1_I2C,
 208         .regshift               = IMX_I2C_REGSHIFT,
 209         .clk_div                = imx_i2c_clk_div,
 210         .ndivs                  = ARRAY_SIZE(imx_i2c_clk_div),
 211         .i2sr_clr_opcode        = I2SR_CLR_OPCODE_W0C,
 212         .i2cr_ien_opcode        = I2CR_IEN_OPCODE_1,
 213
 214 };
 215
 216 static const struct imx_i2c_hwdata imx21_i2c_hwdata = {
 217         .devtype                = IMX21_I2C,
 218         .regshift               = IMX_I2C_REGSHIFT,
 219         .clk_div                = imx_i2c_clk_div,
 220         .ndivs                  = ARRAY_SIZE(imx_i2c_clk_div),
 221         .i2sr_clr_opcode        = I2SR_CLR_OPCODE_W0C,
 222         .i2cr_ien_opcode        = I2CR_IEN_OPCODE_1,
 223
 224 };
 225
 226 static struct imx_i2c_hwdata vf610_i2c_hwdata = {
 227         .devtype                = VF610_I2C,
 228         .regshift               = VF610_I2C_REGSHIFT,
 229         .clk_div                = vf610_i2c_clk_div,
 230         .ndivs                  = ARRAY_SIZE(vf610_i2c_clk_div),
 231         .i2sr_clr_opcode        = I2SR_CLR_OPCODE_W1C,
 232         .i2cr_ien_opcode        = I2CR_IEN_OPCODE_0,
 233
 234 };
 235
 236 static const struct of_device_id i2c_imx_dt_ids[] = {
 237         { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, },
 238         { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, },
 239         { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, },
 240         { /* sentinel */ }
 241 };
 242 MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids);
 243
 244 static const struct acpi_device_id i2c_imx_acpi_ids[] = {
 245         {"NXP0001", .driver_data = (kernel_ulong_t)&vf610_i2c_hwdata},
 246         { }
 247 };
 248 MODULE_DEVICE_TABLE(acpi, i2c_imx_acpi_ids);
 249
 250 static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)
 251 {
 252         return i2c_imx->hwdata->devtype == IMX1_I2C;
 253 }
 254
 255 static inline void imx_i2c_write_reg(unsigned int val,
 256                 struct imx_i2c_struct *i2c_imx, unsigned int reg)
 257 {
 258         writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
 259 }
 260
 261 static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,
 262                 unsigned int reg)
 263 {
 264         return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
 265 }
 266
 267 /* Functions for DMA support */
 268 static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
 269                                                 dma_addr_t phy_addr)
 270 {
 271         struct imx_i2c_dma *dma;
 272         struct dma_slave_config dma_sconfig;
 273         struct device *dev = &i2c_imx->adapter.dev;
 274         int ret;
 275
 276         dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
 277         if (!dma)
 278                 return;
 279
 280         dma->chan_tx = dma_request_chan(dev, "tx");
 281         if (IS_ERR(dma->chan_tx)) {
 282                 ret = PTR_ERR(dma->chan_tx);
 283                 if (ret != -ENODEV && ret != -EPROBE_DEFER)
 284                         dev_err(dev, "can't request DMA tx channel (%d)\n", ret);
 285                 goto fail_al;
 286         }
 287
 288         dma_sconfig.dst_addr = phy_addr +
 289                                 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
 290         dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 291         dma_sconfig.dst_maxburst = 1;
 292         dma_sconfig.direction = DMA_MEM_TO_DEV;
 293         ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig);
 294         if (ret < 0) {
 295                 dev_err(dev, "can't configure tx channel (%d)\n", ret);
 296                 goto fail_tx;
 297         }
 298
 299         dma->chan_rx = dma_request_chan(dev, "rx");
 300         if (IS_ERR(dma->chan_rx)) {
 301                 ret = PTR_ERR(dma->chan_rx);
 302                 if (ret != -ENODEV && ret != -EPROBE_DEFER)
 303                         dev_err(dev, "can't request DMA rx channel (%d)\n", ret);
 304                 goto fail_tx;
 305         }
 306
 307         dma_sconfig.src_addr = phy_addr +
 308                                 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
 309         dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 310         dma_sconfig.src_maxburst = 1;
 311         dma_sconfig.direction = DMA_DEV_TO_MEM;
 312         ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig);
 313         if (ret < 0) {
 314                 dev_err(dev, "can't configure rx channel (%d)\n", ret);
 315                 goto fail_rx;
 316         }
 317
 318         i2c_imx->dma = dma;
 319         init_completion(&dma->cmd_complete);
 320         dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n",
 321                 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
 322
 323         return;
 324
 325 fail_rx:
 326         dma_release_channel(dma->chan_rx);
 327 fail_tx:
 328         dma_release_channel(dma->chan_tx);
 329 fail_al:
 330         devm_kfree(dev, dma);
 331 }
 332
 333 static void i2c_imx_dma_callback(void *arg)
 334 {
 335         struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg;
 336         struct imx_i2c_dma *dma = i2c_imx->dma;
 337
 338         dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf,
 339                         dma->dma_len, dma->dma_data_dir);
 340         complete(&dma->cmd_complete);
 341 }
 342
 343 static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx,
 344                                         struct i2c_msg *msgs)
 345 {
 346         struct imx_i2c_dma *dma = i2c_imx->dma;
 347         struct dma_async_tx_descriptor *txdesc;
 348         struct device *dev = &i2c_imx->adapter.dev;
 349         struct device *chan_dev = dma->chan_using->device->dev;
 350
 351         dma->dma_buf = dma_map_single(chan_dev, msgs->buf,
 352                                         dma->dma_len, dma->dma_data_dir);
 353         if (dma_mapping_error(chan_dev, dma->dma_buf)) {
 354                 dev_err(dev, "DMA mapping failed\n");
 355                 goto err_map;
 356         }
 357
 358         txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf,
 359                                         dma->dma_len, dma->dma_transfer_dir,
 360                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 361         if (!txdesc) {
 362                 dev_err(dev, "Not able to get desc for DMA xfer\n");
 363                 goto err_desc;
 364         }
 365
 366         reinit_completion(&dma->cmd_complete);
 367         txdesc->callback = i2c_imx_dma_callback;
 368         txdesc->callback_param = i2c_imx;
 369         if (dma_submit_error(dmaengine_submit(txdesc))) {
 370                 dev_err(dev, "DMA submit failed\n");
 371                 goto err_submit;
 372         }
 373
 374         dma_async_issue_pending(dma->chan_using);
 375         return 0;
 376
 377 err_submit:
 378         dmaengine_terminate_all(dma->chan_using);
 379 err_desc:
 380         dma_unmap_single(chan_dev, dma->dma_buf,
 381                         dma->dma_len, dma->dma_data_dir);
 382 err_map:
 383         return -EINVAL;
 384 }
 385
 386 static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx)
 387 {
 388         struct imx_i2c_dma *dma = i2c_imx->dma;
 389
 390         dma->dma_buf = 0;
 391         dma->dma_len = 0;
 392
 393         dma_release_channel(dma->chan_tx);
 394         dma->chan_tx = NULL;
 395
 396         dma_release_channel(dma->chan_rx);
 397         dma->chan_rx = NULL;
 398
 399         dma->chan_using = NULL;
 400 }
 401
 402 static void i2c_imx_clear_irq(struct imx_i2c_struct *i2c_imx, unsigned int bits)
 403 {
 404         unsigned int temp;
 405
 406         /*
 407          * i2sr_clr_opcode is the value to clear all interrupts. Here we want to
 408          * clear only <bits>, so we write ~i2sr_clr_opcode with just <bits>
 409          * toggled. This is required because i.MX needs W0C and Vybrid uses W1C.
 410          */
 411         temp = ~i2c_imx->hwdata->i2sr_clr_opcode ^ bits;
 412         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
 413 }
 414
 415 static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy, bool atomic)
 416 {
 417         unsigned long orig_jiffies = jiffies;
 418         unsigned int temp;
 419
 420         dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
 421
 422         while (1) {
 423                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 424
 425                 /* check for arbitration lost */
 426                 if (temp & I2SR_IAL) {
 427                         i2c_imx_clear_irq(i2c_imx, I2SR_IAL);
 428                         return -EAGAIN;
 429                 }
 430
 431                 if (for_busy && (temp & I2SR_IBB)) {
 432                         i2c_imx->stopped = 0;
 433                         break;
 434                 }
 435                 if (!for_busy && !(temp & I2SR_IBB)) {
 436                         i2c_imx->stopped = 1;
 437                         break;
 438                 }
 439                 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
 440                         dev_dbg(&i2c_imx->adapter.dev,
 441                                 "<%s> I2C bus is busy\n", __func__);
 442                         return -ETIMEDOUT;
 443                 }
 444                 if (atomic)
 445                         udelay(100);
 446                 else
 447                         schedule();
 448         }
 449
 450         return 0;
 451 }
 452
 453 static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx, bool atomic)
 454 {
 455         if (atomic) {
 456                 void __iomem *addr = i2c_imx->base + (IMX_I2C_I2SR << i2c_imx->hwdata->regshift);
 457                 unsigned int regval;
 458
 459                 /*
 460                  * The formula for the poll timeout is documented in the RM
 461                  * Rev.5 on page 1878:
 462                  *     T_min = 10/F_scl
 463                  * Set the value hard as it is done for the non-atomic use-case.
 464                  * Use 10 kHz for the calculation since this is the minimum
 465                  * allowed SMBus frequency. Also add an offset of 100us since it
 466                  * turned out that the I2SR_IIF bit isn't set correctly within
 467                  * the minimum timeout in polling mode.
 468                  */
 469                 readb_poll_timeout_atomic(addr, regval, regval & I2SR_IIF, 5, 1000 + 100);
 470                 i2c_imx->i2csr = regval;
 471                 i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL);
 472         } else {
 473                 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
 474         }
 475
 476         if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
 477                 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
 478                 return -ETIMEDOUT;
 479         }
 480
 481         /* check for arbitration lost */
 482         if (i2c_imx->i2csr & I2SR_IAL) {
 483                 dev_dbg(&i2c_imx->adapter.dev, "<%s> Arbitration lost\n", __func__);
 484                 i2c_imx_clear_irq(i2c_imx, I2SR_IAL);
 485
 486                 i2c_imx->i2csr = 0;
 487                 return -EAGAIN;
 488         }
 489
 490         dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
 491         i2c_imx->i2csr = 0;
 492         return 0;
 493 }
 494
 495 static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
 496 {
 497         if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) {
 498                 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
 499                 return -ENXIO;  /* No ACK */
 500         }
 501
 502         dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
 503         return 0;
 504 }
 505
 506 static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
 507                             unsigned int i2c_clk_rate)
 508 {
 509         struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div;
 510         unsigned int div;
 511         int i;
 512
 513         /* Divider value calculation */
 514         if (i2c_imx->cur_clk == i2c_clk_rate)
 515                 return;
 516
 517         i2c_imx->cur_clk = i2c_clk_rate;
 518
 519         div = (i2c_clk_rate + i2c_imx->bitrate - 1) / i2c_imx->bitrate;
 520         if (div < i2c_clk_div[0].div)
 521                 i = 0;
 522         else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div)
 523                 i = i2c_imx->hwdata->ndivs - 1;
 524         else
 525                 for (i = 0; i2c_clk_div[i].div < div; i++)
 526                         ;
 527
 528         /* Store divider value */
 529         i2c_imx->ifdr = i2c_clk_div[i].val;
 530
 531         /*
 532          * There dummy delay is calculated.
 533          * It should be about one I2C clock period long.
 534          * This delay is used in I2C bus disable function
 535          * to fix chip hardware bug.
 536          */
 537         i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div
 538                 + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
 539
 540 #ifdef CONFIG_I2C_DEBUG_BUS
 541         dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n",
 542                 i2c_clk_rate, div);
 543         dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n",
 544                 i2c_clk_div[i].val, i2c_clk_div[i].div);
 545 #endif
 546 }
 547
 548 static int i2c_imx_clk_notifier_call(struct notifier_block *nb,
 549                                      unsigned long action, void *data)
 550 {
 551         struct clk_notifier_data *ndata = data;
 552         struct imx_i2c_struct *i2c_imx = container_of(nb,
 553                                                       struct imx_i2c_struct,
 554                                                       clk_change_nb);
 555
 556         if (action & POST_RATE_CHANGE)
 557                 i2c_imx_set_clk(i2c_imx, ndata->new_rate);
 558
 559         return NOTIFY_OK;
 560 }
 561
 562 static int i2c_imx_start(struct imx_i2c_struct *i2c_imx, bool atomic)
 563 {
 564         unsigned int temp = 0;
 565         int result;
 566
 567         dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
 568
 569         imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR);
 570         /* Enable I2C controller */
 571         imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
 572         imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR);
 573
 574         /* Wait controller to be stable */
 575         if (atomic)
 576                 udelay(50);
 577         else
 578                 usleep_range(50, 150);
 579
 580         /* Start I2C transaction */
 581         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 582         temp |= I2CR_MSTA;
 583         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 584         result = i2c_imx_bus_busy(i2c_imx, 1, atomic);
 585         if (result)
 586                 return result;
 587
 588         temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
 589         if (atomic)
 590                 temp &= ~I2CR_IIEN; /* Disable interrupt */
 591
 592         temp &= ~I2CR_DMAEN;
 593         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 594         return result;
 595 }
 596
 597 static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx, bool atomic)
 598 {
 599         unsigned int temp = 0;
 600
 601         if (!i2c_imx->stopped) {
 602                 /* Stop I2C transaction */
 603                 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
 604                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 605                 if (!(temp & I2CR_MSTA))
 606                         i2c_imx->stopped = 1;
 607                 temp &= ~(I2CR_MSTA | I2CR_MTX);
 608                 if (i2c_imx->dma)
 609                         temp &= ~I2CR_DMAEN;
 610                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 611         }
 612         if (is_imx1_i2c(i2c_imx)) {
 613                 /*
 614                  * This delay caused by an i.MXL hardware bug.
 615                  * If no (or too short) delay, no "STOP" bit will be generated.
 616                  */
 617                 udelay(i2c_imx->disable_delay);
 618         }
 619
 620         if (!i2c_imx->stopped)
 621                 i2c_imx_bus_busy(i2c_imx, 0, atomic);
 622
 623         /* Disable I2C controller */
 624         temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
 625         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 626 }
 627
 628 static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
 629 {
 630         struct imx_i2c_struct *i2c_imx = dev_id;
 631         unsigned int temp;
 632
 633         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 634         if (temp & I2SR_IIF) {
 635                 /* save status register */
 636                 i2c_imx->i2csr = temp;
 637                 i2c_imx_clear_irq(i2c_imx, I2SR_IIF);
 638                 wake_up(&i2c_imx->queue);
 639                 return IRQ_HANDLED;
 640         }
 641
 642         return IRQ_NONE;
 643 }
 644
 645 static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx,
 646                                         struct i2c_msg *msgs)
 647 {
 648         int result;
 649         unsigned long time_left;
 650         unsigned int temp = 0;
 651         unsigned long orig_jiffies = jiffies;
 652         struct imx_i2c_dma *dma = i2c_imx->dma;
 653         struct device *dev = &i2c_imx->adapter.dev;
 654
 655         dma->chan_using = dma->chan_tx;
 656         dma->dma_transfer_dir = DMA_MEM_TO_DEV;
 657         dma->dma_data_dir = DMA_TO_DEVICE;
 658         dma->dma_len = msgs->len - 1;
 659         result = i2c_imx_dma_xfer(i2c_imx, msgs);
 660         if (result)
 661                 return result;
 662
 663         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 664         temp |= I2CR_DMAEN;
 665         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 666
 667         /*
 668          * Write slave address.
 669          * The first byte must be transmitted by the CPU.
 670          */
 671         imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
 672         time_left = wait_for_completion_timeout(
 673                                 &i2c_imx->dma->cmd_complete,
 674                                 msecs_to_jiffies(DMA_TIMEOUT));
 675         if (time_left == 0) {
 676                 dmaengine_terminate_all(dma->chan_using);
 677                 return -ETIMEDOUT;
 678         }
 679
 680         /* Waiting for transfer complete. */
 681         while (1) {
 682                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 683                 if (temp & I2SR_ICF)
 684                         break;
 685                 if (time_after(jiffies, orig_jiffies +
 686                                 msecs_to_jiffies(DMA_TIMEOUT))) {
 687                         dev_dbg(dev, "<%s> Timeout\n", __func__);
 688                         return -ETIMEDOUT;
 689                 }
 690                 schedule();
 691         }
 692
 693         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 694         temp &= ~I2CR_DMAEN;
 695         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 696
 697         /* The last data byte must be transferred by the CPU. */
 698         imx_i2c_write_reg(msgs->buf[msgs->len-1],
 699                                 i2c_imx, IMX_I2C_I2DR);
 700         result = i2c_imx_trx_complete(i2c_imx, false);
 701         if (result)
 702                 return result;
 703
 704         return i2c_imx_acked(i2c_imx);
 705 }
 706
 707 static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx,
 708                         struct i2c_msg *msgs, bool is_lastmsg)
 709 {
 710         int result;
 711         unsigned long time_left;
 712         unsigned int temp;
 713         unsigned long orig_jiffies = jiffies;
 714         struct imx_i2c_dma *dma = i2c_imx->dma;
 715         struct device *dev = &i2c_imx->adapter.dev;
 716
 717
 718         dma->chan_using = dma->chan_rx;
 719         dma->dma_transfer_dir = DMA_DEV_TO_MEM;
 720         dma->dma_data_dir = DMA_FROM_DEVICE;
 721         /* The last two data bytes must be transferred by the CPU. */
 722         dma->dma_len = msgs->len - 2;
 723         result = i2c_imx_dma_xfer(i2c_imx, msgs);
 724         if (result)
 725                 return result;
 726
 727         time_left = wait_for_completion_timeout(
 728                                 &i2c_imx->dma->cmd_complete,
 729                                 msecs_to_jiffies(DMA_TIMEOUT));
 730         if (time_left == 0) {
 731                 dmaengine_terminate_all(dma->chan_using);
 732                 return -ETIMEDOUT;
 733         }
 734
 735         /* waiting for transfer complete. */
 736         while (1) {
 737                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 738                 if (temp & I2SR_ICF)
 739                         break;
 740                 if (time_after(jiffies, orig_jiffies +
 741                                 msecs_to_jiffies(DMA_TIMEOUT))) {
 742                         dev_dbg(dev, "<%s> Timeout\n", __func__);
 743                         return -ETIMEDOUT;
 744                 }
 745                 schedule();
 746         }
 747
 748         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 749         temp &= ~I2CR_DMAEN;
 750         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 751
 752         /* read n-1 byte data */
 753         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 754         temp |= I2CR_TXAK;
 755         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 756
 757         msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
 758         /* read n byte data */
 759         result = i2c_imx_trx_complete(i2c_imx, false);
 760         if (result)
 761                 return result;
 762
 763         if (is_lastmsg) {
 764                 /*
 765                  * It must generate STOP before read I2DR to prevent
 766                  * controller from generating another clock cycle
 767                  */
 768                 dev_dbg(dev, "<%s> clear MSTA\n", __func__);
 769                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 770                 if (!(temp & I2CR_MSTA))
 771                         i2c_imx->stopped = 1;
 772                 temp &= ~(I2CR_MSTA | I2CR_MTX);
 773                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 774                 if (!i2c_imx->stopped)
 775                         i2c_imx_bus_busy(i2c_imx, 0, false);
 776         } else {
 777                 /*
 778                  * For i2c master receiver repeat restart operation like:
 779                  * read -> repeat MSTA -> read/write
 780                  * The controller must set MTX before read the last byte in
 781                  * the first read operation, otherwise the first read cost
 782                  * one extra clock cycle.
 783                  */
 784                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 785                 temp |= I2CR_MTX;
 786                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 787         }
 788         msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
 789
 790         return 0;
 791 }
 792
 793 static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs,
 794                          bool atomic)
 795 {
 796         int i, result;
 797
 798         dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
 799                 __func__, i2c_8bit_addr_from_msg(msgs));
 800
 801         /* write slave address */
 802         imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
 803         result = i2c_imx_trx_complete(i2c_imx, atomic);
 804         if (result)
 805                 return result;
 806         result = i2c_imx_acked(i2c_imx);
 807         if (result)
 808                 return result;
 809         dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
 810
 811         /* write data */
 812         for (i = 0; i < msgs->len; i++) {
 813                 dev_dbg(&i2c_imx->adapter.dev,
 814                         "<%s> write byte: B%d=0x%X\n",
 815                         __func__, i, msgs->buf[i]);
 816                 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR);
 817                 result = i2c_imx_trx_complete(i2c_imx, atomic);
 818                 if (result)
 819                         return result;
 820                 result = i2c_imx_acked(i2c_imx);
 821                 if (result)
 822                         return result;
 823         }
 824         return 0;
 825 }
 826
 827 static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs,
 828                         bool is_lastmsg, bool atomic)
 829 {
 830         int i, result;
 831         unsigned int temp;
 832         int block_data = msgs->flags & I2C_M_RECV_LEN;
 833         int use_dma = i2c_imx->dma && msgs->len >= DMA_THRESHOLD && !block_data;
 834
 835         dev_dbg(&i2c_imx->adapter.dev,
 836                 "<%s> write slave address: addr=0x%x\n",
 837                 __func__, i2c_8bit_addr_from_msg(msgs));
 838
 839         /* write slave address */
 840         imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
 841         result = i2c_imx_trx_complete(i2c_imx, atomic);
 842         if (result)
 843                 return result;
 844         result = i2c_imx_acked(i2c_imx);
 845         if (result)
 846                 return result;
 847
 848         dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
 849
 850         /* setup bus to read data */
 851         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 852         temp &= ~I2CR_MTX;
 853
 854         /*
 855          * Reset the I2CR_TXAK flag initially for SMBus block read since the
 856          * length is unknown
 857          */
 858         if ((msgs->len - 1) || block_data)
 859                 temp &= ~I2CR_TXAK;
 860         if (use_dma)
 861                 temp |= I2CR_DMAEN;
 862         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 863         imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */
 864
 865         dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
 866
 867         if (use_dma)
 868                 return i2c_imx_dma_read(i2c_imx, msgs, is_lastmsg);
 869
 870         /* read data */
 871         for (i = 0; i < msgs->len; i++) {
 872                 u8 len = 0;
 873
 874                 result = i2c_imx_trx_complete(i2c_imx, atomic);
 875                 if (result)
 876                         return result;
 877                 /*
 878                  * First byte is the length of remaining packet
 879                  * in the SMBus block data read. Add it to
 880                  * msgs->len.
 881                  */
 882                 if ((!i) && block_data) {
 883                         len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
 884                         if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX))
 885                                 return -EPROTO;
 886                         dev_dbg(&i2c_imx->adapter.dev,
 887                                 "<%s> read length: 0x%X\n",
 888                                 __func__, len);
 889                         msgs->len += len;
 890                 }
 891                 if (i == (msgs->len - 1)) {
 892                         if (is_lastmsg) {
 893                                 /*
 894                                  * It must generate STOP before read I2DR to prevent
 895                                  * controller from generating another clock cycle
 896                                  */
 897                                 dev_dbg(&i2c_imx->adapter.dev,
 898                                         "<%s> clear MSTA\n", __func__);
 899                                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 900                                 if (!(temp & I2CR_MSTA))
 901                                         i2c_imx->stopped =  1;
 902                                 temp &= ~(I2CR_MSTA | I2CR_MTX);
 903                                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 904                                 if (!i2c_imx->stopped)
 905                                         i2c_imx_bus_busy(i2c_imx, 0, atomic);
 906                         } else {
 907                                 /*
 908                                  * For i2c master receiver repeat restart operation like:
 909                                  * read -> repeat MSTA -> read/write
 910                                  * The controller must set MTX before read the last byte in
 911                                  * the first read operation, otherwise the first read cost
 912                                  * one extra clock cycle.
 913                                  */
 914                                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 915                                 temp |= I2CR_MTX;
 916                                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 917                         }
 918                 } else if (i == (msgs->len - 2)) {
 919                         dev_dbg(&i2c_imx->adapter.dev,
 920                                 "<%s> set TXAK\n", __func__);
 921                         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 922                         temp |= I2CR_TXAK;
 923                         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 924                 }
 925                 if ((!i) && block_data)
 926                         msgs->buf[0] = len;
 927                 else
 928                         msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
 929                 dev_dbg(&i2c_imx->adapter.dev,
 930                         "<%s> read byte: B%d=0x%X\n",
 931                         __func__, i, msgs->buf[i]);
 932         }
 933         return 0;
 934 }
 935
 936 static int i2c_imx_xfer_common(struct i2c_adapter *adapter,
 937                                struct i2c_msg *msgs, int num, bool atomic)
 938 {
 939         unsigned int i, temp;
 940         int result;
 941         bool is_lastmsg = false;
 942         struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
 943
 944         dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
 945
 946         /* Start I2C transfer */
 947         result = i2c_imx_start(i2c_imx, atomic);
 948         if (result) {
 949                 /*
 950                  * Bus recovery uses gpiod_get_value_cansleep() which is not
 951                  * allowed within atomic context.
 952                  */
 953                 if (!atomic && i2c_imx->adapter.bus_recovery_info) {
 954                         i2c_recover_bus(&i2c_imx->adapter);
 955                         result = i2c_imx_start(i2c_imx, atomic);
 956                 }
 957         }
 958
 959         if (result)
 960                 goto fail0;
 961
 962         /* read/write data */
 963         for (i = 0; i < num; i++) {
 964                 if (i == num - 1)
 965                         is_lastmsg = true;
 966
 967                 if (i) {
 968                         dev_dbg(&i2c_imx->adapter.dev,
 969                                 "<%s> repeated start\n", __func__);
 970                         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 971                         temp |= I2CR_RSTA;
 972                         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 973                         result = i2c_imx_bus_busy(i2c_imx, 1, atomic);
 974                         if (result)
 975                                 goto fail0;
 976                 }
 977                 dev_dbg(&i2c_imx->adapter.dev,
 978                         "<%s> transfer message: %d\n", __func__, i);
 979                 /* write/read data */
 980 #ifdef CONFIG_I2C_DEBUG_BUS
 981                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 982                 dev_dbg(&i2c_imx->adapter.dev,
 983                         "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n",
 984                         __func__,
 985                         (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
 986                         (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
 987                         (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
 988                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 989                 dev_dbg(&i2c_imx->adapter.dev,
 990                         "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n",
 991                         __func__,
 992                         (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
 993                         (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
 994                         (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
 995                         (temp & I2SR_RXAK ? 1 : 0));
 996 #endif
 997                 if (msgs[i].flags & I2C_M_RD) {
 998                         result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg, atomic);
 999                 } else {
1000                         if (!atomic &&
1001                             i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD)
1002                                 result = i2c_imx_dma_write(i2c_imx, &msgs[i]);
1003                         else
1004                                 result = i2c_imx_write(i2c_imx, &msgs[i], atomic);
1005                 }
1006                 if (result)
1007                         goto fail0;
1008         }
1009
1010 fail0:
1011         /* Stop I2C transfer */
1012         i2c_imx_stop(i2c_imx, atomic);
1013
1014         dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
1015                 (result < 0) ? "error" : "success msg",
1016                         (result < 0) ? result : num);
1017         return (result < 0) ? result : num;
1018 }
1019
1020 static int i2c_imx_xfer(struct i2c_adapter *adapter,
1021                         struct i2c_msg *msgs, int num)
1022 {
1023         struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
1024         int result;
1025
1026         result = pm_runtime_get_sync(i2c_imx->adapter.dev.parent);
1027         if (result < 0)
1028                 return result;
1029
1030         result = i2c_imx_xfer_common(adapter, msgs, num, false);
1031
1032         pm_runtime_mark_last_busy(i2c_imx->adapter.dev.parent);
1033         pm_runtime_put_autosuspend(i2c_imx->adapter.dev.parent);
1034
1035         return result;
1036 }
1037
1038 static int i2c_imx_xfer_atomic(struct i2c_adapter *adapter,
1039                                struct i2c_msg *msgs, int num)
1040 {
1041         struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
1042         int result;
1043
1044         result = clk_enable(i2c_imx->clk);
1045         if (result)
1046                 return result;
1047
1048         result = i2c_imx_xfer_common(adapter, msgs, num, true);
1049
1050         clk_disable(i2c_imx->clk);
1051
1052         return result;
1053 }
1054
1055 static void i2c_imx_prepare_recovery(struct i2c_adapter *adap)
1056 {
1057         struct imx_i2c_struct *i2c_imx;
1058
1059         i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
1060
1061         pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_gpio);
1062 }
1063
1064 static void i2c_imx_unprepare_recovery(struct i2c_adapter *adap)
1065 {
1066         struct imx_i2c_struct *i2c_imx;
1067
1068         i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
1069
1070         pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_default);
1071 }
1072
1073 /*
1074  * We switch SCL and SDA to their GPIO function and do some bitbanging
1075  * for bus recovery. These alternative pinmux settings can be
1076  * described in the device tree by a separate pinctrl state "gpio". If
1077  * this is missing this is not a big problem, the only implication is
1078  * that we can't do bus recovery.
1079  */
1080 static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx,
1081                 struct platform_device *pdev)
1082 {
1083         struct i2c_bus_recovery_info *rinfo = &i2c_imx->rinfo;
1084
1085         i2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev);
1086         if (!i2c_imx->pinctrl || IS_ERR(i2c_imx->pinctrl)) {
1087                 dev_info(&pdev->dev, "can't get pinctrl, bus recovery not supported\n");
1088                 return PTR_ERR(i2c_imx->pinctrl);
1089         }
1090
1091         i2c_imx->pinctrl_pins_default = pinctrl_lookup_state(i2c_imx->pinctrl,
1092                         PINCTRL_STATE_DEFAULT);
1093         i2c_imx->pinctrl_pins_gpio = pinctrl_lookup_state(i2c_imx->pinctrl,
1094                         "gpio");
1095         rinfo->sda_gpiod = devm_gpiod_get(&pdev->dev, "sda", GPIOD_IN);
1096         rinfo->scl_gpiod = devm_gpiod_get(&pdev->dev, "scl", GPIOD_OUT_HIGH_OPEN_DRAIN);
1097
1098         if (PTR_ERR(rinfo->sda_gpiod) == -EPROBE_DEFER ||
1099             PTR_ERR(rinfo->scl_gpiod) == -EPROBE_DEFER) {
1100                 return -EPROBE_DEFER;
1101         } else if (IS_ERR(rinfo->sda_gpiod) ||
1102                    IS_ERR(rinfo->scl_gpiod) ||
1103                    IS_ERR(i2c_imx->pinctrl_pins_default) ||
1104                    IS_ERR(i2c_imx->pinctrl_pins_gpio)) {
1105                 dev_dbg(&pdev->dev, "recovery information incomplete\n");
1106                 return 0;
1107         }
1108
1109         dev_dbg(&pdev->dev, "using scl%s for recovery\n",
1110                 rinfo->sda_gpiod ? ",sda" : "");
1111
1112         rinfo->prepare_recovery = i2c_imx_prepare_recovery;
1113         rinfo->unprepare_recovery = i2c_imx_unprepare_recovery;
1114         rinfo->recover_bus = i2c_generic_scl_recovery;
1115         i2c_imx->adapter.bus_recovery_info = rinfo;
1116
1117         return 0;
1118 }
1119
1120 static u32 i2c_imx_func(struct i2c_adapter *adapter)
1121 {
1122         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
1123                 | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
1124 }
1125
1126 static const struct i2c_algorithm i2c_imx_algo = {
1127         .master_xfer = i2c_imx_xfer,
1128         .master_xfer_atomic = i2c_imx_xfer_atomic,
1129         .functionality = i2c_imx_func,
1130 };
1131
1132 static int i2c_imx_probe(struct platform_device *pdev)
1133 {
1134         struct imx_i2c_struct *i2c_imx;
1135         struct resource *res;
1136         struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev);
1137         void __iomem *base;
1138         int irq, ret;
1139         dma_addr_t phy_addr;
1140         const struct imx_i2c_hwdata *match;
1141
1142         dev_dbg(&pdev->dev, "<%s>\n", __func__);
1143
1144         irq = platform_get_irq(pdev, 0);
1145         if (irq < 0)
1146                 return irq;
1147
1148         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1149         base = devm_ioremap_resource(&pdev->dev, res);
1150         if (IS_ERR(base))
1151                 return PTR_ERR(base);
1152
1153         phy_addr = (dma_addr_t)res->start;
1154         i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL);
1155         if (!i2c_imx)
1156                 return -ENOMEM;
1157
1158         match = device_get_match_data(&pdev->dev);
1159         i2c_imx->hwdata = match;
1160
1161         /* Setup i2c_imx driver structure */
1162         strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));
1163         i2c_imx->adapter.owner          = THIS_MODULE;
1164         i2c_imx->adapter.algo           = &i2c_imx_algo;
1165         i2c_imx->adapter.dev.parent     = &pdev->dev;
1166         i2c_imx->adapter.nr             = pdev->id;
1167         i2c_imx->adapter.dev.of_node    = pdev->dev.of_node;
1168         i2c_imx->base                   = base;
1169         ACPI_COMPANION_SET(&i2c_imx->adapter.dev, ACPI_COMPANION(&pdev->dev));
1170
1171         /* Get I2C clock */
1172         i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
1173         if (IS_ERR(i2c_imx->clk))
1174                 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_imx->clk),
1175                                      "can't get I2C clock\n");
1176
1177         ret = clk_prepare_enable(i2c_imx->clk);
1178         if (ret) {
1179                 dev_err(&pdev->dev, "can't enable I2C clock, ret=%d\n", ret);
1180                 return ret;
1181         }
1182
1183         /* Init queue */
1184         init_waitqueue_head(&i2c_imx->queue);
1185
1186         /* Set up adapter data */
1187         i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
1188
1189         /* Set up platform driver data */
1190         platform_set_drvdata(pdev, i2c_imx);
1191
1192         pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT);
1193         pm_runtime_use_autosuspend(&pdev->dev);
1194         pm_runtime_set_active(&pdev->dev);
1195         pm_runtime_enable(&pdev->dev);
1196
1197         ret = pm_runtime_get_sync(&pdev->dev);
1198         if (ret < 0)
1199                 goto rpm_disable;
1200
1201         /* Request IRQ */
1202         ret = request_threaded_irq(irq, i2c_imx_isr, NULL, IRQF_SHARED,
1203                                    pdev->name, i2c_imx);
1204         if (ret) {
1205                 dev_err(&pdev->dev, "can't claim irq %d\n", irq);
1206                 goto rpm_disable;
1207         }
1208
1209         /* Set up clock divider */
1210         i2c_imx->bitrate = I2C_MAX_STANDARD_MODE_FREQ;
1211         ret = of_property_read_u32(pdev->dev.of_node,
1212                                    "clock-frequency", &i2c_imx->bitrate);
1213         if (ret < 0 && pdata && pdata->bitrate)
1214                 i2c_imx->bitrate = pdata->bitrate;
1215         i2c_imx->clk_change_nb.notifier_call = i2c_imx_clk_notifier_call;
1216         clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb);
1217         i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk));
1218
1219         /* Set up chip registers to defaults */
1220         imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
1221                         i2c_imx, IMX_I2C_I2CR);
1222         imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
1223
1224         /* Init optional bus recovery function */
1225         ret = i2c_imx_init_recovery_info(i2c_imx, pdev);
1226         /* Give it another chance if pinctrl used is not ready yet */
1227         if (ret == -EPROBE_DEFER)
1228                 goto clk_notifier_unregister;
1229
1230         /* Add I2C adapter */
1231         ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
1232         if (ret < 0)
1233                 goto clk_notifier_unregister;
1234
1235         pm_runtime_mark_last_busy(&pdev->dev);
1236         pm_runtime_put_autosuspend(&pdev->dev);
1237
1238         dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
1239         dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res);
1240         dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
1241                 i2c_imx->adapter.name);
1242         dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
1243
1244         /* Init DMA config if supported */
1245         i2c_imx_dma_request(i2c_imx, phy_addr);
1246
1247         return 0;   /* Return OK */
1248
1249 clk_notifier_unregister:
1250         clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);
1251         free_irq(irq, i2c_imx);
1252 rpm_disable:
1253         pm_runtime_put_noidle(&pdev->dev);
1254         pm_runtime_disable(&pdev->dev);
1255         pm_runtime_set_suspended(&pdev->dev);
1256         pm_runtime_dont_use_autosuspend(&pdev->dev);
1257         clk_disable_unprepare(i2c_imx->clk);
1258         return ret;
1259 }
1260
1261 static int i2c_imx_remove(struct platform_device *pdev)
1262 {
1263         struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
1264         int irq, ret;
1265
1266         ret = pm_runtime_get_sync(&pdev->dev);
1267         if (ret < 0)
1268                 return ret;
1269
1270         /* remove adapter */
1271         dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
1272         i2c_del_adapter(&i2c_imx->adapter);
1273
1274         if (i2c_imx->dma)
1275                 i2c_imx_dma_free(i2c_imx);
1276
1277         /* setup chip registers to defaults */
1278         imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
1279         imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR);
1280         imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR);
1281         imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR);
1282
1283         clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);
1284         irq = platform_get_irq(pdev, 0);
1285         if (irq >= 0)
1286                 free_irq(irq, i2c_imx);
1287         clk_disable_unprepare(i2c_imx->clk);
1288
1289         pm_runtime_put_noidle(&pdev->dev);
1290         pm_runtime_disable(&pdev->dev);
1291
1292         return 0;
1293 }
1294
1295 static int __maybe_unused i2c_imx_runtime_suspend(struct device *dev)
1296 {
1297         struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
1298
1299         clk_disable(i2c_imx->clk);
1300
1301         return 0;
1302 }
1303
1304 static int __maybe_unused i2c_imx_runtime_resume(struct device *dev)
1305 {
1306         struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
1307         int ret;
1308
1309         ret = clk_enable(i2c_imx->clk);
1310         if (ret)
1311                 dev_err(dev, "can't enable I2C clock, ret=%d\n", ret);
1312
1313         return ret;
1314 }
1315
1316 static const struct dev_pm_ops i2c_imx_pm_ops = {
1317         SET_RUNTIME_PM_OPS(i2c_imx_runtime_suspend,
1318                            i2c_imx_runtime_resume, NULL)
1319 };
1320
1321 static struct platform_driver i2c_imx_driver = {
1322         .probe = i2c_imx_probe,
1323         .remove = i2c_imx_remove,
1324         .driver = {
1325                 .name = DRIVER_NAME,
1326                 .pm = &i2c_imx_pm_ops,
1327                 .of_match_table = i2c_imx_dt_ids,
1328                 .acpi_match_table = i2c_imx_acpi_ids,
1329         },
1330 };
1331
1332 static int __init i2c_adap_imx_init(void)
1333 {
1334         return platform_driver_register(&i2c_imx_driver);
1335 }
1336 subsys_initcall(i2c_adap_imx_init);
1337
1338 static void __exit i2c_adap_imx_exit(void)
1339 {
1340         platform_driver_unregister(&i2c_imx_driver);
1341 }
1342 module_exit(i2c_adap_imx_exit);
1343
1344 MODULE_LICENSE("GPL");
1345 MODULE_AUTHOR("Darius Augulis");
1346 MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
1347 MODULE_ALIAS("platform:" DRIVER_NAME);