drivers/i2c/busses/i2c-imx.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *      Copyright (C) 2002 Motorola GSG-China
   4  *
   5  * Author:
   6  *      Darius Augulis, Teltonika Inc.
   7  *
   8  * Desc.:
   9  *      Implementation of I2C Adapter/Algorithm Driver
  10  *      for I2C Bus integrated in Freescale i.MX/MXC processors
  11  *
  12  *      Derived from Motorola GSG China I2C example driver
  13  *
  14  *      Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
  15  *      Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
  16  *      Copyright (C) 2007 RightHand Technologies, Inc.
  17  *      Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
  18  *
  19  *      Copyright 2013 Freescale Semiconductor, Inc.
  20  *
  21  */
  22
  23 #include <linux/acpi.h>
  24 #include <linux/clk.h>
  25 #include <linux/completion.h>
  26 #include <linux/delay.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/dmaengine.h>
  29 #include <linux/dmapool.h>
  30 #include <linux/err.h>
  31 #include <linux/errno.h>
  32 #include <linux/gpio/consumer.h>
  33 #include <linux/i2c.h>
  34 #include <linux/init.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/io.h>
  37 #include <linux/iopoll.h>
  38 #include <linux/kernel.h>
  39 #include <linux/module.h>
  40 #include <linux/of.h>
  41 #include <linux/of_device.h>
  42 #include <linux/of_dma.h>
  43 #include <linux/pinctrl/consumer.h>
  44 #include <linux/platform_data/i2c-imx.h>
  45 #include <linux/platform_device.h>
  46 #include <linux/pm_runtime.h>
  47 #include <linux/sched.h>
  48 #include <linux/slab.h>
  49
  50 /* This will be the driver name the kernel reports */
  51 #define DRIVER_NAME "imx-i2c"
  52
  53 /* Default value */
  54 #define IMX_I2C_BIT_RATE        100000  /* 100kHz */
  55
  56 /*
  57  * Enable DMA if transfer byte size is bigger than this threshold.
  58  * As the hardware request, it must bigger than 4 bytes.\
  59  * I have set '16' here, maybe it's not the best but I think it's
  60  * the appropriate.
  61  */
  62 #define DMA_THRESHOLD   16
  63 #define DMA_TIMEOUT     1000
  64
  65 /* IMX I2C registers:
  66  * the I2C register offset is different between SoCs,
  67  * to provid support for all these chips, split the
  68  * register offset into a fixed base address and a
  69  * variable shift value, then the full register offset
  70  * will be calculated by
  71  * reg_off = ( reg_base_addr << reg_shift)
  72  */
  73 #define IMX_I2C_IADR    0x00    /* i2c slave address */
  74 #define IMX_I2C_IFDR    0x01    /* i2c frequency divider */
  75 #define IMX_I2C_I2CR    0x02    /* i2c control */
  76 #define IMX_I2C_I2SR    0x03    /* i2c status */
  77 #define IMX_I2C_I2DR    0x04    /* i2c transfer data */
  78
  79 #define IMX_I2C_REGSHIFT        2
  80 #define VF610_I2C_REGSHIFT      0
  81
  82 /* Bits of IMX I2C registers */
  83 #define I2SR_RXAK       0x01
  84 #define I2SR_IIF        0x02
  85 #define I2SR_SRW        0x04
  86 #define I2SR_IAL        0x10
  87 #define I2SR_IBB        0x20
  88 #define I2SR_IAAS       0x40
  89 #define I2SR_ICF        0x80
  90 #define I2CR_DMAEN      0x02
  91 #define I2CR_RSTA       0x04
  92 #define I2CR_TXAK       0x08
  93 #define I2CR_MTX        0x10
  94 #define I2CR_MSTA       0x20
  95 #define I2CR_IIEN       0x40
  96 #define I2CR_IEN        0x80
  97
  98 /* register bits different operating codes definition:
  99  * 1) I2SR: Interrupt flags clear operation differ between SoCs:
 100  * - write zero to clear(w0c) INT flag on i.MX,
 101  * - but write one to clear(w1c) INT flag on Vybrid.
 102  * 2) I2CR: I2C module enable operation also differ between SoCs:
 103  * - set I2CR_IEN bit enable the module on i.MX,
 104  * - but clear I2CR_IEN bit enable the module on Vybrid.
 105  */
 106 #define I2SR_CLR_OPCODE_W0C     0x0
 107 #define I2SR_CLR_OPCODE_W1C     (I2SR_IAL | I2SR_IIF)
 108 #define I2CR_IEN_OPCODE_0       0x0
 109 #define I2CR_IEN_OPCODE_1       I2CR_IEN
 110
 111 #define I2C_PM_TIMEOUT          10 /* ms */
 112
 113 /*
 114  * sorted list of clock divider, register value pairs
 115  * taken from table 26-5, p.26-9, Freescale i.MX
 116  * Integrated Portable System Processor Reference Manual
 117  * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
 118  *
 119  * Duplicated divider values removed from list
 120  */
 121 struct imx_i2c_clk_pair {
 122         u16     div;
 123         u16     val;
 124 };
 125
 126 static struct imx_i2c_clk_pair imx_i2c_clk_div[] = {
 127         { 22,   0x20 }, { 24,   0x21 }, { 26,   0x22 }, { 28,   0x23 },
 128         { 30,   0x00 }, { 32,   0x24 }, { 36,   0x25 }, { 40,   0x26 },
 129         { 42,   0x03 }, { 44,   0x27 }, { 48,   0x28 }, { 52,   0x05 },
 130         { 56,   0x29 }, { 60,   0x06 }, { 64,   0x2A }, { 72,   0x2B },
 131         { 80,   0x2C }, { 88,   0x09 }, { 96,   0x2D }, { 104,  0x0A },
 132         { 112,  0x2E }, { 128,  0x2F }, { 144,  0x0C }, { 160,  0x30 },
 133         { 192,  0x31 }, { 224,  0x32 }, { 240,  0x0F }, { 256,  0x33 },
 134         { 288,  0x10 }, { 320,  0x34 }, { 384,  0x35 }, { 448,  0x36 },
 135         { 480,  0x13 }, { 512,  0x37 }, { 576,  0x14 }, { 640,  0x38 },
 136         { 768,  0x39 }, { 896,  0x3A }, { 960,  0x17 }, { 1024, 0x3B },
 137         { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
 138         { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
 139         { 3072, 0x1E }, { 3840, 0x1F }
 140 };
 141
 142 /* Vybrid VF610 clock divider, register value pairs */
 143 static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = {
 144         { 20,   0x00 }, { 22,   0x01 }, { 24,   0x02 }, { 26,   0x03 },
 145         { 28,   0x04 }, { 30,   0x05 }, { 32,   0x09 }, { 34,   0x06 },
 146         { 36,   0x0A }, { 40,   0x07 }, { 44,   0x0C }, { 48,   0x0D },
 147         { 52,   0x43 }, { 56,   0x0E }, { 60,   0x45 }, { 64,   0x12 },
 148         { 68,   0x0F }, { 72,   0x13 }, { 80,   0x14 }, { 88,   0x15 },
 149         { 96,   0x19 }, { 104,  0x16 }, { 112,  0x1A }, { 128,  0x17 },
 150         { 136,  0x4F }, { 144,  0x1C }, { 160,  0x1D }, { 176,  0x55 },
 151         { 192,  0x1E }, { 208,  0x56 }, { 224,  0x22 }, { 228,  0x24 },
 152         { 240,  0x1F }, { 256,  0x23 }, { 288,  0x5C }, { 320,  0x25 },
 153         { 384,  0x26 }, { 448,  0x2A }, { 480,  0x27 }, { 512,  0x2B },
 154         { 576,  0x2C }, { 640,  0x2D }, { 768,  0x31 }, { 896,  0x32 },
 155         { 960,  0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
 156         { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
 157         { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
 158         { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
 159 };
 160
 161 enum imx_i2c_type {
 162         IMX1_I2C,
 163         IMX21_I2C,
 164         VF610_I2C,
 165 };
 166
 167 struct imx_i2c_hwdata {
 168         enum imx_i2c_type       devtype;
 169         unsigned                regshift;
 170         struct imx_i2c_clk_pair *clk_div;
 171         unsigned                ndivs;
 172         unsigned                i2sr_clr_opcode;
 173         unsigned                i2cr_ien_opcode;
 174 };
 175
 176 struct imx_i2c_dma {
 177         struct dma_chan         *chan_tx;
 178         struct dma_chan         *chan_rx;
 179         struct dma_chan         *chan_using;
 180         struct completion       cmd_complete;
 181         dma_addr_t              dma_buf;
 182         unsigned int            dma_len;
 183         enum dma_transfer_direction dma_transfer_dir;
 184         enum dma_data_direction dma_data_dir;
 185 };
 186
 187 struct imx_i2c_struct {
 188         struct i2c_adapter      adapter;
 189         struct clk              *clk;
 190         struct notifier_block   clk_change_nb;
 191         void __iomem            *base;
 192         wait_queue_head_t       queue;
 193         unsigned long           i2csr;
 194         unsigned int            disable_delay;
 195         int                     stopped;
 196         unsigned int            ifdr; /* IMX_I2C_IFDR */
 197         unsigned int            cur_clk;
 198         unsigned int            bitrate;
 199         const struct imx_i2c_hwdata     *hwdata;
 200         struct i2c_bus_recovery_info rinfo;
 201
 202         struct pinctrl *pinctrl;
 203         struct pinctrl_state *pinctrl_pins_default;
 204         struct pinctrl_state *pinctrl_pins_gpio;
 205
 206         struct imx_i2c_dma      *dma;
 207 };
 208
 209 static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
 210         .devtype                = IMX1_I2C,
 211         .regshift               = IMX_I2C_REGSHIFT,
 212         .clk_div                = imx_i2c_clk_div,
 213         .ndivs                  = ARRAY_SIZE(imx_i2c_clk_div),
 214         .i2sr_clr_opcode        = I2SR_CLR_OPCODE_W0C,
 215         .i2cr_ien_opcode        = I2CR_IEN_OPCODE_1,
 216
 217 };
 218
 219 static const struct imx_i2c_hwdata imx21_i2c_hwdata = {
 220         .devtype                = IMX21_I2C,
 221         .regshift               = IMX_I2C_REGSHIFT,
 222         .clk_div                = imx_i2c_clk_div,
 223         .ndivs                  = ARRAY_SIZE(imx_i2c_clk_div),
 224         .i2sr_clr_opcode        = I2SR_CLR_OPCODE_W0C,
 225         .i2cr_ien_opcode        = I2CR_IEN_OPCODE_1,
 226
 227 };
 228
 229 static struct imx_i2c_hwdata vf610_i2c_hwdata = {
 230         .devtype                = VF610_I2C,
 231         .regshift               = VF610_I2C_REGSHIFT,
 232         .clk_div                = vf610_i2c_clk_div,
 233         .ndivs                  = ARRAY_SIZE(vf610_i2c_clk_div),
 234         .i2sr_clr_opcode        = I2SR_CLR_OPCODE_W1C,
 235         .i2cr_ien_opcode        = I2CR_IEN_OPCODE_0,
 236
 237 };
 238
 239 static const struct platform_device_id imx_i2c_devtype[] = {
 240         {
 241                 .name = "imx1-i2c",
 242                 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata,
 243         }, {
 244                 .name = "imx21-i2c",
 245                 .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata,
 246         }, {
 247                 /* sentinel */
 248         }
 249 };
 250 MODULE_DEVICE_TABLE(platform, imx_i2c_devtype);
 251
 252 static const struct of_device_id i2c_imx_dt_ids[] = {
 253         { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, },
 254         { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, },
 255         { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, },
 256         { /* sentinel */ }
 257 };
 258 MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids);
 259
 260 static const struct acpi_device_id i2c_imx_acpi_ids[] = {
 261         {"NXP0001", .driver_data = (kernel_ulong_t)&vf610_i2c_hwdata},
 262         { }
 263 };
 264 MODULE_DEVICE_TABLE(acpi, i2c_imx_acpi_ids);
 265
 266 static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)
 267 {
 268         return i2c_imx->hwdata->devtype == IMX1_I2C;
 269 }
 270
 271 static inline void imx_i2c_write_reg(unsigned int val,
 272                 struct imx_i2c_struct *i2c_imx, unsigned int reg)
 273 {
 274         writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
 275 }
 276
 277 static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,
 278                 unsigned int reg)
 279 {
 280         return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
 281 }
 282
 283 /* Functions for DMA support */
 284 static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
 285                                                 dma_addr_t phy_addr)
 286 {
 287         struct imx_i2c_dma *dma;
 288         struct dma_slave_config dma_sconfig;
 289         struct device *dev = &i2c_imx->adapter.dev;
 290         int ret;
 291
 292         dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
 293         if (!dma)
 294                 return;
 295
 296         dma->chan_tx = dma_request_chan(dev, "tx");
 297         if (IS_ERR(dma->chan_tx)) {
 298                 ret = PTR_ERR(dma->chan_tx);
 299                 if (ret != -ENODEV && ret != -EPROBE_DEFER)
 300                         dev_err(dev, "can't request DMA tx channel (%d)\n", ret);
 301                 goto fail_al;
 302         }
 303
 304         dma_sconfig.dst_addr = phy_addr +
 305                                 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
 306         dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 307         dma_sconfig.dst_maxburst = 1;
 308         dma_sconfig.direction = DMA_MEM_TO_DEV;
 309         ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig);
 310         if (ret < 0) {
 311                 dev_err(dev, "can't configure tx channel (%d)\n", ret);
 312                 goto fail_tx;
 313         }
 314
 315         dma->chan_rx = dma_request_chan(dev, "rx");
 316         if (IS_ERR(dma->chan_rx)) {
 317                 ret = PTR_ERR(dma->chan_rx);
 318                 if (ret != -ENODEV && ret != -EPROBE_DEFER)
 319                         dev_err(dev, "can't request DMA rx channel (%d)\n", ret);
 320                 goto fail_tx;
 321         }
 322
 323         dma_sconfig.src_addr = phy_addr +
 324                                 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
 325         dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 326         dma_sconfig.src_maxburst = 1;
 327         dma_sconfig.direction = DMA_DEV_TO_MEM;
 328         ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig);
 329         if (ret < 0) {
 330                 dev_err(dev, "can't configure rx channel (%d)\n", ret);
 331                 goto fail_rx;
 332         }
 333
 334         i2c_imx->dma = dma;
 335         init_completion(&dma->cmd_complete);
 336         dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n",
 337                 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
 338
 339         return;
 340
 341 fail_rx:
 342         dma_release_channel(dma->chan_rx);
 343 fail_tx:
 344         dma_release_channel(dma->chan_tx);
 345 fail_al:
 346         devm_kfree(dev, dma);
 347 }
 348
 349 static void i2c_imx_dma_callback(void *arg)
 350 {
 351         struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg;
 352         struct imx_i2c_dma *dma = i2c_imx->dma;
 353
 354         dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf,
 355                         dma->dma_len, dma->dma_data_dir);
 356         complete(&dma->cmd_complete);
 357 }
 358
 359 static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx,
 360                                         struct i2c_msg *msgs)
 361 {
 362         struct imx_i2c_dma *dma = i2c_imx->dma;
 363         struct dma_async_tx_descriptor *txdesc;
 364         struct device *dev = &i2c_imx->adapter.dev;
 365         struct device *chan_dev = dma->chan_using->device->dev;
 366
 367         dma->dma_buf = dma_map_single(chan_dev, msgs->buf,
 368                                         dma->dma_len, dma->dma_data_dir);
 369         if (dma_mapping_error(chan_dev, dma->dma_buf)) {
 370                 dev_err(dev, "DMA mapping failed\n");
 371                 goto err_map;
 372         }
 373
 374         txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf,
 375                                         dma->dma_len, dma->dma_transfer_dir,
 376                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 377         if (!txdesc) {
 378                 dev_err(dev, "Not able to get desc for DMA xfer\n");
 379                 goto err_desc;
 380         }
 381
 382         reinit_completion(&dma->cmd_complete);
 383         txdesc->callback = i2c_imx_dma_callback;
 384         txdesc->callback_param = i2c_imx;
 385         if (dma_submit_error(dmaengine_submit(txdesc))) {
 386                 dev_err(dev, "DMA submit failed\n");
 387                 goto err_submit;
 388         }
 389
 390         dma_async_issue_pending(dma->chan_using);
 391         return 0;
 392
 393 err_submit:
 394         dmaengine_terminate_all(dma->chan_using);
 395 err_desc:
 396         dma_unmap_single(chan_dev, dma->dma_buf,
 397                         dma->dma_len, dma->dma_data_dir);
 398 err_map:
 399         return -EINVAL;
 400 }
 401
 402 static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx)
 403 {
 404         struct imx_i2c_dma *dma = i2c_imx->dma;
 405
 406         dma->dma_buf = 0;
 407         dma->dma_len = 0;
 408
 409         dma_release_channel(dma->chan_tx);
 410         dma->chan_tx = NULL;
 411
 412         dma_release_channel(dma->chan_rx);
 413         dma->chan_rx = NULL;
 414
 415         dma->chan_using = NULL;
 416 }
 417
 418 static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy, bool atomic)
 419 {
 420         unsigned long orig_jiffies = jiffies;
 421         unsigned int temp;
 422
 423         dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
 424
 425         while (1) {
 426                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 427
 428                 /* check for arbitration lost */
 429                 if (temp & I2SR_IAL) {
 430                         temp &= ~I2SR_IAL;
 431                         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
 432                         return -EAGAIN;
 433                 }
 434
 435                 if (for_busy && (temp & I2SR_IBB)) {
 436                         i2c_imx->stopped = 0;
 437                         break;
 438                 }
 439                 if (!for_busy && !(temp & I2SR_IBB)) {
 440                         i2c_imx->stopped = 1;
 441                         break;
 442                 }
 443                 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
 444                         dev_dbg(&i2c_imx->adapter.dev,
 445                                 "<%s> I2C bus is busy\n", __func__);
 446                         return -ETIMEDOUT;
 447                 }
 448                 if (atomic)
 449                         udelay(100);
 450                 else
 451                         schedule();
 452         }
 453
 454         return 0;
 455 }
 456
 457 static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx, bool atomic)
 458 {
 459         if (atomic) {
 460                 void __iomem *addr = i2c_imx->base + (IMX_I2C_I2SR << i2c_imx->hwdata->regshift);
 461                 unsigned int regval;
 462
 463                 /*
 464                  * The formula for the poll timeout is documented in the RM
 465                  * Rev.5 on page 1878:
 466                  *     T_min = 10/F_scl
 467                  * Set the value hard as it is done for the non-atomic use-case.
 468                  * Use 10 kHz for the calculation since this is the minimum
 469                  * allowed SMBus frequency. Also add an offset of 100us since it
 470                  * turned out that the I2SR_IIF bit isn't set correctly within
 471                  * the minimum timeout in polling mode.
 472                  */
 473                 readb_poll_timeout_atomic(addr, regval, regval & I2SR_IIF, 5, 1000 + 100);
 474                 i2c_imx->i2csr = regval;
 475                 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR);
 476         } else {
 477                 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
 478         }
 479
 480         if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
 481                 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
 482                 return -ETIMEDOUT;
 483         }
 484         dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
 485         i2c_imx->i2csr = 0;
 486         return 0;
 487 }
 488
 489 static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
 490 {
 491         if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) {
 492                 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
 493                 return -ENXIO;  /* No ACK */
 494         }
 495
 496         dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
 497         return 0;
 498 }
 499
 500 static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
 501                             unsigned int i2c_clk_rate)
 502 {
 503         struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div;
 504         unsigned int div;
 505         int i;
 506
 507         /* Divider value calculation */
 508         if (i2c_imx->cur_clk == i2c_clk_rate)
 509                 return;
 510
 511         i2c_imx->cur_clk = i2c_clk_rate;
 512
 513         div = (i2c_clk_rate + i2c_imx->bitrate - 1) / i2c_imx->bitrate;
 514         if (div < i2c_clk_div[0].div)
 515                 i = 0;
 516         else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div)
 517                 i = i2c_imx->hwdata->ndivs - 1;
 518         else
 519                 for (i = 0; i2c_clk_div[i].div < div; i++)
 520                         ;
 521
 522         /* Store divider value */
 523         i2c_imx->ifdr = i2c_clk_div[i].val;
 524
 525         /*
 526          * There dummy delay is calculated.
 527          * It should be about one I2C clock period long.
 528          * This delay is used in I2C bus disable function
 529          * to fix chip hardware bug.
 530          */
 531         i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div
 532                 + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
 533
 534 #ifdef CONFIG_I2C_DEBUG_BUS
 535         dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n",
 536                 i2c_clk_rate, div);
 537         dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n",
 538                 i2c_clk_div[i].val, i2c_clk_div[i].div);
 539 #endif
 540 }
 541
 542 static int i2c_imx_clk_notifier_call(struct notifier_block *nb,
 543                                      unsigned long action, void *data)
 544 {
 545         struct clk_notifier_data *ndata = data;
 546         struct imx_i2c_struct *i2c_imx = container_of(nb,
 547                                                       struct imx_i2c_struct,
 548                                                       clk_change_nb);
 549
 550         if (action & POST_RATE_CHANGE)
 551                 i2c_imx_set_clk(i2c_imx, ndata->new_rate);
 552
 553         return NOTIFY_OK;
 554 }
 555
 556 static int i2c_imx_start(struct imx_i2c_struct *i2c_imx, bool atomic)
 557 {
 558         unsigned int temp = 0;
 559         int result;
 560
 561         dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
 562
 563         imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR);
 564         /* Enable I2C controller */
 565         imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
 566         imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR);
 567
 568         /* Wait controller to be stable */
 569         if (atomic)
 570                 udelay(50);
 571         else
 572                 usleep_range(50, 150);
 573
 574         /* Start I2C transaction */
 575         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 576         temp |= I2CR_MSTA;
 577         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 578         result = i2c_imx_bus_busy(i2c_imx, 1, atomic);
 579         if (result)
 580                 return result;
 581
 582         temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
 583         if (atomic)
 584                 temp &= ~I2CR_IIEN; /* Disable interrupt */
 585
 586         temp &= ~I2CR_DMAEN;
 587         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 588         return result;
 589 }
 590
 591 static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx, bool atomic)
 592 {
 593         unsigned int temp = 0;
 594
 595         if (!i2c_imx->stopped) {
 596                 /* Stop I2C transaction */
 597                 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
 598                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 599                 temp &= ~(I2CR_MSTA | I2CR_MTX);
 600                 if (i2c_imx->dma)
 601                         temp &= ~I2CR_DMAEN;
 602                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 603         }
 604         if (is_imx1_i2c(i2c_imx)) {
 605                 /*
 606                  * This delay caused by an i.MXL hardware bug.
 607                  * If no (or too short) delay, no "STOP" bit will be generated.
 608                  */
 609                 udelay(i2c_imx->disable_delay);
 610         }
 611
 612         if (!i2c_imx->stopped)
 613                 i2c_imx_bus_busy(i2c_imx, 0, atomic);
 614
 615         /* Disable I2C controller */
 616         temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
 617         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 618 }
 619
 620 static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
 621 {
 622         struct imx_i2c_struct *i2c_imx = dev_id;
 623         unsigned int temp;
 624
 625         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 626         if (temp & I2SR_IIF) {
 627                 /* save status register */
 628                 i2c_imx->i2csr = temp;
 629                 temp &= ~I2SR_IIF;
 630                 temp |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF);
 631                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
 632                 wake_up(&i2c_imx->queue);
 633                 return IRQ_HANDLED;
 634         }
 635
 636         return IRQ_NONE;
 637 }
 638
 639 static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx,
 640                                         struct i2c_msg *msgs)
 641 {
 642         int result;
 643         unsigned long time_left;
 644         unsigned int temp = 0;
 645         unsigned long orig_jiffies = jiffies;
 646         struct imx_i2c_dma *dma = i2c_imx->dma;
 647         struct device *dev = &i2c_imx->adapter.dev;
 648
 649         dma->chan_using = dma->chan_tx;
 650         dma->dma_transfer_dir = DMA_MEM_TO_DEV;
 651         dma->dma_data_dir = DMA_TO_DEVICE;
 652         dma->dma_len = msgs->len - 1;
 653         result = i2c_imx_dma_xfer(i2c_imx, msgs);
 654         if (result)
 655                 return result;
 656
 657         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 658         temp |= I2CR_DMAEN;
 659         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 660
 661         /*
 662          * Write slave address.
 663          * The first byte must be transmitted by the CPU.
 664          */
 665         imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
 666         time_left = wait_for_completion_timeout(
 667                                 &i2c_imx->dma->cmd_complete,
 668                                 msecs_to_jiffies(DMA_TIMEOUT));
 669         if (time_left == 0) {
 670                 dmaengine_terminate_all(dma->chan_using);
 671                 return -ETIMEDOUT;
 672         }
 673
 674         /* Waiting for transfer complete. */
 675         while (1) {
 676                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 677                 if (temp & I2SR_ICF)
 678                         break;
 679                 if (time_after(jiffies, orig_jiffies +
 680                                 msecs_to_jiffies(DMA_TIMEOUT))) {
 681                         dev_dbg(dev, "<%s> Timeout\n", __func__);
 682                         return -ETIMEDOUT;
 683                 }
 684                 schedule();
 685         }
 686
 687         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 688         temp &= ~I2CR_DMAEN;
 689         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 690
 691         /* The last data byte must be transferred by the CPU. */
 692         imx_i2c_write_reg(msgs->buf[msgs->len-1],
 693                                 i2c_imx, IMX_I2C_I2DR);
 694         result = i2c_imx_trx_complete(i2c_imx, false);
 695         if (result)
 696                 return result;
 697
 698         return i2c_imx_acked(i2c_imx);
 699 }
 700
 701 static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx,
 702                         struct i2c_msg *msgs, bool is_lastmsg)
 703 {
 704         int result;
 705         unsigned long time_left;
 706         unsigned int temp;
 707         unsigned long orig_jiffies = jiffies;
 708         struct imx_i2c_dma *dma = i2c_imx->dma;
 709         struct device *dev = &i2c_imx->adapter.dev;
 710
 711
 712         dma->chan_using = dma->chan_rx;
 713         dma->dma_transfer_dir = DMA_DEV_TO_MEM;
 714         dma->dma_data_dir = DMA_FROM_DEVICE;
 715         /* The last two data bytes must be transferred by the CPU. */
 716         dma->dma_len = msgs->len - 2;
 717         result = i2c_imx_dma_xfer(i2c_imx, msgs);
 718         if (result)
 719                 return result;
 720
 721         time_left = wait_for_completion_timeout(
 722                                 &i2c_imx->dma->cmd_complete,
 723                                 msecs_to_jiffies(DMA_TIMEOUT));
 724         if (time_left == 0) {
 725                 dmaengine_terminate_all(dma->chan_using);
 726                 return -ETIMEDOUT;
 727         }
 728
 729         /* waiting for transfer complete. */
 730         while (1) {
 731                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 732                 if (temp & I2SR_ICF)
 733                         break;
 734                 if (time_after(jiffies, orig_jiffies +
 735                                 msecs_to_jiffies(DMA_TIMEOUT))) {
 736                         dev_dbg(dev, "<%s> Timeout\n", __func__);
 737                         return -ETIMEDOUT;
 738                 }
 739                 schedule();
 740         }
 741
 742         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 743         temp &= ~I2CR_DMAEN;
 744         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 745
 746         /* read n-1 byte data */
 747         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 748         temp |= I2CR_TXAK;
 749         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 750
 751         msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
 752         /* read n byte data */
 753         result = i2c_imx_trx_complete(i2c_imx, false);
 754         if (result)
 755                 return result;
 756
 757         if (is_lastmsg) {
 758                 /*
 759                  * It must generate STOP before read I2DR to prevent
 760                  * controller from generating another clock cycle
 761                  */
 762                 dev_dbg(dev, "<%s> clear MSTA\n", __func__);
 763                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 764                 temp &= ~(I2CR_MSTA | I2CR_MTX);
 765                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 766                 i2c_imx_bus_busy(i2c_imx, 0, false);
 767         } else {
 768                 /*
 769                  * For i2c master receiver repeat restart operation like:
 770                  * read -> repeat MSTA -> read/write
 771                  * The controller must set MTX before read the last byte in
 772                  * the first read operation, otherwise the first read cost
 773                  * one extra clock cycle.
 774                  */
 775                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 776                 temp |= I2CR_MTX;
 777                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 778         }
 779         msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
 780
 781         return 0;
 782 }
 783
 784 static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs,
 785                          bool atomic)
 786 {
 787         int i, result;
 788
 789         dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
 790                 __func__, i2c_8bit_addr_from_msg(msgs));
 791
 792         /* write slave address */
 793         imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
 794         result = i2c_imx_trx_complete(i2c_imx, atomic);
 795         if (result)
 796                 return result;
 797         result = i2c_imx_acked(i2c_imx);
 798         if (result)
 799                 return result;
 800         dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
 801
 802         /* write data */
 803         for (i = 0; i < msgs->len; i++) {
 804                 dev_dbg(&i2c_imx->adapter.dev,
 805                         "<%s> write byte: B%d=0x%X\n",
 806                         __func__, i, msgs->buf[i]);
 807                 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR);
 808                 result = i2c_imx_trx_complete(i2c_imx, atomic);
 809                 if (result)
 810                         return result;
 811                 result = i2c_imx_acked(i2c_imx);
 812                 if (result)
 813                         return result;
 814         }
 815         return 0;
 816 }
 817
 818 static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs,
 819                         bool is_lastmsg, bool atomic)
 820 {
 821         int i, result;
 822         unsigned int temp;
 823         int block_data = msgs->flags & I2C_M_RECV_LEN;
 824         int use_dma = i2c_imx->dma && msgs->len >= DMA_THRESHOLD && !block_data;
 825
 826         dev_dbg(&i2c_imx->adapter.dev,
 827                 "<%s> write slave address: addr=0x%x\n",
 828                 __func__, i2c_8bit_addr_from_msg(msgs));
 829
 830         /* write slave address */
 831         imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
 832         result = i2c_imx_trx_complete(i2c_imx, atomic);
 833         if (result)
 834                 return result;
 835         result = i2c_imx_acked(i2c_imx);
 836         if (result)
 837                 return result;
 838
 839         dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
 840
 841         /* setup bus to read data */
 842         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 843         temp &= ~I2CR_MTX;
 844
 845         /*
 846          * Reset the I2CR_TXAK flag initially for SMBus block read since the
 847          * length is unknown
 848          */
 849         if ((msgs->len - 1) || block_data)
 850                 temp &= ~I2CR_TXAK;
 851         if (use_dma)
 852                 temp |= I2CR_DMAEN;
 853         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 854         imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */
 855
 856         dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
 857
 858         if (use_dma)
 859                 return i2c_imx_dma_read(i2c_imx, msgs, is_lastmsg);
 860
 861         /* read data */
 862         for (i = 0; i < msgs->len; i++) {
 863                 u8 len = 0;
 864
 865                 result = i2c_imx_trx_complete(i2c_imx, atomic);
 866                 if (result)
 867                         return result;
 868                 /*
 869                  * First byte is the length of remaining packet
 870                  * in the SMBus block data read. Add it to
 871                  * msgs->len.
 872                  */
 873                 if ((!i) && block_data) {
 874                         len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
 875                         if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX))
 876                                 return -EPROTO;
 877                         dev_dbg(&i2c_imx->adapter.dev,
 878                                 "<%s> read length: 0x%X\n",
 879                                 __func__, len);
 880                         msgs->len += len;
 881                 }
 882                 if (i == (msgs->len - 1)) {
 883                         if (is_lastmsg) {
 884                                 /*
 885                                  * It must generate STOP before read I2DR to prevent
 886                                  * controller from generating another clock cycle
 887                                  */
 888                                 dev_dbg(&i2c_imx->adapter.dev,
 889                                         "<%s> clear MSTA\n", __func__);
 890                                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 891                                 temp &= ~(I2CR_MSTA | I2CR_MTX);
 892                                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 893                                 i2c_imx_bus_busy(i2c_imx, 0, atomic);
 894                         } else {
 895                                 /*
 896                                  * For i2c master receiver repeat restart operation like:
 897                                  * read -> repeat MSTA -> read/write
 898                                  * The controller must set MTX before read the last byte in
 899                                  * the first read operation, otherwise the first read cost
 900                                  * one extra clock cycle.
 901                                  */
 902                                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 903                                 temp |= I2CR_MTX;
 904                                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 905                         }
 906                 } else if (i == (msgs->len - 2)) {
 907                         dev_dbg(&i2c_imx->adapter.dev,
 908                                 "<%s> set TXAK\n", __func__);
 909                         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 910                         temp |= I2CR_TXAK;
 911                         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 912                 }
 913                 if ((!i) && block_data)
 914                         msgs->buf[0] = len;
 915                 else
 916                         msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
 917                 dev_dbg(&i2c_imx->adapter.dev,
 918                         "<%s> read byte: B%d=0x%X\n",
 919                         __func__, i, msgs->buf[i]);
 920         }
 921         return 0;
 922 }
 923
 924 static int i2c_imx_xfer_common(struct i2c_adapter *adapter,
 925                                struct i2c_msg *msgs, int num, bool atomic)
 926 {
 927         unsigned int i, temp;
 928         int result;
 929         bool is_lastmsg = false;
 930         struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
 931
 932         dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
 933
 934         /* Start I2C transfer */
 935         result = i2c_imx_start(i2c_imx, atomic);
 936         if (result) {
 937                 /*
 938                  * Bus recovery uses gpiod_get_value_cansleep() which is not
 939                  * allowed within atomic context.
 940                  */
 941                 if (!atomic && i2c_imx->adapter.bus_recovery_info) {
 942                         i2c_recover_bus(&i2c_imx->adapter);
 943                         result = i2c_imx_start(i2c_imx, atomic);
 944                 }
 945         }
 946
 947         if (result)
 948                 goto fail0;
 949
 950         /* read/write data */
 951         for (i = 0; i < num; i++) {
 952                 if (i == num - 1)
 953                         is_lastmsg = true;
 954
 955                 if (i) {
 956                         dev_dbg(&i2c_imx->adapter.dev,
 957                                 "<%s> repeated start\n", __func__);
 958                         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 959                         temp |= I2CR_RSTA;
 960                         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 961                         result = i2c_imx_bus_busy(i2c_imx, 1, atomic);
 962                         if (result)
 963                                 goto fail0;
 964                 }
 965                 dev_dbg(&i2c_imx->adapter.dev,
 966                         "<%s> transfer message: %d\n", __func__, i);
 967                 /* write/read data */
 968 #ifdef CONFIG_I2C_DEBUG_BUS
 969                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 970                 dev_dbg(&i2c_imx->adapter.dev,
 971                         "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n",
 972                         __func__,
 973                         (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
 974                         (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
 975                         (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
 976                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 977                 dev_dbg(&i2c_imx->adapter.dev,
 978                         "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n",
 979                         __func__,
 980                         (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
 981                         (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
 982                         (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
 983                         (temp & I2SR_RXAK ? 1 : 0));
 984 #endif
 985                 if (msgs[i].flags & I2C_M_RD) {
 986                         result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg, atomic);
 987                 } else {
 988                         if (!atomic &&
 989                             i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD)
 990                                 result = i2c_imx_dma_write(i2c_imx, &msgs[i]);
 991                         else
 992                                 result = i2c_imx_write(i2c_imx, &msgs[i], atomic);
 993                 }
 994                 if (result)
 995                         goto fail0;
 996         }
 997
 998 fail0:
 999         /* Stop I2C transfer */
1000         i2c_imx_stop(i2c_imx, atomic);
1001
1002         dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
1003                 (result < 0) ? "error" : "success msg",
1004                         (result < 0) ? result : num);
1005         return (result < 0) ? result : num;
1006 }
1007
1008 static int i2c_imx_xfer(struct i2c_adapter *adapter,
1009                         struct i2c_msg *msgs, int num)
1010 {
1011         struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
1012         int result;
1013
1014         result = pm_runtime_get_sync(i2c_imx->adapter.dev.parent);
1015         if (result < 0)
1016                 return result;
1017
1018         result = i2c_imx_xfer_common(adapter, msgs, num, false);
1019
1020         pm_runtime_mark_last_busy(i2c_imx->adapter.dev.parent);
1021         pm_runtime_put_autosuspend(i2c_imx->adapter.dev.parent);
1022
1023         return result;
1024 }
1025
1026 static int i2c_imx_xfer_atomic(struct i2c_adapter *adapter,
1027                                struct i2c_msg *msgs, int num)
1028 {
1029         struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
1030         int result;
1031
1032         result = clk_enable(i2c_imx->clk);
1033         if (result)
1034                 return result;
1035
1036         result = i2c_imx_xfer_common(adapter, msgs, num, true);
1037
1038         clk_disable(i2c_imx->clk);
1039
1040         return result;
1041 }
1042
1043 static void i2c_imx_prepare_recovery(struct i2c_adapter *adap)
1044 {
1045         struct imx_i2c_struct *i2c_imx;
1046
1047         i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
1048
1049         pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_gpio);
1050 }
1051
1052 static void i2c_imx_unprepare_recovery(struct i2c_adapter *adap)
1053 {
1054         struct imx_i2c_struct *i2c_imx;
1055
1056         i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
1057
1058         pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_default);
1059 }
1060
1061 /*
1062  * We switch SCL and SDA to their GPIO function and do some bitbanging
1063  * for bus recovery. These alternative pinmux settings can be
1064  * described in the device tree by a separate pinctrl state "gpio". If
1065  * this is missing this is not a big problem, the only implication is
1066  * that we can't do bus recovery.
1067  */
1068 static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx,
1069                 struct platform_device *pdev)
1070 {
1071         struct i2c_bus_recovery_info *rinfo = &i2c_imx->rinfo;
1072
1073         i2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev);
1074         if (!i2c_imx->pinctrl || IS_ERR(i2c_imx->pinctrl)) {
1075                 dev_info(&pdev->dev, "can't get pinctrl, bus recovery not supported\n");
1076                 return PTR_ERR(i2c_imx->pinctrl);
1077         }
1078
1079         i2c_imx->pinctrl_pins_default = pinctrl_lookup_state(i2c_imx->pinctrl,
1080                         PINCTRL_STATE_DEFAULT);
1081         i2c_imx->pinctrl_pins_gpio = pinctrl_lookup_state(i2c_imx->pinctrl,
1082                         "gpio");
1083         rinfo->sda_gpiod = devm_gpiod_get(&pdev->dev, "sda", GPIOD_IN);
1084         rinfo->scl_gpiod = devm_gpiod_get(&pdev->dev, "scl", GPIOD_OUT_HIGH_OPEN_DRAIN);
1085
1086         if (PTR_ERR(rinfo->sda_gpiod) == -EPROBE_DEFER ||
1087             PTR_ERR(rinfo->scl_gpiod) == -EPROBE_DEFER) {
1088                 return -EPROBE_DEFER;
1089         } else if (IS_ERR(rinfo->sda_gpiod) ||
1090                    IS_ERR(rinfo->scl_gpiod) ||
1091                    IS_ERR(i2c_imx->pinctrl_pins_default) ||
1092                    IS_ERR(i2c_imx->pinctrl_pins_gpio)) {
1093                 dev_dbg(&pdev->dev, "recovery information incomplete\n");
1094                 return 0;
1095         }
1096
1097         dev_dbg(&pdev->dev, "using scl%s for recovery\n",
1098                 rinfo->sda_gpiod ? ",sda" : "");
1099
1100         rinfo->prepare_recovery = i2c_imx_prepare_recovery;
1101         rinfo->unprepare_recovery = i2c_imx_unprepare_recovery;
1102         rinfo->recover_bus = i2c_generic_scl_recovery;
1103         i2c_imx->adapter.bus_recovery_info = rinfo;
1104
1105         return 0;
1106 }
1107
1108 static u32 i2c_imx_func(struct i2c_adapter *adapter)
1109 {
1110         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
1111                 | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
1112 }
1113
1114 static const struct i2c_algorithm i2c_imx_algo = {
1115         .master_xfer = i2c_imx_xfer,
1116         .master_xfer_atomic = i2c_imx_xfer_atomic,
1117         .functionality = i2c_imx_func,
1118 };
1119
1120 static int i2c_imx_probe(struct platform_device *pdev)
1121 {
1122         struct imx_i2c_struct *i2c_imx;
1123         struct resource *res;
1124         struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev);
1125         void __iomem *base;
1126         int irq, ret;
1127         dma_addr_t phy_addr;
1128         const struct imx_i2c_hwdata *match;
1129
1130         dev_dbg(&pdev->dev, "<%s>\n", __func__);
1131
1132         irq = platform_get_irq(pdev, 0);
1133         if (irq < 0) {
1134                 dev_err(&pdev->dev, "can't get irq number\n");
1135                 return irq;
1136         }
1137
1138         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1139         base = devm_ioremap_resource(&pdev->dev, res);
1140         if (IS_ERR(base))
1141                 return PTR_ERR(base);
1142
1143         phy_addr = (dma_addr_t)res->start;
1144         i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL);
1145         if (!i2c_imx)
1146                 return -ENOMEM;
1147
1148         match = device_get_match_data(&pdev->dev);
1149         if (match)
1150                 i2c_imx->hwdata = match;
1151         else
1152                 i2c_imx->hwdata = (struct imx_i2c_hwdata *)
1153                                 platform_get_device_id(pdev)->driver_data;
1154
1155         /* Setup i2c_imx driver structure */
1156         strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));
1157         i2c_imx->adapter.owner          = THIS_MODULE;
1158         i2c_imx->adapter.algo           = &i2c_imx_algo;
1159         i2c_imx->adapter.dev.parent     = &pdev->dev;
1160         i2c_imx->adapter.nr             = pdev->id;
1161         i2c_imx->adapter.dev.of_node    = pdev->dev.of_node;
1162         i2c_imx->base                   = base;
1163         ACPI_COMPANION_SET(&i2c_imx->adapter.dev, ACPI_COMPANION(&pdev->dev));
1164
1165         /* Get I2C clock */
1166         i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
1167         if (IS_ERR(i2c_imx->clk)) {
1168                 if (PTR_ERR(i2c_imx->clk) != -EPROBE_DEFER)
1169                         dev_err(&pdev->dev, "can't get I2C clock\n");
1170                 return PTR_ERR(i2c_imx->clk);
1171         }
1172
1173         ret = clk_prepare_enable(i2c_imx->clk);
1174         if (ret) {
1175                 dev_err(&pdev->dev, "can't enable I2C clock, ret=%d\n", ret);
1176                 return ret;
1177         }
1178
1179         /* Request IRQ */
1180         ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, IRQF_SHARED,
1181                                 pdev->name, i2c_imx);
1182         if (ret) {
1183                 dev_err(&pdev->dev, "can't claim irq %d\n", irq);
1184                 goto clk_disable;
1185         }
1186
1187         /* Init queue */
1188         init_waitqueue_head(&i2c_imx->queue);
1189
1190         /* Set up adapter data */
1191         i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
1192
1193         /* Set up platform driver data */
1194         platform_set_drvdata(pdev, i2c_imx);
1195
1196         pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT);
1197         pm_runtime_use_autosuspend(&pdev->dev);
1198         pm_runtime_set_active(&pdev->dev);
1199         pm_runtime_enable(&pdev->dev);
1200
1201         ret = pm_runtime_get_sync(&pdev->dev);
1202         if (ret < 0)
1203                 goto rpm_disable;
1204
1205         /* Set up clock divider */
1206         i2c_imx->bitrate = IMX_I2C_BIT_RATE;
1207         ret = of_property_read_u32(pdev->dev.of_node,
1208                                    "clock-frequency", &i2c_imx->bitrate);
1209         if (ret < 0 && pdata && pdata->bitrate)
1210                 i2c_imx->bitrate = pdata->bitrate;
1211         i2c_imx->clk_change_nb.notifier_call = i2c_imx_clk_notifier_call;
1212         clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb);
1213         i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk));
1214
1215         /* Set up chip registers to defaults */
1216         imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
1217                         i2c_imx, IMX_I2C_I2CR);
1218         imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
1219
1220         /* Init optional bus recovery function */
1221         ret = i2c_imx_init_recovery_info(i2c_imx, pdev);
1222         /* Give it another chance if pinctrl used is not ready yet */
1223         if (ret == -EPROBE_DEFER)
1224                 goto clk_notifier_unregister;
1225
1226         /* Add I2C adapter */
1227         ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
1228         if (ret < 0)
1229                 goto clk_notifier_unregister;
1230
1231         pm_runtime_mark_last_busy(&pdev->dev);
1232         pm_runtime_put_autosuspend(&pdev->dev);
1233
1234         dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
1235         dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res);
1236         dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
1237                 i2c_imx->adapter.name);
1238         dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
1239
1240         /* Init DMA config if supported */
1241         i2c_imx_dma_request(i2c_imx, phy_addr);
1242
1243         return 0;   /* Return OK */
1244
1245 clk_notifier_unregister:
1246         clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);
1247 rpm_disable:
1248         pm_runtime_put_noidle(&pdev->dev);
1249         pm_runtime_disable(&pdev->dev);
1250         pm_runtime_set_suspended(&pdev->dev);
1251         pm_runtime_dont_use_autosuspend(&pdev->dev);
1252
1253 clk_disable:
1254         clk_disable_unprepare(i2c_imx->clk);
1255         return ret;
1256 }
1257
1258 static int i2c_imx_remove(struct platform_device *pdev)
1259 {
1260         struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
1261         int ret;
1262
1263         ret = pm_runtime_get_sync(&pdev->dev);
1264         if (ret < 0)
1265                 return ret;
1266
1267         /* remove adapter */
1268         dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
1269         i2c_del_adapter(&i2c_imx->adapter);
1270
1271         if (i2c_imx->dma)
1272                 i2c_imx_dma_free(i2c_imx);
1273
1274         /* setup chip registers to defaults */
1275         imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
1276         imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR);
1277         imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR);
1278         imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR);
1279
1280         clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);
1281         clk_disable_unprepare(i2c_imx->clk);
1282
1283         pm_runtime_put_noidle(&pdev->dev);
1284         pm_runtime_disable(&pdev->dev);
1285
1286         return 0;
1287 }
1288
1289 static int __maybe_unused i2c_imx_runtime_suspend(struct device *dev)
1290 {
1291         struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
1292
1293         clk_disable(i2c_imx->clk);
1294
1295         return 0;
1296 }
1297
1298 static int __maybe_unused i2c_imx_runtime_resume(struct device *dev)
1299 {
1300         struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
1301         int ret;
1302
1303         ret = clk_enable(i2c_imx->clk);
1304         if (ret)
1305                 dev_err(dev, "can't enable I2C clock, ret=%d\n", ret);
1306
1307         return ret;
1308 }
1309
1310 static const struct dev_pm_ops i2c_imx_pm_ops = {
1311         SET_RUNTIME_PM_OPS(i2c_imx_runtime_suspend,
1312                            i2c_imx_runtime_resume, NULL)
1313 };
1314
1315 static struct platform_driver i2c_imx_driver = {
1316         .probe = i2c_imx_probe,
1317         .remove = i2c_imx_remove,
1318         .driver = {
1319                 .name = DRIVER_NAME,
1320                 .pm = &i2c_imx_pm_ops,
1321                 .of_match_table = i2c_imx_dt_ids,
1322                 .acpi_match_table = i2c_imx_acpi_ids,
1323         },
1324         .id_table = imx_i2c_devtype,
1325 };
1326
1327 static int __init i2c_adap_imx_init(void)
1328 {
1329         return platform_driver_register(&i2c_imx_driver);
1330 }
1331 subsys_initcall(i2c_adap_imx_init);
1332
1333 static void __exit i2c_adap_imx_exit(void)
1334 {
1335         platform_driver_unregister(&i2c_imx_driver);
1336 }
1337 module_exit(i2c_adap_imx_exit);
1338
1339 MODULE_LICENSE("GPL");
1340 MODULE_AUTHOR("Darius Augulis");
1341 MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
1342 MODULE_ALIAS("platform:" DRIVER_NAME);