1 // SPDX-License-Identifier: GPL-2.0-or-later
3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
4 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
6 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de>
7 Copyright (C) 2010 Intel Corporation,
8 David Woodhouse <dwmw2@infradead.org>
13 * Supports the following Intel I/O Controller Hubs (ICH):
16 * region SMBus Block proc. block
17 * Chip name PCI ID size PEC buffer call read
18 * ---------------------------------------------------------------------------
19 * 82801AA (ICH) 0x2413 16 no no no no
20 * 82801AB (ICH0) 0x2423 16 no no no no
21 * 82801BA (ICH2) 0x2443 16 no no no no
22 * 82801CA (ICH3) 0x2483 32 soft no no no
23 * 82801DB (ICH4) 0x24c3 32 hard yes no no
24 * 82801E (ICH5) 0x24d3 32 hard yes yes yes
25 * 6300ESB 0x25a4 32 hard yes yes yes
26 * 82801F (ICH6) 0x266a 32 hard yes yes yes
27 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes
28 * 82801G (ICH7) 0x27da 32 hard yes yes yes
29 * 82801H (ICH8) 0x283e 32 hard yes yes yes
30 * 82801I (ICH9) 0x2930 32 hard yes yes yes
31 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes
32 * ICH10 0x3a30 32 hard yes yes yes
33 * ICH10 0x3a60 32 hard yes yes yes
34 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
35 * 6 Series (PCH) 0x1c22 32 hard yes yes yes
36 * Patsburg (PCH) 0x1d22 32 hard yes yes yes
37 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
38 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
39 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
40 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes
41 * Panther Point (PCH) 0x1e22 32 hard yes yes yes
42 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes
43 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
44 * Avoton (SOC) 0x1f3c 32 hard yes yes yes
45 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes
46 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes
47 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
48 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
49 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes
50 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes
51 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
52 * BayTrail (SOC) 0x0f12 32 hard yes yes yes
53 * Braswell (SOC) 0x2292 32 hard yes yes yes
54 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes
55 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes
56 * DNV (SOC) 0x19df 32 hard yes yes yes
57 * Emmitsburg (PCH) 0x1bc9 32 hard yes yes yes
58 * Broxton (SOC) 0x5ad4 32 hard yes yes yes
59 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes
60 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes
61 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes
62 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes
63 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes
64 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes
65 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes
66 * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes
67 * Comet Lake (PCH) 0x02a3 32 hard yes yes yes
68 * Comet Lake-H (PCH) 0x06a3 32 hard yes yes yes
69 * Elkhart Lake (PCH) 0x4b23 32 hard yes yes yes
70 * Tiger Lake-LP (PCH) 0xa0a3 32 hard yes yes yes
71 * Tiger Lake-H (PCH) 0x43a3 32 hard yes yes yes
72 * Jasper Lake (SOC) 0x4da3 32 hard yes yes yes
73 * Comet Lake-V (PCH) 0xa3a3 32 hard yes yes yes
74 * Alder Lake-S (PCH) 0x7aa3 32 hard yes yes yes
75 * Alder Lake-P (PCH) 0x51a3 32 hard yes yes yes
77 * Features supported by this driver:
81 * Block process call transaction yes
82 * I2C block read transaction yes (doesn't use the block buffer)
84 * SMBus Host Notify yes
85 * Interrupt processing yes
87 * See the file Documentation/i2c/busses/i2c-i801.rst for details.
90 #include <linux/interrupt.h>
91 #include <linux/module.h>
92 #include <linux/pci.h>
93 #include <linux/kernel.h>
94 #include <linux/stddef.h>
95 #include <linux/delay.h>
96 #include <linux/ioport.h>
97 #include <linux/init.h>
98 #include <linux/i2c.h>
99 #include <linux/i2c-smbus.h>
100 #include <linux/acpi.h>
101 #include <linux/io.h>
102 #include <linux/dmi.h>
103 #include <linux/slab.h>
104 #include <linux/string.h>
105 #include <linux/wait.h>
106 #include <linux/err.h>
107 #include <linux/platform_device.h>
108 #include <linux/platform_data/itco_wdt.h>
109 #include <linux/pm_runtime.h>
111 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
112 #include <linux/gpio/machine.h>
113 #include <linux/platform_data/i2c-mux-gpio.h>
116 /* I801 SMBus address offsets */
117 #define SMBHSTSTS(p) (0 + (p)->smba)
118 #define SMBHSTCNT(p) (2 + (p)->smba)
119 #define SMBHSTCMD(p) (3 + (p)->smba)
120 #define SMBHSTADD(p) (4 + (p)->smba)
121 #define SMBHSTDAT0(p) (5 + (p)->smba)
122 #define SMBHSTDAT1(p) (6 + (p)->smba)
123 #define SMBBLKDAT(p) (7 + (p)->smba)
124 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
125 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
126 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
127 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */
128 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */
129 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */
131 /* PCI Address Constants */
133 #define SMBPCICTL 0x004
134 #define SMBPCISTS 0x006
135 #define SMBHSTCFG 0x040
136 #define TCOBASE 0x050
139 #define SBREG_BAR 0x10
140 #define SBREG_SMBCTRL 0xc6000c
141 #define SBREG_SMBCTRL_DNV 0xcf000c
143 /* Host status bits for SMBPCISTS */
144 #define SMBPCISTS_INTS BIT(3)
146 /* Control bits for SMBPCICTL */
147 #define SMBPCICTL_INTDIS BIT(10)
149 /* Host configuration bits for SMBHSTCFG */
150 #define SMBHSTCFG_HST_EN BIT(0)
151 #define SMBHSTCFG_SMB_SMI_EN BIT(1)
152 #define SMBHSTCFG_I2C_EN BIT(2)
153 #define SMBHSTCFG_SPD_WD BIT(4)
155 /* TCO configuration bits for TCOCTL */
156 #define TCOCTL_EN BIT(8)
158 /* Auxiliary status register bits, ICH4+ only */
159 #define SMBAUXSTS_CRCE BIT(0)
160 #define SMBAUXSTS_STCO BIT(1)
162 /* Auxiliary control register bits, ICH4+ only */
163 #define SMBAUXCTL_CRC BIT(0)
164 #define SMBAUXCTL_E32B BIT(1)
167 #define MAX_RETRIES 400
169 /* I801 command constants */
170 #define I801_QUICK 0x00
171 #define I801_BYTE 0x04
172 #define I801_BYTE_DATA 0x08
173 #define I801_WORD_DATA 0x0C
174 #define I801_PROC_CALL 0x10 /* unimplemented */
175 #define I801_BLOCK_DATA 0x14
176 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
177 #define I801_BLOCK_PROC_CALL 0x1C
179 /* I801 Host Control register bits */
180 #define SMBHSTCNT_INTREN BIT(0)
181 #define SMBHSTCNT_KILL BIT(1)
182 #define SMBHSTCNT_LAST_BYTE BIT(5)
183 #define SMBHSTCNT_START BIT(6)
184 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */
186 /* I801 Hosts Status register bits */
187 #define SMBHSTSTS_BYTE_DONE BIT(7)
188 #define SMBHSTSTS_INUSE_STS BIT(6)
189 #define SMBHSTSTS_SMBALERT_STS BIT(5)
190 #define SMBHSTSTS_FAILED BIT(4)
191 #define SMBHSTSTS_BUS_ERR BIT(3)
192 #define SMBHSTSTS_DEV_ERR BIT(2)
193 #define SMBHSTSTS_INTR BIT(1)
194 #define SMBHSTSTS_HOST_BUSY BIT(0)
196 /* Host Notify Status register bits */
197 #define SMBSLVSTS_HST_NTFY_STS BIT(0)
199 /* Host Notify Command register bits */
200 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0)
202 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
205 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
208 /* Older devices have their ID defined in <linux/pci_ids.h> */
209 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS 0x02a3
210 #define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS 0x06a3
211 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12
212 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df
213 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df
214 #define PCI_DEVICE_ID_INTEL_EBG_SMBUS 0x1bc9
215 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
216 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
217 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
218 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
219 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
220 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
221 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
222 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
223 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292
224 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
225 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0
226 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4
227 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3
228 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
229 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS 0x43a3
230 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23
231 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS 0x4da3
232 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS 0x51a3
233 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4
234 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS 0x7aa3
235 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
236 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2
237 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
238 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
239 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
240 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
241 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
242 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2
243 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23
244 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3
245 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS 0xa0a3
246 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123
247 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3
248 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223
249 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3
250 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323
251 #define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS 0xa3a3
253 struct i801_mux_config {
258 unsigned gpios[2]; /* Relative to gpio_chip->base */
263 struct i2c_adapter adapter;
265 unsigned char original_hstcfg;
266 unsigned char original_slvcmd;
267 struct pci_dev *pci_dev;
268 unsigned int features;
271 wait_queue_head_t waitq;
274 /* Command state used by isr for byte-by-byte block transactions */
281 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
282 const struct i801_mux_config *mux_drvdata;
283 struct platform_device *mux_pdev;
284 struct gpiod_lookup_table *lookup;
286 struct platform_device *tco_pdev;
289 * If set to true the host controller registers are reserved for
290 * ACPI AML use. Protected by acpi_lock.
293 struct mutex acpi_lock;
296 #define FEATURE_SMBUS_PEC BIT(0)
297 #define FEATURE_BLOCK_BUFFER BIT(1)
298 #define FEATURE_BLOCK_PROC BIT(2)
299 #define FEATURE_I2C_BLOCK_READ BIT(3)
300 #define FEATURE_IRQ BIT(4)
301 #define FEATURE_HOST_NOTIFY BIT(5)
302 /* Not really a feature, but it's convenient to handle it as such */
303 #define FEATURE_IDF BIT(15)
304 #define FEATURE_TCO_SPT BIT(16)
305 #define FEATURE_TCO_CNL BIT(17)
307 static const char *i801_feature_names[] = {
310 "Block process call",
316 static unsigned int disable_features;
317 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
318 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
319 "\t\t 0x01 disable SMBus PEC\n"
320 "\t\t 0x02 disable the block buffer\n"
321 "\t\t 0x08 disable the I2C block read functionality\n"
322 "\t\t 0x10 don't use interrupts\n"
323 "\t\t 0x20 disable SMBus Host Notify ");
325 /* Make sure the SMBus host is ready to start transmitting.
326 Return 0 if it is, -EBUSY if it is not. */
327 static int i801_check_pre(struct i801_priv *priv)
331 status = inb_p(SMBHSTSTS(priv));
332 if (status & SMBHSTSTS_HOST_BUSY) {
333 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
337 status &= STATUS_FLAGS;
339 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
341 outb_p(status, SMBHSTSTS(priv));
342 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
344 dev_err(&priv->pci_dev->dev,
345 "Failed clearing status flags (%02x)\n",
352 * Clear CRC status if needed.
353 * During normal operation, i801_check_post() takes care
354 * of it after every operation. We do it here only in case
355 * the hardware was already in this state when the driver
358 if (priv->features & FEATURE_SMBUS_PEC) {
359 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
361 dev_dbg(&priv->pci_dev->dev,
362 "Clearing aux status flags (%02x)\n", status);
363 outb_p(status, SMBAUXSTS(priv));
364 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
366 dev_err(&priv->pci_dev->dev,
367 "Failed clearing aux status flags (%02x)\n",
378 * Convert the status register to an error code, and clear it.
379 * Note that status only contains the bits we want to clear, not the
380 * actual register value.
382 static int i801_check_post(struct i801_priv *priv, int status)
387 * If the SMBus is still busy, we give up
388 * Note: This timeout condition only happens when using polling
389 * transactions. For interrupt operation, NAK/timeout is indicated by
392 if (unlikely(status < 0)) {
393 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
394 /* try to stop the current command */
395 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
396 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
398 usleep_range(1000, 2000);
399 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
402 /* Check if it worked */
403 status = inb_p(SMBHSTSTS(priv));
404 if ((status & SMBHSTSTS_HOST_BUSY) ||
405 !(status & SMBHSTSTS_FAILED))
406 dev_err(&priv->pci_dev->dev,
407 "Failed terminating the transaction\n");
408 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
412 if (status & SMBHSTSTS_FAILED) {
414 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
416 if (status & SMBHSTSTS_DEV_ERR) {
418 * This may be a PEC error, check and clear it.
420 * AUXSTS is handled differently from HSTSTS.
421 * For HSTSTS, i801_isr() or i801_wait_intr()
422 * has already cleared the error bits in hardware,
423 * and we are passed a copy of the original value
425 * For AUXSTS, the hardware register is left
426 * for us to handle here.
427 * This is asymmetric, slightly iffy, but safe,
428 * since all this code is serialized and the CRCE
429 * bit is harmless as long as it's cleared before
430 * the next operation.
432 if ((priv->features & FEATURE_SMBUS_PEC) &&
433 (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
434 outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
436 dev_dbg(&priv->pci_dev->dev, "PEC error\n");
439 dev_dbg(&priv->pci_dev->dev, "No response\n");
442 if (status & SMBHSTSTS_BUS_ERR) {
444 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
447 /* Clear status flags except BYTE_DONE, to be cleared by caller */
448 outb_p(status, SMBHSTSTS(priv));
453 /* Wait for BUSY being cleared and either INTR or an error flag being set */
454 static int i801_wait_intr(struct i801_priv *priv)
459 /* We will always wait for a fraction of a second! */
461 usleep_range(250, 500);
462 status = inb_p(SMBHSTSTS(priv));
463 } while (((status & SMBHSTSTS_HOST_BUSY) ||
464 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
465 (timeout++ < MAX_RETRIES));
467 if (timeout > MAX_RETRIES) {
468 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
471 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
474 /* Wait for either BYTE_DONE or an error flag being set */
475 static int i801_wait_byte_done(struct i801_priv *priv)
480 /* We will always wait for a fraction of a second! */
482 usleep_range(250, 500);
483 status = inb_p(SMBHSTSTS(priv));
484 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
485 (timeout++ < MAX_RETRIES));
487 if (timeout > MAX_RETRIES) {
488 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
491 return status & STATUS_ERROR_FLAGS;
494 static int i801_transaction(struct i801_priv *priv, int xact)
498 const struct i2c_adapter *adap = &priv->adapter;
500 result = i801_check_pre(priv);
504 if (priv->features & FEATURE_IRQ) {
505 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
507 result = wait_event_timeout(priv->waitq,
508 (status = priv->status),
512 dev_warn(&priv->pci_dev->dev,
513 "Timeout waiting for interrupt!\n");
516 return i801_check_post(priv, status);
519 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
520 * SMBSCMD are passed in xact */
521 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
523 status = i801_wait_intr(priv);
524 return i801_check_post(priv, status);
527 static int i801_block_transaction_by_block(struct i801_priv *priv,
528 union i2c_smbus_data *data,
529 char read_write, int command,
534 int xact = hwpec ? SMBHSTCNT_PEC_EN : 0;
537 case I2C_SMBUS_BLOCK_PROC_CALL:
538 xact |= I801_BLOCK_PROC_CALL;
540 case I2C_SMBUS_BLOCK_DATA:
541 xact |= I801_BLOCK_DATA;
547 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
549 /* Use 32-byte buffer to process this transaction */
550 if (read_write == I2C_SMBUS_WRITE) {
551 len = data->block[0];
552 outb_p(len, SMBHSTDAT0(priv));
553 for (i = 0; i < len; i++)
554 outb_p(data->block[i+1], SMBBLKDAT(priv));
557 status = i801_transaction(priv, xact);
561 if (read_write == I2C_SMBUS_READ ||
562 command == I2C_SMBUS_BLOCK_PROC_CALL) {
563 len = inb_p(SMBHSTDAT0(priv));
564 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
567 data->block[0] = len;
568 for (i = 0; i < len; i++)
569 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
574 static void i801_isr_byte_done(struct i801_priv *priv)
577 /* For SMBus block reads, length is received with first byte */
578 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
579 (priv->count == 0)) {
580 priv->len = inb_p(SMBHSTDAT0(priv));
581 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
582 dev_err(&priv->pci_dev->dev,
583 "Illegal SMBus block read size %d\n",
586 priv->len = I2C_SMBUS_BLOCK_MAX;
588 dev_dbg(&priv->pci_dev->dev,
589 "SMBus block read size is %d\n",
592 priv->data[-1] = priv->len;
596 if (priv->count < priv->len)
597 priv->data[priv->count++] = inb(SMBBLKDAT(priv));
599 dev_dbg(&priv->pci_dev->dev,
600 "Discarding extra byte on block read\n");
602 /* Set LAST_BYTE for last byte of read transaction */
603 if (priv->count == priv->len - 1)
604 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
606 } else if (priv->count < priv->len - 1) {
607 /* Write next byte, except for IRQ after last byte */
608 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
611 /* Clear BYTE_DONE to continue with next byte */
612 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
615 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
619 addr = inb_p(SMBNTFDADD(priv)) >> 1;
622 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
623 * always returns 0. Our current implementation doesn't provide
624 * data, so we just ignore it.
626 i2c_handle_smbus_host_notify(&priv->adapter, addr);
628 /* clear Host Notify bit and return */
629 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
634 * There are three kinds of interrupts:
636 * 1) i801 signals transaction completion with one of these interrupts:
638 * DEV_ERR - Invalid command, NAK or communication timeout
639 * BUS_ERR - SMI# transaction collision
640 * FAILED - transaction was canceled due to a KILL request
641 * When any of these occur, update ->status and wake up the waitq.
642 * ->status must be cleared before kicking off the next transaction.
644 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
645 * occurs for each byte of a byte-by-byte to prepare the next byte.
647 * 3) Host Notify interrupts
649 static irqreturn_t i801_isr(int irq, void *dev_id)
651 struct i801_priv *priv = dev_id;
655 /* Confirm this is our interrupt */
656 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
657 if (!(pcists & SMBPCISTS_INTS))
660 if (priv->features & FEATURE_HOST_NOTIFY) {
661 status = inb_p(SMBSLVSTS(priv));
662 if (status & SMBSLVSTS_HST_NTFY_STS)
663 return i801_host_notify_isr(priv);
666 status = inb_p(SMBHSTSTS(priv));
667 if (status & SMBHSTSTS_BYTE_DONE)
668 i801_isr_byte_done(priv);
671 * Clear irq sources and report transaction result.
672 * ->status must be cleared before the next transaction is started.
674 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
676 outb_p(status, SMBHSTSTS(priv));
677 priv->status = status;
678 wake_up(&priv->waitq);
685 * For "byte-by-byte" block transactions:
686 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
687 * I2C read uses cmd=I801_I2C_BLOCK_DATA
689 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
690 union i2c_smbus_data *data,
691 char read_write, int command,
698 const struct i2c_adapter *adap = &priv->adapter;
700 if (command == I2C_SMBUS_BLOCK_PROC_CALL)
703 result = i801_check_pre(priv);
707 len = data->block[0];
709 if (read_write == I2C_SMBUS_WRITE) {
710 outb_p(len, SMBHSTDAT0(priv));
711 outb_p(data->block[1], SMBBLKDAT(priv));
714 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
715 read_write == I2C_SMBUS_READ)
716 smbcmd = I801_I2C_BLOCK_DATA;
718 smbcmd = I801_BLOCK_DATA;
720 if (priv->features & FEATURE_IRQ) {
721 priv->is_read = (read_write == I2C_SMBUS_READ);
722 if (len == 1 && priv->is_read)
723 smbcmd |= SMBHSTCNT_LAST_BYTE;
724 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
727 priv->data = &data->block[1];
729 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
730 result = wait_event_timeout(priv->waitq,
731 (status = priv->status),
735 dev_warn(&priv->pci_dev->dev,
736 "Timeout waiting for interrupt!\n");
739 return i801_check_post(priv, status);
742 for (i = 1; i <= len; i++) {
743 if (i == len && read_write == I2C_SMBUS_READ)
744 smbcmd |= SMBHSTCNT_LAST_BYTE;
745 outb_p(smbcmd, SMBHSTCNT(priv));
748 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
751 status = i801_wait_byte_done(priv);
755 if (i == 1 && read_write == I2C_SMBUS_READ
756 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
757 len = inb_p(SMBHSTDAT0(priv));
758 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
759 dev_err(&priv->pci_dev->dev,
760 "Illegal SMBus block read size %d\n",
763 while (inb_p(SMBHSTSTS(priv)) &
765 outb_p(SMBHSTSTS_BYTE_DONE,
767 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
770 data->block[0] = len;
773 /* Retrieve/store value in SMBBLKDAT */
774 if (read_write == I2C_SMBUS_READ)
775 data->block[i] = inb_p(SMBBLKDAT(priv));
776 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
777 outb_p(data->block[i+1], SMBBLKDAT(priv));
779 /* signals SMBBLKDAT ready */
780 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
783 status = i801_wait_intr(priv);
785 return i801_check_post(priv, status);
788 static int i801_set_block_buffer_mode(struct i801_priv *priv)
790 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
791 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
796 /* Block transaction function */
797 static int i801_block_transaction(struct i801_priv *priv,
798 union i2c_smbus_data *data, char read_write,
799 int command, int hwpec)
804 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
805 if (read_write == I2C_SMBUS_WRITE) {
806 /* set I2C_EN bit in configuration register */
807 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
808 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
809 hostc | SMBHSTCFG_I2C_EN);
810 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
811 dev_err(&priv->pci_dev->dev,
812 "I2C block read is unsupported!\n");
817 if (read_write == I2C_SMBUS_WRITE
818 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
819 if (data->block[0] < 1)
821 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
822 data->block[0] = I2C_SMBUS_BLOCK_MAX;
824 data->block[0] = 32; /* max for SMBus block reads */
827 /* Experience has shown that the block buffer can only be used for
828 SMBus (not I2C) block transactions, even though the datasheet
829 doesn't mention this limitation. */
830 if ((priv->features & FEATURE_BLOCK_BUFFER)
831 && command != I2C_SMBUS_I2C_BLOCK_DATA
832 && i801_set_block_buffer_mode(priv) == 0)
833 result = i801_block_transaction_by_block(priv, data,
837 result = i801_block_transaction_byte_by_byte(priv, data,
841 if (command == I2C_SMBUS_I2C_BLOCK_DATA
842 && read_write == I2C_SMBUS_WRITE) {
843 /* restore saved configuration register value */
844 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
849 /* Return negative errno on error. */
850 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
851 unsigned short flags, char read_write, u8 command,
852 int size, union i2c_smbus_data *data)
856 int ret = 0, xact = 0;
857 struct i801_priv *priv = i2c_get_adapdata(adap);
859 mutex_lock(&priv->acpi_lock);
860 if (priv->acpi_reserved) {
861 mutex_unlock(&priv->acpi_lock);
865 pm_runtime_get_sync(&priv->pci_dev->dev);
867 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
868 && size != I2C_SMBUS_QUICK
869 && size != I2C_SMBUS_I2C_BLOCK_DATA;
872 case I2C_SMBUS_QUICK:
873 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
878 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
880 if (read_write == I2C_SMBUS_WRITE)
881 outb_p(command, SMBHSTCMD(priv));
884 case I2C_SMBUS_BYTE_DATA:
885 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
887 outb_p(command, SMBHSTCMD(priv));
888 if (read_write == I2C_SMBUS_WRITE)
889 outb_p(data->byte, SMBHSTDAT0(priv));
890 xact = I801_BYTE_DATA;
892 case I2C_SMBUS_WORD_DATA:
893 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
895 outb_p(command, SMBHSTCMD(priv));
896 if (read_write == I2C_SMBUS_WRITE) {
897 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
898 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
900 xact = I801_WORD_DATA;
902 case I2C_SMBUS_BLOCK_DATA:
903 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
905 outb_p(command, SMBHSTCMD(priv));
908 case I2C_SMBUS_I2C_BLOCK_DATA:
910 * NB: page 240 of ICH5 datasheet shows that the R/#W
911 * bit should be cleared here, even when reading.
912 * However if SPD Write Disable is set (Lynx Point and later),
913 * the read will fail if we don't set the R/#W bit.
915 outb_p(((addr & 0x7f) << 1) |
916 ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ?
917 (read_write & 0x01) : 0),
919 if (read_write == I2C_SMBUS_READ) {
920 /* NB: page 240 of ICH5 datasheet also shows
921 * that DATA1 is the cmd field when reading */
922 outb_p(command, SMBHSTDAT1(priv));
924 outb_p(command, SMBHSTCMD(priv));
927 case I2C_SMBUS_BLOCK_PROC_CALL:
929 * Bit 0 of the slave address register always indicate a write
932 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
933 outb_p(command, SMBHSTCMD(priv));
937 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
943 if (hwpec) /* enable/disable hardware PEC */
944 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
946 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
950 ret = i801_block_transaction(priv, data, read_write, size,
953 ret = i801_transaction(priv, xact);
955 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
956 time, so we forcibly disable it after every transaction. Turn off
957 E32B for the same reason. */
959 outb_p(inb_p(SMBAUXCTL(priv)) &
960 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
966 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
969 switch (xact & 0x7f) {
970 case I801_BYTE: /* Result put in SMBHSTDAT0 */
972 data->byte = inb_p(SMBHSTDAT0(priv));
975 data->word = inb_p(SMBHSTDAT0(priv)) +
976 (inb_p(SMBHSTDAT1(priv)) << 8);
981 pm_runtime_mark_last_busy(&priv->pci_dev->dev);
982 pm_runtime_put_autosuspend(&priv->pci_dev->dev);
983 mutex_unlock(&priv->acpi_lock);
988 static u32 i801_func(struct i2c_adapter *adapter)
990 struct i801_priv *priv = i2c_get_adapdata(adapter);
992 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
993 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
994 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
995 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
996 ((priv->features & FEATURE_BLOCK_PROC) ?
997 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) |
998 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
999 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
1000 ((priv->features & FEATURE_HOST_NOTIFY) ?
1001 I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
1004 static void i801_enable_host_notify(struct i2c_adapter *adapter)
1006 struct i801_priv *priv = i2c_get_adapdata(adapter);
1008 if (!(priv->features & FEATURE_HOST_NOTIFY))
1011 if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd))
1012 outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd,
1015 /* clear Host Notify bit to allow a new notification */
1016 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
1019 static void i801_disable_host_notify(struct i801_priv *priv)
1021 if (!(priv->features & FEATURE_HOST_NOTIFY))
1024 outb_p(priv->original_slvcmd, SMBSLVCMD(priv));
1027 static const struct i2c_algorithm smbus_algorithm = {
1028 .smbus_xfer = i801_access,
1029 .functionality = i801_func,
1032 static const struct pci_device_id i801_ids[] = {
1033 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
1034 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
1035 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
1036 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
1037 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
1038 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
1039 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
1040 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
1041 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
1042 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
1043 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
1044 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
1045 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
1046 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
1047 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
1048 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
1049 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
1050 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
1051 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
1052 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
1053 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
1054 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
1055 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
1056 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
1057 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
1058 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
1059 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
1060 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
1061 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
1062 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
1063 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
1064 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) },
1065 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
1066 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
1067 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
1068 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
1069 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
1070 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
1071 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMBUS) },
1072 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
1073 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EBG_SMBUS) },
1074 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
1075 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) },
1076 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) },
1077 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) },
1078 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS) },
1079 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS) },
1080 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS) },
1081 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS) },
1082 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS) },
1083 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS) },
1084 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS) },
1085 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS) },
1086 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS) },
1087 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS) },
1088 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS) },
1089 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS) },
1093 MODULE_DEVICE_TABLE(pci, i801_ids);
1095 #if defined CONFIG_X86 && defined CONFIG_DMI
1096 static unsigned char apanel_addr;
1098 /* Scan the system ROM for the signature "FJKEYINF" */
1099 static __init const void __iomem *bios_signature(const void __iomem *bios)
1102 const unsigned char signature[] = "FJKEYINF";
1104 for (offset = 0; offset < 0x10000; offset += 0x10) {
1105 if (check_signature(bios + offset, signature,
1106 sizeof(signature)-1))
1107 return bios + offset;
1112 static void __init input_apanel_init(void)
1115 const void __iomem *p;
1117 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1118 p = bios_signature(bios);
1120 /* just use the first address */
1121 apanel_addr = readb(p + 8 + 3) >> 1;
1126 struct dmi_onboard_device_info {
1129 unsigned short i2c_addr;
1130 const char *i2c_type;
1133 static const struct dmi_onboard_device_info dmi_devices[] = {
1134 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1135 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1136 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1139 static void dmi_check_onboard_device(u8 type, const char *name,
1140 struct i2c_adapter *adap)
1143 struct i2c_board_info info;
1145 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1146 /* & ~0x80, ignore enabled/disabled bit */
1147 if ((type & ~0x80) != dmi_devices[i].type)
1149 if (strcasecmp(name, dmi_devices[i].name))
1152 memset(&info, 0, sizeof(struct i2c_board_info));
1153 info.addr = dmi_devices[i].i2c_addr;
1154 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1155 i2c_new_client_device(adap, &info);
1160 /* We use our own function to check for onboard devices instead of
1161 dmi_find_device() as some buggy BIOS's have the devices we are interested
1162 in marked as disabled */
1163 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1170 count = (dm->length - sizeof(struct dmi_header)) / 2;
1171 for (i = 0; i < count; i++) {
1172 const u8 *d = (char *)(dm + 1) + (i * 2);
1173 const char *name = ((char *) dm) + dm->length;
1180 while (s > 0 && name[0]) {
1181 name += strlen(name) + 1;
1184 if (name[0] == 0) /* Bogus string reference */
1187 dmi_check_onboard_device(type, name, adap);
1191 /* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */
1192 static const char *const acpi_smo8800_ids[] = {
1203 static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle,
1206 void **return_value)
1208 struct acpi_device_info *info;
1213 status = acpi_get_object_info(obj_handle, &info);
1214 if (ACPI_FAILURE(status))
1217 if (!(info->valid & ACPI_VALID_HID))
1218 goto smo88xx_not_found;
1220 hid = info->hardware_id.string;
1222 goto smo88xx_not_found;
1224 i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid);
1226 goto smo88xx_not_found;
1230 *((bool *)return_value) = true;
1231 return AE_CTRL_TERMINATE;
1238 static bool is_dell_system_with_lis3lv02d(void)
1243 vendor = dmi_get_system_info(DMI_SYS_VENDOR);
1244 if (!vendor || strcmp(vendor, "Dell Inc."))
1248 * Check that ACPI device SMO88xx is present and is functioning.
1249 * Function acpi_get_devices() already filters all ACPI devices
1250 * which are not present or are not functioning.
1251 * ACPI device SMO88xx represents our ST microelectronics lis3lv02d
1252 * accelerometer but unfortunately ACPI does not provide any other
1253 * information (like I2C address).
1256 acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL,
1263 * Accelerometer's I2C address is not specified in DMI nor ACPI,
1264 * so it is needed to define mapping table based on DMI product names.
1266 static const struct {
1267 const char *dmi_product_name;
1268 unsigned short i2c_addr;
1269 } dell_lis3lv02d_devices[] = {
1271 * Dell platform team told us that these Latitude devices have
1272 * ST microelectronics accelerometer at I2C address 0x29.
1274 { "Latitude E5250", 0x29 },
1275 { "Latitude E5450", 0x29 },
1276 { "Latitude E5550", 0x29 },
1277 { "Latitude E6440", 0x29 },
1278 { "Latitude E6440 ATG", 0x29 },
1279 { "Latitude E6540", 0x29 },
1281 * Additional individual entries were added after verification.
1283 { "Latitude 5480", 0x29 },
1284 { "Vostro V131", 0x1d },
1287 static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv)
1289 struct i2c_board_info info;
1290 const char *dmi_product_name;
1293 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
1294 for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) {
1295 if (strcmp(dmi_product_name,
1296 dell_lis3lv02d_devices[i].dmi_product_name) == 0)
1300 if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) {
1301 dev_warn(&priv->pci_dev->dev,
1302 "Accelerometer lis3lv02d is present on SMBus but its"
1303 " address is unknown, skipping registration\n");
1307 memset(&info, 0, sizeof(struct i2c_board_info));
1308 info.addr = dell_lis3lv02d_devices[i].i2c_addr;
1309 strlcpy(info.type, "lis3lv02d", I2C_NAME_SIZE);
1310 i2c_new_client_device(&priv->adapter, &info);
1313 /* Register optional slaves */
1314 static void i801_probe_optional_slaves(struct i801_priv *priv)
1316 /* Only register slaves on main SMBus channel */
1317 if (priv->features & FEATURE_IDF)
1321 struct i2c_board_info info;
1323 memset(&info, 0, sizeof(struct i2c_board_info));
1324 info.addr = apanel_addr;
1325 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
1326 i2c_new_client_device(&priv->adapter, &info);
1329 if (dmi_name_in_vendors("FUJITSU"))
1330 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1332 if (is_dell_system_with_lis3lv02d())
1333 register_dell_lis3lv02d_i2c_device(priv);
1335 /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */
1336 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO)
1337 if (!priv->mux_drvdata)
1339 i2c_register_spd(&priv->adapter);
1342 static void __init input_apanel_init(void) {}
1343 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1344 #endif /* CONFIG_X86 && CONFIG_DMI */
1346 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
1347 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1348 .gpio_chip = "gpio_ich",
1349 .values = { 0x02, 0x03 },
1351 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1352 .gpios = { 52, 53 },
1356 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1357 .gpio_chip = "gpio_ich",
1358 .values = { 0x02, 0x03, 0x01 },
1360 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1361 .gpios = { 52, 53 },
1365 static const struct dmi_system_id mux_dmi_table[] = {
1368 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1369 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1371 .driver_data = &i801_mux_config_asus_z8_d12,
1375 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1376 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1378 .driver_data = &i801_mux_config_asus_z8_d12,
1382 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1383 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1385 .driver_data = &i801_mux_config_asus_z8_d12,
1389 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1390 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1392 .driver_data = &i801_mux_config_asus_z8_d12,
1396 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1397 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1399 .driver_data = &i801_mux_config_asus_z8_d12,
1403 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1404 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1406 .driver_data = &i801_mux_config_asus_z8_d12,
1410 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1411 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1413 .driver_data = &i801_mux_config_asus_z8_d18,
1417 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1418 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1420 .driver_data = &i801_mux_config_asus_z8_d18,
1424 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1425 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1427 .driver_data = &i801_mux_config_asus_z8_d12,
1432 /* Setup multiplexing if needed */
1433 static int i801_add_mux(struct i801_priv *priv)
1435 struct device *dev = &priv->adapter.dev;
1436 const struct i801_mux_config *mux_config;
1437 struct i2c_mux_gpio_platform_data gpio_data;
1438 struct gpiod_lookup_table *lookup;
1441 if (!priv->mux_drvdata)
1443 mux_config = priv->mux_drvdata;
1445 /* Prepare the platform data */
1446 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1447 gpio_data.parent = priv->adapter.nr;
1448 gpio_data.values = mux_config->values;
1449 gpio_data.n_values = mux_config->n_values;
1450 gpio_data.classes = mux_config->classes;
1451 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1453 /* Register GPIO descriptor lookup table */
1454 lookup = devm_kzalloc(dev,
1455 struct_size(lookup, table, mux_config->n_gpios + 1),
1459 lookup->dev_id = "i2c-mux-gpio";
1460 for (i = 0; i < mux_config->n_gpios; i++) {
1461 lookup->table[i] = (struct gpiod_lookup)
1462 GPIO_LOOKUP(mux_config->gpio_chip,
1463 mux_config->gpios[i], "mux", 0);
1465 gpiod_add_lookup_table(lookup);
1466 priv->lookup = lookup;
1469 * Register the mux device, we use PLATFORM_DEVID_NONE here
1470 * because since we are referring to the GPIO chip by name we are
1471 * anyways in deep trouble if there is more than one of these
1472 * devices, and there should likely only be one platform controller
1475 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1476 PLATFORM_DEVID_NONE, &gpio_data,
1477 sizeof(struct i2c_mux_gpio_platform_data));
1478 if (IS_ERR(priv->mux_pdev)) {
1479 gpiod_remove_lookup_table(lookup);
1480 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1483 return PTR_ERR_OR_ZERO(priv->mux_pdev);
1486 static void i801_del_mux(struct i801_priv *priv)
1488 platform_device_unregister(priv->mux_pdev);
1489 gpiod_remove_lookup_table(priv->lookup);
1492 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1494 const struct dmi_system_id *id;
1495 const struct i801_mux_config *mux_config;
1496 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1499 id = dmi_first_match(mux_dmi_table);
1501 /* Remove branch classes from trunk */
1502 mux_config = id->driver_data;
1503 for (i = 0; i < mux_config->n_values; i++)
1504 class &= ~mux_config->classes[i];
1506 /* Remember for later */
1507 priv->mux_drvdata = mux_config;
1513 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1514 static inline void i801_del_mux(struct i801_priv *priv) { }
1516 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1518 return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1522 static const struct itco_wdt_platform_data spt_tco_platform_data = {
1523 .name = "Intel PCH",
1527 static DEFINE_SPINLOCK(p2sb_spinlock);
1529 static struct platform_device *
1530 i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev,
1531 struct resource *tco_res)
1533 struct resource *res;
1540 * We must access the NO_REBOOT bit over the Primary to Sideband
1541 * bridge (P2SB). The BIOS prevents the P2SB device from being
1542 * enumerated by the PCI subsystem, so we need to unhide/hide it
1543 * to lookup the P2SB BAR.
1545 spin_lock(&p2sb_spinlock);
1547 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1549 /* Unhide the P2SB device, if it is hidden */
1550 pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden);
1552 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1554 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1555 base64_addr = base_addr & 0xfffffff0;
1557 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1558 base64_addr |= (u64)base_addr << 32;
1560 /* Hide the P2SB device, if it was hidden before */
1562 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden);
1563 spin_unlock(&p2sb_spinlock);
1566 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1567 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV;
1569 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1571 res->end = res->start + 3;
1572 res->flags = IORESOURCE_MEM;
1574 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1575 tco_res, 2, &spt_tco_platform_data,
1576 sizeof(spt_tco_platform_data));
1579 static const struct itco_wdt_platform_data cnl_tco_platform_data = {
1580 .name = "Intel PCH",
1584 static struct platform_device *
1585 i801_add_tco_cnl(struct i801_priv *priv, struct pci_dev *pci_dev,
1586 struct resource *tco_res)
1588 return platform_device_register_resndata(&pci_dev->dev,
1589 "iTCO_wdt", -1, tco_res, 1, &cnl_tco_platform_data,
1590 sizeof(cnl_tco_platform_data));
1593 static void i801_add_tco(struct i801_priv *priv)
1595 struct pci_dev *pci_dev = priv->pci_dev;
1596 struct resource tco_res[2], *res;
1597 u32 tco_base, tco_ctl;
1599 /* If we have ACPI based watchdog use that instead */
1600 if (acpi_has_watchdog())
1603 if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL)))
1606 pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1607 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1608 if (!(tco_ctl & TCOCTL_EN))
1611 memset(tco_res, 0, sizeof(tco_res));
1613 * Always populate the main iTCO IO resource here. The second entry
1614 * for NO_REBOOT MMIO is filled by the SPT specific function.
1617 res->start = tco_base & ~1;
1618 res->end = res->start + 32 - 1;
1619 res->flags = IORESOURCE_IO;
1621 if (priv->features & FEATURE_TCO_CNL)
1622 priv->tco_pdev = i801_add_tco_cnl(priv, pci_dev, tco_res);
1624 priv->tco_pdev = i801_add_tco_spt(priv, pci_dev, tco_res);
1626 if (IS_ERR(priv->tco_pdev))
1627 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1631 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv,
1632 acpi_physical_address address)
1634 return address >= priv->smba &&
1635 address <= pci_resource_end(priv->pci_dev, SMBBAR);
1639 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1640 u64 *value, void *handler_context, void *region_context)
1642 struct i801_priv *priv = handler_context;
1643 struct pci_dev *pdev = priv->pci_dev;
1647 * Once BIOS AML code touches the OpRegion we warn and inhibit any
1648 * further access from the driver itself. This device is now owned
1649 * by the system firmware.
1651 mutex_lock(&priv->acpi_lock);
1653 if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) {
1654 priv->acpi_reserved = true;
1656 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1657 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1660 * BIOS is accessing the host controller so prevent it from
1661 * suspending automatically from now on.
1663 pm_runtime_get_sync(&pdev->dev);
1666 if ((function & ACPI_IO_MASK) == ACPI_READ)
1667 status = acpi_os_read_port(address, (u32 *)value, bits);
1669 status = acpi_os_write_port(address, (u32)*value, bits);
1671 mutex_unlock(&priv->acpi_lock);
1676 static int i801_acpi_probe(struct i801_priv *priv)
1678 struct acpi_device *adev;
1681 adev = ACPI_COMPANION(&priv->pci_dev->dev);
1683 status = acpi_install_address_space_handler(adev->handle,
1684 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler,
1686 if (ACPI_SUCCESS(status))
1690 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1693 static void i801_acpi_remove(struct i801_priv *priv)
1695 struct acpi_device *adev;
1697 adev = ACPI_COMPANION(&priv->pci_dev->dev);
1701 acpi_remove_address_space_handler(adev->handle,
1702 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1704 mutex_lock(&priv->acpi_lock);
1705 if (priv->acpi_reserved)
1706 pm_runtime_put(&priv->pci_dev->dev);
1707 mutex_unlock(&priv->acpi_lock);
1710 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
1711 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1714 static unsigned char i801_setup_hstcfg(struct i801_priv *priv)
1716 unsigned char hstcfg = priv->original_hstcfg;
1718 hstcfg &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
1719 hstcfg |= SMBHSTCFG_HST_EN;
1720 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg);
1724 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1728 struct i801_priv *priv;
1730 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1734 i2c_set_adapdata(&priv->adapter, priv);
1735 priv->adapter.owner = THIS_MODULE;
1736 priv->adapter.class = i801_get_adapter_class(priv);
1737 priv->adapter.algo = &smbus_algorithm;
1738 priv->adapter.dev.parent = &dev->dev;
1739 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1740 priv->adapter.retries = 3;
1741 mutex_init(&priv->acpi_lock);
1743 priv->pci_dev = dev;
1744 switch (dev->device) {
1745 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
1746 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
1747 case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS:
1748 case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS:
1749 case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
1750 case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS:
1751 case PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS:
1752 priv->features |= FEATURE_BLOCK_PROC;
1753 priv->features |= FEATURE_I2C_BLOCK_READ;
1754 priv->features |= FEATURE_IRQ;
1755 priv->features |= FEATURE_SMBUS_PEC;
1756 priv->features |= FEATURE_BLOCK_BUFFER;
1757 priv->features |= FEATURE_TCO_SPT;
1758 priv->features |= FEATURE_HOST_NOTIFY;
1761 case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS:
1762 case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS:
1763 case PCI_DEVICE_ID_INTEL_CDF_SMBUS:
1764 case PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS:
1765 case PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS:
1766 case PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS:
1767 case PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS:
1768 case PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS:
1769 case PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS:
1770 case PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS:
1771 case PCI_DEVICE_ID_INTEL_EBG_SMBUS:
1772 case PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS:
1773 case PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS:
1774 priv->features |= FEATURE_BLOCK_PROC;
1775 priv->features |= FEATURE_I2C_BLOCK_READ;
1776 priv->features |= FEATURE_IRQ;
1777 priv->features |= FEATURE_SMBUS_PEC;
1778 priv->features |= FEATURE_BLOCK_BUFFER;
1779 priv->features |= FEATURE_TCO_CNL;
1780 priv->features |= FEATURE_HOST_NOTIFY;
1783 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1784 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1785 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1786 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1787 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1788 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1789 priv->features |= FEATURE_IDF;
1792 priv->features |= FEATURE_BLOCK_PROC;
1793 priv->features |= FEATURE_I2C_BLOCK_READ;
1794 priv->features |= FEATURE_IRQ;
1796 case PCI_DEVICE_ID_INTEL_82801DB_3:
1797 priv->features |= FEATURE_SMBUS_PEC;
1798 priv->features |= FEATURE_BLOCK_BUFFER;
1800 case PCI_DEVICE_ID_INTEL_82801CA_3:
1801 priv->features |= FEATURE_HOST_NOTIFY;
1803 case PCI_DEVICE_ID_INTEL_82801BA_2:
1804 case PCI_DEVICE_ID_INTEL_82801AB_3:
1805 case PCI_DEVICE_ID_INTEL_82801AA_3:
1809 /* Disable features on user request */
1810 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1811 if (priv->features & disable_features & (1 << i))
1812 dev_notice(&dev->dev, "%s disabled by user\n",
1813 i801_feature_names[i]);
1815 priv->features &= ~disable_features;
1817 err = pcim_enable_device(dev);
1819 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1823 pcim_pin_device(dev);
1825 /* Determine the address of the SMBus area */
1826 priv->smba = pci_resource_start(dev, SMBBAR);
1829 "SMBus base address uninitialized, upgrade BIOS\n");
1833 if (i801_acpi_probe(priv))
1836 err = pcim_iomap_regions(dev, 1 << SMBBAR,
1837 dev_driver_string(&dev->dev));
1840 "Failed to request SMBus region 0x%lx-0x%Lx\n",
1842 (unsigned long long)pci_resource_end(dev, SMBBAR));
1843 i801_acpi_remove(priv);
1847 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &priv->original_hstcfg);
1848 temp = i801_setup_hstcfg(priv);
1849 if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN))
1850 dev_info(&dev->dev, "Enabling SMBus device\n");
1852 if (temp & SMBHSTCFG_SMB_SMI_EN) {
1853 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1854 /* Disable SMBus interrupt feature if SMBus using SMI# */
1855 priv->features &= ~FEATURE_IRQ;
1857 if (temp & SMBHSTCFG_SPD_WD)
1858 dev_info(&dev->dev, "SPD Write Disable is set\n");
1860 /* Clear special mode bits */
1861 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1862 outb_p(inb_p(SMBAUXCTL(priv)) &
1863 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1865 /* Remember original Host Notify setting */
1866 if (priv->features & FEATURE_HOST_NOTIFY)
1867 priv->original_slvcmd = inb_p(SMBSLVCMD(priv));
1869 /* Default timeout in interrupt mode: 200 ms */
1870 priv->adapter.timeout = HZ / 5;
1872 if (dev->irq == IRQ_NOTCONNECTED)
1873 priv->features &= ~FEATURE_IRQ;
1875 if (priv->features & FEATURE_IRQ) {
1878 /* Complain if an interrupt is already pending */
1879 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
1880 if (pcists & SMBPCISTS_INTS)
1881 dev_warn(&dev->dev, "An interrupt is pending!\n");
1883 /* Check if interrupts have been disabled */
1884 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
1885 if (pcictl & SMBPCICTL_INTDIS) {
1886 dev_info(&dev->dev, "Interrupts are disabled\n");
1887 priv->features &= ~FEATURE_IRQ;
1891 if (priv->features & FEATURE_IRQ) {
1892 init_waitqueue_head(&priv->waitq);
1894 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1896 dev_driver_string(&dev->dev), priv);
1898 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1900 priv->features &= ~FEATURE_IRQ;
1903 dev_info(&dev->dev, "SMBus using %s\n",
1904 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1908 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1909 "SMBus I801 adapter at %04lx", priv->smba);
1910 err = i2c_add_adapter(&priv->adapter);
1912 i801_acpi_remove(priv);
1916 i801_enable_host_notify(&priv->adapter);
1918 i801_probe_optional_slaves(priv);
1919 /* We ignore errors - multiplexing is optional */
1922 pci_set_drvdata(dev, priv);
1924 dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
1925 pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1926 pm_runtime_use_autosuspend(&dev->dev);
1927 pm_runtime_put_autosuspend(&dev->dev);
1928 pm_runtime_allow(&dev->dev);
1933 static void i801_remove(struct pci_dev *dev)
1935 struct i801_priv *priv = pci_get_drvdata(dev);
1937 pm_runtime_forbid(&dev->dev);
1938 pm_runtime_get_noresume(&dev->dev);
1940 i801_disable_host_notify(priv);
1942 i2c_del_adapter(&priv->adapter);
1943 i801_acpi_remove(priv);
1944 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1946 platform_device_unregister(priv->tco_pdev);
1949 * do not call pci_disable_device(dev) since it can cause hard hangs on
1950 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1954 static void i801_shutdown(struct pci_dev *dev)
1956 struct i801_priv *priv = pci_get_drvdata(dev);
1958 /* Restore config registers to avoid hard hang on some systems */
1959 i801_disable_host_notify(priv);
1960 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1963 #ifdef CONFIG_PM_SLEEP
1964 static int i801_suspend(struct device *dev)
1966 struct i801_priv *priv = dev_get_drvdata(dev);
1968 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, priv->original_hstcfg);
1972 static int i801_resume(struct device *dev)
1974 struct i801_priv *priv = dev_get_drvdata(dev);
1976 i801_setup_hstcfg(priv);
1977 i801_enable_host_notify(&priv->adapter);
1983 static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume);
1985 static struct pci_driver i801_driver = {
1986 .name = "i801_smbus",
1987 .id_table = i801_ids,
1988 .probe = i801_probe,
1989 .remove = i801_remove,
1990 .shutdown = i801_shutdown,
1996 static int __init i2c_i801_init(void)
1998 if (dmi_name_in_vendors("FUJITSU"))
1999 input_apanel_init();
2000 return pci_register_driver(&i801_driver);
2003 static void __exit i2c_i801_exit(void)
2005 pci_unregister_driver(&i801_driver);
2008 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>");
2009 MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>");
2010 MODULE_DESCRIPTION("I801 SMBus driver");
2011 MODULE_LICENSE("GPL");
2013 module_init(i2c_i801_init);
2014 module_exit(i2c_i801_exit);