drivers/i2c/busses/i2c-i801.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   4     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   5     <mdsxyz123@yahoo.com>
   6     Copyright (C) 2007 - 2014  Jean Delvare <jdelvare@suse.de>
   7     Copyright (C) 2010         Intel Corporation,
   8                                David Woodhouse <dwmw2@infradead.org>
   9
  10 */
  11
  12 /*
  13  * Supports the following Intel I/O Controller Hubs (ICH):
  14  *
  15  *                                      I/O                     Block   I2C
  16  *                                      region  SMBus   Block   proc.   block
  17  * Chip name                    PCI ID  size    PEC     buffer  call    read
  18  * ---------------------------------------------------------------------------
  19  * 82801AA (ICH)                0x2413  16      no      no      no      no
  20  * 82801AB (ICH0)               0x2423  16      no      no      no      no
  21  * 82801BA (ICH2)               0x2443  16      no      no      no      no
  22  * 82801CA (ICH3)               0x2483  32      soft    no      no      no
  23  * 82801DB (ICH4)               0x24c3  32      hard    yes     no      no
  24  * 82801E (ICH5)                0x24d3  32      hard    yes     yes     yes
  25  * 6300ESB                      0x25a4  32      hard    yes     yes     yes
  26  * 82801F (ICH6)                0x266a  32      hard    yes     yes     yes
  27  * 6310ESB/6320ESB              0x269b  32      hard    yes     yes     yes
  28  * 82801G (ICH7)                0x27da  32      hard    yes     yes     yes
  29  * 82801H (ICH8)                0x283e  32      hard    yes     yes     yes
  30  * 82801I (ICH9)                0x2930  32      hard    yes     yes     yes
  31  * EP80579 (Tolapai)            0x5032  32      hard    yes     yes     yes
  32  * ICH10                        0x3a30  32      hard    yes     yes     yes
  33  * ICH10                        0x3a60  32      hard    yes     yes     yes
  34  * 5/3400 Series (PCH)          0x3b30  32      hard    yes     yes     yes
  35  * 6 Series (PCH)               0x1c22  32      hard    yes     yes     yes
  36  * Patsburg (PCH)               0x1d22  32      hard    yes     yes     yes
  37  * Patsburg (PCH) IDF           0x1d70  32      hard    yes     yes     yes
  38  * Patsburg (PCH) IDF           0x1d71  32      hard    yes     yes     yes
  39  * Patsburg (PCH) IDF           0x1d72  32      hard    yes     yes     yes
  40  * DH89xxCC (PCH)               0x2330  32      hard    yes     yes     yes
  41  * Panther Point (PCH)          0x1e22  32      hard    yes     yes     yes
  42  * Lynx Point (PCH)             0x8c22  32      hard    yes     yes     yes
  43  * Lynx Point-LP (PCH)          0x9c22  32      hard    yes     yes     yes
  44  * Avoton (SOC)                 0x1f3c  32      hard    yes     yes     yes
  45  * Wellsburg (PCH)              0x8d22  32      hard    yes     yes     yes
  46  * Wellsburg (PCH) MS           0x8d7d  32      hard    yes     yes     yes
  47  * Wellsburg (PCH) MS           0x8d7e  32      hard    yes     yes     yes
  48  * Wellsburg (PCH) MS           0x8d7f  32      hard    yes     yes     yes
  49  * Coleto Creek (PCH)           0x23b0  32      hard    yes     yes     yes
  50  * Wildcat Point (PCH)          0x8ca2  32      hard    yes     yes     yes
  51  * Wildcat Point-LP (PCH)       0x9ca2  32      hard    yes     yes     yes
  52  * BayTrail (SOC)               0x0f12  32      hard    yes     yes     yes
  53  * Braswell (SOC)               0x2292  32      hard    yes     yes     yes
  54  * Sunrise Point-H (PCH)        0xa123  32      hard    yes     yes     yes
  55  * Sunrise Point-LP (PCH)       0x9d23  32      hard    yes     yes     yes
  56  * DNV (SOC)                    0x19df  32      hard    yes     yes     yes
  57  * Emmitsburg (PCH)             0x1bc9  32      hard    yes     yes     yes
  58  * Broxton (SOC)                0x5ad4  32      hard    yes     yes     yes
  59  * Lewisburg (PCH)              0xa1a3  32      hard    yes     yes     yes
  60  * Lewisburg Supersku (PCH)     0xa223  32      hard    yes     yes     yes
  61  * Kaby Lake PCH-H (PCH)        0xa2a3  32      hard    yes     yes     yes
  62  * Gemini Lake (SOC)            0x31d4  32      hard    yes     yes     yes
  63  * Cannon Lake-H (PCH)          0xa323  32      hard    yes     yes     yes
  64  * Cannon Lake-LP (PCH)         0x9da3  32      hard    yes     yes     yes
  65  * Cedar Fork (PCH)             0x18df  32      hard    yes     yes     yes
  66  * Ice Lake-LP (PCH)            0x34a3  32      hard    yes     yes     yes
  67  * Comet Lake (PCH)             0x02a3  32      hard    yes     yes     yes
  68  * Comet Lake-H (PCH)           0x06a3  32      hard    yes     yes     yes
  69  * Elkhart Lake (PCH)           0x4b23  32      hard    yes     yes     yes
  70  * Tiger Lake-LP (PCH)          0xa0a3  32      hard    yes     yes     yes
  71  * Tiger Lake-H (PCH)           0x43a3  32      hard    yes     yes     yes
  72  * Jasper Lake (SOC)            0x4da3  32      hard    yes     yes     yes
  73  * Comet Lake-V (PCH)           0xa3a3  32      hard    yes     yes     yes
  74  * Alder Lake-S (PCH)           0x7aa3  32      hard    yes     yes     yes
  75  *
  76  * Features supported by this driver:
  77  * Software PEC                         no
  78  * Hardware PEC                         yes
  79  * Block buffer                         yes
  80  * Block process call transaction       yes
  81  * I2C block read transaction           yes (doesn't use the block buffer)
  82  * Slave mode                           no
  83  * SMBus Host Notify                    yes
  84  * Interrupt processing                 yes
  85  *
  86  * See the file Documentation/i2c/busses/i2c-i801.rst for details.
  87  */
  88
  89 #include <linux/interrupt.h>
  90 #include <linux/module.h>
  91 #include <linux/pci.h>
  92 #include <linux/kernel.h>
  93 #include <linux/stddef.h>
  94 #include <linux/delay.h>
  95 #include <linux/ioport.h>
  96 #include <linux/init.h>
  97 #include <linux/i2c.h>
  98 #include <linux/i2c-smbus.h>
  99 #include <linux/acpi.h>
 100 #include <linux/io.h>
 101 #include <linux/dmi.h>
 102 #include <linux/slab.h>
 103 #include <linux/string.h>
 104 #include <linux/wait.h>
 105 #include <linux/err.h>
 106 #include <linux/platform_device.h>
 107 #include <linux/platform_data/itco_wdt.h>
 108 #include <linux/pm_runtime.h>
 109
 110 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
 111 #include <linux/gpio/machine.h>
 112 #include <linux/platform_data/i2c-mux-gpio.h>
 113 #endif
 114
 115 /* I801 SMBus address offsets */
 116 #define SMBHSTSTS(p)    (0 + (p)->smba)
 117 #define SMBHSTCNT(p)    (2 + (p)->smba)
 118 #define SMBHSTCMD(p)    (3 + (p)->smba)
 119 #define SMBHSTADD(p)    (4 + (p)->smba)
 120 #define SMBHSTDAT0(p)   (5 + (p)->smba)
 121 #define SMBHSTDAT1(p)   (6 + (p)->smba)
 122 #define SMBBLKDAT(p)    (7 + (p)->smba)
 123 #define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
 124 #define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
 125 #define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
 126 #define SMBSLVSTS(p)    (16 + (p)->smba)        /* ICH3 and later */
 127 #define SMBSLVCMD(p)    (17 + (p)->smba)        /* ICH3 and later */
 128 #define SMBNTFDADD(p)   (20 + (p)->smba)        /* ICH3 and later */
 129
 130 /* PCI Address Constants */
 131 #define SMBBAR          4
 132 #define SMBPCICTL       0x004
 133 #define SMBPCISTS       0x006
 134 #define SMBHSTCFG       0x040
 135 #define TCOBASE         0x050
 136 #define TCOCTL          0x054
 137
 138 #define SBREG_BAR               0x10
 139 #define SBREG_SMBCTRL           0xc6000c
 140 #define SBREG_SMBCTRL_DNV       0xcf000c
 141
 142 /* Host status bits for SMBPCISTS */
 143 #define SMBPCISTS_INTS          BIT(3)
 144
 145 /* Control bits for SMBPCICTL */
 146 #define SMBPCICTL_INTDIS        BIT(10)
 147
 148 /* Host configuration bits for SMBHSTCFG */
 149 #define SMBHSTCFG_HST_EN        BIT(0)
 150 #define SMBHSTCFG_SMB_SMI_EN    BIT(1)
 151 #define SMBHSTCFG_I2C_EN        BIT(2)
 152 #define SMBHSTCFG_SPD_WD        BIT(4)
 153
 154 /* TCO configuration bits for TCOCTL */
 155 #define TCOCTL_EN               BIT(8)
 156
 157 /* Auxiliary status register bits, ICH4+ only */
 158 #define SMBAUXSTS_CRCE          BIT(0)
 159 #define SMBAUXSTS_STCO          BIT(1)
 160
 161 /* Auxiliary control register bits, ICH4+ only */
 162 #define SMBAUXCTL_CRC           BIT(0)
 163 #define SMBAUXCTL_E32B          BIT(1)
 164
 165 /* Other settings */
 166 #define MAX_RETRIES             400
 167
 168 /* I801 command constants */
 169 #define I801_QUICK              0x00
 170 #define I801_BYTE               0x04
 171 #define I801_BYTE_DATA          0x08
 172 #define I801_WORD_DATA          0x0C
 173 #define I801_PROC_CALL          0x10    /* unimplemented */
 174 #define I801_BLOCK_DATA         0x14
 175 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 176 #define I801_BLOCK_PROC_CALL    0x1C
 177
 178 /* I801 Host Control register bits */
 179 #define SMBHSTCNT_INTREN        BIT(0)
 180 #define SMBHSTCNT_KILL          BIT(1)
 181 #define SMBHSTCNT_LAST_BYTE     BIT(5)
 182 #define SMBHSTCNT_START         BIT(6)
 183 #define SMBHSTCNT_PEC_EN        BIT(7)  /* ICH3 and later */
 184
 185 /* I801 Hosts Status register bits */
 186 #define SMBHSTSTS_BYTE_DONE     BIT(7)
 187 #define SMBHSTSTS_INUSE_STS     BIT(6)
 188 #define SMBHSTSTS_SMBALERT_STS  BIT(5)
 189 #define SMBHSTSTS_FAILED        BIT(4)
 190 #define SMBHSTSTS_BUS_ERR       BIT(3)
 191 #define SMBHSTSTS_DEV_ERR       BIT(2)
 192 #define SMBHSTSTS_INTR          BIT(1)
 193 #define SMBHSTSTS_HOST_BUSY     BIT(0)
 194
 195 /* Host Notify Status register bits */
 196 #define SMBSLVSTS_HST_NTFY_STS  BIT(0)
 197
 198 /* Host Notify Command register bits */
 199 #define SMBSLVCMD_HST_NTFY_INTREN       BIT(0)
 200
 201 #define STATUS_ERROR_FLAGS      (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
 202                                  SMBHSTSTS_DEV_ERR)
 203
 204 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
 205                                  STATUS_ERROR_FLAGS)
 206
 207 /* Older devices have their ID defined in <linux/pci_ids.h> */
 208 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS             0x02a3
 209 #define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS           0x06a3
 210 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS              0x0f12
 211 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS                   0x18df
 212 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS                   0x19df
 213 #define PCI_DEVICE_ID_INTEL_EBG_SMBUS                   0x1bc9
 214 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS           0x1c22
 215 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS              0x1d22
 216 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
 217 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0         0x1d70
 218 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1         0x1d71
 219 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2         0x1d72
 220 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS          0x1e22
 221 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS                0x1f3c
 222 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS              0x2292
 223 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS              0x2330
 224 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS           0x23b0
 225 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS            0x31d4
 226 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS            0x34a3
 227 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS         0x3b30
 228 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS           0x43a3
 229 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS          0x4b23
 230 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS           0x4da3
 231 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS               0x5ad4
 232 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS          0x7aa3
 233 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS             0x8c22
 234 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS          0x8ca2
 235 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS             0x8d22
 236 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0         0x8d7d
 237 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1         0x8d7e
 238 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2         0x8d7f
 239 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS          0x9c22
 240 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS       0x9ca2
 241 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS       0x9d23
 242 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS         0x9da3
 243 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS          0xa0a3
 244 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS        0xa123
 245 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS             0xa1a3
 246 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS        0xa223
 247 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS        0xa2a3
 248 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS          0xa323
 249 #define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS           0xa3a3
 250
 251 struct i801_mux_config {
 252         char *gpio_chip;
 253         unsigned values[3];
 254         int n_values;
 255         unsigned classes[3];
 256         unsigned gpios[2];              /* Relative to gpio_chip->base */
 257         int n_gpios;
 258 };
 259
 260 struct i801_priv {
 261         struct i2c_adapter adapter;
 262         unsigned long smba;
 263         unsigned char original_hstcfg;
 264         unsigned char original_slvcmd;
 265         struct pci_dev *pci_dev;
 266         unsigned int features;
 267
 268         /* isr processing */
 269         wait_queue_head_t waitq;
 270         u8 status;
 271
 272         /* Command state used by isr for byte-by-byte block transactions */
 273         u8 cmd;
 274         bool is_read;
 275         int count;
 276         int len;
 277         u8 *data;
 278
 279 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
 280         const struct i801_mux_config *mux_drvdata;
 281         struct platform_device *mux_pdev;
 282         struct gpiod_lookup_table *lookup;
 283 #endif
 284         struct platform_device *tco_pdev;
 285
 286         /*
 287          * If set to true the host controller registers are reserved for
 288          * ACPI AML use. Protected by acpi_lock.
 289          */
 290         bool acpi_reserved;
 291         struct mutex acpi_lock;
 292 };
 293
 294 #define FEATURE_SMBUS_PEC       BIT(0)
 295 #define FEATURE_BLOCK_BUFFER    BIT(1)
 296 #define FEATURE_BLOCK_PROC      BIT(2)
 297 #define FEATURE_I2C_BLOCK_READ  BIT(3)
 298 #define FEATURE_IRQ             BIT(4)
 299 #define FEATURE_HOST_NOTIFY     BIT(5)
 300 /* Not really a feature, but it's convenient to handle it as such */
 301 #define FEATURE_IDF             BIT(15)
 302 #define FEATURE_TCO_SPT         BIT(16)
 303 #define FEATURE_TCO_CNL         BIT(17)
 304
 305 static const char *i801_feature_names[] = {
 306         "SMBus PEC",
 307         "Block buffer",
 308         "Block process call",
 309         "I2C block read",
 310         "Interrupt",
 311         "SMBus Host Notify",
 312 };
 313
 314 static unsigned int disable_features;
 315 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 316 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
 317         "\t\t  0x01  disable SMBus PEC\n"
 318         "\t\t  0x02  disable the block buffer\n"
 319         "\t\t  0x08  disable the I2C block read functionality\n"
 320         "\t\t  0x10  don't use interrupts\n"
 321         "\t\t  0x20  disable SMBus Host Notify ");
 322
 323 /* Make sure the SMBus host is ready to start transmitting.
 324    Return 0 if it is, -EBUSY if it is not. */
 325 static int i801_check_pre(struct i801_priv *priv)
 326 {
 327         int status;
 328
 329         status = inb_p(SMBHSTSTS(priv));
 330         if (status & SMBHSTSTS_HOST_BUSY) {
 331                 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
 332                 return -EBUSY;
 333         }
 334
 335         status &= STATUS_FLAGS;
 336         if (status) {
 337                 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
 338                         status);
 339                 outb_p(status, SMBHSTSTS(priv));
 340                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 341                 if (status) {
 342                         dev_err(&priv->pci_dev->dev,
 343                                 "Failed clearing status flags (%02x)\n",
 344                                 status);
 345                         return -EBUSY;
 346                 }
 347         }
 348
 349         /*
 350          * Clear CRC status if needed.
 351          * During normal operation, i801_check_post() takes care
 352          * of it after every operation.  We do it here only in case
 353          * the hardware was already in this state when the driver
 354          * started.
 355          */
 356         if (priv->features & FEATURE_SMBUS_PEC) {
 357                 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
 358                 if (status) {
 359                         dev_dbg(&priv->pci_dev->dev,
 360                                 "Clearing aux status flags (%02x)\n", status);
 361                         outb_p(status, SMBAUXSTS(priv));
 362                         status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
 363                         if (status) {
 364                                 dev_err(&priv->pci_dev->dev,
 365                                         "Failed clearing aux status flags (%02x)\n",
 366                                         status);
 367                                 return -EBUSY;
 368                         }
 369                 }
 370         }
 371
 372         return 0;
 373 }
 374
 375 /*
 376  * Convert the status register to an error code, and clear it.
 377  * Note that status only contains the bits we want to clear, not the
 378  * actual register value.
 379  */
 380 static int i801_check_post(struct i801_priv *priv, int status)
 381 {
 382         int result = 0;
 383
 384         /*
 385          * If the SMBus is still busy, we give up
 386          * Note: This timeout condition only happens when using polling
 387          * transactions.  For interrupt operation, NAK/timeout is indicated by
 388          * DEV_ERR.
 389          */
 390         if (unlikely(status < 0)) {
 391                 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
 392                 /* try to stop the current command */
 393                 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
 394                 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
 395                        SMBHSTCNT(priv));
 396                 usleep_range(1000, 2000);
 397                 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
 398                        SMBHSTCNT(priv));
 399
 400                 /* Check if it worked */
 401                 status = inb_p(SMBHSTSTS(priv));
 402                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 403                     !(status & SMBHSTSTS_FAILED))
 404                         dev_err(&priv->pci_dev->dev,
 405                                 "Failed terminating the transaction\n");
 406                 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
 407                 return -ETIMEDOUT;
 408         }
 409
 410         if (status & SMBHSTSTS_FAILED) {
 411                 result = -EIO;
 412                 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 413         }
 414         if (status & SMBHSTSTS_DEV_ERR) {
 415                 /*
 416                  * This may be a PEC error, check and clear it.
 417                  *
 418                  * AUXSTS is handled differently from HSTSTS.
 419                  * For HSTSTS, i801_isr() or i801_wait_intr()
 420                  * has already cleared the error bits in hardware,
 421                  * and we are passed a copy of the original value
 422                  * in "status".
 423                  * For AUXSTS, the hardware register is left
 424                  * for us to handle here.
 425                  * This is asymmetric, slightly iffy, but safe,
 426                  * since all this code is serialized and the CRCE
 427                  * bit is harmless as long as it's cleared before
 428                  * the next operation.
 429                  */
 430                 if ((priv->features & FEATURE_SMBUS_PEC) &&
 431                     (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
 432                         outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
 433                         result = -EBADMSG;
 434                         dev_dbg(&priv->pci_dev->dev, "PEC error\n");
 435                 } else {
 436                         result = -ENXIO;
 437                         dev_dbg(&priv->pci_dev->dev, "No response\n");
 438                 }
 439         }
 440         if (status & SMBHSTSTS_BUS_ERR) {
 441                 result = -EAGAIN;
 442                 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 443         }
 444
 445         /* Clear status flags except BYTE_DONE, to be cleared by caller */
 446         outb_p(status, SMBHSTSTS(priv));
 447
 448         return result;
 449 }
 450
 451 /* Wait for BUSY being cleared and either INTR or an error flag being set */
 452 static int i801_wait_intr(struct i801_priv *priv)
 453 {
 454         int timeout = 0;
 455         int status;
 456
 457         /* We will always wait for a fraction of a second! */
 458         do {
 459                 usleep_range(250, 500);
 460                 status = inb_p(SMBHSTSTS(priv));
 461         } while (((status & SMBHSTSTS_HOST_BUSY) ||
 462                   !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
 463                  (timeout++ < MAX_RETRIES));
 464
 465         if (timeout > MAX_RETRIES) {
 466                 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
 467                 return -ETIMEDOUT;
 468         }
 469         return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
 470 }
 471
 472 /* Wait for either BYTE_DONE or an error flag being set */
 473 static int i801_wait_byte_done(struct i801_priv *priv)
 474 {
 475         int timeout = 0;
 476         int status;
 477
 478         /* We will always wait for a fraction of a second! */
 479         do {
 480                 usleep_range(250, 500);
 481                 status = inb_p(SMBHSTSTS(priv));
 482         } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
 483                  (timeout++ < MAX_RETRIES));
 484
 485         if (timeout > MAX_RETRIES) {
 486                 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
 487                 return -ETIMEDOUT;
 488         }
 489         return status & STATUS_ERROR_FLAGS;
 490 }
 491
 492 static int i801_transaction(struct i801_priv *priv, int xact)
 493 {
 494         int status;
 495         int result;
 496         const struct i2c_adapter *adap = &priv->adapter;
 497
 498         result = i801_check_pre(priv);
 499         if (result < 0)
 500                 return result;
 501
 502         if (priv->features & FEATURE_IRQ) {
 503                 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
 504                        SMBHSTCNT(priv));
 505                 result = wait_event_timeout(priv->waitq,
 506                                             (status = priv->status),
 507                                             adap->timeout);
 508                 if (!result) {
 509                         status = -ETIMEDOUT;
 510                         dev_warn(&priv->pci_dev->dev,
 511                                  "Timeout waiting for interrupt!\n");
 512                 }
 513                 priv->status = 0;
 514                 return i801_check_post(priv, status);
 515         }
 516
 517         /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 518          * SMBSCMD are passed in xact */
 519         outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
 520
 521         status = i801_wait_intr(priv);
 522         return i801_check_post(priv, status);
 523 }
 524
 525 static int i801_block_transaction_by_block(struct i801_priv *priv,
 526                                            union i2c_smbus_data *data,
 527                                            char read_write, int command,
 528                                            int hwpec)
 529 {
 530         int i, len;
 531         int status;
 532         int xact = hwpec ? SMBHSTCNT_PEC_EN : 0;
 533
 534         switch (command) {
 535         case I2C_SMBUS_BLOCK_PROC_CALL:
 536                 xact |= I801_BLOCK_PROC_CALL;
 537                 break;
 538         case I2C_SMBUS_BLOCK_DATA:
 539                 xact |= I801_BLOCK_DATA;
 540                 break;
 541         default:
 542                 return -EOPNOTSUPP;
 543         }
 544
 545         inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 546
 547         /* Use 32-byte buffer to process this transaction */
 548         if (read_write == I2C_SMBUS_WRITE) {
 549                 len = data->block[0];
 550                 outb_p(len, SMBHSTDAT0(priv));
 551                 for (i = 0; i < len; i++)
 552                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 553         }
 554
 555         status = i801_transaction(priv, xact);
 556         if (status)
 557                 return status;
 558
 559         if (read_write == I2C_SMBUS_READ ||
 560             command == I2C_SMBUS_BLOCK_PROC_CALL) {
 561                 len = inb_p(SMBHSTDAT0(priv));
 562                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 563                         return -EPROTO;
 564
 565                 data->block[0] = len;
 566                 for (i = 0; i < len; i++)
 567                         data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 568         }
 569         return 0;
 570 }
 571
 572 static void i801_isr_byte_done(struct i801_priv *priv)
 573 {
 574         if (priv->is_read) {
 575                 /* For SMBus block reads, length is received with first byte */
 576                 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
 577                     (priv->count == 0)) {
 578                         priv->len = inb_p(SMBHSTDAT0(priv));
 579                         if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
 580                                 dev_err(&priv->pci_dev->dev,
 581                                         "Illegal SMBus block read size %d\n",
 582                                         priv->len);
 583                                 /* FIXME: Recover */
 584                                 priv->len = I2C_SMBUS_BLOCK_MAX;
 585                         } else {
 586                                 dev_dbg(&priv->pci_dev->dev,
 587                                         "SMBus block read size is %d\n",
 588                                         priv->len);
 589                         }
 590                         priv->data[-1] = priv->len;
 591                 }
 592
 593                 /* Read next byte */
 594                 if (priv->count < priv->len)
 595                         priv->data[priv->count++] = inb(SMBBLKDAT(priv));
 596                 else
 597                         dev_dbg(&priv->pci_dev->dev,
 598                                 "Discarding extra byte on block read\n");
 599
 600                 /* Set LAST_BYTE for last byte of read transaction */
 601                 if (priv->count == priv->len - 1)
 602                         outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
 603                                SMBHSTCNT(priv));
 604         } else if (priv->count < priv->len - 1) {
 605                 /* Write next byte, except for IRQ after last byte */
 606                 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
 607         }
 608
 609         /* Clear BYTE_DONE to continue with next byte */
 610         outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 611 }
 612
 613 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
 614 {
 615         unsigned short addr;
 616
 617         addr = inb_p(SMBNTFDADD(priv)) >> 1;
 618
 619         /*
 620          * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
 621          * always returns 0. Our current implementation doesn't provide
 622          * data, so we just ignore it.
 623          */
 624         i2c_handle_smbus_host_notify(&priv->adapter, addr);
 625
 626         /* clear Host Notify bit and return */
 627         outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
 628         return IRQ_HANDLED;
 629 }
 630
 631 /*
 632  * There are three kinds of interrupts:
 633  *
 634  * 1) i801 signals transaction completion with one of these interrupts:
 635  *      INTR - Success
 636  *      DEV_ERR - Invalid command, NAK or communication timeout
 637  *      BUS_ERR - SMI# transaction collision
 638  *      FAILED - transaction was canceled due to a KILL request
 639  *    When any of these occur, update ->status and wake up the waitq.
 640  *    ->status must be cleared before kicking off the next transaction.
 641  *
 642  * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
 643  *    occurs for each byte of a byte-by-byte to prepare the next byte.
 644  *
 645  * 3) Host Notify interrupts
 646  */
 647 static irqreturn_t i801_isr(int irq, void *dev_id)
 648 {
 649         struct i801_priv *priv = dev_id;
 650         u16 pcists;
 651         u8 status;
 652
 653         /* Confirm this is our interrupt */
 654         pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
 655         if (!(pcists & SMBPCISTS_INTS))
 656                 return IRQ_NONE;
 657
 658         if (priv->features & FEATURE_HOST_NOTIFY) {
 659                 status = inb_p(SMBSLVSTS(priv));
 660                 if (status & SMBSLVSTS_HST_NTFY_STS)
 661                         return i801_host_notify_isr(priv);
 662         }
 663
 664         status = inb_p(SMBHSTSTS(priv));
 665         if (status & SMBHSTSTS_BYTE_DONE)
 666                 i801_isr_byte_done(priv);
 667
 668         /*
 669          * Clear irq sources and report transaction result.
 670          * ->status must be cleared before the next transaction is started.
 671          */
 672         status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
 673         if (status) {
 674                 outb_p(status, SMBHSTSTS(priv));
 675                 priv->status = status;
 676                 wake_up(&priv->waitq);
 677         }
 678
 679         return IRQ_HANDLED;
 680 }
 681
 682 /*
 683  * For "byte-by-byte" block transactions:
 684  *   I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
 685  *   I2C read uses cmd=I801_I2C_BLOCK_DATA
 686  */
 687 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 688                                                union i2c_smbus_data *data,
 689                                                char read_write, int command,
 690                                                int hwpec)
 691 {
 692         int i, len;
 693         int smbcmd;
 694         int status;
 695         int result;
 696         const struct i2c_adapter *adap = &priv->adapter;
 697
 698         if (command == I2C_SMBUS_BLOCK_PROC_CALL)
 699                 return -EOPNOTSUPP;
 700
 701         result = i801_check_pre(priv);
 702         if (result < 0)
 703                 return result;
 704
 705         len = data->block[0];
 706
 707         if (read_write == I2C_SMBUS_WRITE) {
 708                 outb_p(len, SMBHSTDAT0(priv));
 709                 outb_p(data->block[1], SMBBLKDAT(priv));
 710         }
 711
 712         if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
 713             read_write == I2C_SMBUS_READ)
 714                 smbcmd = I801_I2C_BLOCK_DATA;
 715         else
 716                 smbcmd = I801_BLOCK_DATA;
 717
 718         if (priv->features & FEATURE_IRQ) {
 719                 priv->is_read = (read_write == I2C_SMBUS_READ);
 720                 if (len == 1 && priv->is_read)
 721                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 722                 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
 723                 priv->len = len;
 724                 priv->count = 0;
 725                 priv->data = &data->block[1];
 726
 727                 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
 728                 result = wait_event_timeout(priv->waitq,
 729                                             (status = priv->status),
 730                                             adap->timeout);
 731                 if (!result) {
 732                         status = -ETIMEDOUT;
 733                         dev_warn(&priv->pci_dev->dev,
 734                                  "Timeout waiting for interrupt!\n");
 735                 }
 736                 priv->status = 0;
 737                 return i801_check_post(priv, status);
 738         }
 739
 740         for (i = 1; i <= len; i++) {
 741                 if (i == len && read_write == I2C_SMBUS_READ)
 742                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 743                 outb_p(smbcmd, SMBHSTCNT(priv));
 744
 745                 if (i == 1)
 746                         outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
 747                                SMBHSTCNT(priv));
 748
 749                 status = i801_wait_byte_done(priv);
 750                 if (status)
 751                         goto exit;
 752
 753                 if (i == 1 && read_write == I2C_SMBUS_READ
 754                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 755                         len = inb_p(SMBHSTDAT0(priv));
 756                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 757                                 dev_err(&priv->pci_dev->dev,
 758                                         "Illegal SMBus block read size %d\n",
 759                                         len);
 760                                 /* Recover */
 761                                 while (inb_p(SMBHSTSTS(priv)) &
 762                                        SMBHSTSTS_HOST_BUSY)
 763                                         outb_p(SMBHSTSTS_BYTE_DONE,
 764                                                SMBHSTSTS(priv));
 765                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 766                                 return -EPROTO;
 767                         }
 768                         data->block[0] = len;
 769                 }
 770
 771                 /* Retrieve/store value in SMBBLKDAT */
 772                 if (read_write == I2C_SMBUS_READ)
 773                         data->block[i] = inb_p(SMBBLKDAT(priv));
 774                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 775                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 776
 777                 /* signals SMBBLKDAT ready */
 778                 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 779         }
 780
 781         status = i801_wait_intr(priv);
 782 exit:
 783         return i801_check_post(priv, status);
 784 }
 785
 786 static int i801_set_block_buffer_mode(struct i801_priv *priv)
 787 {
 788         outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 789         if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
 790                 return -EIO;
 791         return 0;
 792 }
 793
 794 /* Block transaction function */
 795 static int i801_block_transaction(struct i801_priv *priv,
 796                                   union i2c_smbus_data *data, char read_write,
 797                                   int command, int hwpec)
 798 {
 799         int result = 0;
 800         unsigned char hostc;
 801
 802         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 803                 if (read_write == I2C_SMBUS_WRITE) {
 804                         /* set I2C_EN bit in configuration register */
 805                         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 806                         pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
 807                                               hostc | SMBHSTCFG_I2C_EN);
 808                 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 809                         dev_err(&priv->pci_dev->dev,
 810                                 "I2C block read is unsupported!\n");
 811                         return -EOPNOTSUPP;
 812                 }
 813         }
 814
 815         if (read_write == I2C_SMBUS_WRITE
 816          || command == I2C_SMBUS_I2C_BLOCK_DATA) {
 817                 if (data->block[0] < 1)
 818                         data->block[0] = 1;
 819                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
 820                         data->block[0] = I2C_SMBUS_BLOCK_MAX;
 821         } else {
 822                 data->block[0] = 32;    /* max for SMBus block reads */
 823         }
 824
 825         /* Experience has shown that the block buffer can only be used for
 826            SMBus (not I2C) block transactions, even though the datasheet
 827            doesn't mention this limitation. */
 828         if ((priv->features & FEATURE_BLOCK_BUFFER)
 829          && command != I2C_SMBUS_I2C_BLOCK_DATA
 830          && i801_set_block_buffer_mode(priv) == 0)
 831                 result = i801_block_transaction_by_block(priv, data,
 832                                                          read_write,
 833                                                          command, hwpec);
 834         else
 835                 result = i801_block_transaction_byte_by_byte(priv, data,
 836                                                              read_write,
 837                                                              command, hwpec);
 838
 839         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 840          && read_write == I2C_SMBUS_WRITE) {
 841                 /* restore saved configuration register value */
 842                 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 843         }
 844         return result;
 845 }
 846
 847 /* Return negative errno on error. */
 848 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 849                        unsigned short flags, char read_write, u8 command,
 850                        int size, union i2c_smbus_data *data)
 851 {
 852         int hwpec;
 853         int block = 0;
 854         int ret = 0, xact = 0;
 855         struct i801_priv *priv = i2c_get_adapdata(adap);
 856
 857         mutex_lock(&priv->acpi_lock);
 858         if (priv->acpi_reserved) {
 859                 mutex_unlock(&priv->acpi_lock);
 860                 return -EBUSY;
 861         }
 862
 863         pm_runtime_get_sync(&priv->pci_dev->dev);
 864
 865         hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 866                 && size != I2C_SMBUS_QUICK
 867                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 868
 869         switch (size) {
 870         case I2C_SMBUS_QUICK:
 871                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 872                        SMBHSTADD(priv));
 873                 xact = I801_QUICK;
 874                 break;
 875         case I2C_SMBUS_BYTE:
 876                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 877                        SMBHSTADD(priv));
 878                 if (read_write == I2C_SMBUS_WRITE)
 879                         outb_p(command, SMBHSTCMD(priv));
 880                 xact = I801_BYTE;
 881                 break;
 882         case I2C_SMBUS_BYTE_DATA:
 883                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 884                        SMBHSTADD(priv));
 885                 outb_p(command, SMBHSTCMD(priv));
 886                 if (read_write == I2C_SMBUS_WRITE)
 887                         outb_p(data->byte, SMBHSTDAT0(priv));
 888                 xact = I801_BYTE_DATA;
 889                 break;
 890         case I2C_SMBUS_WORD_DATA:
 891                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 892                        SMBHSTADD(priv));
 893                 outb_p(command, SMBHSTCMD(priv));
 894                 if (read_write == I2C_SMBUS_WRITE) {
 895                         outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 896                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 897                 }
 898                 xact = I801_WORD_DATA;
 899                 break;
 900         case I2C_SMBUS_BLOCK_DATA:
 901                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 902                        SMBHSTADD(priv));
 903                 outb_p(command, SMBHSTCMD(priv));
 904                 block = 1;
 905                 break;
 906         case I2C_SMBUS_I2C_BLOCK_DATA:
 907                 /*
 908                  * NB: page 240 of ICH5 datasheet shows that the R/#W
 909                  * bit should be cleared here, even when reading.
 910                  * However if SPD Write Disable is set (Lynx Point and later),
 911                  * the read will fail if we don't set the R/#W bit.
 912                  */
 913                 outb_p(((addr & 0x7f) << 1) |
 914                        ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ?
 915                         (read_write & 0x01) : 0),
 916                        SMBHSTADD(priv));
 917                 if (read_write == I2C_SMBUS_READ) {
 918                         /* NB: page 240 of ICH5 datasheet also shows
 919                          * that DATA1 is the cmd field when reading */
 920                         outb_p(command, SMBHSTDAT1(priv));
 921                 } else
 922                         outb_p(command, SMBHSTCMD(priv));
 923                 block = 1;
 924                 break;
 925         case I2C_SMBUS_BLOCK_PROC_CALL:
 926                 /*
 927                  * Bit 0 of the slave address register always indicate a write
 928                  * command.
 929                  */
 930                 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
 931                 outb_p(command, SMBHSTCMD(priv));
 932                 block = 1;
 933                 break;
 934         default:
 935                 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
 936                         size);
 937                 ret = -EOPNOTSUPP;
 938                 goto out;
 939         }
 940
 941         if (hwpec)      /* enable/disable hardware PEC */
 942                 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 943         else
 944                 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 945                        SMBAUXCTL(priv));
 946
 947         if (block)
 948                 ret = i801_block_transaction(priv, data, read_write, size,
 949                                              hwpec);
 950         else
 951                 ret = i801_transaction(priv, xact);
 952
 953         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 954            time, so we forcibly disable it after every transaction. Turn off
 955            E32B for the same reason. */
 956         if (hwpec || block)
 957                 outb_p(inb_p(SMBAUXCTL(priv)) &
 958                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 959
 960         if (block)
 961                 goto out;
 962         if (ret)
 963                 goto out;
 964         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 965                 goto out;
 966
 967         switch (xact & 0x7f) {
 968         case I801_BYTE: /* Result put in SMBHSTDAT0 */
 969         case I801_BYTE_DATA:
 970                 data->byte = inb_p(SMBHSTDAT0(priv));
 971                 break;
 972         case I801_WORD_DATA:
 973                 data->word = inb_p(SMBHSTDAT0(priv)) +
 974                              (inb_p(SMBHSTDAT1(priv)) << 8);
 975                 break;
 976         }
 977
 978 out:
 979         pm_runtime_mark_last_busy(&priv->pci_dev->dev);
 980         pm_runtime_put_autosuspend(&priv->pci_dev->dev);
 981         mutex_unlock(&priv->acpi_lock);
 982         return ret;
 983 }
 984
 985
 986 static u32 i801_func(struct i2c_adapter *adapter)
 987 {
 988         struct i801_priv *priv = i2c_get_adapdata(adapter);
 989
 990         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 991                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 992                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 993                ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 994                ((priv->features & FEATURE_BLOCK_PROC) ?
 995                 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) |
 996                ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 997                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
 998                ((priv->features & FEATURE_HOST_NOTIFY) ?
 999                 I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
1000 }
1001
1002 static void i801_enable_host_notify(struct i2c_adapter *adapter)
1003 {
1004         struct i801_priv *priv = i2c_get_adapdata(adapter);
1005
1006         if (!(priv->features & FEATURE_HOST_NOTIFY))
1007                 return;
1008
1009         if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd))
1010                 outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd,
1011                        SMBSLVCMD(priv));
1012
1013         /* clear Host Notify bit to allow a new notification */
1014         outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
1015 }
1016
1017 static void i801_disable_host_notify(struct i801_priv *priv)
1018 {
1019         if (!(priv->features & FEATURE_HOST_NOTIFY))
1020                 return;
1021
1022         outb_p(priv->original_slvcmd, SMBSLVCMD(priv));
1023 }
1024
1025 static const struct i2c_algorithm smbus_algorithm = {
1026         .smbus_xfer     = i801_access,
1027         .functionality  = i801_func,
1028 };
1029
1030 static const struct pci_device_id i801_ids[] = {
1031         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
1032         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
1033         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
1034         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
1035         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
1036         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
1037         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
1038         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
1039         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
1040         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
1041         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
1042         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
1043         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
1044         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
1045         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
1046         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
1047         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
1048         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
1049         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
1050         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
1051         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
1052         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
1053         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
1054         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
1055         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
1056         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
1057         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
1058         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
1059         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
1060         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
1061         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
1062         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) },
1063         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
1064         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
1065         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
1066         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
1067         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
1068         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
1069         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMBUS) },
1070         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
1071         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EBG_SMBUS) },
1072         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
1073         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) },
1074         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) },
1075         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) },
1076         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS) },
1077         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS) },
1078         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS) },
1079         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS) },
1080         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS) },
1081         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS) },
1082         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS) },
1083         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS) },
1084         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS) },
1085         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS) },
1086         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS) },
1087         { 0, }
1088 };
1089
1090 MODULE_DEVICE_TABLE(pci, i801_ids);
1091
1092 #if defined CONFIG_X86 && defined CONFIG_DMI
1093 static unsigned char apanel_addr;
1094
1095 /* Scan the system ROM for the signature "FJKEYINF" */
1096 static __init const void __iomem *bios_signature(const void __iomem *bios)
1097 {
1098         ssize_t offset;
1099         const unsigned char signature[] = "FJKEYINF";
1100
1101         for (offset = 0; offset < 0x10000; offset += 0x10) {
1102                 if (check_signature(bios + offset, signature,
1103                                     sizeof(signature)-1))
1104                         return bios + offset;
1105         }
1106         return NULL;
1107 }
1108
1109 static void __init input_apanel_init(void)
1110 {
1111         void __iomem *bios;
1112         const void __iomem *p;
1113
1114         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1115         p = bios_signature(bios);
1116         if (p) {
1117                 /* just use the first address */
1118                 apanel_addr = readb(p + 8 + 3) >> 1;
1119         }
1120         iounmap(bios);
1121 }
1122
1123 struct dmi_onboard_device_info {
1124         const char *name;
1125         u8 type;
1126         unsigned short i2c_addr;
1127         const char *i2c_type;
1128 };
1129
1130 static const struct dmi_onboard_device_info dmi_devices[] = {
1131         { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1132         { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1133         { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1134 };
1135
1136 static void dmi_check_onboard_device(u8 type, const char *name,
1137                                      struct i2c_adapter *adap)
1138 {
1139         int i;
1140         struct i2c_board_info info;
1141
1142         for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1143                 /* & ~0x80, ignore enabled/disabled bit */
1144                 if ((type & ~0x80) != dmi_devices[i].type)
1145                         continue;
1146                 if (strcasecmp(name, dmi_devices[i].name))
1147                         continue;
1148
1149                 memset(&info, 0, sizeof(struct i2c_board_info));
1150                 info.addr = dmi_devices[i].i2c_addr;
1151                 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1152                 i2c_new_client_device(adap, &info);
1153                 break;
1154         }
1155 }
1156
1157 /* We use our own function to check for onboard devices instead of
1158    dmi_find_device() as some buggy BIOS's have the devices we are interested
1159    in marked as disabled */
1160 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1161 {
1162         int i, count;
1163
1164         if (dm->type != 10)
1165                 return;
1166
1167         count = (dm->length - sizeof(struct dmi_header)) / 2;
1168         for (i = 0; i < count; i++) {
1169                 const u8 *d = (char *)(dm + 1) + (i * 2);
1170                 const char *name = ((char *) dm) + dm->length;
1171                 u8 type = d[0];
1172                 u8 s = d[1];
1173
1174                 if (!s)
1175                         continue;
1176                 s--;
1177                 while (s > 0 && name[0]) {
1178                         name += strlen(name) + 1;
1179                         s--;
1180                 }
1181                 if (name[0] == 0) /* Bogus string reference */
1182                         continue;
1183
1184                 dmi_check_onboard_device(type, name, adap);
1185         }
1186 }
1187
1188 /* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */
1189 static const char *const acpi_smo8800_ids[] = {
1190         "SMO8800",
1191         "SMO8801",
1192         "SMO8810",
1193         "SMO8811",
1194         "SMO8820",
1195         "SMO8821",
1196         "SMO8830",
1197         "SMO8831",
1198 };
1199
1200 static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle,
1201                                              u32 nesting_level,
1202                                              void *context,
1203                                              void **return_value)
1204 {
1205         struct acpi_device_info *info;
1206         acpi_status status;
1207         char *hid;
1208         int i;
1209
1210         status = acpi_get_object_info(obj_handle, &info);
1211         if (ACPI_FAILURE(status))
1212                 return AE_OK;
1213
1214         if (!(info->valid & ACPI_VALID_HID))
1215                 goto smo88xx_not_found;
1216
1217         hid = info->hardware_id.string;
1218         if (!hid)
1219                 goto smo88xx_not_found;
1220
1221         i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid);
1222         if (i < 0)
1223                 goto smo88xx_not_found;
1224
1225         kfree(info);
1226
1227         *((bool *)return_value) = true;
1228         return AE_CTRL_TERMINATE;
1229
1230 smo88xx_not_found:
1231         kfree(info);
1232         return AE_OK;
1233 }
1234
1235 static bool is_dell_system_with_lis3lv02d(void)
1236 {
1237         bool found;
1238         const char *vendor;
1239
1240         vendor = dmi_get_system_info(DMI_SYS_VENDOR);
1241         if (!vendor || strcmp(vendor, "Dell Inc."))
1242                 return false;
1243
1244         /*
1245          * Check that ACPI device SMO88xx is present and is functioning.
1246          * Function acpi_get_devices() already filters all ACPI devices
1247          * which are not present or are not functioning.
1248          * ACPI device SMO88xx represents our ST microelectronics lis3lv02d
1249          * accelerometer but unfortunately ACPI does not provide any other
1250          * information (like I2C address).
1251          */
1252         found = false;
1253         acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL,
1254                          (void **)&found);
1255
1256         return found;
1257 }
1258
1259 /*
1260  * Accelerometer's I2C address is not specified in DMI nor ACPI,
1261  * so it is needed to define mapping table based on DMI product names.
1262  */
1263 static const struct {
1264         const char *dmi_product_name;
1265         unsigned short i2c_addr;
1266 } dell_lis3lv02d_devices[] = {
1267         /*
1268          * Dell platform team told us that these Latitude devices have
1269          * ST microelectronics accelerometer at I2C address 0x29.
1270          */
1271         { "Latitude E5250",     0x29 },
1272         { "Latitude E5450",     0x29 },
1273         { "Latitude E5550",     0x29 },
1274         { "Latitude E6440",     0x29 },
1275         { "Latitude E6440 ATG", 0x29 },
1276         { "Latitude E6540",     0x29 },
1277         /*
1278          * Additional individual entries were added after verification.
1279          */
1280         { "Latitude 5480",      0x29 },
1281         { "Vostro V131",        0x1d },
1282 };
1283
1284 static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv)
1285 {
1286         struct i2c_board_info info;
1287         const char *dmi_product_name;
1288         int i;
1289
1290         dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
1291         for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) {
1292                 if (strcmp(dmi_product_name,
1293                            dell_lis3lv02d_devices[i].dmi_product_name) == 0)
1294                         break;
1295         }
1296
1297         if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) {
1298                 dev_warn(&priv->pci_dev->dev,
1299                          "Accelerometer lis3lv02d is present on SMBus but its"
1300                          " address is unknown, skipping registration\n");
1301                 return;
1302         }
1303
1304         memset(&info, 0, sizeof(struct i2c_board_info));
1305         info.addr = dell_lis3lv02d_devices[i].i2c_addr;
1306         strlcpy(info.type, "lis3lv02d", I2C_NAME_SIZE);
1307         i2c_new_client_device(&priv->adapter, &info);
1308 }
1309
1310 /* Register optional slaves */
1311 static void i801_probe_optional_slaves(struct i801_priv *priv)
1312 {
1313         /* Only register slaves on main SMBus channel */
1314         if (priv->features & FEATURE_IDF)
1315                 return;
1316
1317         if (apanel_addr) {
1318                 struct i2c_board_info info;
1319
1320                 memset(&info, 0, sizeof(struct i2c_board_info));
1321                 info.addr = apanel_addr;
1322                 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
1323                 i2c_new_client_device(&priv->adapter, &info);
1324         }
1325
1326         if (dmi_name_in_vendors("FUJITSU"))
1327                 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1328
1329         if (is_dell_system_with_lis3lv02d())
1330                 register_dell_lis3lv02d_i2c_device(priv);
1331
1332         /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */
1333 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO)
1334         if (!priv->mux_drvdata)
1335 #endif
1336                 i2c_register_spd(&priv->adapter);
1337 }
1338 #else
1339 static void __init input_apanel_init(void) {}
1340 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1341 #endif  /* CONFIG_X86 && CONFIG_DMI */
1342
1343 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
1344 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1345         .gpio_chip = "gpio_ich",
1346         .values = { 0x02, 0x03 },
1347         .n_values = 2,
1348         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1349         .gpios = { 52, 53 },
1350         .n_gpios = 2,
1351 };
1352
1353 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1354         .gpio_chip = "gpio_ich",
1355         .values = { 0x02, 0x03, 0x01 },
1356         .n_values = 3,
1357         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1358         .gpios = { 52, 53 },
1359         .n_gpios = 2,
1360 };
1361
1362 static const struct dmi_system_id mux_dmi_table[] = {
1363         {
1364                 .matches = {
1365                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1366                         DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1367                 },
1368                 .driver_data = &i801_mux_config_asus_z8_d12,
1369         },
1370         {
1371                 .matches = {
1372                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1373                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1374                 },
1375                 .driver_data = &i801_mux_config_asus_z8_d12,
1376         },
1377         {
1378                 .matches = {
1379                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1380                         DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1381                 },
1382                 .driver_data = &i801_mux_config_asus_z8_d12,
1383         },
1384         {
1385                 .matches = {
1386                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1387                         DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1388                 },
1389                 .driver_data = &i801_mux_config_asus_z8_d12,
1390         },
1391         {
1392                 .matches = {
1393                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1394                         DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1395                 },
1396                 .driver_data = &i801_mux_config_asus_z8_d12,
1397         },
1398         {
1399                 .matches = {
1400                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1401                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1402                 },
1403                 .driver_data = &i801_mux_config_asus_z8_d12,
1404         },
1405         {
1406                 .matches = {
1407                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1408                         DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1409                 },
1410                 .driver_data = &i801_mux_config_asus_z8_d18,
1411         },
1412         {
1413                 .matches = {
1414                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1415                         DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1416                 },
1417                 .driver_data = &i801_mux_config_asus_z8_d18,
1418         },
1419         {
1420                 .matches = {
1421                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1422                         DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1423                 },
1424                 .driver_data = &i801_mux_config_asus_z8_d12,
1425         },
1426         { }
1427 };
1428
1429 /* Setup multiplexing if needed */
1430 static int i801_add_mux(struct i801_priv *priv)
1431 {
1432         struct device *dev = &priv->adapter.dev;
1433         const struct i801_mux_config *mux_config;
1434         struct i2c_mux_gpio_platform_data gpio_data;
1435         struct gpiod_lookup_table *lookup;
1436         int err, i;
1437
1438         if (!priv->mux_drvdata)
1439                 return 0;
1440         mux_config = priv->mux_drvdata;
1441
1442         /* Prepare the platform data */
1443         memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1444         gpio_data.parent = priv->adapter.nr;
1445         gpio_data.values = mux_config->values;
1446         gpio_data.n_values = mux_config->n_values;
1447         gpio_data.classes = mux_config->classes;
1448         gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1449
1450         /* Register GPIO descriptor lookup table */
1451         lookup = devm_kzalloc(dev,
1452                               struct_size(lookup, table, mux_config->n_gpios),
1453                               GFP_KERNEL);
1454         if (!lookup)
1455                 return -ENOMEM;
1456         lookup->dev_id = "i2c-mux-gpio";
1457         for (i = 0; i < mux_config->n_gpios; i++) {
1458                 lookup->table[i] = (struct gpiod_lookup)
1459                         GPIO_LOOKUP(mux_config->gpio_chip,
1460                                     mux_config->gpios[i], "mux", 0);
1461         }
1462         gpiod_add_lookup_table(lookup);
1463         priv->lookup = lookup;
1464
1465         /*
1466          * Register the mux device, we use PLATFORM_DEVID_NONE here
1467          * because since we are referring to the GPIO chip by name we are
1468          * anyways in deep trouble if there is more than one of these
1469          * devices, and there should likely only be one platform controller
1470          * hub.
1471          */
1472         priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1473                                 PLATFORM_DEVID_NONE, &gpio_data,
1474                                 sizeof(struct i2c_mux_gpio_platform_data));
1475         if (IS_ERR(priv->mux_pdev)) {
1476                 err = PTR_ERR(priv->mux_pdev);
1477                 gpiod_remove_lookup_table(lookup);
1478                 priv->mux_pdev = NULL;
1479                 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1480                 return err;
1481         }
1482
1483         return 0;
1484 }
1485
1486 static void i801_del_mux(struct i801_priv *priv)
1487 {
1488         if (priv->mux_pdev)
1489                 platform_device_unregister(priv->mux_pdev);
1490         if (priv->lookup)
1491                 gpiod_remove_lookup_table(priv->lookup);
1492 }
1493
1494 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1495 {
1496         const struct dmi_system_id *id;
1497         const struct i801_mux_config *mux_config;
1498         unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1499         int i;
1500
1501         id = dmi_first_match(mux_dmi_table);
1502         if (id) {
1503                 /* Remove branch classes from trunk */
1504                 mux_config = id->driver_data;
1505                 for (i = 0; i < mux_config->n_values; i++)
1506                         class &= ~mux_config->classes[i];
1507
1508                 /* Remember for later */
1509                 priv->mux_drvdata = mux_config;
1510         }
1511
1512         return class;
1513 }
1514 #else
1515 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1516 static inline void i801_del_mux(struct i801_priv *priv) { }
1517
1518 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1519 {
1520         return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1521 }
1522 #endif
1523
1524 static const struct itco_wdt_platform_data spt_tco_platform_data = {
1525         .name = "Intel PCH",
1526         .version = 4,
1527 };
1528
1529 static DEFINE_SPINLOCK(p2sb_spinlock);
1530
1531 static struct platform_device *
1532 i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev,
1533                  struct resource *tco_res)
1534 {
1535         struct resource *res;
1536         unsigned int devfn;
1537         u64 base64_addr;
1538         u32 base_addr;
1539         u8 hidden;
1540
1541         /*
1542          * We must access the NO_REBOOT bit over the Primary to Sideband
1543          * bridge (P2SB). The BIOS prevents the P2SB device from being
1544          * enumerated by the PCI subsystem, so we need to unhide/hide it
1545          * to lookup the P2SB BAR.
1546          */
1547         spin_lock(&p2sb_spinlock);
1548
1549         devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1550
1551         /* Unhide the P2SB device, if it is hidden */
1552         pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden);
1553         if (hidden)
1554                 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1555
1556         pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1557         base64_addr = base_addr & 0xfffffff0;
1558
1559         pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1560         base64_addr |= (u64)base_addr << 32;
1561
1562         /* Hide the P2SB device, if it was hidden before */
1563         if (hidden)
1564                 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden);
1565         spin_unlock(&p2sb_spinlock);
1566
1567         res = &tco_res[1];
1568         if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1569                 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV;
1570         else
1571                 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1572
1573         res->end = res->start + 3;
1574         res->flags = IORESOURCE_MEM;
1575
1576         return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1577                                         tco_res, 2, &spt_tco_platform_data,
1578                                         sizeof(spt_tco_platform_data));
1579 }
1580
1581 static const struct itco_wdt_platform_data cnl_tco_platform_data = {
1582         .name = "Intel PCH",
1583         .version = 6,
1584 };
1585
1586 static struct platform_device *
1587 i801_add_tco_cnl(struct i801_priv *priv, struct pci_dev *pci_dev,
1588                  struct resource *tco_res)
1589 {
1590         return platform_device_register_resndata(&pci_dev->dev,
1591                         "iTCO_wdt", -1, tco_res, 1, &cnl_tco_platform_data,
1592                         sizeof(cnl_tco_platform_data));
1593 }
1594
1595 static void i801_add_tco(struct i801_priv *priv)
1596 {
1597         struct pci_dev *pci_dev = priv->pci_dev;
1598         struct resource tco_res[2], *res;
1599         u32 tco_base, tco_ctl;
1600
1601         /* If we have ACPI based watchdog use that instead */
1602         if (acpi_has_watchdog())
1603                 return;
1604
1605         if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL)))
1606                 return;
1607
1608         pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1609         pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1610         if (!(tco_ctl & TCOCTL_EN))
1611                 return;
1612
1613         memset(tco_res, 0, sizeof(tco_res));
1614         /*
1615          * Always populate the main iTCO IO resource here. The second entry
1616          * for NO_REBOOT MMIO is filled by the SPT specific function.
1617          */
1618         res = &tco_res[0];
1619         res->start = tco_base & ~1;
1620         res->end = res->start + 32 - 1;
1621         res->flags = IORESOURCE_IO;
1622
1623         if (priv->features & FEATURE_TCO_CNL)
1624                 priv->tco_pdev = i801_add_tco_cnl(priv, pci_dev, tco_res);
1625         else
1626                 priv->tco_pdev = i801_add_tco_spt(priv, pci_dev, tco_res);
1627
1628         if (IS_ERR(priv->tco_pdev))
1629                 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1630 }
1631
1632 #ifdef CONFIG_ACPI
1633 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv,
1634                                       acpi_physical_address address)
1635 {
1636         return address >= priv->smba &&
1637                address <= pci_resource_end(priv->pci_dev, SMBBAR);
1638 }
1639
1640 static acpi_status
1641 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1642                      u64 *value, void *handler_context, void *region_context)
1643 {
1644         struct i801_priv *priv = handler_context;
1645         struct pci_dev *pdev = priv->pci_dev;
1646         acpi_status status;
1647
1648         /*
1649          * Once BIOS AML code touches the OpRegion we warn and inhibit any
1650          * further access from the driver itself. This device is now owned
1651          * by the system firmware.
1652          */
1653         mutex_lock(&priv->acpi_lock);
1654
1655         if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) {
1656                 priv->acpi_reserved = true;
1657
1658                 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1659                 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1660
1661                 /*
1662                  * BIOS is accessing the host controller so prevent it from
1663                  * suspending automatically from now on.
1664                  */
1665                 pm_runtime_get_sync(&pdev->dev);
1666         }
1667
1668         if ((function & ACPI_IO_MASK) == ACPI_READ)
1669                 status = acpi_os_read_port(address, (u32 *)value, bits);
1670         else
1671                 status = acpi_os_write_port(address, (u32)*value, bits);
1672
1673         mutex_unlock(&priv->acpi_lock);
1674
1675         return status;
1676 }
1677
1678 static int i801_acpi_probe(struct i801_priv *priv)
1679 {
1680         struct acpi_device *adev;
1681         acpi_status status;
1682
1683         adev = ACPI_COMPANION(&priv->pci_dev->dev);
1684         if (adev) {
1685                 status = acpi_install_address_space_handler(adev->handle,
1686                                 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler,
1687                                 NULL, priv);
1688                 if (ACPI_SUCCESS(status))
1689                         return 0;
1690         }
1691
1692         return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1693 }
1694
1695 static void i801_acpi_remove(struct i801_priv *priv)
1696 {
1697         struct acpi_device *adev;
1698
1699         adev = ACPI_COMPANION(&priv->pci_dev->dev);
1700         if (!adev)
1701                 return;
1702
1703         acpi_remove_address_space_handler(adev->handle,
1704                 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1705
1706         mutex_lock(&priv->acpi_lock);
1707         if (priv->acpi_reserved)
1708                 pm_runtime_put(&priv->pci_dev->dev);
1709         mutex_unlock(&priv->acpi_lock);
1710 }
1711 #else
1712 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
1713 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1714 #endif
1715
1716 static unsigned char i801_setup_hstcfg(struct i801_priv *priv)
1717 {
1718         unsigned char hstcfg = priv->original_hstcfg;
1719
1720         hstcfg &= ~SMBHSTCFG_I2C_EN;    /* SMBus timing */
1721         hstcfg |= SMBHSTCFG_HST_EN;
1722         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg);
1723         return hstcfg;
1724 }
1725
1726 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1727 {
1728         unsigned char temp;
1729         int err, i;
1730         struct i801_priv *priv;
1731
1732         priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1733         if (!priv)
1734                 return -ENOMEM;
1735
1736         i2c_set_adapdata(&priv->adapter, priv);
1737         priv->adapter.owner = THIS_MODULE;
1738         priv->adapter.class = i801_get_adapter_class(priv);
1739         priv->adapter.algo = &smbus_algorithm;
1740         priv->adapter.dev.parent = &dev->dev;
1741         ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1742         priv->adapter.retries = 3;
1743         mutex_init(&priv->acpi_lock);
1744
1745         priv->pci_dev = dev;
1746         switch (dev->device) {
1747         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
1748         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
1749         case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS:
1750         case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS:
1751         case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
1752         case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS:
1753         case PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS:
1754                 priv->features |= FEATURE_BLOCK_PROC;
1755                 priv->features |= FEATURE_I2C_BLOCK_READ;
1756                 priv->features |= FEATURE_IRQ;
1757                 priv->features |= FEATURE_SMBUS_PEC;
1758                 priv->features |= FEATURE_BLOCK_BUFFER;
1759                 priv->features |= FEATURE_TCO_SPT;
1760                 priv->features |= FEATURE_HOST_NOTIFY;
1761                 break;
1762
1763         case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS:
1764         case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS:
1765         case PCI_DEVICE_ID_INTEL_CDF_SMBUS:
1766         case PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS:
1767         case PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS:
1768         case PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS:
1769         case PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS:
1770         case PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS:
1771         case PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS:
1772         case PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS:
1773         case PCI_DEVICE_ID_INTEL_EBG_SMBUS:
1774         case PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS:
1775                 priv->features |= FEATURE_BLOCK_PROC;
1776                 priv->features |= FEATURE_I2C_BLOCK_READ;
1777                 priv->features |= FEATURE_IRQ;
1778                 priv->features |= FEATURE_SMBUS_PEC;
1779                 priv->features |= FEATURE_BLOCK_BUFFER;
1780                 priv->features |= FEATURE_TCO_CNL;
1781                 priv->features |= FEATURE_HOST_NOTIFY;
1782                 break;
1783
1784         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1785         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1786         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1787         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1788         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1789         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1790                 priv->features |= FEATURE_IDF;
1791                 fallthrough;
1792         default:
1793                 priv->features |= FEATURE_BLOCK_PROC;
1794                 priv->features |= FEATURE_I2C_BLOCK_READ;
1795                 priv->features |= FEATURE_IRQ;
1796                 fallthrough;
1797         case PCI_DEVICE_ID_INTEL_82801DB_3:
1798                 priv->features |= FEATURE_SMBUS_PEC;
1799                 priv->features |= FEATURE_BLOCK_BUFFER;
1800                 fallthrough;
1801         case PCI_DEVICE_ID_INTEL_82801CA_3:
1802                 priv->features |= FEATURE_HOST_NOTIFY;
1803                 fallthrough;
1804         case PCI_DEVICE_ID_INTEL_82801BA_2:
1805         case PCI_DEVICE_ID_INTEL_82801AB_3:
1806         case PCI_DEVICE_ID_INTEL_82801AA_3:
1807                 break;
1808         }
1809
1810         /* Disable features on user request */
1811         for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1812                 if (priv->features & disable_features & (1 << i))
1813                         dev_notice(&dev->dev, "%s disabled by user\n",
1814                                    i801_feature_names[i]);
1815         }
1816         priv->features &= ~disable_features;
1817
1818         err = pcim_enable_device(dev);
1819         if (err) {
1820                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1821                         err);
1822                 return err;
1823         }
1824         pcim_pin_device(dev);
1825
1826         /* Determine the address of the SMBus area */
1827         priv->smba = pci_resource_start(dev, SMBBAR);
1828         if (!priv->smba) {
1829                 dev_err(&dev->dev,
1830                         "SMBus base address uninitialized, upgrade BIOS\n");
1831                 return -ENODEV;
1832         }
1833
1834         if (i801_acpi_probe(priv))
1835                 return -ENODEV;
1836
1837         err = pcim_iomap_regions(dev, 1 << SMBBAR,
1838                                  dev_driver_string(&dev->dev));
1839         if (err) {
1840                 dev_err(&dev->dev,
1841                         "Failed to request SMBus region 0x%lx-0x%Lx\n",
1842                         priv->smba,
1843                         (unsigned long long)pci_resource_end(dev, SMBBAR));
1844                 i801_acpi_remove(priv);
1845                 return err;
1846         }
1847
1848         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &priv->original_hstcfg);
1849         temp = i801_setup_hstcfg(priv);
1850         if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN))
1851                 dev_info(&dev->dev, "Enabling SMBus device\n");
1852
1853         if (temp & SMBHSTCFG_SMB_SMI_EN) {
1854                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1855                 /* Disable SMBus interrupt feature if SMBus using SMI# */
1856                 priv->features &= ~FEATURE_IRQ;
1857         }
1858         if (temp & SMBHSTCFG_SPD_WD)
1859                 dev_info(&dev->dev, "SPD Write Disable is set\n");
1860
1861         /* Clear special mode bits */
1862         if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1863                 outb_p(inb_p(SMBAUXCTL(priv)) &
1864                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1865
1866         /* Remember original Host Notify setting */
1867         if (priv->features & FEATURE_HOST_NOTIFY)
1868                 priv->original_slvcmd = inb_p(SMBSLVCMD(priv));
1869
1870         /* Default timeout in interrupt mode: 200 ms */
1871         priv->adapter.timeout = HZ / 5;
1872
1873         if (dev->irq == IRQ_NOTCONNECTED)
1874                 priv->features &= ~FEATURE_IRQ;
1875
1876         if (priv->features & FEATURE_IRQ) {
1877                 u16 pcictl, pcists;
1878
1879                 /* Complain if an interrupt is already pending */
1880                 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
1881                 if (pcists & SMBPCISTS_INTS)
1882                         dev_warn(&dev->dev, "An interrupt is pending!\n");
1883
1884                 /* Check if interrupts have been disabled */
1885                 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
1886                 if (pcictl & SMBPCICTL_INTDIS) {
1887                         dev_info(&dev->dev, "Interrupts are disabled\n");
1888                         priv->features &= ~FEATURE_IRQ;
1889                 }
1890         }
1891
1892         if (priv->features & FEATURE_IRQ) {
1893                 init_waitqueue_head(&priv->waitq);
1894
1895                 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1896                                        IRQF_SHARED,
1897                                        dev_driver_string(&dev->dev), priv);
1898                 if (err) {
1899                         dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1900                                 dev->irq, err);
1901                         priv->features &= ~FEATURE_IRQ;
1902                 }
1903         }
1904         dev_info(&dev->dev, "SMBus using %s\n",
1905                  priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1906
1907         i801_add_tco(priv);
1908
1909         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1910                 "SMBus I801 adapter at %04lx", priv->smba);
1911         err = i2c_add_adapter(&priv->adapter);
1912         if (err) {
1913                 i801_acpi_remove(priv);
1914                 return err;
1915         }
1916
1917         i801_enable_host_notify(&priv->adapter);
1918
1919         i801_probe_optional_slaves(priv);
1920         /* We ignore errors - multiplexing is optional */
1921         i801_add_mux(priv);
1922
1923         pci_set_drvdata(dev, priv);
1924
1925         dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
1926         pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1927         pm_runtime_use_autosuspend(&dev->dev);
1928         pm_runtime_put_autosuspend(&dev->dev);
1929         pm_runtime_allow(&dev->dev);
1930
1931         return 0;
1932 }
1933
1934 static void i801_remove(struct pci_dev *dev)
1935 {
1936         struct i801_priv *priv = pci_get_drvdata(dev);
1937
1938         pm_runtime_forbid(&dev->dev);
1939         pm_runtime_get_noresume(&dev->dev);
1940
1941         i801_disable_host_notify(priv);
1942         i801_del_mux(priv);
1943         i2c_del_adapter(&priv->adapter);
1944         i801_acpi_remove(priv);
1945         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1946
1947         platform_device_unregister(priv->tco_pdev);
1948
1949         /*
1950          * do not call pci_disable_device(dev) since it can cause hard hangs on
1951          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1952          */
1953 }
1954
1955 static void i801_shutdown(struct pci_dev *dev)
1956 {
1957         struct i801_priv *priv = pci_get_drvdata(dev);
1958
1959         /* Restore config registers to avoid hard hang on some systems */
1960         i801_disable_host_notify(priv);
1961         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1962 }
1963
1964 #ifdef CONFIG_PM_SLEEP
1965 static int i801_suspend(struct device *dev)
1966 {
1967         struct i801_priv *priv = dev_get_drvdata(dev);
1968
1969         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, priv->original_hstcfg);
1970         return 0;
1971 }
1972
1973 static int i801_resume(struct device *dev)
1974 {
1975         struct i801_priv *priv = dev_get_drvdata(dev);
1976
1977         i801_setup_hstcfg(priv);
1978         i801_enable_host_notify(&priv->adapter);
1979
1980         return 0;
1981 }
1982 #endif
1983
1984 static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume);
1985
1986 static struct pci_driver i801_driver = {
1987         .name           = "i801_smbus",
1988         .id_table       = i801_ids,
1989         .probe          = i801_probe,
1990         .remove         = i801_remove,
1991         .shutdown       = i801_shutdown,
1992         .driver         = {
1993                 .pm     = &i801_pm_ops,
1994         },
1995 };
1996
1997 static int __init i2c_i801_init(void)
1998 {
1999         if (dmi_name_in_vendors("FUJITSU"))
2000                 input_apanel_init();
2001         return pci_register_driver(&i801_driver);
2002 }
2003
2004 static void __exit i2c_i801_exit(void)
2005 {
2006         pci_unregister_driver(&i801_driver);
2007 }
2008
2009 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>");
2010 MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>");
2011 MODULE_DESCRIPTION("I801 SMBus driver");
2012 MODULE_LICENSE("GPL");
2013
2014 module_init(i2c_i801_init);
2015 module_exit(i2c_i801_exit);