drivers/i2c/busses/i2c-i801.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   4     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   5     <mdsxyz123@yahoo.com>
   6     Copyright (C) 2007 - 2014  Jean Delvare <jdelvare@suse.de>
   7     Copyright (C) 2010         Intel Corporation,
   8                                David Woodhouse <dwmw2@infradead.org>
   9
  10 */
  11
  12 /*
  13  * Supports the following Intel I/O Controller Hubs (ICH):
  14  *
  15  *                                      I/O                     Block   I2C
  16  *                                      region  SMBus   Block   proc.   block
  17  * Chip name                    PCI ID  size    PEC     buffer  call    read
  18  * ---------------------------------------------------------------------------
  19  * 82801AA (ICH)                0x2413  16      no      no      no      no
  20  * 82801AB (ICH0)               0x2423  16      no      no      no      no
  21  * 82801BA (ICH2)               0x2443  16      no      no      no      no
  22  * 82801CA (ICH3)               0x2483  32      soft    no      no      no
  23  * 82801DB (ICH4)               0x24c3  32      hard    yes     no      no
  24  * 82801E (ICH5)                0x24d3  32      hard    yes     yes     yes
  25  * 6300ESB                      0x25a4  32      hard    yes     yes     yes
  26  * 82801F (ICH6)                0x266a  32      hard    yes     yes     yes
  27  * 6310ESB/6320ESB              0x269b  32      hard    yes     yes     yes
  28  * 82801G (ICH7)                0x27da  32      hard    yes     yes     yes
  29  * 82801H (ICH8)                0x283e  32      hard    yes     yes     yes
  30  * 82801I (ICH9)                0x2930  32      hard    yes     yes     yes
  31  * EP80579 (Tolapai)            0x5032  32      hard    yes     yes     yes
  32  * ICH10                        0x3a30  32      hard    yes     yes     yes
  33  * ICH10                        0x3a60  32      hard    yes     yes     yes
  34  * 5/3400 Series (PCH)          0x3b30  32      hard    yes     yes     yes
  35  * 6 Series (PCH)               0x1c22  32      hard    yes     yes     yes
  36  * Patsburg (PCH)               0x1d22  32      hard    yes     yes     yes
  37  * Patsburg (PCH) IDF           0x1d70  32      hard    yes     yes     yes
  38  * Patsburg (PCH) IDF           0x1d71  32      hard    yes     yes     yes
  39  * Patsburg (PCH) IDF           0x1d72  32      hard    yes     yes     yes
  40  * DH89xxCC (PCH)               0x2330  32      hard    yes     yes     yes
  41  * Panther Point (PCH)          0x1e22  32      hard    yes     yes     yes
  42  * Lynx Point (PCH)             0x8c22  32      hard    yes     yes     yes
  43  * Lynx Point-LP (PCH)          0x9c22  32      hard    yes     yes     yes
  44  * Avoton (SOC)                 0x1f3c  32      hard    yes     yes     yes
  45  * Wellsburg (PCH)              0x8d22  32      hard    yes     yes     yes
  46  * Wellsburg (PCH) MS           0x8d7d  32      hard    yes     yes     yes
  47  * Wellsburg (PCH) MS           0x8d7e  32      hard    yes     yes     yes
  48  * Wellsburg (PCH) MS           0x8d7f  32      hard    yes     yes     yes
  49  * Coleto Creek (PCH)           0x23b0  32      hard    yes     yes     yes
  50  * Wildcat Point (PCH)          0x8ca2  32      hard    yes     yes     yes
  51  * Wildcat Point-LP (PCH)       0x9ca2  32      hard    yes     yes     yes
  52  * BayTrail (SOC)               0x0f12  32      hard    yes     yes     yes
  53  * Braswell (SOC)               0x2292  32      hard    yes     yes     yes
  54  * Sunrise Point-H (PCH)        0xa123  32      hard    yes     yes     yes
  55  * Sunrise Point-LP (PCH)       0x9d23  32      hard    yes     yes     yes
  56  * DNV (SOC)                    0x19df  32      hard    yes     yes     yes
  57  * Emmitsburg (PCH)             0x1bc9  32      hard    yes     yes     yes
  58  * Broxton (SOC)                0x5ad4  32      hard    yes     yes     yes
  59  * Lewisburg (PCH)              0xa1a3  32      hard    yes     yes     yes
  60  * Lewisburg Supersku (PCH)     0xa223  32      hard    yes     yes     yes
  61  * Kaby Lake PCH-H (PCH)        0xa2a3  32      hard    yes     yes     yes
  62  * Gemini Lake (SOC)            0x31d4  32      hard    yes     yes     yes
  63  * Cannon Lake-H (PCH)          0xa323  32      hard    yes     yes     yes
  64  * Cannon Lake-LP (PCH)         0x9da3  32      hard    yes     yes     yes
  65  * Cedar Fork (PCH)             0x18df  32      hard    yes     yes     yes
  66  * Ice Lake-LP (PCH)            0x34a3  32      hard    yes     yes     yes
  67  * Comet Lake (PCH)             0x02a3  32      hard    yes     yes     yes
  68  * Comet Lake-H (PCH)           0x06a3  32      hard    yes     yes     yes
  69  * Elkhart Lake (PCH)           0x4b23  32      hard    yes     yes     yes
  70  * Tiger Lake-LP (PCH)          0xa0a3  32      hard    yes     yes     yes
  71  * Jasper Lake (SOC)            0x4da3  32      hard    yes     yes     yes
  72  * Comet Lake-V (PCH)           0xa3a3  32      hard    yes     yes     yes
  73  *
  74  * Features supported by this driver:
  75  * Software PEC                         no
  76  * Hardware PEC                         yes
  77  * Block buffer                         yes
  78  * Block process call transaction       yes
  79  * I2C block read transaction           yes (doesn't use the block buffer)
  80  * Slave mode                           no
  81  * SMBus Host Notify                    yes
  82  * Interrupt processing                 yes
  83  *
  84  * See the file Documentation/i2c/busses/i2c-i801.rst for details.
  85  */
  86
  87 #include <linux/interrupt.h>
  88 #include <linux/module.h>
  89 #include <linux/pci.h>
  90 #include <linux/kernel.h>
  91 #include <linux/stddef.h>
  92 #include <linux/delay.h>
  93 #include <linux/ioport.h>
  94 #include <linux/init.h>
  95 #include <linux/i2c.h>
  96 #include <linux/i2c-smbus.h>
  97 #include <linux/acpi.h>
  98 #include <linux/io.h>
  99 #include <linux/dmi.h>
 100 #include <linux/slab.h>
 101 #include <linux/string.h>
 102 #include <linux/wait.h>
 103 #include <linux/err.h>
 104 #include <linux/platform_device.h>
 105 #include <linux/platform_data/itco_wdt.h>
 106 #include <linux/pm_runtime.h>
 107
 108 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
 109 #include <linux/gpio/machine.h>
 110 #include <linux/platform_data/i2c-mux-gpio.h>
 111 #endif
 112
 113 /* I801 SMBus address offsets */
 114 #define SMBHSTSTS(p)    (0 + (p)->smba)
 115 #define SMBHSTCNT(p)    (2 + (p)->smba)
 116 #define SMBHSTCMD(p)    (3 + (p)->smba)
 117 #define SMBHSTADD(p)    (4 + (p)->smba)
 118 #define SMBHSTDAT0(p)   (5 + (p)->smba)
 119 #define SMBHSTDAT1(p)   (6 + (p)->smba)
 120 #define SMBBLKDAT(p)    (7 + (p)->smba)
 121 #define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
 122 #define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
 123 #define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
 124 #define SMBSLVSTS(p)    (16 + (p)->smba)        /* ICH3 and later */
 125 #define SMBSLVCMD(p)    (17 + (p)->smba)        /* ICH3 and later */
 126 #define SMBNTFDADD(p)   (20 + (p)->smba)        /* ICH3 and later */
 127
 128 /* PCI Address Constants */
 129 #define SMBBAR          4
 130 #define SMBPCICTL       0x004
 131 #define SMBPCISTS       0x006
 132 #define SMBHSTCFG       0x040
 133 #define TCOBASE         0x050
 134 #define TCOCTL          0x054
 135
 136 #define SBREG_BAR               0x10
 137 #define SBREG_SMBCTRL           0xc6000c
 138 #define SBREG_SMBCTRL_DNV       0xcf000c
 139
 140 /* Host status bits for SMBPCISTS */
 141 #define SMBPCISTS_INTS          BIT(3)
 142
 143 /* Control bits for SMBPCICTL */
 144 #define SMBPCICTL_INTDIS        BIT(10)
 145
 146 /* Host configuration bits for SMBHSTCFG */
 147 #define SMBHSTCFG_HST_EN        BIT(0)
 148 #define SMBHSTCFG_SMB_SMI_EN    BIT(1)
 149 #define SMBHSTCFG_I2C_EN        BIT(2)
 150 #define SMBHSTCFG_SPD_WD        BIT(4)
 151
 152 /* TCO configuration bits for TCOCTL */
 153 #define TCOCTL_EN               BIT(8)
 154
 155 /* Auxiliary status register bits, ICH4+ only */
 156 #define SMBAUXSTS_CRCE          BIT(0)
 157 #define SMBAUXSTS_STCO          BIT(1)
 158
 159 /* Auxiliary control register bits, ICH4+ only */
 160 #define SMBAUXCTL_CRC           BIT(0)
 161 #define SMBAUXCTL_E32B          BIT(1)
 162
 163 /* Other settings */
 164 #define MAX_RETRIES             400
 165
 166 /* I801 command constants */
 167 #define I801_QUICK              0x00
 168 #define I801_BYTE               0x04
 169 #define I801_BYTE_DATA          0x08
 170 #define I801_WORD_DATA          0x0C
 171 #define I801_PROC_CALL          0x10    /* unimplemented */
 172 #define I801_BLOCK_DATA         0x14
 173 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 174 #define I801_BLOCK_PROC_CALL    0x1C
 175
 176 /* I801 Host Control register bits */
 177 #define SMBHSTCNT_INTREN        BIT(0)
 178 #define SMBHSTCNT_KILL          BIT(1)
 179 #define SMBHSTCNT_LAST_BYTE     BIT(5)
 180 #define SMBHSTCNT_START         BIT(6)
 181 #define SMBHSTCNT_PEC_EN        BIT(7)  /* ICH3 and later */
 182
 183 /* I801 Hosts Status register bits */
 184 #define SMBHSTSTS_BYTE_DONE     BIT(7)
 185 #define SMBHSTSTS_INUSE_STS     BIT(6)
 186 #define SMBHSTSTS_SMBALERT_STS  BIT(5)
 187 #define SMBHSTSTS_FAILED        BIT(4)
 188 #define SMBHSTSTS_BUS_ERR       BIT(3)
 189 #define SMBHSTSTS_DEV_ERR       BIT(2)
 190 #define SMBHSTSTS_INTR          BIT(1)
 191 #define SMBHSTSTS_HOST_BUSY     BIT(0)
 192
 193 /* Host Notify Status register bits */
 194 #define SMBSLVSTS_HST_NTFY_STS  BIT(0)
 195
 196 /* Host Notify Command register bits */
 197 #define SMBSLVCMD_HST_NTFY_INTREN       BIT(0)
 198
 199 #define STATUS_ERROR_FLAGS      (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
 200                                  SMBHSTSTS_DEV_ERR)
 201
 202 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
 203                                  STATUS_ERROR_FLAGS)
 204
 205 /* Older devices have their ID defined in <linux/pci_ids.h> */
 206 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS             0x02a3
 207 #define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS           0x06a3
 208 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS              0x0f12
 209 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS                   0x18df
 210 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS                   0x19df
 211 #define PCI_DEVICE_ID_INTEL_EBG_SMBUS                   0x1bc9
 212 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS           0x1c22
 213 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS              0x1d22
 214 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
 215 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0         0x1d70
 216 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1         0x1d71
 217 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2         0x1d72
 218 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS          0x1e22
 219 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS                0x1f3c
 220 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS              0x2292
 221 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS              0x2330
 222 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS           0x23b0
 223 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS            0x31d4
 224 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS            0x34a3
 225 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS         0x3b30
 226 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS          0x4b23
 227 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS           0x4da3
 228 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS               0x5ad4
 229 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS             0x8c22
 230 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS          0x8ca2
 231 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS             0x8d22
 232 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0         0x8d7d
 233 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1         0x8d7e
 234 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2         0x8d7f
 235 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS          0x9c22
 236 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS       0x9ca2
 237 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS       0x9d23
 238 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS         0x9da3
 239 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS          0xa0a3
 240 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS        0xa123
 241 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS             0xa1a3
 242 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS        0xa223
 243 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS        0xa2a3
 244 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS          0xa323
 245 #define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS           0xa3a3
 246
 247 struct i801_mux_config {
 248         char *gpio_chip;
 249         unsigned values[3];
 250         int n_values;
 251         unsigned classes[3];
 252         unsigned gpios[2];              /* Relative to gpio_chip->base */
 253         int n_gpios;
 254 };
 255
 256 struct i801_priv {
 257         struct i2c_adapter adapter;
 258         unsigned long smba;
 259         unsigned char original_hstcfg;
 260         unsigned char original_slvcmd;
 261         struct pci_dev *pci_dev;
 262         unsigned int features;
 263
 264         /* isr processing */
 265         wait_queue_head_t waitq;
 266         u8 status;
 267
 268         /* Command state used by isr for byte-by-byte block transactions */
 269         u8 cmd;
 270         bool is_read;
 271         int count;
 272         int len;
 273         u8 *data;
 274
 275 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
 276         const struct i801_mux_config *mux_drvdata;
 277         struct platform_device *mux_pdev;
 278         struct gpiod_lookup_table *lookup;
 279 #endif
 280         struct platform_device *tco_pdev;
 281
 282         /*
 283          * If set to true the host controller registers are reserved for
 284          * ACPI AML use. Protected by acpi_lock.
 285          */
 286         bool acpi_reserved;
 287         struct mutex acpi_lock;
 288 };
 289
 290 #define FEATURE_SMBUS_PEC       BIT(0)
 291 #define FEATURE_BLOCK_BUFFER    BIT(1)
 292 #define FEATURE_BLOCK_PROC      BIT(2)
 293 #define FEATURE_I2C_BLOCK_READ  BIT(3)
 294 #define FEATURE_IRQ             BIT(4)
 295 #define FEATURE_HOST_NOTIFY     BIT(5)
 296 /* Not really a feature, but it's convenient to handle it as such */
 297 #define FEATURE_IDF             BIT(15)
 298 #define FEATURE_TCO_SPT         BIT(16)
 299 #define FEATURE_TCO_CNL         BIT(17)
 300
 301 static const char *i801_feature_names[] = {
 302         "SMBus PEC",
 303         "Block buffer",
 304         "Block process call",
 305         "I2C block read",
 306         "Interrupt",
 307         "SMBus Host Notify",
 308 };
 309
 310 static unsigned int disable_features;
 311 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 312 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
 313         "\t\t  0x01  disable SMBus PEC\n"
 314         "\t\t  0x02  disable the block buffer\n"
 315         "\t\t  0x08  disable the I2C block read functionality\n"
 316         "\t\t  0x10  don't use interrupts\n"
 317         "\t\t  0x20  disable SMBus Host Notify ");
 318
 319 /* Make sure the SMBus host is ready to start transmitting.
 320    Return 0 if it is, -EBUSY if it is not. */
 321 static int i801_check_pre(struct i801_priv *priv)
 322 {
 323         int status;
 324
 325         status = inb_p(SMBHSTSTS(priv));
 326         if (status & SMBHSTSTS_HOST_BUSY) {
 327                 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
 328                 return -EBUSY;
 329         }
 330
 331         status &= STATUS_FLAGS;
 332         if (status) {
 333                 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
 334                         status);
 335                 outb_p(status, SMBHSTSTS(priv));
 336                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 337                 if (status) {
 338                         dev_err(&priv->pci_dev->dev,
 339                                 "Failed clearing status flags (%02x)\n",
 340                                 status);
 341                         return -EBUSY;
 342                 }
 343         }
 344
 345         /*
 346          * Clear CRC status if needed.
 347          * During normal operation, i801_check_post() takes care
 348          * of it after every operation.  We do it here only in case
 349          * the hardware was already in this state when the driver
 350          * started.
 351          */
 352         if (priv->features & FEATURE_SMBUS_PEC) {
 353                 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
 354                 if (status) {
 355                         dev_dbg(&priv->pci_dev->dev,
 356                                 "Clearing aux status flags (%02x)\n", status);
 357                         outb_p(status, SMBAUXSTS(priv));
 358                         status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
 359                         if (status) {
 360                                 dev_err(&priv->pci_dev->dev,
 361                                         "Failed clearing aux status flags (%02x)\n",
 362                                         status);
 363                                 return -EBUSY;
 364                         }
 365                 }
 366         }
 367
 368         return 0;
 369 }
 370
 371 /*
 372  * Convert the status register to an error code, and clear it.
 373  * Note that status only contains the bits we want to clear, not the
 374  * actual register value.
 375  */
 376 static int i801_check_post(struct i801_priv *priv, int status)
 377 {
 378         int result = 0;
 379
 380         /*
 381          * If the SMBus is still busy, we give up
 382          * Note: This timeout condition only happens when using polling
 383          * transactions.  For interrupt operation, NAK/timeout is indicated by
 384          * DEV_ERR.
 385          */
 386         if (unlikely(status < 0)) {
 387                 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
 388                 /* try to stop the current command */
 389                 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
 390                 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
 391                        SMBHSTCNT(priv));
 392                 usleep_range(1000, 2000);
 393                 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
 394                        SMBHSTCNT(priv));
 395
 396                 /* Check if it worked */
 397                 status = inb_p(SMBHSTSTS(priv));
 398                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 399                     !(status & SMBHSTSTS_FAILED))
 400                         dev_err(&priv->pci_dev->dev,
 401                                 "Failed terminating the transaction\n");
 402                 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
 403                 return -ETIMEDOUT;
 404         }
 405
 406         if (status & SMBHSTSTS_FAILED) {
 407                 result = -EIO;
 408                 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 409         }
 410         if (status & SMBHSTSTS_DEV_ERR) {
 411                 /*
 412                  * This may be a PEC error, check and clear it.
 413                  *
 414                  * AUXSTS is handled differently from HSTSTS.
 415                  * For HSTSTS, i801_isr() or i801_wait_intr()
 416                  * has already cleared the error bits in hardware,
 417                  * and we are passed a copy of the original value
 418                  * in "status".
 419                  * For AUXSTS, the hardware register is left
 420                  * for us to handle here.
 421                  * This is asymmetric, slightly iffy, but safe,
 422                  * since all this code is serialized and the CRCE
 423                  * bit is harmless as long as it's cleared before
 424                  * the next operation.
 425                  */
 426                 if ((priv->features & FEATURE_SMBUS_PEC) &&
 427                     (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
 428                         outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
 429                         result = -EBADMSG;
 430                         dev_dbg(&priv->pci_dev->dev, "PEC error\n");
 431                 } else {
 432                         result = -ENXIO;
 433                         dev_dbg(&priv->pci_dev->dev, "No response\n");
 434                 }
 435         }
 436         if (status & SMBHSTSTS_BUS_ERR) {
 437                 result = -EAGAIN;
 438                 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 439         }
 440
 441         /* Clear status flags except BYTE_DONE, to be cleared by caller */
 442         outb_p(status, SMBHSTSTS(priv));
 443
 444         return result;
 445 }
 446
 447 /* Wait for BUSY being cleared and either INTR or an error flag being set */
 448 static int i801_wait_intr(struct i801_priv *priv)
 449 {
 450         int timeout = 0;
 451         int status;
 452
 453         /* We will always wait for a fraction of a second! */
 454         do {
 455                 usleep_range(250, 500);
 456                 status = inb_p(SMBHSTSTS(priv));
 457         } while (((status & SMBHSTSTS_HOST_BUSY) ||
 458                   !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
 459                  (timeout++ < MAX_RETRIES));
 460
 461         if (timeout > MAX_RETRIES) {
 462                 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
 463                 return -ETIMEDOUT;
 464         }
 465         return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
 466 }
 467
 468 /* Wait for either BYTE_DONE or an error flag being set */
 469 static int i801_wait_byte_done(struct i801_priv *priv)
 470 {
 471         int timeout = 0;
 472         int status;
 473
 474         /* We will always wait for a fraction of a second! */
 475         do {
 476                 usleep_range(250, 500);
 477                 status = inb_p(SMBHSTSTS(priv));
 478         } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
 479                  (timeout++ < MAX_RETRIES));
 480
 481         if (timeout > MAX_RETRIES) {
 482                 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
 483                 return -ETIMEDOUT;
 484         }
 485         return status & STATUS_ERROR_FLAGS;
 486 }
 487
 488 static int i801_transaction(struct i801_priv *priv, int xact)
 489 {
 490         int status;
 491         int result;
 492         const struct i2c_adapter *adap = &priv->adapter;
 493
 494         result = i801_check_pre(priv);
 495         if (result < 0)
 496                 return result;
 497
 498         if (priv->features & FEATURE_IRQ) {
 499                 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
 500                        SMBHSTCNT(priv));
 501                 result = wait_event_timeout(priv->waitq,
 502                                             (status = priv->status),
 503                                             adap->timeout);
 504                 if (!result) {
 505                         status = -ETIMEDOUT;
 506                         dev_warn(&priv->pci_dev->dev,
 507                                  "Timeout waiting for interrupt!\n");
 508                 }
 509                 priv->status = 0;
 510                 return i801_check_post(priv, status);
 511         }
 512
 513         /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 514          * SMBSCMD are passed in xact */
 515         outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
 516
 517         status = i801_wait_intr(priv);
 518         return i801_check_post(priv, status);
 519 }
 520
 521 static int i801_block_transaction_by_block(struct i801_priv *priv,
 522                                            union i2c_smbus_data *data,
 523                                            char read_write, int command,
 524                                            int hwpec)
 525 {
 526         int i, len;
 527         int status;
 528         int xact = hwpec ? SMBHSTCNT_PEC_EN : 0;
 529
 530         switch (command) {
 531         case I2C_SMBUS_BLOCK_PROC_CALL:
 532                 xact |= I801_BLOCK_PROC_CALL;
 533                 break;
 534         case I2C_SMBUS_BLOCK_DATA:
 535                 xact |= I801_BLOCK_DATA;
 536                 break;
 537         default:
 538                 return -EOPNOTSUPP;
 539         }
 540
 541         inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 542
 543         /* Use 32-byte buffer to process this transaction */
 544         if (read_write == I2C_SMBUS_WRITE) {
 545                 len = data->block[0];
 546                 outb_p(len, SMBHSTDAT0(priv));
 547                 for (i = 0; i < len; i++)
 548                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 549         }
 550
 551         status = i801_transaction(priv, xact);
 552         if (status)
 553                 return status;
 554
 555         if (read_write == I2C_SMBUS_READ ||
 556             command == I2C_SMBUS_BLOCK_PROC_CALL) {
 557                 len = inb_p(SMBHSTDAT0(priv));
 558                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 559                         return -EPROTO;
 560
 561                 data->block[0] = len;
 562                 for (i = 0; i < len; i++)
 563                         data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 564         }
 565         return 0;
 566 }
 567
 568 static void i801_isr_byte_done(struct i801_priv *priv)
 569 {
 570         if (priv->is_read) {
 571                 /* For SMBus block reads, length is received with first byte */
 572                 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
 573                     (priv->count == 0)) {
 574                         priv->len = inb_p(SMBHSTDAT0(priv));
 575                         if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
 576                                 dev_err(&priv->pci_dev->dev,
 577                                         "Illegal SMBus block read size %d\n",
 578                                         priv->len);
 579                                 /* FIXME: Recover */
 580                                 priv->len = I2C_SMBUS_BLOCK_MAX;
 581                         } else {
 582                                 dev_dbg(&priv->pci_dev->dev,
 583                                         "SMBus block read size is %d\n",
 584                                         priv->len);
 585                         }
 586                         priv->data[-1] = priv->len;
 587                 }
 588
 589                 /* Read next byte */
 590                 if (priv->count < priv->len)
 591                         priv->data[priv->count++] = inb(SMBBLKDAT(priv));
 592                 else
 593                         dev_dbg(&priv->pci_dev->dev,
 594                                 "Discarding extra byte on block read\n");
 595
 596                 /* Set LAST_BYTE for last byte of read transaction */
 597                 if (priv->count == priv->len - 1)
 598                         outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
 599                                SMBHSTCNT(priv));
 600         } else if (priv->count < priv->len - 1) {
 601                 /* Write next byte, except for IRQ after last byte */
 602                 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
 603         }
 604
 605         /* Clear BYTE_DONE to continue with next byte */
 606         outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 607 }
 608
 609 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
 610 {
 611         unsigned short addr;
 612
 613         addr = inb_p(SMBNTFDADD(priv)) >> 1;
 614
 615         /*
 616          * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
 617          * always returns 0. Our current implementation doesn't provide
 618          * data, so we just ignore it.
 619          */
 620         i2c_handle_smbus_host_notify(&priv->adapter, addr);
 621
 622         /* clear Host Notify bit and return */
 623         outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
 624         return IRQ_HANDLED;
 625 }
 626
 627 /*
 628  * There are three kinds of interrupts:
 629  *
 630  * 1) i801 signals transaction completion with one of these interrupts:
 631  *      INTR - Success
 632  *      DEV_ERR - Invalid command, NAK or communication timeout
 633  *      BUS_ERR - SMI# transaction collision
 634  *      FAILED - transaction was canceled due to a KILL request
 635  *    When any of these occur, update ->status and wake up the waitq.
 636  *    ->status must be cleared before kicking off the next transaction.
 637  *
 638  * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
 639  *    occurs for each byte of a byte-by-byte to prepare the next byte.
 640  *
 641  * 3) Host Notify interrupts
 642  */
 643 static irqreturn_t i801_isr(int irq, void *dev_id)
 644 {
 645         struct i801_priv *priv = dev_id;
 646         u16 pcists;
 647         u8 status;
 648
 649         /* Confirm this is our interrupt */
 650         pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
 651         if (!(pcists & SMBPCISTS_INTS))
 652                 return IRQ_NONE;
 653
 654         if (priv->features & FEATURE_HOST_NOTIFY) {
 655                 status = inb_p(SMBSLVSTS(priv));
 656                 if (status & SMBSLVSTS_HST_NTFY_STS)
 657                         return i801_host_notify_isr(priv);
 658         }
 659
 660         status = inb_p(SMBHSTSTS(priv));
 661         if (status & SMBHSTSTS_BYTE_DONE)
 662                 i801_isr_byte_done(priv);
 663
 664         /*
 665          * Clear irq sources and report transaction result.
 666          * ->status must be cleared before the next transaction is started.
 667          */
 668         status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
 669         if (status) {
 670                 outb_p(status, SMBHSTSTS(priv));
 671                 priv->status = status;
 672                 wake_up(&priv->waitq);
 673         }
 674
 675         return IRQ_HANDLED;
 676 }
 677
 678 /*
 679  * For "byte-by-byte" block transactions:
 680  *   I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
 681  *   I2C read uses cmd=I801_I2C_BLOCK_DATA
 682  */
 683 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 684                                                union i2c_smbus_data *data,
 685                                                char read_write, int command,
 686                                                int hwpec)
 687 {
 688         int i, len;
 689         int smbcmd;
 690         int status;
 691         int result;
 692         const struct i2c_adapter *adap = &priv->adapter;
 693
 694         if (command == I2C_SMBUS_BLOCK_PROC_CALL)
 695                 return -EOPNOTSUPP;
 696
 697         result = i801_check_pre(priv);
 698         if (result < 0)
 699                 return result;
 700
 701         len = data->block[0];
 702
 703         if (read_write == I2C_SMBUS_WRITE) {
 704                 outb_p(len, SMBHSTDAT0(priv));
 705                 outb_p(data->block[1], SMBBLKDAT(priv));
 706         }
 707
 708         if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
 709             read_write == I2C_SMBUS_READ)
 710                 smbcmd = I801_I2C_BLOCK_DATA;
 711         else
 712                 smbcmd = I801_BLOCK_DATA;
 713
 714         if (priv->features & FEATURE_IRQ) {
 715                 priv->is_read = (read_write == I2C_SMBUS_READ);
 716                 if (len == 1 && priv->is_read)
 717                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 718                 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
 719                 priv->len = len;
 720                 priv->count = 0;
 721                 priv->data = &data->block[1];
 722
 723                 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
 724                 result = wait_event_timeout(priv->waitq,
 725                                             (status = priv->status),
 726                                             adap->timeout);
 727                 if (!result) {
 728                         status = -ETIMEDOUT;
 729                         dev_warn(&priv->pci_dev->dev,
 730                                  "Timeout waiting for interrupt!\n");
 731                 }
 732                 priv->status = 0;
 733                 return i801_check_post(priv, status);
 734         }
 735
 736         for (i = 1; i <= len; i++) {
 737                 if (i == len && read_write == I2C_SMBUS_READ)
 738                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 739                 outb_p(smbcmd, SMBHSTCNT(priv));
 740
 741                 if (i == 1)
 742                         outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
 743                                SMBHSTCNT(priv));
 744
 745                 status = i801_wait_byte_done(priv);
 746                 if (status)
 747                         goto exit;
 748
 749                 if (i == 1 && read_write == I2C_SMBUS_READ
 750                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 751                         len = inb_p(SMBHSTDAT0(priv));
 752                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 753                                 dev_err(&priv->pci_dev->dev,
 754                                         "Illegal SMBus block read size %d\n",
 755                                         len);
 756                                 /* Recover */
 757                                 while (inb_p(SMBHSTSTS(priv)) &
 758                                        SMBHSTSTS_HOST_BUSY)
 759                                         outb_p(SMBHSTSTS_BYTE_DONE,
 760                                                SMBHSTSTS(priv));
 761                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 762                                 return -EPROTO;
 763                         }
 764                         data->block[0] = len;
 765                 }
 766
 767                 /* Retrieve/store value in SMBBLKDAT */
 768                 if (read_write == I2C_SMBUS_READ)
 769                         data->block[i] = inb_p(SMBBLKDAT(priv));
 770                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 771                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 772
 773                 /* signals SMBBLKDAT ready */
 774                 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 775         }
 776
 777         status = i801_wait_intr(priv);
 778 exit:
 779         return i801_check_post(priv, status);
 780 }
 781
 782 static int i801_set_block_buffer_mode(struct i801_priv *priv)
 783 {
 784         outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 785         if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
 786                 return -EIO;
 787         return 0;
 788 }
 789
 790 /* Block transaction function */
 791 static int i801_block_transaction(struct i801_priv *priv,
 792                                   union i2c_smbus_data *data, char read_write,
 793                                   int command, int hwpec)
 794 {
 795         int result = 0;
 796         unsigned char hostc;
 797
 798         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 799                 if (read_write == I2C_SMBUS_WRITE) {
 800                         /* set I2C_EN bit in configuration register */
 801                         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 802                         pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
 803                                               hostc | SMBHSTCFG_I2C_EN);
 804                 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 805                         dev_err(&priv->pci_dev->dev,
 806                                 "I2C block read is unsupported!\n");
 807                         return -EOPNOTSUPP;
 808                 }
 809         }
 810
 811         if (read_write == I2C_SMBUS_WRITE
 812          || command == I2C_SMBUS_I2C_BLOCK_DATA) {
 813                 if (data->block[0] < 1)
 814                         data->block[0] = 1;
 815                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
 816                         data->block[0] = I2C_SMBUS_BLOCK_MAX;
 817         } else {
 818                 data->block[0] = 32;    /* max for SMBus block reads */
 819         }
 820
 821         /* Experience has shown that the block buffer can only be used for
 822            SMBus (not I2C) block transactions, even though the datasheet
 823            doesn't mention this limitation. */
 824         if ((priv->features & FEATURE_BLOCK_BUFFER)
 825          && command != I2C_SMBUS_I2C_BLOCK_DATA
 826          && i801_set_block_buffer_mode(priv) == 0)
 827                 result = i801_block_transaction_by_block(priv, data,
 828                                                          read_write,
 829                                                          command, hwpec);
 830         else
 831                 result = i801_block_transaction_byte_by_byte(priv, data,
 832                                                              read_write,
 833                                                              command, hwpec);
 834
 835         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 836          && read_write == I2C_SMBUS_WRITE) {
 837                 /* restore saved configuration register value */
 838                 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 839         }
 840         return result;
 841 }
 842
 843 /* Return negative errno on error. */
 844 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 845                        unsigned short flags, char read_write, u8 command,
 846                        int size, union i2c_smbus_data *data)
 847 {
 848         int hwpec;
 849         int block = 0;
 850         int ret = 0, xact = 0;
 851         struct i801_priv *priv = i2c_get_adapdata(adap);
 852
 853         mutex_lock(&priv->acpi_lock);
 854         if (priv->acpi_reserved) {
 855                 mutex_unlock(&priv->acpi_lock);
 856                 return -EBUSY;
 857         }
 858
 859         pm_runtime_get_sync(&priv->pci_dev->dev);
 860
 861         hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 862                 && size != I2C_SMBUS_QUICK
 863                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 864
 865         switch (size) {
 866         case I2C_SMBUS_QUICK:
 867                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 868                        SMBHSTADD(priv));
 869                 xact = I801_QUICK;
 870                 break;
 871         case I2C_SMBUS_BYTE:
 872                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 873                        SMBHSTADD(priv));
 874                 if (read_write == I2C_SMBUS_WRITE)
 875                         outb_p(command, SMBHSTCMD(priv));
 876                 xact = I801_BYTE;
 877                 break;
 878         case I2C_SMBUS_BYTE_DATA:
 879                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 880                        SMBHSTADD(priv));
 881                 outb_p(command, SMBHSTCMD(priv));
 882                 if (read_write == I2C_SMBUS_WRITE)
 883                         outb_p(data->byte, SMBHSTDAT0(priv));
 884                 xact = I801_BYTE_DATA;
 885                 break;
 886         case I2C_SMBUS_WORD_DATA:
 887                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 888                        SMBHSTADD(priv));
 889                 outb_p(command, SMBHSTCMD(priv));
 890                 if (read_write == I2C_SMBUS_WRITE) {
 891                         outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 892                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 893                 }
 894                 xact = I801_WORD_DATA;
 895                 break;
 896         case I2C_SMBUS_BLOCK_DATA:
 897                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 898                        SMBHSTADD(priv));
 899                 outb_p(command, SMBHSTCMD(priv));
 900                 block = 1;
 901                 break;
 902         case I2C_SMBUS_I2C_BLOCK_DATA:
 903                 /*
 904                  * NB: page 240 of ICH5 datasheet shows that the R/#W
 905                  * bit should be cleared here, even when reading.
 906                  * However if SPD Write Disable is set (Lynx Point and later),
 907                  * the read will fail if we don't set the R/#W bit.
 908                  */
 909                 outb_p(((addr & 0x7f) << 1) |
 910                        ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ?
 911                         (read_write & 0x01) : 0),
 912                        SMBHSTADD(priv));
 913                 if (read_write == I2C_SMBUS_READ) {
 914                         /* NB: page 240 of ICH5 datasheet also shows
 915                          * that DATA1 is the cmd field when reading */
 916                         outb_p(command, SMBHSTDAT1(priv));
 917                 } else
 918                         outb_p(command, SMBHSTCMD(priv));
 919                 block = 1;
 920                 break;
 921         case I2C_SMBUS_BLOCK_PROC_CALL:
 922                 /*
 923                  * Bit 0 of the slave address register always indicate a write
 924                  * command.
 925                  */
 926                 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
 927                 outb_p(command, SMBHSTCMD(priv));
 928                 block = 1;
 929                 break;
 930         default:
 931                 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
 932                         size);
 933                 ret = -EOPNOTSUPP;
 934                 goto out;
 935         }
 936
 937         if (hwpec)      /* enable/disable hardware PEC */
 938                 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 939         else
 940                 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 941                        SMBAUXCTL(priv));
 942
 943         if (block)
 944                 ret = i801_block_transaction(priv, data, read_write, size,
 945                                              hwpec);
 946         else
 947                 ret = i801_transaction(priv, xact);
 948
 949         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 950            time, so we forcibly disable it after every transaction. Turn off
 951            E32B for the same reason. */
 952         if (hwpec || block)
 953                 outb_p(inb_p(SMBAUXCTL(priv)) &
 954                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 955
 956         if (block)
 957                 goto out;
 958         if (ret)
 959                 goto out;
 960         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 961                 goto out;
 962
 963         switch (xact & 0x7f) {
 964         case I801_BYTE: /* Result put in SMBHSTDAT0 */
 965         case I801_BYTE_DATA:
 966                 data->byte = inb_p(SMBHSTDAT0(priv));
 967                 break;
 968         case I801_WORD_DATA:
 969                 data->word = inb_p(SMBHSTDAT0(priv)) +
 970                              (inb_p(SMBHSTDAT1(priv)) << 8);
 971                 break;
 972         }
 973
 974 out:
 975         pm_runtime_mark_last_busy(&priv->pci_dev->dev);
 976         pm_runtime_put_autosuspend(&priv->pci_dev->dev);
 977         mutex_unlock(&priv->acpi_lock);
 978         return ret;
 979 }
 980
 981
 982 static u32 i801_func(struct i2c_adapter *adapter)
 983 {
 984         struct i801_priv *priv = i2c_get_adapdata(adapter);
 985
 986         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 987                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 988                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 989                ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 990                ((priv->features & FEATURE_BLOCK_PROC) ?
 991                 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) |
 992                ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 993                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
 994                ((priv->features & FEATURE_HOST_NOTIFY) ?
 995                 I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
 996 }
 997
 998 static void i801_enable_host_notify(struct i2c_adapter *adapter)
 999 {
1000         struct i801_priv *priv = i2c_get_adapdata(adapter);
1001
1002         if (!(priv->features & FEATURE_HOST_NOTIFY))
1003                 return;
1004
1005         if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd))
1006                 outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd,
1007                        SMBSLVCMD(priv));
1008
1009         /* clear Host Notify bit to allow a new notification */
1010         outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
1011 }
1012
1013 static void i801_disable_host_notify(struct i801_priv *priv)
1014 {
1015         if (!(priv->features & FEATURE_HOST_NOTIFY))
1016                 return;
1017
1018         outb_p(priv->original_slvcmd, SMBSLVCMD(priv));
1019 }
1020
1021 static const struct i2c_algorithm smbus_algorithm = {
1022         .smbus_xfer     = i801_access,
1023         .functionality  = i801_func,
1024 };
1025
1026 static const struct pci_device_id i801_ids[] = {
1027         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
1028         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
1029         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
1030         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
1031         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
1032         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
1033         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
1034         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
1035         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
1036         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
1037         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
1038         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
1039         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
1040         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
1041         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
1042         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
1043         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
1044         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
1045         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
1046         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
1047         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
1048         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
1049         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
1050         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
1051         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
1052         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
1053         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
1054         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
1055         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
1056         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
1057         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
1058         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) },
1059         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
1060         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
1061         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
1062         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
1063         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
1064         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
1065         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMBUS) },
1066         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
1067         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EBG_SMBUS) },
1068         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
1069         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) },
1070         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) },
1071         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) },
1072         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS) },
1073         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS) },
1074         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS) },
1075         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS) },
1076         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS) },
1077         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS) },
1078         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS) },
1079         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS) },
1080         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS) },
1081         { 0, }
1082 };
1083
1084 MODULE_DEVICE_TABLE(pci, i801_ids);
1085
1086 #if defined CONFIG_X86 && defined CONFIG_DMI
1087 static unsigned char apanel_addr;
1088
1089 /* Scan the system ROM for the signature "FJKEYINF" */
1090 static __init const void __iomem *bios_signature(const void __iomem *bios)
1091 {
1092         ssize_t offset;
1093         const unsigned char signature[] = "FJKEYINF";
1094
1095         for (offset = 0; offset < 0x10000; offset += 0x10) {
1096                 if (check_signature(bios + offset, signature,
1097                                     sizeof(signature)-1))
1098                         return bios + offset;
1099         }
1100         return NULL;
1101 }
1102
1103 static void __init input_apanel_init(void)
1104 {
1105         void __iomem *bios;
1106         const void __iomem *p;
1107
1108         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1109         p = bios_signature(bios);
1110         if (p) {
1111                 /* just use the first address */
1112                 apanel_addr = readb(p + 8 + 3) >> 1;
1113         }
1114         iounmap(bios);
1115 }
1116
1117 struct dmi_onboard_device_info {
1118         const char *name;
1119         u8 type;
1120         unsigned short i2c_addr;
1121         const char *i2c_type;
1122 };
1123
1124 static const struct dmi_onboard_device_info dmi_devices[] = {
1125         { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1126         { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1127         { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1128 };
1129
1130 static void dmi_check_onboard_device(u8 type, const char *name,
1131                                      struct i2c_adapter *adap)
1132 {
1133         int i;
1134         struct i2c_board_info info;
1135
1136         for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1137                 /* & ~0x80, ignore enabled/disabled bit */
1138                 if ((type & ~0x80) != dmi_devices[i].type)
1139                         continue;
1140                 if (strcasecmp(name, dmi_devices[i].name))
1141                         continue;
1142
1143                 memset(&info, 0, sizeof(struct i2c_board_info));
1144                 info.addr = dmi_devices[i].i2c_addr;
1145                 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1146                 i2c_new_client_device(adap, &info);
1147                 break;
1148         }
1149 }
1150
1151 /* We use our own function to check for onboard devices instead of
1152    dmi_find_device() as some buggy BIOS's have the devices we are interested
1153    in marked as disabled */
1154 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1155 {
1156         int i, count;
1157
1158         if (dm->type != 10)
1159                 return;
1160
1161         count = (dm->length - sizeof(struct dmi_header)) / 2;
1162         for (i = 0; i < count; i++) {
1163                 const u8 *d = (char *)(dm + 1) + (i * 2);
1164                 const char *name = ((char *) dm) + dm->length;
1165                 u8 type = d[0];
1166                 u8 s = d[1];
1167
1168                 if (!s)
1169                         continue;
1170                 s--;
1171                 while (s > 0 && name[0]) {
1172                         name += strlen(name) + 1;
1173                         s--;
1174                 }
1175                 if (name[0] == 0) /* Bogus string reference */
1176                         continue;
1177
1178                 dmi_check_onboard_device(type, name, adap);
1179         }
1180 }
1181
1182 /* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */
1183 static const char *const acpi_smo8800_ids[] = {
1184         "SMO8800",
1185         "SMO8801",
1186         "SMO8810",
1187         "SMO8811",
1188         "SMO8820",
1189         "SMO8821",
1190         "SMO8830",
1191         "SMO8831",
1192 };
1193
1194 static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle,
1195                                              u32 nesting_level,
1196                                              void *context,
1197                                              void **return_value)
1198 {
1199         struct acpi_device_info *info;
1200         acpi_status status;
1201         char *hid;
1202         int i;
1203
1204         status = acpi_get_object_info(obj_handle, &info);
1205         if (ACPI_FAILURE(status))
1206                 return AE_OK;
1207
1208         if (!(info->valid & ACPI_VALID_HID))
1209                 goto smo88xx_not_found;
1210
1211         hid = info->hardware_id.string;
1212         if (!hid)
1213                 goto smo88xx_not_found;
1214
1215         i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid);
1216         if (i < 0)
1217                 goto smo88xx_not_found;
1218
1219         kfree(info);
1220
1221         *((bool *)return_value) = true;
1222         return AE_CTRL_TERMINATE;
1223
1224 smo88xx_not_found:
1225         kfree(info);
1226         return AE_OK;
1227 }
1228
1229 static bool is_dell_system_with_lis3lv02d(void)
1230 {
1231         bool found;
1232         const char *vendor;
1233
1234         vendor = dmi_get_system_info(DMI_SYS_VENDOR);
1235         if (!vendor || strcmp(vendor, "Dell Inc."))
1236                 return false;
1237
1238         /*
1239          * Check that ACPI device SMO88xx is present and is functioning.
1240          * Function acpi_get_devices() already filters all ACPI devices
1241          * which are not present or are not functioning.
1242          * ACPI device SMO88xx represents our ST microelectronics lis3lv02d
1243          * accelerometer but unfortunately ACPI does not provide any other
1244          * information (like I2C address).
1245          */
1246         found = false;
1247         acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL,
1248                          (void **)&found);
1249
1250         return found;
1251 }
1252
1253 /*
1254  * Accelerometer's I2C address is not specified in DMI nor ACPI,
1255  * so it is needed to define mapping table based on DMI product names.
1256  */
1257 static const struct {
1258         const char *dmi_product_name;
1259         unsigned short i2c_addr;
1260 } dell_lis3lv02d_devices[] = {
1261         /*
1262          * Dell platform team told us that these Latitude devices have
1263          * ST microelectronics accelerometer at I2C address 0x29.
1264          */
1265         { "Latitude E5250",     0x29 },
1266         { "Latitude E5450",     0x29 },
1267         { "Latitude E5550",     0x29 },
1268         { "Latitude E6440",     0x29 },
1269         { "Latitude E6440 ATG", 0x29 },
1270         { "Latitude E6540",     0x29 },
1271         /*
1272          * Additional individual entries were added after verification.
1273          */
1274         { "Vostro V131",        0x1d },
1275 };
1276
1277 static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv)
1278 {
1279         struct i2c_board_info info;
1280         const char *dmi_product_name;
1281         int i;
1282
1283         dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
1284         for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) {
1285                 if (strcmp(dmi_product_name,
1286                            dell_lis3lv02d_devices[i].dmi_product_name) == 0)
1287                         break;
1288         }
1289
1290         if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) {
1291                 dev_warn(&priv->pci_dev->dev,
1292                          "Accelerometer lis3lv02d is present on SMBus but its"
1293                          " address is unknown, skipping registration\n");
1294                 return;
1295         }
1296
1297         memset(&info, 0, sizeof(struct i2c_board_info));
1298         info.addr = dell_lis3lv02d_devices[i].i2c_addr;
1299         strlcpy(info.type, "lis3lv02d", I2C_NAME_SIZE);
1300         i2c_new_client_device(&priv->adapter, &info);
1301 }
1302
1303 /* Register optional slaves */
1304 static void i801_probe_optional_slaves(struct i801_priv *priv)
1305 {
1306         /* Only register slaves on main SMBus channel */
1307         if (priv->features & FEATURE_IDF)
1308                 return;
1309
1310         if (apanel_addr) {
1311                 struct i2c_board_info info;
1312
1313                 memset(&info, 0, sizeof(struct i2c_board_info));
1314                 info.addr = apanel_addr;
1315                 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
1316                 i2c_new_client_device(&priv->adapter, &info);
1317         }
1318
1319         if (dmi_name_in_vendors("FUJITSU"))
1320                 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1321
1322         if (is_dell_system_with_lis3lv02d())
1323                 register_dell_lis3lv02d_i2c_device(priv);
1324
1325         /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */
1326 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO)
1327         if (!priv->mux_drvdata)
1328 #endif
1329                 i2c_register_spd(&priv->adapter);
1330 }
1331 #else
1332 static void __init input_apanel_init(void) {}
1333 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1334 #endif  /* CONFIG_X86 && CONFIG_DMI */
1335
1336 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
1337 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1338         .gpio_chip = "gpio_ich",
1339         .values = { 0x02, 0x03 },
1340         .n_values = 2,
1341         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1342         .gpios = { 52, 53 },
1343         .n_gpios = 2,
1344 };
1345
1346 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1347         .gpio_chip = "gpio_ich",
1348         .values = { 0x02, 0x03, 0x01 },
1349         .n_values = 3,
1350         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1351         .gpios = { 52, 53 },
1352         .n_gpios = 2,
1353 };
1354
1355 static const struct dmi_system_id mux_dmi_table[] = {
1356         {
1357                 .matches = {
1358                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1359                         DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1360                 },
1361                 .driver_data = &i801_mux_config_asus_z8_d12,
1362         },
1363         {
1364                 .matches = {
1365                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1366                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1367                 },
1368                 .driver_data = &i801_mux_config_asus_z8_d12,
1369         },
1370         {
1371                 .matches = {
1372                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1373                         DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1374                 },
1375                 .driver_data = &i801_mux_config_asus_z8_d12,
1376         },
1377         {
1378                 .matches = {
1379                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1380                         DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1381                 },
1382                 .driver_data = &i801_mux_config_asus_z8_d12,
1383         },
1384         {
1385                 .matches = {
1386                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1387                         DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1388                 },
1389                 .driver_data = &i801_mux_config_asus_z8_d12,
1390         },
1391         {
1392                 .matches = {
1393                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1394                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1395                 },
1396                 .driver_data = &i801_mux_config_asus_z8_d12,
1397         },
1398         {
1399                 .matches = {
1400                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1401                         DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1402                 },
1403                 .driver_data = &i801_mux_config_asus_z8_d18,
1404         },
1405         {
1406                 .matches = {
1407                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1408                         DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1409                 },
1410                 .driver_data = &i801_mux_config_asus_z8_d18,
1411         },
1412         {
1413                 .matches = {
1414                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1415                         DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1416                 },
1417                 .driver_data = &i801_mux_config_asus_z8_d12,
1418         },
1419         { }
1420 };
1421
1422 /* Setup multiplexing if needed */
1423 static int i801_add_mux(struct i801_priv *priv)
1424 {
1425         struct device *dev = &priv->adapter.dev;
1426         const struct i801_mux_config *mux_config;
1427         struct i2c_mux_gpio_platform_data gpio_data;
1428         struct gpiod_lookup_table *lookup;
1429         int err, i;
1430
1431         if (!priv->mux_drvdata)
1432                 return 0;
1433         mux_config = priv->mux_drvdata;
1434
1435         /* Prepare the platform data */
1436         memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1437         gpio_data.parent = priv->adapter.nr;
1438         gpio_data.values = mux_config->values;
1439         gpio_data.n_values = mux_config->n_values;
1440         gpio_data.classes = mux_config->classes;
1441         gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1442
1443         /* Register GPIO descriptor lookup table */
1444         lookup = devm_kzalloc(dev,
1445                               struct_size(lookup, table, mux_config->n_gpios),
1446                               GFP_KERNEL);
1447         if (!lookup)
1448                 return -ENOMEM;
1449         lookup->dev_id = "i2c-mux-gpio";
1450         for (i = 0; i < mux_config->n_gpios; i++) {
1451                 lookup->table[i] = (struct gpiod_lookup)
1452                         GPIO_LOOKUP(mux_config->gpio_chip,
1453                                     mux_config->gpios[i], "mux", 0);
1454         }
1455         gpiod_add_lookup_table(lookup);
1456         priv->lookup = lookup;
1457
1458         /*
1459          * Register the mux device, we use PLATFORM_DEVID_NONE here
1460          * because since we are referring to the GPIO chip by name we are
1461          * anyways in deep trouble if there is more than one of these
1462          * devices, and there should likely only be one platform controller
1463          * hub.
1464          */
1465         priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1466                                 PLATFORM_DEVID_NONE, &gpio_data,
1467                                 sizeof(struct i2c_mux_gpio_platform_data));
1468         if (IS_ERR(priv->mux_pdev)) {
1469                 err = PTR_ERR(priv->mux_pdev);
1470                 gpiod_remove_lookup_table(lookup);
1471                 priv->mux_pdev = NULL;
1472                 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1473                 return err;
1474         }
1475
1476         return 0;
1477 }
1478
1479 static void i801_del_mux(struct i801_priv *priv)
1480 {
1481         if (priv->mux_pdev)
1482                 platform_device_unregister(priv->mux_pdev);
1483         if (priv->lookup)
1484                 gpiod_remove_lookup_table(priv->lookup);
1485 }
1486
1487 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1488 {
1489         const struct dmi_system_id *id;
1490         const struct i801_mux_config *mux_config;
1491         unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1492         int i;
1493
1494         id = dmi_first_match(mux_dmi_table);
1495         if (id) {
1496                 /* Remove branch classes from trunk */
1497                 mux_config = id->driver_data;
1498                 for (i = 0; i < mux_config->n_values; i++)
1499                         class &= ~mux_config->classes[i];
1500
1501                 /* Remember for later */
1502                 priv->mux_drvdata = mux_config;
1503         }
1504
1505         return class;
1506 }
1507 #else
1508 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1509 static inline void i801_del_mux(struct i801_priv *priv) { }
1510
1511 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1512 {
1513         return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1514 }
1515 #endif
1516
1517 static const struct itco_wdt_platform_data spt_tco_platform_data = {
1518         .name = "Intel PCH",
1519         .version = 4,
1520 };
1521
1522 static DEFINE_SPINLOCK(p2sb_spinlock);
1523
1524 static struct platform_device *
1525 i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev,
1526                  struct resource *tco_res)
1527 {
1528         struct resource *res;
1529         unsigned int devfn;
1530         u64 base64_addr;
1531         u32 base_addr;
1532         u8 hidden;
1533
1534         /*
1535          * We must access the NO_REBOOT bit over the Primary to Sideband
1536          * bridge (P2SB). The BIOS prevents the P2SB device from being
1537          * enumerated by the PCI subsystem, so we need to unhide/hide it
1538          * to lookup the P2SB BAR.
1539          */
1540         spin_lock(&p2sb_spinlock);
1541
1542         devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1543
1544         /* Unhide the P2SB device, if it is hidden */
1545         pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden);
1546         if (hidden)
1547                 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1548
1549         pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1550         base64_addr = base_addr & 0xfffffff0;
1551
1552         pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1553         base64_addr |= (u64)base_addr << 32;
1554
1555         /* Hide the P2SB device, if it was hidden before */
1556         if (hidden)
1557                 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden);
1558         spin_unlock(&p2sb_spinlock);
1559
1560         res = &tco_res[1];
1561         if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1562                 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV;
1563         else
1564                 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1565
1566         res->end = res->start + 3;
1567         res->flags = IORESOURCE_MEM;
1568
1569         return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1570                                         tco_res, 2, &spt_tco_platform_data,
1571                                         sizeof(spt_tco_platform_data));
1572 }
1573
1574 static const struct itco_wdt_platform_data cnl_tco_platform_data = {
1575         .name = "Intel PCH",
1576         .version = 6,
1577 };
1578
1579 static struct platform_device *
1580 i801_add_tco_cnl(struct i801_priv *priv, struct pci_dev *pci_dev,
1581                  struct resource *tco_res)
1582 {
1583         return platform_device_register_resndata(&pci_dev->dev,
1584                         "iTCO_wdt", -1, tco_res, 1, &cnl_tco_platform_data,
1585                         sizeof(cnl_tco_platform_data));
1586 }
1587
1588 static void i801_add_tco(struct i801_priv *priv)
1589 {
1590         struct pci_dev *pci_dev = priv->pci_dev;
1591         struct resource tco_res[2], *res;
1592         u32 tco_base, tco_ctl;
1593
1594         /* If we have ACPI based watchdog use that instead */
1595         if (acpi_has_watchdog())
1596                 return;
1597
1598         if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL)))
1599                 return;
1600
1601         pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1602         pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1603         if (!(tco_ctl & TCOCTL_EN))
1604                 return;
1605
1606         memset(tco_res, 0, sizeof(tco_res));
1607         /*
1608          * Always populate the main iTCO IO resource here. The second entry
1609          * for NO_REBOOT MMIO is filled by the SPT specific function.
1610          */
1611         res = &tco_res[0];
1612         res->start = tco_base & ~1;
1613         res->end = res->start + 32 - 1;
1614         res->flags = IORESOURCE_IO;
1615
1616         if (priv->features & FEATURE_TCO_CNL)
1617                 priv->tco_pdev = i801_add_tco_cnl(priv, pci_dev, tco_res);
1618         else
1619                 priv->tco_pdev = i801_add_tco_spt(priv, pci_dev, tco_res);
1620
1621         if (IS_ERR(priv->tco_pdev))
1622                 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1623 }
1624
1625 #ifdef CONFIG_ACPI
1626 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv,
1627                                       acpi_physical_address address)
1628 {
1629         return address >= priv->smba &&
1630                address <= pci_resource_end(priv->pci_dev, SMBBAR);
1631 }
1632
1633 static acpi_status
1634 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1635                      u64 *value, void *handler_context, void *region_context)
1636 {
1637         struct i801_priv *priv = handler_context;
1638         struct pci_dev *pdev = priv->pci_dev;
1639         acpi_status status;
1640
1641         /*
1642          * Once BIOS AML code touches the OpRegion we warn and inhibit any
1643          * further access from the driver itself. This device is now owned
1644          * by the system firmware.
1645          */
1646         mutex_lock(&priv->acpi_lock);
1647
1648         if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) {
1649                 priv->acpi_reserved = true;
1650
1651                 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1652                 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1653
1654                 /*
1655                  * BIOS is accessing the host controller so prevent it from
1656                  * suspending automatically from now on.
1657                  */
1658                 pm_runtime_get_sync(&pdev->dev);
1659         }
1660
1661         if ((function & ACPI_IO_MASK) == ACPI_READ)
1662                 status = acpi_os_read_port(address, (u32 *)value, bits);
1663         else
1664                 status = acpi_os_write_port(address, (u32)*value, bits);
1665
1666         mutex_unlock(&priv->acpi_lock);
1667
1668         return status;
1669 }
1670
1671 static int i801_acpi_probe(struct i801_priv *priv)
1672 {
1673         struct acpi_device *adev;
1674         acpi_status status;
1675
1676         adev = ACPI_COMPANION(&priv->pci_dev->dev);
1677         if (adev) {
1678                 status = acpi_install_address_space_handler(adev->handle,
1679                                 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler,
1680                                 NULL, priv);
1681                 if (ACPI_SUCCESS(status))
1682                         return 0;
1683         }
1684
1685         return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1686 }
1687
1688 static void i801_acpi_remove(struct i801_priv *priv)
1689 {
1690         struct acpi_device *adev;
1691
1692         adev = ACPI_COMPANION(&priv->pci_dev->dev);
1693         if (!adev)
1694                 return;
1695
1696         acpi_remove_address_space_handler(adev->handle,
1697                 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1698
1699         mutex_lock(&priv->acpi_lock);
1700         if (priv->acpi_reserved)
1701                 pm_runtime_put(&priv->pci_dev->dev);
1702         mutex_unlock(&priv->acpi_lock);
1703 }
1704 #else
1705 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
1706 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1707 #endif
1708
1709 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1710 {
1711         unsigned char temp;
1712         int err, i;
1713         struct i801_priv *priv;
1714
1715         priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1716         if (!priv)
1717                 return -ENOMEM;
1718
1719         i2c_set_adapdata(&priv->adapter, priv);
1720         priv->adapter.owner = THIS_MODULE;
1721         priv->adapter.class = i801_get_adapter_class(priv);
1722         priv->adapter.algo = &smbus_algorithm;
1723         priv->adapter.dev.parent = &dev->dev;
1724         ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1725         priv->adapter.retries = 3;
1726         mutex_init(&priv->acpi_lock);
1727
1728         priv->pci_dev = dev;
1729         switch (dev->device) {
1730         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
1731         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
1732         case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS:
1733         case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS:
1734         case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
1735         case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS:
1736         case PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS:
1737                 priv->features |= FEATURE_BLOCK_PROC;
1738                 priv->features |= FEATURE_I2C_BLOCK_READ;
1739                 priv->features |= FEATURE_IRQ;
1740                 priv->features |= FEATURE_SMBUS_PEC;
1741                 priv->features |= FEATURE_BLOCK_BUFFER;
1742                 priv->features |= FEATURE_TCO_SPT;
1743                 priv->features |= FEATURE_HOST_NOTIFY;
1744                 break;
1745
1746         case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS:
1747         case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS:
1748         case PCI_DEVICE_ID_INTEL_CDF_SMBUS:
1749         case PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS:
1750         case PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS:
1751         case PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS:
1752         case PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS:
1753         case PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS:
1754         case PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS:
1755         case PCI_DEVICE_ID_INTEL_EBG_SMBUS:
1756                 priv->features |= FEATURE_BLOCK_PROC;
1757                 priv->features |= FEATURE_I2C_BLOCK_READ;
1758                 priv->features |= FEATURE_IRQ;
1759                 priv->features |= FEATURE_SMBUS_PEC;
1760                 priv->features |= FEATURE_BLOCK_BUFFER;
1761                 priv->features |= FEATURE_TCO_CNL;
1762                 priv->features |= FEATURE_HOST_NOTIFY;
1763                 break;
1764
1765         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1766         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1767         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1768         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1769         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1770         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1771                 priv->features |= FEATURE_IDF;
1772                 fallthrough;
1773         default:
1774                 priv->features |= FEATURE_BLOCK_PROC;
1775                 priv->features |= FEATURE_I2C_BLOCK_READ;
1776                 priv->features |= FEATURE_IRQ;
1777                 fallthrough;
1778         case PCI_DEVICE_ID_INTEL_82801DB_3:
1779                 priv->features |= FEATURE_SMBUS_PEC;
1780                 priv->features |= FEATURE_BLOCK_BUFFER;
1781                 fallthrough;
1782         case PCI_DEVICE_ID_INTEL_82801CA_3:
1783                 priv->features |= FEATURE_HOST_NOTIFY;
1784                 fallthrough;
1785         case PCI_DEVICE_ID_INTEL_82801BA_2:
1786         case PCI_DEVICE_ID_INTEL_82801AB_3:
1787         case PCI_DEVICE_ID_INTEL_82801AA_3:
1788                 break;
1789         }
1790
1791         /* Disable features on user request */
1792         for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1793                 if (priv->features & disable_features & (1 << i))
1794                         dev_notice(&dev->dev, "%s disabled by user\n",
1795                                    i801_feature_names[i]);
1796         }
1797         priv->features &= ~disable_features;
1798
1799         err = pcim_enable_device(dev);
1800         if (err) {
1801                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1802                         err);
1803                 return err;
1804         }
1805         pcim_pin_device(dev);
1806
1807         /* Determine the address of the SMBus area */
1808         priv->smba = pci_resource_start(dev, SMBBAR);
1809         if (!priv->smba) {
1810                 dev_err(&dev->dev,
1811                         "SMBus base address uninitialized, upgrade BIOS\n");
1812                 return -ENODEV;
1813         }
1814
1815         if (i801_acpi_probe(priv))
1816                 return -ENODEV;
1817
1818         err = pcim_iomap_regions(dev, 1 << SMBBAR,
1819                                  dev_driver_string(&dev->dev));
1820         if (err) {
1821                 dev_err(&dev->dev,
1822                         "Failed to request SMBus region 0x%lx-0x%Lx\n",
1823                         priv->smba,
1824                         (unsigned long long)pci_resource_end(dev, SMBBAR));
1825                 i801_acpi_remove(priv);
1826                 return err;
1827         }
1828
1829         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1830         priv->original_hstcfg = temp;
1831         temp &= ~SMBHSTCFG_I2C_EN;      /* SMBus timing */
1832         if (!(temp & SMBHSTCFG_HST_EN)) {
1833                 dev_info(&dev->dev, "Enabling SMBus device\n");
1834                 temp |= SMBHSTCFG_HST_EN;
1835         }
1836         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1837
1838         if (temp & SMBHSTCFG_SMB_SMI_EN) {
1839                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1840                 /* Disable SMBus interrupt feature if SMBus using SMI# */
1841                 priv->features &= ~FEATURE_IRQ;
1842         }
1843         if (temp & SMBHSTCFG_SPD_WD)
1844                 dev_info(&dev->dev, "SPD Write Disable is set\n");
1845
1846         /* Clear special mode bits */
1847         if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1848                 outb_p(inb_p(SMBAUXCTL(priv)) &
1849                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1850
1851         /* Remember original Host Notify setting */
1852         if (priv->features & FEATURE_HOST_NOTIFY)
1853                 priv->original_slvcmd = inb_p(SMBSLVCMD(priv));
1854
1855         /* Default timeout in interrupt mode: 200 ms */
1856         priv->adapter.timeout = HZ / 5;
1857
1858         if (dev->irq == IRQ_NOTCONNECTED)
1859                 priv->features &= ~FEATURE_IRQ;
1860
1861         if (priv->features & FEATURE_IRQ) {
1862                 u16 pcictl, pcists;
1863
1864                 /* Complain if an interrupt is already pending */
1865                 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
1866                 if (pcists & SMBPCISTS_INTS)
1867                         dev_warn(&dev->dev, "An interrupt is pending!\n");
1868
1869                 /* Check if interrupts have been disabled */
1870                 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
1871                 if (pcictl & SMBPCICTL_INTDIS) {
1872                         dev_info(&dev->dev, "Interrupts are disabled\n");
1873                         priv->features &= ~FEATURE_IRQ;
1874                 }
1875         }
1876
1877         if (priv->features & FEATURE_IRQ) {
1878                 init_waitqueue_head(&priv->waitq);
1879
1880                 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1881                                        IRQF_SHARED,
1882                                        dev_driver_string(&dev->dev), priv);
1883                 if (err) {
1884                         dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1885                                 dev->irq, err);
1886                         priv->features &= ~FEATURE_IRQ;
1887                 }
1888         }
1889         dev_info(&dev->dev, "SMBus using %s\n",
1890                  priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1891
1892         i801_add_tco(priv);
1893
1894         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1895                 "SMBus I801 adapter at %04lx", priv->smba);
1896         err = i2c_add_adapter(&priv->adapter);
1897         if (err) {
1898                 i801_acpi_remove(priv);
1899                 return err;
1900         }
1901
1902         i801_enable_host_notify(&priv->adapter);
1903
1904         i801_probe_optional_slaves(priv);
1905         /* We ignore errors - multiplexing is optional */
1906         i801_add_mux(priv);
1907
1908         pci_set_drvdata(dev, priv);
1909
1910         pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1911         pm_runtime_use_autosuspend(&dev->dev);
1912         pm_runtime_put_autosuspend(&dev->dev);
1913         pm_runtime_allow(&dev->dev);
1914
1915         return 0;
1916 }
1917
1918 static void i801_remove(struct pci_dev *dev)
1919 {
1920         struct i801_priv *priv = pci_get_drvdata(dev);
1921
1922         pm_runtime_forbid(&dev->dev);
1923         pm_runtime_get_noresume(&dev->dev);
1924
1925         i801_disable_host_notify(priv);
1926         i801_del_mux(priv);
1927         i2c_del_adapter(&priv->adapter);
1928         i801_acpi_remove(priv);
1929         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1930
1931         platform_device_unregister(priv->tco_pdev);
1932
1933         /*
1934          * do not call pci_disable_device(dev) since it can cause hard hangs on
1935          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1936          */
1937 }
1938
1939 static void i801_shutdown(struct pci_dev *dev)
1940 {
1941         struct i801_priv *priv = pci_get_drvdata(dev);
1942
1943         /* Restore config registers to avoid hard hang on some systems */
1944         i801_disable_host_notify(priv);
1945         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1946 }
1947
1948 #ifdef CONFIG_PM_SLEEP
1949 static int i801_suspend(struct device *dev)
1950 {
1951         struct pci_dev *pci_dev = to_pci_dev(dev);
1952         struct i801_priv *priv = pci_get_drvdata(pci_dev);
1953
1954         pci_write_config_byte(pci_dev, SMBHSTCFG, priv->original_hstcfg);
1955         return 0;
1956 }
1957
1958 static int i801_resume(struct device *dev)
1959 {
1960         struct i801_priv *priv = dev_get_drvdata(dev);
1961
1962         i801_enable_host_notify(&priv->adapter);
1963
1964         return 0;
1965 }
1966 #endif
1967
1968 static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume);
1969
1970 static struct pci_driver i801_driver = {
1971         .name           = "i801_smbus",
1972         .id_table       = i801_ids,
1973         .probe          = i801_probe,
1974         .remove         = i801_remove,
1975         .shutdown       = i801_shutdown,
1976         .driver         = {
1977                 .pm     = &i801_pm_ops,
1978         },
1979 };
1980
1981 static int __init i2c_i801_init(void)
1982 {
1983         if (dmi_name_in_vendors("FUJITSU"))
1984                 input_apanel_init();
1985         return pci_register_driver(&i801_driver);
1986 }
1987
1988 static void __exit i2c_i801_exit(void)
1989 {
1990         pci_unregister_driver(&i801_driver);
1991 }
1992
1993 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>");
1994 MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>");
1995 MODULE_DESCRIPTION("I801 SMBus driver");
1996 MODULE_LICENSE("GPL");
1997
1998 module_init(i2c_i801_init);
1999 module_exit(i2c_i801_exit);