1 // SPDX-License-Identifier: GPL-2.0-or-later
3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
4 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
6 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de>
7 Copyright (C) 2010 Intel Corporation,
8 David Woodhouse <dwmw2@infradead.org>
13 * Supports the following Intel I/O Controller Hubs (ICH):
16 * region SMBus Block proc. block
17 * Chip name PCI ID size PEC buffer call read
18 * ---------------------------------------------------------------------------
19 * 82801AA (ICH) 0x2413 16 no no no no
20 * 82801AB (ICH0) 0x2423 16 no no no no
21 * 82801BA (ICH2) 0x2443 16 no no no no
22 * 82801CA (ICH3) 0x2483 32 soft no no no
23 * 82801DB (ICH4) 0x24c3 32 hard yes no no
24 * 82801E (ICH5) 0x24d3 32 hard yes yes yes
25 * 6300ESB 0x25a4 32 hard yes yes yes
26 * 82801F (ICH6) 0x266a 32 hard yes yes yes
27 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes
28 * 82801G (ICH7) 0x27da 32 hard yes yes yes
29 * 82801H (ICH8) 0x283e 32 hard yes yes yes
30 * 82801I (ICH9) 0x2930 32 hard yes yes yes
31 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes
32 * ICH10 0x3a30 32 hard yes yes yes
33 * ICH10 0x3a60 32 hard yes yes yes
34 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
35 * 6 Series (PCH) 0x1c22 32 hard yes yes yes
36 * Patsburg (PCH) 0x1d22 32 hard yes yes yes
37 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
38 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
39 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
40 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes
41 * Panther Point (PCH) 0x1e22 32 hard yes yes yes
42 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes
43 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
44 * Avoton (SOC) 0x1f3c 32 hard yes yes yes
45 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes
46 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes
47 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
48 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
49 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes
50 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes
51 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
52 * BayTrail (SOC) 0x0f12 32 hard yes yes yes
53 * Braswell (SOC) 0x2292 32 hard yes yes yes
54 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes
55 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes
56 * DNV (SOC) 0x19df 32 hard yes yes yes
57 * Broxton (SOC) 0x5ad4 32 hard yes yes yes
58 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes
59 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes
60 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes
61 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes
62 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes
63 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes
64 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes
65 * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes
66 * Comet Lake (PCH) 0x02a3 32 hard yes yes yes
67 * Comet Lake-H (PCH) 0x06a3 32 hard yes yes yes
68 * Elkhart Lake (PCH) 0x4b23 32 hard yes yes yes
69 * Tiger Lake-LP (PCH) 0xa0a3 32 hard yes yes yes
70 * Jasper Lake (SOC) 0x4da3 32 hard yes yes yes
71 * Comet Lake-V (PCH) 0xa3a3 32 hard yes yes yes
73 * Features supported by this driver:
77 * Block process call transaction yes
78 * I2C block read transaction yes (doesn't use the block buffer)
80 * SMBus Host Notify yes
81 * Interrupt processing yes
83 * See the file Documentation/i2c/busses/i2c-i801.rst for details.
86 #include <linux/interrupt.h>
87 #include <linux/module.h>
88 #include <linux/pci.h>
89 #include <linux/kernel.h>
90 #include <linux/stddef.h>
91 #include <linux/delay.h>
92 #include <linux/ioport.h>
93 #include <linux/init.h>
94 #include <linux/i2c.h>
95 #include <linux/i2c-smbus.h>
96 #include <linux/acpi.h>
98 #include <linux/dmi.h>
99 #include <linux/slab.h>
100 #include <linux/string.h>
101 #include <linux/wait.h>
102 #include <linux/err.h>
103 #include <linux/platform_device.h>
104 #include <linux/platform_data/itco_wdt.h>
105 #include <linux/pm_runtime.h>
107 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
108 #include <linux/gpio/machine.h>
109 #include <linux/platform_data/i2c-mux-gpio.h>
112 /* I801 SMBus address offsets */
113 #define SMBHSTSTS(p) (0 + (p)->smba)
114 #define SMBHSTCNT(p) (2 + (p)->smba)
115 #define SMBHSTCMD(p) (3 + (p)->smba)
116 #define SMBHSTADD(p) (4 + (p)->smba)
117 #define SMBHSTDAT0(p) (5 + (p)->smba)
118 #define SMBHSTDAT1(p) (6 + (p)->smba)
119 #define SMBBLKDAT(p) (7 + (p)->smba)
120 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
121 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
122 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
123 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */
124 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */
125 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */
127 /* PCI Address Constants */
129 #define SMBPCICTL 0x004
130 #define SMBPCISTS 0x006
131 #define SMBHSTCFG 0x040
132 #define TCOBASE 0x050
135 #define SBREG_BAR 0x10
136 #define SBREG_SMBCTRL 0xc6000c
137 #define SBREG_SMBCTRL_DNV 0xcf000c
139 /* Host status bits for SMBPCISTS */
140 #define SMBPCISTS_INTS BIT(3)
142 /* Control bits for SMBPCICTL */
143 #define SMBPCICTL_INTDIS BIT(10)
145 /* Host configuration bits for SMBHSTCFG */
146 #define SMBHSTCFG_HST_EN BIT(0)
147 #define SMBHSTCFG_SMB_SMI_EN BIT(1)
148 #define SMBHSTCFG_I2C_EN BIT(2)
149 #define SMBHSTCFG_SPD_WD BIT(4)
151 /* TCO configuration bits for TCOCTL */
152 #define TCOCTL_EN BIT(8)
154 /* Auxiliary status register bits, ICH4+ only */
155 #define SMBAUXSTS_CRCE BIT(0)
156 #define SMBAUXSTS_STCO BIT(1)
158 /* Auxiliary control register bits, ICH4+ only */
159 #define SMBAUXCTL_CRC BIT(0)
160 #define SMBAUXCTL_E32B BIT(1)
163 #define MAX_RETRIES 400
165 /* I801 command constants */
166 #define I801_QUICK 0x00
167 #define I801_BYTE 0x04
168 #define I801_BYTE_DATA 0x08
169 #define I801_WORD_DATA 0x0C
170 #define I801_PROC_CALL 0x10 /* unimplemented */
171 #define I801_BLOCK_DATA 0x14
172 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
173 #define I801_BLOCK_PROC_CALL 0x1C
175 /* I801 Host Control register bits */
176 #define SMBHSTCNT_INTREN BIT(0)
177 #define SMBHSTCNT_KILL BIT(1)
178 #define SMBHSTCNT_LAST_BYTE BIT(5)
179 #define SMBHSTCNT_START BIT(6)
180 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */
182 /* I801 Hosts Status register bits */
183 #define SMBHSTSTS_BYTE_DONE BIT(7)
184 #define SMBHSTSTS_INUSE_STS BIT(6)
185 #define SMBHSTSTS_SMBALERT_STS BIT(5)
186 #define SMBHSTSTS_FAILED BIT(4)
187 #define SMBHSTSTS_BUS_ERR BIT(3)
188 #define SMBHSTSTS_DEV_ERR BIT(2)
189 #define SMBHSTSTS_INTR BIT(1)
190 #define SMBHSTSTS_HOST_BUSY BIT(0)
192 /* Host Notify Status register bits */
193 #define SMBSLVSTS_HST_NTFY_STS BIT(0)
195 /* Host Notify Command register bits */
196 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0)
198 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
201 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
204 /* Older devices have their ID defined in <linux/pci_ids.h> */
205 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS 0x02a3
206 #define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS 0x06a3
207 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12
208 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df
209 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df
210 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
211 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
212 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
213 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
214 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
215 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
216 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
217 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
218 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292
219 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
220 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0
221 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4
222 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3
223 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
224 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23
225 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS 0x4da3
226 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4
227 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
228 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2
229 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
230 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
231 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
232 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
233 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
234 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2
235 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23
236 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3
237 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS 0xa0a3
238 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123
239 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3
240 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223
241 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3
242 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323
243 #define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS 0xa3a3
245 struct i801_mux_config {
250 unsigned gpios[2]; /* Relative to gpio_chip->base */
255 struct i2c_adapter adapter;
257 unsigned char original_hstcfg;
258 unsigned char original_slvcmd;
259 struct pci_dev *pci_dev;
260 unsigned int features;
263 wait_queue_head_t waitq;
266 /* Command state used by isr for byte-by-byte block transactions */
273 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
274 const struct i801_mux_config *mux_drvdata;
275 struct platform_device *mux_pdev;
276 struct gpiod_lookup_table *lookup;
278 struct platform_device *tco_pdev;
281 * If set to true the host controller registers are reserved for
282 * ACPI AML use. Protected by acpi_lock.
285 struct mutex acpi_lock;
288 #define FEATURE_SMBUS_PEC BIT(0)
289 #define FEATURE_BLOCK_BUFFER BIT(1)
290 #define FEATURE_BLOCK_PROC BIT(2)
291 #define FEATURE_I2C_BLOCK_READ BIT(3)
292 #define FEATURE_IRQ BIT(4)
293 #define FEATURE_HOST_NOTIFY BIT(5)
294 /* Not really a feature, but it's convenient to handle it as such */
295 #define FEATURE_IDF BIT(15)
296 #define FEATURE_TCO_SPT BIT(16)
297 #define FEATURE_TCO_CNL BIT(17)
299 static const char *i801_feature_names[] = {
302 "Block process call",
308 static unsigned int disable_features;
309 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
310 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
311 "\t\t 0x01 disable SMBus PEC\n"
312 "\t\t 0x02 disable the block buffer\n"
313 "\t\t 0x08 disable the I2C block read functionality\n"
314 "\t\t 0x10 don't use interrupts\n"
315 "\t\t 0x20 disable SMBus Host Notify ");
317 /* Make sure the SMBus host is ready to start transmitting.
318 Return 0 if it is, -EBUSY if it is not. */
319 static int i801_check_pre(struct i801_priv *priv)
323 status = inb_p(SMBHSTSTS(priv));
324 if (status & SMBHSTSTS_HOST_BUSY) {
325 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
329 status &= STATUS_FLAGS;
331 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
333 outb_p(status, SMBHSTSTS(priv));
334 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
336 dev_err(&priv->pci_dev->dev,
337 "Failed clearing status flags (%02x)\n",
344 * Clear CRC status if needed.
345 * During normal operation, i801_check_post() takes care
346 * of it after every operation. We do it here only in case
347 * the hardware was already in this state when the driver
350 if (priv->features & FEATURE_SMBUS_PEC) {
351 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
353 dev_dbg(&priv->pci_dev->dev,
354 "Clearing aux status flags (%02x)\n", status);
355 outb_p(status, SMBAUXSTS(priv));
356 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
358 dev_err(&priv->pci_dev->dev,
359 "Failed clearing aux status flags (%02x)\n",
370 * Convert the status register to an error code, and clear it.
371 * Note that status only contains the bits we want to clear, not the
372 * actual register value.
374 static int i801_check_post(struct i801_priv *priv, int status)
379 * If the SMBus is still busy, we give up
380 * Note: This timeout condition only happens when using polling
381 * transactions. For interrupt operation, NAK/timeout is indicated by
384 if (unlikely(status < 0)) {
385 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
386 /* try to stop the current command */
387 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
388 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
390 usleep_range(1000, 2000);
391 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
394 /* Check if it worked */
395 status = inb_p(SMBHSTSTS(priv));
396 if ((status & SMBHSTSTS_HOST_BUSY) ||
397 !(status & SMBHSTSTS_FAILED))
398 dev_err(&priv->pci_dev->dev,
399 "Failed terminating the transaction\n");
400 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
404 if (status & SMBHSTSTS_FAILED) {
406 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
408 if (status & SMBHSTSTS_DEV_ERR) {
410 * This may be a PEC error, check and clear it.
412 * AUXSTS is handled differently from HSTSTS.
413 * For HSTSTS, i801_isr() or i801_wait_intr()
414 * has already cleared the error bits in hardware,
415 * and we are passed a copy of the original value
417 * For AUXSTS, the hardware register is left
418 * for us to handle here.
419 * This is asymmetric, slightly iffy, but safe,
420 * since all this code is serialized and the CRCE
421 * bit is harmless as long as it's cleared before
422 * the next operation.
424 if ((priv->features & FEATURE_SMBUS_PEC) &&
425 (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
426 outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
428 dev_dbg(&priv->pci_dev->dev, "PEC error\n");
431 dev_dbg(&priv->pci_dev->dev, "No response\n");
434 if (status & SMBHSTSTS_BUS_ERR) {
436 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
439 /* Clear status flags except BYTE_DONE, to be cleared by caller */
440 outb_p(status, SMBHSTSTS(priv));
445 /* Wait for BUSY being cleared and either INTR or an error flag being set */
446 static int i801_wait_intr(struct i801_priv *priv)
451 /* We will always wait for a fraction of a second! */
453 usleep_range(250, 500);
454 status = inb_p(SMBHSTSTS(priv));
455 } while (((status & SMBHSTSTS_HOST_BUSY) ||
456 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
457 (timeout++ < MAX_RETRIES));
459 if (timeout > MAX_RETRIES) {
460 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
463 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
466 /* Wait for either BYTE_DONE or an error flag being set */
467 static int i801_wait_byte_done(struct i801_priv *priv)
472 /* We will always wait for a fraction of a second! */
474 usleep_range(250, 500);
475 status = inb_p(SMBHSTSTS(priv));
476 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
477 (timeout++ < MAX_RETRIES));
479 if (timeout > MAX_RETRIES) {
480 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
483 return status & STATUS_ERROR_FLAGS;
486 static int i801_transaction(struct i801_priv *priv, int xact)
490 const struct i2c_adapter *adap = &priv->adapter;
492 result = i801_check_pre(priv);
496 if (priv->features & FEATURE_IRQ) {
497 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
499 result = wait_event_timeout(priv->waitq,
500 (status = priv->status),
504 dev_warn(&priv->pci_dev->dev,
505 "Timeout waiting for interrupt!\n");
508 return i801_check_post(priv, status);
511 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
512 * SMBSCMD are passed in xact */
513 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
515 status = i801_wait_intr(priv);
516 return i801_check_post(priv, status);
519 static int i801_block_transaction_by_block(struct i801_priv *priv,
520 union i2c_smbus_data *data,
521 char read_write, int command,
526 int xact = hwpec ? SMBHSTCNT_PEC_EN : 0;
529 case I2C_SMBUS_BLOCK_PROC_CALL:
530 xact |= I801_BLOCK_PROC_CALL;
532 case I2C_SMBUS_BLOCK_DATA:
533 xact |= I801_BLOCK_DATA;
539 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
541 /* Use 32-byte buffer to process this transaction */
542 if (read_write == I2C_SMBUS_WRITE) {
543 len = data->block[0];
544 outb_p(len, SMBHSTDAT0(priv));
545 for (i = 0; i < len; i++)
546 outb_p(data->block[i+1], SMBBLKDAT(priv));
549 status = i801_transaction(priv, xact);
553 if (read_write == I2C_SMBUS_READ ||
554 command == I2C_SMBUS_BLOCK_PROC_CALL) {
555 len = inb_p(SMBHSTDAT0(priv));
556 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
559 data->block[0] = len;
560 for (i = 0; i < len; i++)
561 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
566 static void i801_isr_byte_done(struct i801_priv *priv)
569 /* For SMBus block reads, length is received with first byte */
570 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
571 (priv->count == 0)) {
572 priv->len = inb_p(SMBHSTDAT0(priv));
573 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
574 dev_err(&priv->pci_dev->dev,
575 "Illegal SMBus block read size %d\n",
578 priv->len = I2C_SMBUS_BLOCK_MAX;
580 dev_dbg(&priv->pci_dev->dev,
581 "SMBus block read size is %d\n",
584 priv->data[-1] = priv->len;
588 if (priv->count < priv->len)
589 priv->data[priv->count++] = inb(SMBBLKDAT(priv));
591 dev_dbg(&priv->pci_dev->dev,
592 "Discarding extra byte on block read\n");
594 /* Set LAST_BYTE for last byte of read transaction */
595 if (priv->count == priv->len - 1)
596 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
598 } else if (priv->count < priv->len - 1) {
599 /* Write next byte, except for IRQ after last byte */
600 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
603 /* Clear BYTE_DONE to continue with next byte */
604 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
607 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
611 addr = inb_p(SMBNTFDADD(priv)) >> 1;
614 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
615 * always returns 0. Our current implementation doesn't provide
616 * data, so we just ignore it.
618 i2c_handle_smbus_host_notify(&priv->adapter, addr);
620 /* clear Host Notify bit and return */
621 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
626 * There are three kinds of interrupts:
628 * 1) i801 signals transaction completion with one of these interrupts:
630 * DEV_ERR - Invalid command, NAK or communication timeout
631 * BUS_ERR - SMI# transaction collision
632 * FAILED - transaction was canceled due to a KILL request
633 * When any of these occur, update ->status and wake up the waitq.
634 * ->status must be cleared before kicking off the next transaction.
636 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
637 * occurs for each byte of a byte-by-byte to prepare the next byte.
639 * 3) Host Notify interrupts
641 static irqreturn_t i801_isr(int irq, void *dev_id)
643 struct i801_priv *priv = dev_id;
647 /* Confirm this is our interrupt */
648 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
649 if (!(pcists & SMBPCISTS_INTS))
652 if (priv->features & FEATURE_HOST_NOTIFY) {
653 status = inb_p(SMBSLVSTS(priv));
654 if (status & SMBSLVSTS_HST_NTFY_STS)
655 return i801_host_notify_isr(priv);
658 status = inb_p(SMBHSTSTS(priv));
659 if (status & SMBHSTSTS_BYTE_DONE)
660 i801_isr_byte_done(priv);
663 * Clear irq sources and report transaction result.
664 * ->status must be cleared before the next transaction is started.
666 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
668 outb_p(status, SMBHSTSTS(priv));
669 priv->status = status;
670 wake_up(&priv->waitq);
677 * For "byte-by-byte" block transactions:
678 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
679 * I2C read uses cmd=I801_I2C_BLOCK_DATA
681 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
682 union i2c_smbus_data *data,
683 char read_write, int command,
690 const struct i2c_adapter *adap = &priv->adapter;
692 if (command == I2C_SMBUS_BLOCK_PROC_CALL)
695 result = i801_check_pre(priv);
699 len = data->block[0];
701 if (read_write == I2C_SMBUS_WRITE) {
702 outb_p(len, SMBHSTDAT0(priv));
703 outb_p(data->block[1], SMBBLKDAT(priv));
706 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
707 read_write == I2C_SMBUS_READ)
708 smbcmd = I801_I2C_BLOCK_DATA;
710 smbcmd = I801_BLOCK_DATA;
712 if (priv->features & FEATURE_IRQ) {
713 priv->is_read = (read_write == I2C_SMBUS_READ);
714 if (len == 1 && priv->is_read)
715 smbcmd |= SMBHSTCNT_LAST_BYTE;
716 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
719 priv->data = &data->block[1];
721 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
722 result = wait_event_timeout(priv->waitq,
723 (status = priv->status),
727 dev_warn(&priv->pci_dev->dev,
728 "Timeout waiting for interrupt!\n");
731 return i801_check_post(priv, status);
734 for (i = 1; i <= len; i++) {
735 if (i == len && read_write == I2C_SMBUS_READ)
736 smbcmd |= SMBHSTCNT_LAST_BYTE;
737 outb_p(smbcmd, SMBHSTCNT(priv));
740 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
743 status = i801_wait_byte_done(priv);
747 if (i == 1 && read_write == I2C_SMBUS_READ
748 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
749 len = inb_p(SMBHSTDAT0(priv));
750 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
751 dev_err(&priv->pci_dev->dev,
752 "Illegal SMBus block read size %d\n",
755 while (inb_p(SMBHSTSTS(priv)) &
757 outb_p(SMBHSTSTS_BYTE_DONE,
759 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
762 data->block[0] = len;
765 /* Retrieve/store value in SMBBLKDAT */
766 if (read_write == I2C_SMBUS_READ)
767 data->block[i] = inb_p(SMBBLKDAT(priv));
768 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
769 outb_p(data->block[i+1], SMBBLKDAT(priv));
771 /* signals SMBBLKDAT ready */
772 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
775 status = i801_wait_intr(priv);
777 return i801_check_post(priv, status);
780 static int i801_set_block_buffer_mode(struct i801_priv *priv)
782 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
783 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
788 /* Block transaction function */
789 static int i801_block_transaction(struct i801_priv *priv,
790 union i2c_smbus_data *data, char read_write,
791 int command, int hwpec)
796 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
797 if (read_write == I2C_SMBUS_WRITE) {
798 /* set I2C_EN bit in configuration register */
799 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
800 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
801 hostc | SMBHSTCFG_I2C_EN);
802 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
803 dev_err(&priv->pci_dev->dev,
804 "I2C block read is unsupported!\n");
809 if (read_write == I2C_SMBUS_WRITE
810 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
811 if (data->block[0] < 1)
813 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
814 data->block[0] = I2C_SMBUS_BLOCK_MAX;
816 data->block[0] = 32; /* max for SMBus block reads */
819 /* Experience has shown that the block buffer can only be used for
820 SMBus (not I2C) block transactions, even though the datasheet
821 doesn't mention this limitation. */
822 if ((priv->features & FEATURE_BLOCK_BUFFER)
823 && command != I2C_SMBUS_I2C_BLOCK_DATA
824 && i801_set_block_buffer_mode(priv) == 0)
825 result = i801_block_transaction_by_block(priv, data,
829 result = i801_block_transaction_byte_by_byte(priv, data,
833 if (command == I2C_SMBUS_I2C_BLOCK_DATA
834 && read_write == I2C_SMBUS_WRITE) {
835 /* restore saved configuration register value */
836 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
841 /* Return negative errno on error. */
842 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
843 unsigned short flags, char read_write, u8 command,
844 int size, union i2c_smbus_data *data)
848 int ret = 0, xact = 0;
849 struct i801_priv *priv = i2c_get_adapdata(adap);
851 mutex_lock(&priv->acpi_lock);
852 if (priv->acpi_reserved) {
853 mutex_unlock(&priv->acpi_lock);
857 pm_runtime_get_sync(&priv->pci_dev->dev);
859 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
860 && size != I2C_SMBUS_QUICK
861 && size != I2C_SMBUS_I2C_BLOCK_DATA;
864 case I2C_SMBUS_QUICK:
865 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
870 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
872 if (read_write == I2C_SMBUS_WRITE)
873 outb_p(command, SMBHSTCMD(priv));
876 case I2C_SMBUS_BYTE_DATA:
877 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
879 outb_p(command, SMBHSTCMD(priv));
880 if (read_write == I2C_SMBUS_WRITE)
881 outb_p(data->byte, SMBHSTDAT0(priv));
882 xact = I801_BYTE_DATA;
884 case I2C_SMBUS_WORD_DATA:
885 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
887 outb_p(command, SMBHSTCMD(priv));
888 if (read_write == I2C_SMBUS_WRITE) {
889 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
890 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
892 xact = I801_WORD_DATA;
894 case I2C_SMBUS_BLOCK_DATA:
895 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
897 outb_p(command, SMBHSTCMD(priv));
900 case I2C_SMBUS_I2C_BLOCK_DATA:
902 * NB: page 240 of ICH5 datasheet shows that the R/#W
903 * bit should be cleared here, even when reading.
904 * However if SPD Write Disable is set (Lynx Point and later),
905 * the read will fail if we don't set the R/#W bit.
907 outb_p(((addr & 0x7f) << 1) |
908 ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ?
909 (read_write & 0x01) : 0),
911 if (read_write == I2C_SMBUS_READ) {
912 /* NB: page 240 of ICH5 datasheet also shows
913 * that DATA1 is the cmd field when reading */
914 outb_p(command, SMBHSTDAT1(priv));
916 outb_p(command, SMBHSTCMD(priv));
919 case I2C_SMBUS_BLOCK_PROC_CALL:
921 * Bit 0 of the slave address register always indicate a write
924 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
925 outb_p(command, SMBHSTCMD(priv));
929 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
935 if (hwpec) /* enable/disable hardware PEC */
936 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
938 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
942 ret = i801_block_transaction(priv, data, read_write, size,
945 ret = i801_transaction(priv, xact);
947 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
948 time, so we forcibly disable it after every transaction. Turn off
949 E32B for the same reason. */
951 outb_p(inb_p(SMBAUXCTL(priv)) &
952 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
958 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
961 switch (xact & 0x7f) {
962 case I801_BYTE: /* Result put in SMBHSTDAT0 */
964 data->byte = inb_p(SMBHSTDAT0(priv));
967 data->word = inb_p(SMBHSTDAT0(priv)) +
968 (inb_p(SMBHSTDAT1(priv)) << 8);
973 pm_runtime_mark_last_busy(&priv->pci_dev->dev);
974 pm_runtime_put_autosuspend(&priv->pci_dev->dev);
975 mutex_unlock(&priv->acpi_lock);
980 static u32 i801_func(struct i2c_adapter *adapter)
982 struct i801_priv *priv = i2c_get_adapdata(adapter);
984 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
985 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
986 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
987 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
988 ((priv->features & FEATURE_BLOCK_PROC) ?
989 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) |
990 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
991 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
992 ((priv->features & FEATURE_HOST_NOTIFY) ?
993 I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
996 static void i801_enable_host_notify(struct i2c_adapter *adapter)
998 struct i801_priv *priv = i2c_get_adapdata(adapter);
1000 if (!(priv->features & FEATURE_HOST_NOTIFY))
1003 if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd))
1004 outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd,
1007 /* clear Host Notify bit to allow a new notification */
1008 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
1011 static void i801_disable_host_notify(struct i801_priv *priv)
1013 if (!(priv->features & FEATURE_HOST_NOTIFY))
1016 outb_p(priv->original_slvcmd, SMBSLVCMD(priv));
1019 static const struct i2c_algorithm smbus_algorithm = {
1020 .smbus_xfer = i801_access,
1021 .functionality = i801_func,
1024 static const struct pci_device_id i801_ids[] = {
1025 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
1026 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
1027 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
1028 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
1029 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
1030 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
1031 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
1032 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
1033 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
1034 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
1035 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
1036 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
1037 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
1038 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
1039 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
1040 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
1041 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
1042 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
1043 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
1044 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
1045 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
1046 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
1047 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
1048 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
1049 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
1050 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
1051 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
1052 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
1053 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
1054 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
1055 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
1056 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) },
1057 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
1058 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
1059 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
1060 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
1061 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
1062 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
1063 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMBUS) },
1064 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
1065 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
1066 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) },
1067 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) },
1068 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) },
1069 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS) },
1070 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS) },
1071 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS) },
1072 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS) },
1073 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS) },
1074 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS) },
1075 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS) },
1076 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS) },
1077 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS) },
1081 MODULE_DEVICE_TABLE(pci, i801_ids);
1083 #if defined CONFIG_X86 && defined CONFIG_DMI
1084 static unsigned char apanel_addr;
1086 /* Scan the system ROM for the signature "FJKEYINF" */
1087 static __init const void __iomem *bios_signature(const void __iomem *bios)
1090 const unsigned char signature[] = "FJKEYINF";
1092 for (offset = 0; offset < 0x10000; offset += 0x10) {
1093 if (check_signature(bios + offset, signature,
1094 sizeof(signature)-1))
1095 return bios + offset;
1100 static void __init input_apanel_init(void)
1103 const void __iomem *p;
1105 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1106 p = bios_signature(bios);
1108 /* just use the first address */
1109 apanel_addr = readb(p + 8 + 3) >> 1;
1114 struct dmi_onboard_device_info {
1117 unsigned short i2c_addr;
1118 const char *i2c_type;
1121 static const struct dmi_onboard_device_info dmi_devices[] = {
1122 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1123 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1124 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1127 static void dmi_check_onboard_device(u8 type, const char *name,
1128 struct i2c_adapter *adap)
1131 struct i2c_board_info info;
1133 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1134 /* & ~0x80, ignore enabled/disabled bit */
1135 if ((type & ~0x80) != dmi_devices[i].type)
1137 if (strcasecmp(name, dmi_devices[i].name))
1140 memset(&info, 0, sizeof(struct i2c_board_info));
1141 info.addr = dmi_devices[i].i2c_addr;
1142 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1143 i2c_new_client_device(adap, &info);
1148 /* We use our own function to check for onboard devices instead of
1149 dmi_find_device() as some buggy BIOS's have the devices we are interested
1150 in marked as disabled */
1151 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1158 count = (dm->length - sizeof(struct dmi_header)) / 2;
1159 for (i = 0; i < count; i++) {
1160 const u8 *d = (char *)(dm + 1) + (i * 2);
1161 const char *name = ((char *) dm) + dm->length;
1168 while (s > 0 && name[0]) {
1169 name += strlen(name) + 1;
1172 if (name[0] == 0) /* Bogus string reference */
1175 dmi_check_onboard_device(type, name, adap);
1179 /* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */
1180 static const char *const acpi_smo8800_ids[] = {
1191 static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle,
1194 void **return_value)
1196 struct acpi_device_info *info;
1201 status = acpi_get_object_info(obj_handle, &info);
1202 if (ACPI_FAILURE(status))
1205 if (!(info->valid & ACPI_VALID_HID))
1206 goto smo88xx_not_found;
1208 hid = info->hardware_id.string;
1210 goto smo88xx_not_found;
1212 i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid);
1214 goto smo88xx_not_found;
1218 *((bool *)return_value) = true;
1219 return AE_CTRL_TERMINATE;
1226 static bool is_dell_system_with_lis3lv02d(void)
1231 vendor = dmi_get_system_info(DMI_SYS_VENDOR);
1232 if (!vendor || strcmp(vendor, "Dell Inc."))
1236 * Check that ACPI device SMO88xx is present and is functioning.
1237 * Function acpi_get_devices() already filters all ACPI devices
1238 * which are not present or are not functioning.
1239 * ACPI device SMO88xx represents our ST microelectronics lis3lv02d
1240 * accelerometer but unfortunately ACPI does not provide any other
1241 * information (like I2C address).
1244 acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL,
1251 * Accelerometer's I2C address is not specified in DMI nor ACPI,
1252 * so it is needed to define mapping table based on DMI product names.
1254 static const struct {
1255 const char *dmi_product_name;
1256 unsigned short i2c_addr;
1257 } dell_lis3lv02d_devices[] = {
1259 * Dell platform team told us that these Latitude devices have
1260 * ST microelectronics accelerometer at I2C address 0x29.
1262 { "Latitude E5250", 0x29 },
1263 { "Latitude E5450", 0x29 },
1264 { "Latitude E5550", 0x29 },
1265 { "Latitude E6440", 0x29 },
1266 { "Latitude E6440 ATG", 0x29 },
1267 { "Latitude E6540", 0x29 },
1269 * Additional individual entries were added after verification.
1271 { "Vostro V131", 0x1d },
1274 static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv)
1276 struct i2c_board_info info;
1277 const char *dmi_product_name;
1280 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
1281 for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) {
1282 if (strcmp(dmi_product_name,
1283 dell_lis3lv02d_devices[i].dmi_product_name) == 0)
1287 if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) {
1288 dev_warn(&priv->pci_dev->dev,
1289 "Accelerometer lis3lv02d is present on SMBus but its"
1290 " address is unknown, skipping registration\n");
1294 memset(&info, 0, sizeof(struct i2c_board_info));
1295 info.addr = dell_lis3lv02d_devices[i].i2c_addr;
1296 strlcpy(info.type, "lis3lv02d", I2C_NAME_SIZE);
1297 i2c_new_client_device(&priv->adapter, &info);
1300 /* Register optional slaves */
1301 static void i801_probe_optional_slaves(struct i801_priv *priv)
1303 /* Only register slaves on main SMBus channel */
1304 if (priv->features & FEATURE_IDF)
1308 struct i2c_board_info info;
1310 memset(&info, 0, sizeof(struct i2c_board_info));
1311 info.addr = apanel_addr;
1312 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
1313 i2c_new_client_device(&priv->adapter, &info);
1316 if (dmi_name_in_vendors("FUJITSU"))
1317 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1319 if (is_dell_system_with_lis3lv02d())
1320 register_dell_lis3lv02d_i2c_device(priv);
1322 /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */
1323 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO)
1324 if (!priv->mux_drvdata)
1326 i2c_register_spd(&priv->adapter);
1329 static void __init input_apanel_init(void) {}
1330 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1331 #endif /* CONFIG_X86 && CONFIG_DMI */
1333 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
1334 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1335 .gpio_chip = "gpio_ich",
1336 .values = { 0x02, 0x03 },
1338 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1339 .gpios = { 52, 53 },
1343 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1344 .gpio_chip = "gpio_ich",
1345 .values = { 0x02, 0x03, 0x01 },
1347 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1348 .gpios = { 52, 53 },
1352 static const struct dmi_system_id mux_dmi_table[] = {
1355 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1356 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1358 .driver_data = &i801_mux_config_asus_z8_d12,
1362 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1363 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1365 .driver_data = &i801_mux_config_asus_z8_d12,
1369 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1370 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1372 .driver_data = &i801_mux_config_asus_z8_d12,
1376 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1377 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1379 .driver_data = &i801_mux_config_asus_z8_d12,
1383 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1384 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1386 .driver_data = &i801_mux_config_asus_z8_d12,
1390 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1391 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1393 .driver_data = &i801_mux_config_asus_z8_d12,
1397 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1398 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1400 .driver_data = &i801_mux_config_asus_z8_d18,
1404 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1405 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1407 .driver_data = &i801_mux_config_asus_z8_d18,
1411 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1412 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1414 .driver_data = &i801_mux_config_asus_z8_d12,
1419 /* Setup multiplexing if needed */
1420 static int i801_add_mux(struct i801_priv *priv)
1422 struct device *dev = &priv->adapter.dev;
1423 const struct i801_mux_config *mux_config;
1424 struct i2c_mux_gpio_platform_data gpio_data;
1425 struct gpiod_lookup_table *lookup;
1428 if (!priv->mux_drvdata)
1430 mux_config = priv->mux_drvdata;
1432 /* Prepare the platform data */
1433 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1434 gpio_data.parent = priv->adapter.nr;
1435 gpio_data.values = mux_config->values;
1436 gpio_data.n_values = mux_config->n_values;
1437 gpio_data.classes = mux_config->classes;
1438 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1440 /* Register GPIO descriptor lookup table */
1441 lookup = devm_kzalloc(dev,
1442 struct_size(lookup, table, mux_config->n_gpios),
1446 lookup->dev_id = "i2c-mux-gpio";
1447 for (i = 0; i < mux_config->n_gpios; i++) {
1448 lookup->table[i] = (struct gpiod_lookup)
1449 GPIO_LOOKUP(mux_config->gpio_chip,
1450 mux_config->gpios[i], "mux", 0);
1452 gpiod_add_lookup_table(lookup);
1453 priv->lookup = lookup;
1456 * Register the mux device, we use PLATFORM_DEVID_NONE here
1457 * because since we are referring to the GPIO chip by name we are
1458 * anyways in deep trouble if there is more than one of these
1459 * devices, and there should likely only be one platform controller
1462 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1463 PLATFORM_DEVID_NONE, &gpio_data,
1464 sizeof(struct i2c_mux_gpio_platform_data));
1465 if (IS_ERR(priv->mux_pdev)) {
1466 err = PTR_ERR(priv->mux_pdev);
1467 gpiod_remove_lookup_table(lookup);
1468 priv->mux_pdev = NULL;
1469 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1476 static void i801_del_mux(struct i801_priv *priv)
1479 platform_device_unregister(priv->mux_pdev);
1481 gpiod_remove_lookup_table(priv->lookup);
1484 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1486 const struct dmi_system_id *id;
1487 const struct i801_mux_config *mux_config;
1488 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1491 id = dmi_first_match(mux_dmi_table);
1493 /* Remove branch classes from trunk */
1494 mux_config = id->driver_data;
1495 for (i = 0; i < mux_config->n_values; i++)
1496 class &= ~mux_config->classes[i];
1498 /* Remember for later */
1499 priv->mux_drvdata = mux_config;
1505 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1506 static inline void i801_del_mux(struct i801_priv *priv) { }
1508 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1510 return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1514 static const struct itco_wdt_platform_data spt_tco_platform_data = {
1515 .name = "Intel PCH",
1519 static DEFINE_SPINLOCK(p2sb_spinlock);
1521 static struct platform_device *
1522 i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev,
1523 struct resource *tco_res)
1525 struct resource *res;
1532 * We must access the NO_REBOOT bit over the Primary to Sideband
1533 * bridge (P2SB). The BIOS prevents the P2SB device from being
1534 * enumerated by the PCI subsystem, so we need to unhide/hide it
1535 * to lookup the P2SB BAR.
1537 spin_lock(&p2sb_spinlock);
1539 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1541 /* Unhide the P2SB device, if it is hidden */
1542 pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden);
1544 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1546 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1547 base64_addr = base_addr & 0xfffffff0;
1549 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1550 base64_addr |= (u64)base_addr << 32;
1552 /* Hide the P2SB device, if it was hidden before */
1554 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden);
1555 spin_unlock(&p2sb_spinlock);
1558 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1559 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV;
1561 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1563 res->end = res->start + 3;
1564 res->flags = IORESOURCE_MEM;
1566 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1567 tco_res, 2, &spt_tco_platform_data,
1568 sizeof(spt_tco_platform_data));
1571 static const struct itco_wdt_platform_data cnl_tco_platform_data = {
1572 .name = "Intel PCH",
1576 static struct platform_device *
1577 i801_add_tco_cnl(struct i801_priv *priv, struct pci_dev *pci_dev,
1578 struct resource *tco_res)
1580 return platform_device_register_resndata(&pci_dev->dev,
1581 "iTCO_wdt", -1, tco_res, 1, &cnl_tco_platform_data,
1582 sizeof(cnl_tco_platform_data));
1585 static void i801_add_tco(struct i801_priv *priv)
1587 struct pci_dev *pci_dev = priv->pci_dev;
1588 struct resource tco_res[2], *res;
1589 u32 tco_base, tco_ctl;
1591 /* If we have ACPI based watchdog use that instead */
1592 if (acpi_has_watchdog())
1595 if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL)))
1598 pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1599 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1600 if (!(tco_ctl & TCOCTL_EN))
1603 memset(tco_res, 0, sizeof(tco_res));
1605 * Always populate the main iTCO IO resource here. The second entry
1606 * for NO_REBOOT MMIO is filled by the SPT specific function.
1609 res->start = tco_base & ~1;
1610 res->end = res->start + 32 - 1;
1611 res->flags = IORESOURCE_IO;
1613 if (priv->features & FEATURE_TCO_CNL)
1614 priv->tco_pdev = i801_add_tco_cnl(priv, pci_dev, tco_res);
1616 priv->tco_pdev = i801_add_tco_spt(priv, pci_dev, tco_res);
1618 if (IS_ERR(priv->tco_pdev))
1619 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1623 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv,
1624 acpi_physical_address address)
1626 return address >= priv->smba &&
1627 address <= pci_resource_end(priv->pci_dev, SMBBAR);
1631 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1632 u64 *value, void *handler_context, void *region_context)
1634 struct i801_priv *priv = handler_context;
1635 struct pci_dev *pdev = priv->pci_dev;
1639 * Once BIOS AML code touches the OpRegion we warn and inhibit any
1640 * further access from the driver itself. This device is now owned
1641 * by the system firmware.
1643 mutex_lock(&priv->acpi_lock);
1645 if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) {
1646 priv->acpi_reserved = true;
1648 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1649 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1652 * BIOS is accessing the host controller so prevent it from
1653 * suspending automatically from now on.
1655 pm_runtime_get_sync(&pdev->dev);
1658 if ((function & ACPI_IO_MASK) == ACPI_READ)
1659 status = acpi_os_read_port(address, (u32 *)value, bits);
1661 status = acpi_os_write_port(address, (u32)*value, bits);
1663 mutex_unlock(&priv->acpi_lock);
1668 static int i801_acpi_probe(struct i801_priv *priv)
1670 struct acpi_device *adev;
1673 adev = ACPI_COMPANION(&priv->pci_dev->dev);
1675 status = acpi_install_address_space_handler(adev->handle,
1676 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler,
1678 if (ACPI_SUCCESS(status))
1682 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1685 static void i801_acpi_remove(struct i801_priv *priv)
1687 struct acpi_device *adev;
1689 adev = ACPI_COMPANION(&priv->pci_dev->dev);
1693 acpi_remove_address_space_handler(adev->handle,
1694 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1696 mutex_lock(&priv->acpi_lock);
1697 if (priv->acpi_reserved)
1698 pm_runtime_put(&priv->pci_dev->dev);
1699 mutex_unlock(&priv->acpi_lock);
1702 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
1703 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1706 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1710 struct i801_priv *priv;
1712 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1716 i2c_set_adapdata(&priv->adapter, priv);
1717 priv->adapter.owner = THIS_MODULE;
1718 priv->adapter.class = i801_get_adapter_class(priv);
1719 priv->adapter.algo = &smbus_algorithm;
1720 priv->adapter.dev.parent = &dev->dev;
1721 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1722 priv->adapter.retries = 3;
1723 mutex_init(&priv->acpi_lock);
1725 priv->pci_dev = dev;
1726 switch (dev->device) {
1727 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
1728 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
1729 case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS:
1730 case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS:
1731 case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
1732 case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS:
1733 case PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS:
1734 priv->features |= FEATURE_BLOCK_PROC;
1735 priv->features |= FEATURE_I2C_BLOCK_READ;
1736 priv->features |= FEATURE_IRQ;
1737 priv->features |= FEATURE_SMBUS_PEC;
1738 priv->features |= FEATURE_BLOCK_BUFFER;
1739 priv->features |= FEATURE_TCO_SPT;
1740 priv->features |= FEATURE_HOST_NOTIFY;
1743 case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS:
1744 case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS:
1745 case PCI_DEVICE_ID_INTEL_CDF_SMBUS:
1746 case PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS:
1747 case PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS:
1748 case PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS:
1749 case PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS:
1750 case PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS:
1751 case PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS:
1752 priv->features |= FEATURE_BLOCK_PROC;
1753 priv->features |= FEATURE_I2C_BLOCK_READ;
1754 priv->features |= FEATURE_IRQ;
1755 priv->features |= FEATURE_SMBUS_PEC;
1756 priv->features |= FEATURE_BLOCK_BUFFER;
1757 priv->features |= FEATURE_TCO_CNL;
1758 priv->features |= FEATURE_HOST_NOTIFY;
1761 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1762 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1763 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1764 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1765 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1766 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1767 priv->features |= FEATURE_IDF;
1770 priv->features |= FEATURE_BLOCK_PROC;
1771 priv->features |= FEATURE_I2C_BLOCK_READ;
1772 priv->features |= FEATURE_IRQ;
1774 case PCI_DEVICE_ID_INTEL_82801DB_3:
1775 priv->features |= FEATURE_SMBUS_PEC;
1776 priv->features |= FEATURE_BLOCK_BUFFER;
1778 case PCI_DEVICE_ID_INTEL_82801CA_3:
1779 priv->features |= FEATURE_HOST_NOTIFY;
1781 case PCI_DEVICE_ID_INTEL_82801BA_2:
1782 case PCI_DEVICE_ID_INTEL_82801AB_3:
1783 case PCI_DEVICE_ID_INTEL_82801AA_3:
1787 /* Disable features on user request */
1788 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1789 if (priv->features & disable_features & (1 << i))
1790 dev_notice(&dev->dev, "%s disabled by user\n",
1791 i801_feature_names[i]);
1793 priv->features &= ~disable_features;
1795 err = pcim_enable_device(dev);
1797 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1801 pcim_pin_device(dev);
1803 /* Determine the address of the SMBus area */
1804 priv->smba = pci_resource_start(dev, SMBBAR);
1807 "SMBus base address uninitialized, upgrade BIOS\n");
1811 if (i801_acpi_probe(priv))
1814 err = pcim_iomap_regions(dev, 1 << SMBBAR,
1815 dev_driver_string(&dev->dev));
1818 "Failed to request SMBus region 0x%lx-0x%Lx\n",
1820 (unsigned long long)pci_resource_end(dev, SMBBAR));
1821 i801_acpi_remove(priv);
1825 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1826 priv->original_hstcfg = temp;
1827 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
1828 if (!(temp & SMBHSTCFG_HST_EN)) {
1829 dev_info(&dev->dev, "Enabling SMBus device\n");
1830 temp |= SMBHSTCFG_HST_EN;
1832 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1834 if (temp & SMBHSTCFG_SMB_SMI_EN) {
1835 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1836 /* Disable SMBus interrupt feature if SMBus using SMI# */
1837 priv->features &= ~FEATURE_IRQ;
1839 if (temp & SMBHSTCFG_SPD_WD)
1840 dev_info(&dev->dev, "SPD Write Disable is set\n");
1842 /* Clear special mode bits */
1843 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1844 outb_p(inb_p(SMBAUXCTL(priv)) &
1845 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1847 /* Remember original Host Notify setting */
1848 if (priv->features & FEATURE_HOST_NOTIFY)
1849 priv->original_slvcmd = inb_p(SMBSLVCMD(priv));
1851 /* Default timeout in interrupt mode: 200 ms */
1852 priv->adapter.timeout = HZ / 5;
1854 if (dev->irq == IRQ_NOTCONNECTED)
1855 priv->features &= ~FEATURE_IRQ;
1857 if (priv->features & FEATURE_IRQ) {
1860 /* Complain if an interrupt is already pending */
1861 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
1862 if (pcists & SMBPCISTS_INTS)
1863 dev_warn(&dev->dev, "An interrupt is pending!\n");
1865 /* Check if interrupts have been disabled */
1866 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
1867 if (pcictl & SMBPCICTL_INTDIS) {
1868 dev_info(&dev->dev, "Interrupts are disabled\n");
1869 priv->features &= ~FEATURE_IRQ;
1873 if (priv->features & FEATURE_IRQ) {
1874 init_waitqueue_head(&priv->waitq);
1876 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1878 dev_driver_string(&dev->dev), priv);
1880 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1882 priv->features &= ~FEATURE_IRQ;
1885 dev_info(&dev->dev, "SMBus using %s\n",
1886 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1890 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1891 "SMBus I801 adapter at %04lx", priv->smba);
1892 err = i2c_add_adapter(&priv->adapter);
1894 i801_acpi_remove(priv);
1898 i801_enable_host_notify(&priv->adapter);
1900 i801_probe_optional_slaves(priv);
1901 /* We ignore errors - multiplexing is optional */
1904 pci_set_drvdata(dev, priv);
1906 pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1907 pm_runtime_use_autosuspend(&dev->dev);
1908 pm_runtime_put_autosuspend(&dev->dev);
1909 pm_runtime_allow(&dev->dev);
1914 static void i801_remove(struct pci_dev *dev)
1916 struct i801_priv *priv = pci_get_drvdata(dev);
1918 pm_runtime_forbid(&dev->dev);
1919 pm_runtime_get_noresume(&dev->dev);
1921 i801_disable_host_notify(priv);
1923 i2c_del_adapter(&priv->adapter);
1924 i801_acpi_remove(priv);
1925 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1927 platform_device_unregister(priv->tco_pdev);
1930 * do not call pci_disable_device(dev) since it can cause hard hangs on
1931 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1935 static void i801_shutdown(struct pci_dev *dev)
1937 struct i801_priv *priv = pci_get_drvdata(dev);
1939 /* Restore config registers to avoid hard hang on some systems */
1940 i801_disable_host_notify(priv);
1941 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1944 #ifdef CONFIG_PM_SLEEP
1945 static int i801_suspend(struct device *dev)
1947 struct pci_dev *pci_dev = to_pci_dev(dev);
1948 struct i801_priv *priv = pci_get_drvdata(pci_dev);
1950 pci_write_config_byte(pci_dev, SMBHSTCFG, priv->original_hstcfg);
1954 static int i801_resume(struct device *dev)
1956 struct i801_priv *priv = dev_get_drvdata(dev);
1958 i801_enable_host_notify(&priv->adapter);
1964 static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume);
1966 static struct pci_driver i801_driver = {
1967 .name = "i801_smbus",
1968 .id_table = i801_ids,
1969 .probe = i801_probe,
1970 .remove = i801_remove,
1971 .shutdown = i801_shutdown,
1977 static int __init i2c_i801_init(void)
1979 if (dmi_name_in_vendors("FUJITSU"))
1980 input_apanel_init();
1981 return pci_register_driver(&i801_driver);
1984 static void __exit i2c_i801_exit(void)
1986 pci_unregister_driver(&i801_driver);
1989 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>");
1990 MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>");
1991 MODULE_DESCRIPTION("I801 SMBus driver");
1992 MODULE_LICENSE("GPL");
1994 module_init(i2c_i801_init);
1995 module_exit(i2c_i801_exit);