drivers/i2c/busses/i2c-cadence.c

   1 /*
   2  * I2C bus driver for the Cadence I2C controller.
   3  *
   4  * Copyright (C) 2009 - 2014 Xilinx, Inc.
   5  *
   6  * This program is free software; you can redistribute it
   7  * and/or modify it under the terms of the GNU General Public
   8  * License as published by the Free Software Foundation;
   9  * either version 2 of the License, or (at your option) any
  10  * later version.
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/delay.h>
  15 #include <linux/i2c.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/module.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/of.h>
  21 #include <linux/pm_runtime.h>
  22
  23 /* Register offsets for the I2C device. */
  24 #define CDNS_I2C_CR_OFFSET              0x00 /* Control Register, RW */
  25 #define CDNS_I2C_SR_OFFSET              0x04 /* Status Register, RO */
  26 #define CDNS_I2C_ADDR_OFFSET            0x08 /* I2C Address Register, RW */
  27 #define CDNS_I2C_DATA_OFFSET            0x0C /* I2C Data Register, RW */
  28 #define CDNS_I2C_ISR_OFFSET             0x10 /* IRQ Status Register, RW */
  29 #define CDNS_I2C_XFER_SIZE_OFFSET       0x14 /* Transfer Size Register, RW */
  30 #define CDNS_I2C_TIME_OUT_OFFSET        0x1C /* Time Out Register, RW */
  31 #define CDNS_I2C_IER_OFFSET             0x24 /* IRQ Enable Register, WO */
  32 #define CDNS_I2C_IDR_OFFSET             0x28 /* IRQ Disable Register, WO */
  33
  34 /* Control Register Bit mask definitions */
  35 #define CDNS_I2C_CR_HOLD                BIT(4) /* Hold Bus bit */
  36 #define CDNS_I2C_CR_ACK_EN              BIT(3)
  37 #define CDNS_I2C_CR_NEA                 BIT(2)
  38 #define CDNS_I2C_CR_MS                  BIT(1)
  39 /* Read or Write Master transfer 0 = Transmitter, 1 = Receiver */
  40 #define CDNS_I2C_CR_RW                  BIT(0)
  41 /* 1 = Auto init FIFO to zeroes */
  42 #define CDNS_I2C_CR_CLR_FIFO            BIT(6)
  43 #define CDNS_I2C_CR_DIVA_SHIFT          14
  44 #define CDNS_I2C_CR_DIVA_MASK           (3 << CDNS_I2C_CR_DIVA_SHIFT)
  45 #define CDNS_I2C_CR_DIVB_SHIFT          8
  46 #define CDNS_I2C_CR_DIVB_MASK           (0x3f << CDNS_I2C_CR_DIVB_SHIFT)
  47
  48 /* Status Register Bit mask definitions */
  49 #define CDNS_I2C_SR_BA          BIT(8)
  50 #define CDNS_I2C_SR_RXDV        BIT(5)
  51
  52 /*
  53  * I2C Address Register Bit mask definitions
  54  * Normal addressing mode uses [6:0] bits. Extended addressing mode uses [9:0]
  55  * bits. A write access to this register always initiates a transfer if the I2C
  56  * is in master mode.
  57  */
  58 #define CDNS_I2C_ADDR_MASK      0x000003FF /* I2C Address Mask */
  59
  60 /*
  61  * I2C Interrupt Registers Bit mask definitions
  62  * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
  63  * bit definitions.
  64  */
  65 #define CDNS_I2C_IXR_ARB_LOST           BIT(9)
  66 #define CDNS_I2C_IXR_RX_UNF             BIT(7)
  67 #define CDNS_I2C_IXR_TX_OVF             BIT(6)
  68 #define CDNS_I2C_IXR_RX_OVF             BIT(5)
  69 #define CDNS_I2C_IXR_SLV_RDY            BIT(4)
  70 #define CDNS_I2C_IXR_TO                 BIT(3)
  71 #define CDNS_I2C_IXR_NACK               BIT(2)
  72 #define CDNS_I2C_IXR_DATA               BIT(1)
  73 #define CDNS_I2C_IXR_COMP               BIT(0)
  74
  75 #define CDNS_I2C_IXR_ALL_INTR_MASK      (CDNS_I2C_IXR_ARB_LOST | \
  76                                          CDNS_I2C_IXR_RX_UNF | \
  77                                          CDNS_I2C_IXR_TX_OVF | \
  78                                          CDNS_I2C_IXR_RX_OVF | \
  79                                          CDNS_I2C_IXR_SLV_RDY | \
  80                                          CDNS_I2C_IXR_TO | \
  81                                          CDNS_I2C_IXR_NACK | \
  82                                          CDNS_I2C_IXR_DATA | \
  83                                          CDNS_I2C_IXR_COMP)
  84
  85 #define CDNS_I2C_IXR_ERR_INTR_MASK      (CDNS_I2C_IXR_ARB_LOST | \
  86                                          CDNS_I2C_IXR_RX_UNF | \
  87                                          CDNS_I2C_IXR_TX_OVF | \
  88                                          CDNS_I2C_IXR_RX_OVF | \
  89                                          CDNS_I2C_IXR_NACK)
  90
  91 #define CDNS_I2C_ENABLED_INTR_MASK      (CDNS_I2C_IXR_ARB_LOST | \
  92                                          CDNS_I2C_IXR_RX_UNF | \
  93                                          CDNS_I2C_IXR_TX_OVF | \
  94                                          CDNS_I2C_IXR_RX_OVF | \
  95                                          CDNS_I2C_IXR_NACK | \
  96                                          CDNS_I2C_IXR_DATA | \
  97                                          CDNS_I2C_IXR_COMP)
  98
  99 #define CDNS_I2C_TIMEOUT                msecs_to_jiffies(1000)
 100 /* timeout for pm runtime autosuspend */
 101 #define CNDS_I2C_PM_TIMEOUT             1000    /* ms */
 102
 103 #define CDNS_I2C_FIFO_DEPTH             16
 104 /* FIFO depth at which the DATA interrupt occurs */
 105 #define CDNS_I2C_DATA_INTR_DEPTH        (CDNS_I2C_FIFO_DEPTH - 2)
 106 #define CDNS_I2C_MAX_TRANSFER_SIZE      255
 107 /* Transfer size in multiples of data interrupt depth */
 108 #define CDNS_I2C_TRANSFER_SIZE  (CDNS_I2C_MAX_TRANSFER_SIZE - 3)
 109
 110 #define DRIVER_NAME             "cdns-i2c"
 111
 112 #define CDNS_I2C_SPEED_MAX      400000
 113 #define CDNS_I2C_SPEED_DEFAULT  100000
 114
 115 #define CDNS_I2C_DIVA_MAX       4
 116 #define CDNS_I2C_DIVB_MAX       64
 117
 118 #define CDNS_I2C_TIMEOUT_MAX    0xFF
 119
 120 #define CDNS_I2C_BROKEN_HOLD_BIT        BIT(0)
 121
 122 #define cdns_i2c_readreg(offset)       readl_relaxed(id->membase + offset)
 123 #define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset)
 124
 125 /**
 126  * struct cdns_i2c - I2C device private data structure
 127  *
 128  * @dev:                Pointer to device structure
 129  * @membase:            Base address of the I2C device
 130  * @adap:               I2C adapter instance
 131  * @p_msg:              Message pointer
 132  * @err_status:         Error status in Interrupt Status Register
 133  * @xfer_done:          Transfer complete status
 134  * @p_send_buf:         Pointer to transmit buffer
 135  * @p_recv_buf:         Pointer to receive buffer
 136  * @send_count:         Number of bytes still expected to send
 137  * @recv_count:         Number of bytes still expected to receive
 138  * @curr_recv_count:    Number of bytes to be received in current transfer
 139  * @irq:                IRQ number
 140  * @input_clk:          Input clock to I2C controller
 141  * @i2c_clk:            Maximum I2C clock speed
 142  * @bus_hold_flag:      Flag used in repeated start for clearing HOLD bit
 143  * @clk:                Pointer to struct clk
 144  * @clk_rate_change_nb: Notifier block for clock rate changes
 145  * @quirks:             flag for broken hold bit usage in r1p10
 146  */
 147 struct cdns_i2c {
 148         struct device           *dev;
 149         void __iomem *membase;
 150         struct i2c_adapter adap;
 151         struct i2c_msg *p_msg;
 152         int err_status;
 153         struct completion xfer_done;
 154         unsigned char *p_send_buf;
 155         unsigned char *p_recv_buf;
 156         unsigned int send_count;
 157         unsigned int recv_count;
 158         unsigned int curr_recv_count;
 159         int irq;
 160         unsigned long input_clk;
 161         unsigned int i2c_clk;
 162         unsigned int bus_hold_flag;
 163         struct clk *clk;
 164         struct notifier_block clk_rate_change_nb;
 165         u32 quirks;
 166 };
 167
 168 struct cdns_platform_data {
 169         u32 quirks;
 170 };
 171
 172 #define to_cdns_i2c(_nb)        container_of(_nb, struct cdns_i2c, \
 173                                              clk_rate_change_nb)
 174
 175 /**
 176  * cdns_i2c_clear_bus_hold - Clear bus hold bit
 177  * @id: Pointer to driver data struct
 178  *
 179  * Helper to clear the controller's bus hold bit.
 180  */
 181 static void cdns_i2c_clear_bus_hold(struct cdns_i2c *id)
 182 {
 183         u32 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
 184         if (reg & CDNS_I2C_CR_HOLD)
 185                 cdns_i2c_writereg(reg & ~CDNS_I2C_CR_HOLD, CDNS_I2C_CR_OFFSET);
 186 }
 187
 188 static inline bool cdns_is_holdquirk(struct cdns_i2c *id, bool hold_wrkaround)
 189 {
 190         return (hold_wrkaround &&
 191                 (id->curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1));
 192 }
 193
 194 /**
 195  * cdns_i2c_isr - Interrupt handler for the I2C device
 196  * @irq:        irq number for the I2C device
 197  * @ptr:        void pointer to cdns_i2c structure
 198  *
 199  * This function handles the data interrupt, transfer complete interrupt and
 200  * the error interrupts of the I2C device.
 201  *
 202  * Return: IRQ_HANDLED always
 203  */
 204 static irqreturn_t cdns_i2c_isr(int irq, void *ptr)
 205 {
 206         unsigned int isr_status, avail_bytes, updatetx;
 207         unsigned int bytes_to_send;
 208         bool hold_quirk;
 209         struct cdns_i2c *id = ptr;
 210         /* Signal completion only after everything is updated */
 211         int done_flag = 0;
 212         irqreturn_t status = IRQ_NONE;
 213
 214         isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
 215         cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
 216
 217         /* Handling nack and arbitration lost interrupt */
 218         if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_ARB_LOST)) {
 219                 done_flag = 1;
 220                 status = IRQ_HANDLED;
 221         }
 222
 223         /*
 224          * Check if transfer size register needs to be updated again for a
 225          * large data receive operation.
 226          */
 227         updatetx = 0;
 228         if (id->recv_count > id->curr_recv_count)
 229                 updatetx = 1;
 230
 231         hold_quirk = (id->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx;
 232
 233         /* When receiving, handle data interrupt and completion interrupt */
 234         if (id->p_recv_buf &&
 235             ((isr_status & CDNS_I2C_IXR_COMP) ||
 236              (isr_status & CDNS_I2C_IXR_DATA))) {
 237                 /* Read data if receive data valid is set */
 238                 while (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) &
 239                        CDNS_I2C_SR_RXDV) {
 240                         /*
 241                          * Clear hold bit that was set for FIFO control if
 242                          * RX data left is less than FIFO depth, unless
 243                          * repeated start is selected.
 244                          */
 245                         if ((id->recv_count < CDNS_I2C_FIFO_DEPTH) &&
 246                             !id->bus_hold_flag)
 247                                 cdns_i2c_clear_bus_hold(id);
 248
 249                         *(id->p_recv_buf)++ =
 250                                 cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET);
 251                         id->recv_count--;
 252                         id->curr_recv_count--;
 253
 254                         if (cdns_is_holdquirk(id, hold_quirk))
 255                                 break;
 256                 }
 257
 258                 /*
 259                  * The controller sends NACK to the slave when transfer size
 260                  * register reaches zero without considering the HOLD bit.
 261                  * This workaround is implemented for large data transfers to
 262                  * maintain transfer size non-zero while performing a large
 263                  * receive operation.
 264                  */
 265                 if (cdns_is_holdquirk(id, hold_quirk)) {
 266                         /* wait while fifo is full */
 267                         while (cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET) !=
 268                                (id->curr_recv_count - CDNS_I2C_FIFO_DEPTH))
 269                                 ;
 270
 271                         /*
 272                          * Check number of bytes to be received against maximum
 273                          * transfer size and update register accordingly.
 274                          */
 275                         if (((int)(id->recv_count) - CDNS_I2C_FIFO_DEPTH) >
 276                             CDNS_I2C_TRANSFER_SIZE) {
 277                                 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,
 278                                                   CDNS_I2C_XFER_SIZE_OFFSET);
 279                                 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE +
 280                                                       CDNS_I2C_FIFO_DEPTH;
 281                         } else {
 282                                 cdns_i2c_writereg(id->recv_count -
 283                                                   CDNS_I2C_FIFO_DEPTH,
 284                                                   CDNS_I2C_XFER_SIZE_OFFSET);
 285                                 id->curr_recv_count = id->recv_count;
 286                         }
 287                 } else if (id->recv_count && !hold_quirk &&
 288                                                 !id->curr_recv_count) {
 289
 290                         /* Set the slave address in address register*/
 291                         cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,
 292                                                 CDNS_I2C_ADDR_OFFSET);
 293
 294                         if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) {
 295                                 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,
 296                                                 CDNS_I2C_XFER_SIZE_OFFSET);
 297                                 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
 298                         } else {
 299                                 cdns_i2c_writereg(id->recv_count,
 300                                                 CDNS_I2C_XFER_SIZE_OFFSET);
 301                                 id->curr_recv_count = id->recv_count;
 302                         }
 303                 }
 304
 305                 /* Clear hold (if not repeated start) and signal completion */
 306                 if ((isr_status & CDNS_I2C_IXR_COMP) && !id->recv_count) {
 307                         if (!id->bus_hold_flag)
 308                                 cdns_i2c_clear_bus_hold(id);
 309                         done_flag = 1;
 310                 }
 311
 312                 status = IRQ_HANDLED;
 313         }
 314
 315         /* When sending, handle transfer complete interrupt */
 316         if ((isr_status & CDNS_I2C_IXR_COMP) && !id->p_recv_buf) {
 317                 /*
 318                  * If there is more data to be sent, calculate the
 319                  * space available in FIFO and fill with that many bytes.
 320                  */
 321                 if (id->send_count) {
 322                         avail_bytes = CDNS_I2C_FIFO_DEPTH -
 323                             cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
 324                         if (id->send_count > avail_bytes)
 325                                 bytes_to_send = avail_bytes;
 326                         else
 327                                 bytes_to_send = id->send_count;
 328
 329                         while (bytes_to_send--) {
 330                                 cdns_i2c_writereg(
 331                                         (*(id->p_send_buf)++),
 332                                          CDNS_I2C_DATA_OFFSET);
 333                                 id->send_count--;
 334                         }
 335                 } else {
 336                         /*
 337                          * Signal the completion of transaction and
 338                          * clear the hold bus bit if there are no
 339                          * further messages to be processed.
 340                          */
 341                         done_flag = 1;
 342                 }
 343                 if (!id->send_count && !id->bus_hold_flag)
 344                         cdns_i2c_clear_bus_hold(id);
 345
 346                 status = IRQ_HANDLED;
 347         }
 348
 349         /* Update the status for errors */
 350         id->err_status = isr_status & CDNS_I2C_IXR_ERR_INTR_MASK;
 351         if (id->err_status)
 352                 status = IRQ_HANDLED;
 353
 354         if (done_flag)
 355                 complete(&id->xfer_done);
 356
 357         return status;
 358 }
 359
 360 /**
 361  * cdns_i2c_mrecv - Prepare and start a master receive operation
 362  * @id:         pointer to the i2c device structure
 363  */
 364 static void cdns_i2c_mrecv(struct cdns_i2c *id)
 365 {
 366         unsigned int ctrl_reg;
 367         unsigned int isr_status;
 368
 369         id->p_recv_buf = id->p_msg->buf;
 370         id->recv_count = id->p_msg->len;
 371
 372         /* Put the controller in master receive mode and clear the FIFO */
 373         ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
 374         ctrl_reg |= CDNS_I2C_CR_RW | CDNS_I2C_CR_CLR_FIFO;
 375
 376         if (id->p_msg->flags & I2C_M_RECV_LEN)
 377                 id->recv_count = I2C_SMBUS_BLOCK_MAX + 1;
 378
 379         id->curr_recv_count = id->recv_count;
 380
 381         /*
 382          * Check for the message size against FIFO depth and set the
 383          * 'hold bus' bit if it is greater than FIFO depth.
 384          */
 385         if ((id->recv_count > CDNS_I2C_FIFO_DEPTH)  || id->bus_hold_flag)
 386                 ctrl_reg |= CDNS_I2C_CR_HOLD;
 387         else
 388                 ctrl_reg = ctrl_reg & ~CDNS_I2C_CR_HOLD;
 389
 390         cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
 391
 392         /* Clear the interrupts in interrupt status register */
 393         isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
 394         cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
 395
 396         /*
 397          * The no. of bytes to receive is checked against the limit of
 398          * max transfer size. Set transfer size register with no of bytes
 399          * receive if it is less than transfer size and transfer size if
 400          * it is more. Enable the interrupts.
 401          */
 402         if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) {
 403                 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,
 404                                   CDNS_I2C_XFER_SIZE_OFFSET);
 405                 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
 406         } else {
 407                 cdns_i2c_writereg(id->recv_count, CDNS_I2C_XFER_SIZE_OFFSET);
 408         }
 409
 410         /* Set the slave address in address register - triggers operation */
 411         cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,
 412                                                 CDNS_I2C_ADDR_OFFSET);
 413         /* Clear the bus hold flag if bytes to receive is less than FIFO size */
 414         if (!id->bus_hold_flag &&
 415                 ((id->p_msg->flags & I2C_M_RECV_LEN) != I2C_M_RECV_LEN) &&
 416                 (id->recv_count <= CDNS_I2C_FIFO_DEPTH))
 417                         cdns_i2c_clear_bus_hold(id);
 418         cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET);
 419 }
 420
 421 /**
 422  * cdns_i2c_msend - Prepare and start a master send operation
 423  * @id:         pointer to the i2c device
 424  */
 425 static void cdns_i2c_msend(struct cdns_i2c *id)
 426 {
 427         unsigned int avail_bytes;
 428         unsigned int bytes_to_send;
 429         unsigned int ctrl_reg;
 430         unsigned int isr_status;
 431
 432         id->p_recv_buf = NULL;
 433         id->p_send_buf = id->p_msg->buf;
 434         id->send_count = id->p_msg->len;
 435
 436         /* Set the controller in Master transmit mode and clear the FIFO. */
 437         ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
 438         ctrl_reg &= ~CDNS_I2C_CR_RW;
 439         ctrl_reg |= CDNS_I2C_CR_CLR_FIFO;
 440
 441         /*
 442          * Check for the message size against FIFO depth and set the
 443          * 'hold bus' bit if it is greater than FIFO depth.
 444          */
 445         if ((id->send_count > CDNS_I2C_FIFO_DEPTH) || id->bus_hold_flag)
 446                 ctrl_reg |= CDNS_I2C_CR_HOLD;
 447         else
 448                 ctrl_reg = ctrl_reg & ~CDNS_I2C_CR_HOLD;
 449
 450         cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
 451
 452         /* Clear the interrupts in interrupt status register. */
 453         isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
 454         cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
 455
 456         /*
 457          * Calculate the space available in FIFO. Check the message length
 458          * against the space available, and fill the FIFO accordingly.
 459          * Enable the interrupts.
 460          */
 461         avail_bytes = CDNS_I2C_FIFO_DEPTH -
 462                                 cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
 463
 464         if (id->send_count > avail_bytes)
 465                 bytes_to_send = avail_bytes;
 466         else
 467                 bytes_to_send = id->send_count;
 468
 469         while (bytes_to_send--) {
 470                 cdns_i2c_writereg((*(id->p_send_buf)++), CDNS_I2C_DATA_OFFSET);
 471                 id->send_count--;
 472         }
 473
 474         /*
 475          * Clear the bus hold flag if there is no more data
 476          * and if it is the last message.
 477          */
 478         if (!id->bus_hold_flag && !id->send_count)
 479                 cdns_i2c_clear_bus_hold(id);
 480         /* Set the slave address in address register - triggers operation. */
 481         cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,
 482                                                 CDNS_I2C_ADDR_OFFSET);
 483
 484         cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET);
 485 }
 486
 487 /**
 488  * cdns_i2c_master_reset - Reset the interface
 489  * @adap:       pointer to the i2c adapter driver instance
 490  *
 491  * This function cleanup the fifos, clear the hold bit and status
 492  * and disable the interrupts.
 493  */
 494 static void cdns_i2c_master_reset(struct i2c_adapter *adap)
 495 {
 496         struct cdns_i2c *id = adap->algo_data;
 497         u32 regval;
 498
 499         /* Disable the interrupts */
 500         cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET);
 501         /* Clear the hold bit and fifos */
 502         regval = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
 503         regval &= ~CDNS_I2C_CR_HOLD;
 504         regval |= CDNS_I2C_CR_CLR_FIFO;
 505         cdns_i2c_writereg(regval, CDNS_I2C_CR_OFFSET);
 506         /* Update the transfercount register to zero */
 507         cdns_i2c_writereg(0, CDNS_I2C_XFER_SIZE_OFFSET);
 508         /* Clear the interupt status register */
 509         regval = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
 510         cdns_i2c_writereg(regval, CDNS_I2C_ISR_OFFSET);
 511         /* Clear the status register */
 512         regval = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET);
 513         cdns_i2c_writereg(regval, CDNS_I2C_SR_OFFSET);
 514 }
 515
 516 static int cdns_i2c_process_msg(struct cdns_i2c *id, struct i2c_msg *msg,
 517                 struct i2c_adapter *adap)
 518 {
 519         unsigned long time_left;
 520         u32 reg;
 521
 522         id->p_msg = msg;
 523         id->err_status = 0;
 524         reinit_completion(&id->xfer_done);
 525
 526         /* Check for the TEN Bit mode on each msg */
 527         reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
 528         if (msg->flags & I2C_M_TEN) {
 529                 if (reg & CDNS_I2C_CR_NEA)
 530                         cdns_i2c_writereg(reg & ~CDNS_I2C_CR_NEA,
 531                                         CDNS_I2C_CR_OFFSET);
 532         } else {
 533                 if (!(reg & CDNS_I2C_CR_NEA))
 534                         cdns_i2c_writereg(reg | CDNS_I2C_CR_NEA,
 535                                         CDNS_I2C_CR_OFFSET);
 536         }
 537
 538         /* Check for the R/W flag on each msg */
 539         if (msg->flags & I2C_M_RD)
 540                 cdns_i2c_mrecv(id);
 541         else
 542                 cdns_i2c_msend(id);
 543
 544         /* Wait for the signal of completion */
 545         time_left = wait_for_completion_timeout(&id->xfer_done, adap->timeout);
 546         if (time_left == 0) {
 547                 cdns_i2c_master_reset(adap);
 548                 dev_err(id->adap.dev.parent,
 549                                 "timeout waiting on completion\n");
 550                 return -ETIMEDOUT;
 551         }
 552
 553         cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK,
 554                           CDNS_I2C_IDR_OFFSET);
 555
 556         /* If it is bus arbitration error, try again */
 557         if (id->err_status & CDNS_I2C_IXR_ARB_LOST)
 558                 return -EAGAIN;
 559
 560         return 0;
 561 }
 562
 563 /**
 564  * cdns_i2c_master_xfer - The main i2c transfer function
 565  * @adap:       pointer to the i2c adapter driver instance
 566  * @msgs:       pointer to the i2c message structure
 567  * @num:        the number of messages to transfer
 568  *
 569  * Initiates the send/recv activity based on the transfer message received.
 570  *
 571  * Return: number of msgs processed on success, negative error otherwise
 572  */
 573 static int cdns_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
 574                                 int num)
 575 {
 576         int ret, count;
 577         u32 reg;
 578         struct cdns_i2c *id = adap->algo_data;
 579         bool hold_quirk;
 580
 581         ret = pm_runtime_get_sync(id->dev);
 582         if (ret < 0)
 583                 return ret;
 584         /* Check if the bus is free */
 585         if (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) & CDNS_I2C_SR_BA) {
 586                 ret = -EAGAIN;
 587                 goto out;
 588         }
 589
 590         hold_quirk = !!(id->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
 591         /*
 592          * Set the flag to one when multiple messages are to be
 593          * processed with a repeated start.
 594          */
 595         if (num > 1) {
 596                 /*
 597                  * This controller does not give completion interrupt after a
 598                  * master receive message if HOLD bit is set (repeated start),
 599                  * resulting in SW timeout. Hence, if a receive message is
 600                  * followed by any other message, an error is returned
 601                  * indicating that this sequence is not supported.
 602                  */
 603                 for (count = 0; (count < num - 1 && hold_quirk); count++) {
 604                         if (msgs[count].flags & I2C_M_RD) {
 605                                 dev_warn(adap->dev.parent,
 606                                          "Can't do repeated start after a receive message\n");
 607                                 ret = -EOPNOTSUPP;
 608                                 goto out;
 609                         }
 610                 }
 611                 id->bus_hold_flag = 1;
 612                 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
 613                 reg |= CDNS_I2C_CR_HOLD;
 614                 cdns_i2c_writereg(reg, CDNS_I2C_CR_OFFSET);
 615         } else {
 616                 id->bus_hold_flag = 0;
 617         }
 618
 619         /* Process the msg one by one */
 620         for (count = 0; count < num; count++, msgs++) {
 621                 if (count == (num - 1))
 622                         id->bus_hold_flag = 0;
 623
 624                 ret = cdns_i2c_process_msg(id, msgs, adap);
 625                 if (ret)
 626                         goto out;
 627
 628                 /* Report the other error interrupts to application */
 629                 if (id->err_status) {
 630                         cdns_i2c_master_reset(adap);
 631
 632                         if (id->err_status & CDNS_I2C_IXR_NACK) {
 633                                 ret = -ENXIO;
 634                                 goto out;
 635                         }
 636                         ret = -EIO;
 637                         goto out;
 638                 }
 639         }
 640
 641         ret = num;
 642 out:
 643         pm_runtime_mark_last_busy(id->dev);
 644         pm_runtime_put_autosuspend(id->dev);
 645         return ret;
 646 }
 647
 648 /**
 649  * cdns_i2c_func - Returns the supported features of the I2C driver
 650  * @adap:       pointer to the i2c adapter structure
 651  *
 652  * Return: 32 bit value, each bit corresponding to a feature
 653  */
 654 static u32 cdns_i2c_func(struct i2c_adapter *adap)
 655 {
 656         return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR |
 657                 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
 658                 I2C_FUNC_SMBUS_BLOCK_DATA;
 659 }
 660
 661 static const struct i2c_algorithm cdns_i2c_algo = {
 662         .master_xfer    = cdns_i2c_master_xfer,
 663         .functionality  = cdns_i2c_func,
 664 };
 665
 666 /**
 667  * cdns_i2c_calc_divs - Calculate clock dividers
 668  * @f:          I2C clock frequency
 669  * @input_clk:  Input clock frequency
 670  * @a:          First divider (return value)
 671  * @b:          Second divider (return value)
 672  *
 673  * f is used as input and output variable. As input it is used as target I2C
 674  * frequency. On function exit f holds the actually resulting I2C frequency.
 675  *
 676  * Return: 0 on success, negative errno otherwise.
 677  */
 678 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk,
 679                 unsigned int *a, unsigned int *b)
 680 {
 681         unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp;
 682         unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0;
 683         unsigned int last_error, current_error;
 684
 685         /* calculate (divisor_a+1) x (divisor_b+1) */
 686         temp = input_clk / (22 * fscl);
 687
 688         /*
 689          * If the calculated value is negative or 0, the fscl input is out of
 690          * range. Return error.
 691          */
 692         if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX)))
 693                 return -EINVAL;
 694
 695         last_error = -1;
 696         for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) {
 697                 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1));
 698
 699                 if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX))
 700                         continue;
 701                 div_b--;
 702
 703                 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1));
 704
 705                 if (actual_fscl > fscl)
 706                         continue;
 707
 708                 current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) :
 709                                                         (fscl - actual_fscl));
 710
 711                 if (last_error > current_error) {
 712                         calc_div_a = div_a;
 713                         calc_div_b = div_b;
 714                         best_fscl = actual_fscl;
 715                         last_error = current_error;
 716                 }
 717         }
 718
 719         *a = calc_div_a;
 720         *b = calc_div_b;
 721         *f = best_fscl;
 722
 723         return 0;
 724 }
 725
 726 /**
 727  * cdns_i2c_setclk - This function sets the serial clock rate for the I2C device
 728  * @clk_in:     I2C clock input frequency in Hz
 729  * @id:         Pointer to the I2C device structure
 730  *
 731  * The device must be idle rather than busy transferring data before setting
 732  * these device options.
 733  * The data rate is set by values in the control register.
 734  * The formula for determining the correct register values is
 735  *      Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
 736  * See the hardware data sheet for a full explanation of setting the serial
 737  * clock rate. The clock can not be faster than the input clock divide by 22.
 738  * The two most common clock rates are 100KHz and 400KHz.
 739  *
 740  * Return: 0 on success, negative error otherwise
 741  */
 742 static int cdns_i2c_setclk(unsigned long clk_in, struct cdns_i2c *id)
 743 {
 744         unsigned int div_a, div_b;
 745         unsigned int ctrl_reg;
 746         int ret = 0;
 747         unsigned long fscl = id->i2c_clk;
 748
 749         ret = cdns_i2c_calc_divs(&fscl, clk_in, &div_a, &div_b);
 750         if (ret)
 751                 return ret;
 752
 753         ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
 754         ctrl_reg &= ~(CDNS_I2C_CR_DIVA_MASK | CDNS_I2C_CR_DIVB_MASK);
 755         ctrl_reg |= ((div_a << CDNS_I2C_CR_DIVA_SHIFT) |
 756                         (div_b << CDNS_I2C_CR_DIVB_SHIFT));
 757         cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
 758
 759         return 0;
 760 }
 761
 762 /**
 763  * cdns_i2c_clk_notifier_cb - Clock rate change callback
 764  * @nb:         Pointer to notifier block
 765  * @event:      Notification reason
 766  * @data:       Pointer to notification data object
 767  *
 768  * This function is called when the cdns_i2c input clock frequency changes.
 769  * The callback checks whether a valid bus frequency can be generated after the
 770  * change. If so, the change is acknowledged, otherwise the change is aborted.
 771  * New dividers are written to the HW in the pre- or post change notification
 772  * depending on the scaling direction.
 773  *
 774  * Return:      NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK
 775  *              to acknowledge the change, NOTIFY_DONE if the notification is
 776  *              considered irrelevant.
 777  */
 778 static int cdns_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long
 779                 event, void *data)
 780 {
 781         struct clk_notifier_data *ndata = data;
 782         struct cdns_i2c *id = to_cdns_i2c(nb);
 783
 784         if (pm_runtime_suspended(id->dev))
 785                 return NOTIFY_OK;
 786
 787         switch (event) {
 788         case PRE_RATE_CHANGE:
 789         {
 790                 unsigned long input_clk = ndata->new_rate;
 791                 unsigned long fscl = id->i2c_clk;
 792                 unsigned int div_a, div_b;
 793                 int ret;
 794
 795                 ret = cdns_i2c_calc_divs(&fscl, input_clk, &div_a, &div_b);
 796                 if (ret) {
 797                         dev_warn(id->adap.dev.parent,
 798                                         "clock rate change rejected\n");
 799                         return NOTIFY_STOP;
 800                 }
 801
 802                 /* scale up */
 803                 if (ndata->new_rate > ndata->old_rate)
 804                         cdns_i2c_setclk(ndata->new_rate, id);
 805
 806                 return NOTIFY_OK;
 807         }
 808         case POST_RATE_CHANGE:
 809                 id->input_clk = ndata->new_rate;
 810                 /* scale down */
 811                 if (ndata->new_rate < ndata->old_rate)
 812                         cdns_i2c_setclk(ndata->new_rate, id);
 813                 return NOTIFY_OK;
 814         case ABORT_RATE_CHANGE:
 815                 /* scale up */
 816                 if (ndata->new_rate > ndata->old_rate)
 817                         cdns_i2c_setclk(ndata->old_rate, id);
 818                 return NOTIFY_OK;
 819         default:
 820                 return NOTIFY_DONE;
 821         }
 822 }
 823
 824 /**
 825  * cdns_i2c_runtime_suspend -  Runtime suspend method for the driver
 826  * @dev:        Address of the platform_device structure
 827  *
 828  * Put the driver into low power mode.
 829  *
 830  * Return: 0 always
 831  */
 832 static int __maybe_unused cdns_i2c_runtime_suspend(struct device *dev)
 833 {
 834         struct cdns_i2c *xi2c = dev_get_drvdata(dev);
 835
 836         clk_disable(xi2c->clk);
 837
 838         return 0;
 839 }
 840
 841 /**
 842  * cdns_i2c_runtime_resume - Runtime resume
 843  * @dev:        Address of the platform_device structure
 844  *
 845  * Runtime resume callback.
 846  *
 847  * Return: 0 on success and error value on error
 848  */
 849 static int __maybe_unused cdns_i2c_runtime_resume(struct device *dev)
 850 {
 851         struct cdns_i2c *xi2c = dev_get_drvdata(dev);
 852         int ret;
 853
 854         ret = clk_enable(xi2c->clk);
 855         if (ret) {
 856                 dev_err(dev, "Cannot enable clock.\n");
 857                 return ret;
 858         }
 859
 860         return 0;
 861 }
 862
 863 static const struct dev_pm_ops cdns_i2c_dev_pm_ops = {
 864         SET_RUNTIME_PM_OPS(cdns_i2c_runtime_suspend,
 865                            cdns_i2c_runtime_resume, NULL)
 866 };
 867
 868 static const struct cdns_platform_data r1p10_i2c_def = {
 869         .quirks = CDNS_I2C_BROKEN_HOLD_BIT,
 870 };
 871
 872 static const struct of_device_id cdns_i2c_of_match[] = {
 873         { .compatible = "cdns,i2c-r1p10", .data = &r1p10_i2c_def },
 874         { .compatible = "cdns,i2c-r1p14",},
 875         { /* end of table */ }
 876 };
 877 MODULE_DEVICE_TABLE(of, cdns_i2c_of_match);
 878
 879 /**
 880  * cdns_i2c_probe - Platform registration call
 881  * @pdev:       Handle to the platform device structure
 882  *
 883  * This function does all the memory allocation and registration for the i2c
 884  * device. User can modify the address mode to 10 bit address mode using the
 885  * ioctl call with option I2C_TENBIT.
 886  *
 887  * Return: 0 on success, negative error otherwise
 888  */
 889 static int cdns_i2c_probe(struct platform_device *pdev)
 890 {
 891         struct resource *r_mem;
 892         struct cdns_i2c *id;
 893         int ret;
 894         const struct of_device_id *match;
 895
 896         id = devm_kzalloc(&pdev->dev, sizeof(*id), GFP_KERNEL);
 897         if (!id)
 898                 return -ENOMEM;
 899
 900         id->dev = &pdev->dev;
 901         platform_set_drvdata(pdev, id);
 902
 903         match = of_match_node(cdns_i2c_of_match, pdev->dev.of_node);
 904         if (match && match->data) {
 905                 const struct cdns_platform_data *data = match->data;
 906                 id->quirks = data->quirks;
 907         }
 908
 909         r_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 910         id->membase = devm_ioremap_resource(&pdev->dev, r_mem);
 911         if (IS_ERR(id->membase))
 912                 return PTR_ERR(id->membase);
 913
 914         id->irq = platform_get_irq(pdev, 0);
 915
 916         id->adap.owner = THIS_MODULE;
 917         id->adap.dev.of_node = pdev->dev.of_node;
 918         id->adap.algo = &cdns_i2c_algo;
 919         id->adap.timeout = CDNS_I2C_TIMEOUT;
 920         id->adap.retries = 3;           /* Default retry value. */
 921         id->adap.algo_data = id;
 922         id->adap.dev.parent = &pdev->dev;
 923         init_completion(&id->xfer_done);
 924         snprintf(id->adap.name, sizeof(id->adap.name),
 925                  "Cadence I2C at %08lx", (unsigned long)r_mem->start);
 926
 927         id->clk = devm_clk_get(&pdev->dev, NULL);
 928         if (IS_ERR(id->clk)) {
 929                 dev_err(&pdev->dev, "input clock not found.\n");
 930                 return PTR_ERR(id->clk);
 931         }
 932         ret = clk_prepare_enable(id->clk);
 933         if (ret)
 934                 dev_err(&pdev->dev, "Unable to enable clock.\n");
 935
 936         pm_runtime_enable(id->dev);
 937         pm_runtime_set_autosuspend_delay(id->dev, CNDS_I2C_PM_TIMEOUT);
 938         pm_runtime_use_autosuspend(id->dev);
 939         pm_runtime_set_active(id->dev);
 940
 941         id->clk_rate_change_nb.notifier_call = cdns_i2c_clk_notifier_cb;
 942         if (clk_notifier_register(id->clk, &id->clk_rate_change_nb))
 943                 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
 944         id->input_clk = clk_get_rate(id->clk);
 945
 946         ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
 947                         &id->i2c_clk);
 948         if (ret || (id->i2c_clk > CDNS_I2C_SPEED_MAX))
 949                 id->i2c_clk = CDNS_I2C_SPEED_DEFAULT;
 950
 951         cdns_i2c_writereg(CDNS_I2C_CR_ACK_EN | CDNS_I2C_CR_NEA | CDNS_I2C_CR_MS,
 952                           CDNS_I2C_CR_OFFSET);
 953
 954         ret = cdns_i2c_setclk(id->input_clk, id);
 955         if (ret) {
 956                 dev_err(&pdev->dev, "invalid SCL clock: %u Hz\n", id->i2c_clk);
 957                 ret = -EINVAL;
 958                 goto err_clk_dis;
 959         }
 960
 961         ret = devm_request_irq(&pdev->dev, id->irq, cdns_i2c_isr, 0,
 962                                  DRIVER_NAME, id);
 963         if (ret) {
 964                 dev_err(&pdev->dev, "cannot get irq %d\n", id->irq);
 965                 goto err_clk_dis;
 966         }
 967
 968         /*
 969          * Cadence I2C controller has a bug wherein it generates
 970          * invalid read transaction after HW timeout in master receiver mode.
 971          * HW timeout is not used by this driver and the interrupt is disabled.
 972          * But the feature itself cannot be disabled. Hence maximum value
 973          * is written to this register to reduce the chances of error.
 974          */
 975         cdns_i2c_writereg(CDNS_I2C_TIMEOUT_MAX, CDNS_I2C_TIME_OUT_OFFSET);
 976
 977         ret = i2c_add_adapter(&id->adap);
 978         if (ret < 0)
 979                 goto err_clk_dis;
 980
 981         dev_info(&pdev->dev, "%u kHz mmio %08lx irq %d\n",
 982                  id->i2c_clk / 1000, (unsigned long)r_mem->start, id->irq);
 983
 984         return 0;
 985
 986 err_clk_dis:
 987         clk_disable_unprepare(id->clk);
 988         pm_runtime_set_suspended(&pdev->dev);
 989         pm_runtime_disable(&pdev->dev);
 990         return ret;
 991 }
 992
 993 /**
 994  * cdns_i2c_remove - Unregister the device after releasing the resources
 995  * @pdev:       Handle to the platform device structure
 996  *
 997  * This function frees all the resources allocated to the device.
 998  *
 999  * Return: 0 always
1000  */
1001 static int cdns_i2c_remove(struct platform_device *pdev)
1002 {
1003         struct cdns_i2c *id = platform_get_drvdata(pdev);
1004
1005         i2c_del_adapter(&id->adap);
1006         clk_notifier_unregister(id->clk, &id->clk_rate_change_nb);
1007         clk_disable_unprepare(id->clk);
1008         pm_runtime_disable(&pdev->dev);
1009
1010         return 0;
1011 }
1012
1013 static struct platform_driver cdns_i2c_drv = {
1014         .driver = {
1015                 .name  = DRIVER_NAME,
1016                 .of_match_table = cdns_i2c_of_match,
1017                 .pm = &cdns_i2c_dev_pm_ops,
1018         },
1019         .probe  = cdns_i2c_probe,
1020         .remove = cdns_i2c_remove,
1021 };
1022
1023 module_platform_driver(cdns_i2c_drv);
1024
1025 MODULE_AUTHOR("Xilinx Inc.");
1026 MODULE_DESCRIPTION("Cadence I2C bus driver");
1027 MODULE_LICENSE("GPL");