1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * I2C bus driver for the Cadence I2C controller.
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
9 #include <linux/delay.h>
10 #include <linux/i2c.h>
11 #include <linux/interrupt.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
18 /* Register offsets for the I2C device. */
19 #define CDNS_I2C_CR_OFFSET 0x00 /* Control Register, RW */
20 #define CDNS_I2C_SR_OFFSET 0x04 /* Status Register, RO */
21 #define CDNS_I2C_ADDR_OFFSET 0x08 /* I2C Address Register, RW */
22 #define CDNS_I2C_DATA_OFFSET 0x0C /* I2C Data Register, RW */
23 #define CDNS_I2C_ISR_OFFSET 0x10 /* IRQ Status Register, RW */
24 #define CDNS_I2C_XFER_SIZE_OFFSET 0x14 /* Transfer Size Register, RW */
25 #define CDNS_I2C_TIME_OUT_OFFSET 0x1C /* Time Out Register, RW */
26 #define CDNS_I2C_IMR_OFFSET 0x20 /* IRQ Mask Register, RO */
27 #define CDNS_I2C_IER_OFFSET 0x24 /* IRQ Enable Register, WO */
28 #define CDNS_I2C_IDR_OFFSET 0x28 /* IRQ Disable Register, WO */
30 /* Control Register Bit mask definitions */
31 #define CDNS_I2C_CR_HOLD BIT(4) /* Hold Bus bit */
32 #define CDNS_I2C_CR_ACK_EN BIT(3)
33 #define CDNS_I2C_CR_NEA BIT(2)
34 #define CDNS_I2C_CR_MS BIT(1)
35 /* Read or Write Master transfer 0 = Transmitter, 1 = Receiver */
36 #define CDNS_I2C_CR_RW BIT(0)
37 /* 1 = Auto init FIFO to zeroes */
38 #define CDNS_I2C_CR_CLR_FIFO BIT(6)
39 #define CDNS_I2C_CR_DIVA_SHIFT 14
40 #define CDNS_I2C_CR_DIVA_MASK (3 << CDNS_I2C_CR_DIVA_SHIFT)
41 #define CDNS_I2C_CR_DIVB_SHIFT 8
42 #define CDNS_I2C_CR_DIVB_MASK (0x3f << CDNS_I2C_CR_DIVB_SHIFT)
44 #define CDNS_I2C_CR_MASTER_EN_MASK (CDNS_I2C_CR_NEA | \
45 CDNS_I2C_CR_ACK_EN | \
48 #define CDNS_I2C_CR_SLAVE_EN_MASK ~CDNS_I2C_CR_MASTER_EN_MASK
50 /* Status Register Bit mask definitions */
51 #define CDNS_I2C_SR_BA BIT(8)
52 #define CDNS_I2C_SR_TXDV BIT(6)
53 #define CDNS_I2C_SR_RXDV BIT(5)
54 #define CDNS_I2C_SR_RXRW BIT(3)
57 * I2C Address Register Bit mask definitions
58 * Normal addressing mode uses [6:0] bits. Extended addressing mode uses [9:0]
59 * bits. A write access to this register always initiates a transfer if the I2C
62 #define CDNS_I2C_ADDR_MASK 0x000003FF /* I2C Address Mask */
65 * I2C Interrupt Registers Bit mask definitions
66 * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
69 #define CDNS_I2C_IXR_ARB_LOST BIT(9)
70 #define CDNS_I2C_IXR_RX_UNF BIT(7)
71 #define CDNS_I2C_IXR_TX_OVF BIT(6)
72 #define CDNS_I2C_IXR_RX_OVF BIT(5)
73 #define CDNS_I2C_IXR_SLV_RDY BIT(4)
74 #define CDNS_I2C_IXR_TO BIT(3)
75 #define CDNS_I2C_IXR_NACK BIT(2)
76 #define CDNS_I2C_IXR_DATA BIT(1)
77 #define CDNS_I2C_IXR_COMP BIT(0)
79 #define CDNS_I2C_IXR_ALL_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \
80 CDNS_I2C_IXR_RX_UNF | \
81 CDNS_I2C_IXR_TX_OVF | \
82 CDNS_I2C_IXR_RX_OVF | \
83 CDNS_I2C_IXR_SLV_RDY | \
89 #define CDNS_I2C_IXR_ERR_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \
90 CDNS_I2C_IXR_RX_UNF | \
91 CDNS_I2C_IXR_TX_OVF | \
92 CDNS_I2C_IXR_RX_OVF | \
95 #define CDNS_I2C_ENABLED_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \
96 CDNS_I2C_IXR_RX_UNF | \
97 CDNS_I2C_IXR_TX_OVF | \
98 CDNS_I2C_IXR_RX_OVF | \
100 CDNS_I2C_IXR_DATA | \
103 #define CDNS_I2C_IXR_SLAVE_INTR_MASK (CDNS_I2C_IXR_RX_UNF | \
104 CDNS_I2C_IXR_TX_OVF | \
105 CDNS_I2C_IXR_RX_OVF | \
107 CDNS_I2C_IXR_NACK | \
108 CDNS_I2C_IXR_DATA | \
111 #define CDNS_I2C_TIMEOUT msecs_to_jiffies(1000)
112 /* timeout for pm runtime autosuspend */
113 #define CNDS_I2C_PM_TIMEOUT 1000 /* ms */
115 #define CDNS_I2C_FIFO_DEPTH 16
116 /* FIFO depth at which the DATA interrupt occurs */
117 #define CDNS_I2C_DATA_INTR_DEPTH (CDNS_I2C_FIFO_DEPTH - 2)
118 #define CDNS_I2C_MAX_TRANSFER_SIZE 255
119 /* Transfer size in multiples of data interrupt depth */
120 #define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_MAX_TRANSFER_SIZE - 3)
122 #define DRIVER_NAME "cdns-i2c"
124 #define CDNS_I2C_DIVA_MAX 4
125 #define CDNS_I2C_DIVB_MAX 64
127 #define CDNS_I2C_TIMEOUT_MAX 0xFF
129 #define CDNS_I2C_BROKEN_HOLD_BIT BIT(0)
131 #define cdns_i2c_readreg(offset) readl_relaxed(id->membase + offset)
132 #define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset)
134 #if IS_ENABLED(CONFIG_I2C_SLAVE)
136 * enum cdns_i2c_mode - I2C Controller current operating mode
138 * @CDNS_I2C_MODE_SLAVE: I2C controller operating in slave mode
139 * @CDNS_I2C_MODE_MASTER: I2C Controller operating in master mode
143 CDNS_I2C_MODE_MASTER,
147 * enum cdns_i2c_slave_mode - Slave state when I2C is operating in slave mode
149 * @CDNS_I2C_SLAVE_STATE_IDLE: I2C slave idle
150 * @CDNS_I2C_SLAVE_STATE_SEND: I2C slave sending data to master
151 * @CDNS_I2C_SLAVE_STATE_RECV: I2C slave receiving data from master
153 enum cdns_i2c_slave_state {
154 CDNS_I2C_SLAVE_STATE_IDLE,
155 CDNS_I2C_SLAVE_STATE_SEND,
156 CDNS_I2C_SLAVE_STATE_RECV,
161 * struct cdns_i2c - I2C device private data structure
163 * @dev: Pointer to device structure
164 * @membase: Base address of the I2C device
165 * @adap: I2C adapter instance
166 * @p_msg: Message pointer
167 * @err_status: Error status in Interrupt Status Register
168 * @xfer_done: Transfer complete status
169 * @p_send_buf: Pointer to transmit buffer
170 * @p_recv_buf: Pointer to receive buffer
171 * @send_count: Number of bytes still expected to send
172 * @recv_count: Number of bytes still expected to receive
173 * @curr_recv_count: Number of bytes to be received in current transfer
175 * @input_clk: Input clock to I2C controller
176 * @i2c_clk: Maximum I2C clock speed
177 * @bus_hold_flag: Flag used in repeated start for clearing HOLD bit
178 * @clk: Pointer to struct clk
179 * @clk_rate_change_nb: Notifier block for clock rate changes
180 * @quirks: flag for broken hold bit usage in r1p10
181 * @ctrl_reg_diva_divb: value of fields DIV_A and DIV_B from CR register
182 * @slave: Registered slave instance.
183 * @dev_mode: I2C operating role(master/slave).
184 * @slave_state: I2C Slave state(idle/read/write).
188 void __iomem *membase;
189 struct i2c_adapter adap;
190 struct i2c_msg *p_msg;
192 struct completion xfer_done;
193 unsigned char *p_send_buf;
194 unsigned char *p_recv_buf;
195 unsigned int send_count;
196 unsigned int recv_count;
197 unsigned int curr_recv_count;
199 unsigned long input_clk;
200 unsigned int i2c_clk;
201 unsigned int bus_hold_flag;
203 struct notifier_block clk_rate_change_nb;
205 #if IS_ENABLED(CONFIG_I2C_SLAVE)
206 u16 ctrl_reg_diva_divb;
207 struct i2c_client *slave;
208 enum cdns_i2c_mode dev_mode;
209 enum cdns_i2c_slave_state slave_state;
213 struct cdns_platform_data {
217 #define to_cdns_i2c(_nb) container_of(_nb, struct cdns_i2c, \
221 * cdns_i2c_clear_bus_hold - Clear bus hold bit
222 * @id: Pointer to driver data struct
224 * Helper to clear the controller's bus hold bit.
226 static void cdns_i2c_clear_bus_hold(struct cdns_i2c *id)
228 u32 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
229 if (reg & CDNS_I2C_CR_HOLD)
230 cdns_i2c_writereg(reg & ~CDNS_I2C_CR_HOLD, CDNS_I2C_CR_OFFSET);
233 static inline bool cdns_is_holdquirk(struct cdns_i2c *id, bool hold_wrkaround)
235 return (hold_wrkaround &&
236 (id->curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1));
239 #if IS_ENABLED(CONFIG_I2C_SLAVE)
240 static void cdns_i2c_set_mode(enum cdns_i2c_mode mode, struct cdns_i2c *id)
242 /* Disable all interrupts */
243 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET);
245 /* Clear FIFO and transfer size */
246 cdns_i2c_writereg(CDNS_I2C_CR_CLR_FIFO, CDNS_I2C_CR_OFFSET);
248 /* Update device mode and state */
250 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
253 case CDNS_I2C_MODE_MASTER:
254 /* Enable i2c master */
255 cdns_i2c_writereg(id->ctrl_reg_diva_divb |
256 CDNS_I2C_CR_MASTER_EN_MASK,
259 * This delay is needed to give the IP some time to switch to
260 * the master mode. With lower values(like 110 us) i2cdetect
261 * will not detect any slave and without this delay, the IP will
262 * trigger a timeout interrupt.
264 usleep_range(115, 125);
266 case CDNS_I2C_MODE_SLAVE:
267 /* Enable i2c slave */
268 cdns_i2c_writereg(id->ctrl_reg_diva_divb &
269 CDNS_I2C_CR_SLAVE_EN_MASK,
272 /* Setting slave address */
273 cdns_i2c_writereg(id->slave->addr & CDNS_I2C_ADDR_MASK,
274 CDNS_I2C_ADDR_OFFSET);
276 /* Enable slave send/receive interrupts */
277 cdns_i2c_writereg(CDNS_I2C_IXR_SLAVE_INTR_MASK,
278 CDNS_I2C_IER_OFFSET);
283 static void cdns_i2c_slave_rcv_data(struct cdns_i2c *id)
288 /* Prepare backend for data reception */
289 if (id->slave_state == CDNS_I2C_SLAVE_STATE_IDLE) {
290 id->slave_state = CDNS_I2C_SLAVE_STATE_RECV;
291 i2c_slave_event(id->slave, I2C_SLAVE_WRITE_REQUESTED, NULL);
294 /* Fetch number of bytes to receive */
295 bytes = cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
297 /* Read data and send to backend */
299 data = cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET);
300 i2c_slave_event(id->slave, I2C_SLAVE_WRITE_RECEIVED, &data);
304 static void cdns_i2c_slave_send_data(struct cdns_i2c *id)
308 /* Prepare backend for data transmission */
309 if (id->slave_state == CDNS_I2C_SLAVE_STATE_IDLE) {
310 id->slave_state = CDNS_I2C_SLAVE_STATE_SEND;
311 i2c_slave_event(id->slave, I2C_SLAVE_READ_REQUESTED, &data);
313 i2c_slave_event(id->slave, I2C_SLAVE_READ_PROCESSED, &data);
316 /* Send data over bus */
317 cdns_i2c_writereg(data, CDNS_I2C_DATA_OFFSET);
321 * cdns_i2c_slave_isr - Interrupt handler for the I2C device in slave role
322 * @ptr: Pointer to I2C device private data
324 * This function handles the data interrupt and transfer complete interrupt of
325 * the I2C device in slave role.
327 * Return: IRQ_HANDLED always
329 static irqreturn_t cdns_i2c_slave_isr(void *ptr)
331 struct cdns_i2c *id = ptr;
332 unsigned int isr_status, i2c_status;
334 /* Fetch the interrupt status */
335 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
336 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
338 /* Ignore masked interrupts */
339 isr_status &= ~cdns_i2c_readreg(CDNS_I2C_IMR_OFFSET);
341 /* Fetch transfer mode (send/receive) */
342 i2c_status = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET);
344 /* Handle data send/receive */
345 if (i2c_status & CDNS_I2C_SR_RXRW) {
346 /* Send data to master */
347 if (isr_status & CDNS_I2C_IXR_DATA)
348 cdns_i2c_slave_send_data(id);
350 if (isr_status & CDNS_I2C_IXR_COMP) {
351 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
352 i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL);
355 /* Receive data from master */
356 if (isr_status & CDNS_I2C_IXR_DATA)
357 cdns_i2c_slave_rcv_data(id);
359 if (isr_status & CDNS_I2C_IXR_COMP) {
360 cdns_i2c_slave_rcv_data(id);
361 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
362 i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL);
366 /* Master indicated xfer stop or fifo underflow/overflow */
367 if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_RX_OVF |
368 CDNS_I2C_IXR_RX_UNF | CDNS_I2C_IXR_TX_OVF)) {
369 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
370 i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL);
371 cdns_i2c_writereg(CDNS_I2C_CR_CLR_FIFO, CDNS_I2C_CR_OFFSET);
379 * cdns_i2c_master_isr - Interrupt handler for the I2C device in master role
380 * @ptr: Pointer to I2C device private data
382 * This function handles the data interrupt, transfer complete interrupt and
383 * the error interrupts of the I2C device in master role.
385 * Return: IRQ_HANDLED always
387 static irqreturn_t cdns_i2c_master_isr(void *ptr)
389 unsigned int isr_status, avail_bytes, updatetx;
390 unsigned int bytes_to_send;
392 struct cdns_i2c *id = ptr;
393 /* Signal completion only after everything is updated */
395 irqreturn_t status = IRQ_NONE;
397 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
398 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
401 /* Handling nack and arbitration lost interrupt */
402 if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_ARB_LOST)) {
404 status = IRQ_HANDLED;
408 * Check if transfer size register needs to be updated again for a
409 * large data receive operation.
412 if (id->recv_count > id->curr_recv_count)
415 hold_quirk = (id->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx;
417 /* When receiving, handle data interrupt and completion interrupt */
418 if (id->p_recv_buf &&
419 ((isr_status & CDNS_I2C_IXR_COMP) ||
420 (isr_status & CDNS_I2C_IXR_DATA))) {
421 /* Read data if receive data valid is set */
422 while (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) &
425 * Clear hold bit that was set for FIFO control if
426 * RX data left is less than FIFO depth, unless
427 * repeated start is selected.
429 if ((id->recv_count < CDNS_I2C_FIFO_DEPTH) &&
431 cdns_i2c_clear_bus_hold(id);
433 if (id->recv_count > 0) {
434 *(id->p_recv_buf)++ =
435 cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET);
437 id->curr_recv_count--;
439 dev_err(id->adap.dev.parent,
440 "xfer_size reg rollover. xfer aborted!\n");
441 id->err_status |= CDNS_I2C_IXR_TO;
445 if (cdns_is_holdquirk(id, hold_quirk))
450 * The controller sends NACK to the slave when transfer size
451 * register reaches zero without considering the HOLD bit.
452 * This workaround is implemented for large data transfers to
453 * maintain transfer size non-zero while performing a large
456 if (cdns_is_holdquirk(id, hold_quirk)) {
457 /* wait while fifo is full */
458 while (cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET) !=
459 (id->curr_recv_count - CDNS_I2C_FIFO_DEPTH))
463 * Check number of bytes to be received against maximum
464 * transfer size and update register accordingly.
466 if (((int)(id->recv_count) - CDNS_I2C_FIFO_DEPTH) >
467 CDNS_I2C_TRANSFER_SIZE) {
468 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,
469 CDNS_I2C_XFER_SIZE_OFFSET);
470 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE +
473 cdns_i2c_writereg(id->recv_count -
475 CDNS_I2C_XFER_SIZE_OFFSET);
476 id->curr_recv_count = id->recv_count;
478 } else if (id->recv_count && !hold_quirk &&
479 !id->curr_recv_count) {
481 /* Set the slave address in address register*/
482 cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,
483 CDNS_I2C_ADDR_OFFSET);
485 if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) {
486 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,
487 CDNS_I2C_XFER_SIZE_OFFSET);
488 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
490 cdns_i2c_writereg(id->recv_count,
491 CDNS_I2C_XFER_SIZE_OFFSET);
492 id->curr_recv_count = id->recv_count;
496 /* Clear hold (if not repeated start) and signal completion */
497 if ((isr_status & CDNS_I2C_IXR_COMP) && !id->recv_count) {
498 if (!id->bus_hold_flag)
499 cdns_i2c_clear_bus_hold(id);
503 status = IRQ_HANDLED;
506 /* When sending, handle transfer complete interrupt */
507 if ((isr_status & CDNS_I2C_IXR_COMP) && !id->p_recv_buf) {
509 * If there is more data to be sent, calculate the
510 * space available in FIFO and fill with that many bytes.
512 if (id->send_count) {
513 avail_bytes = CDNS_I2C_FIFO_DEPTH -
514 cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
515 if (id->send_count > avail_bytes)
516 bytes_to_send = avail_bytes;
518 bytes_to_send = id->send_count;
520 while (bytes_to_send--) {
522 (*(id->p_send_buf)++),
523 CDNS_I2C_DATA_OFFSET);
528 * Signal the completion of transaction and
529 * clear the hold bus bit if there are no
530 * further messages to be processed.
534 if (!id->send_count && !id->bus_hold_flag)
535 cdns_i2c_clear_bus_hold(id);
537 status = IRQ_HANDLED;
540 /* Update the status for errors */
541 id->err_status |= isr_status & CDNS_I2C_IXR_ERR_INTR_MASK;
543 status = IRQ_HANDLED;
546 complete(&id->xfer_done);
552 * cdns_i2c_isr - Interrupt handler for the I2C device
553 * @irq: irq number for the I2C device
554 * @ptr: void pointer to cdns_i2c structure
556 * This function passes the control to slave/master based on current role of
559 * Return: IRQ_HANDLED always
561 static irqreturn_t cdns_i2c_isr(int irq, void *ptr)
563 #if IS_ENABLED(CONFIG_I2C_SLAVE)
564 struct cdns_i2c *id = ptr;
566 if (id->dev_mode == CDNS_I2C_MODE_SLAVE)
567 return cdns_i2c_slave_isr(ptr);
569 return cdns_i2c_master_isr(ptr);
573 * cdns_i2c_mrecv - Prepare and start a master receive operation
574 * @id: pointer to the i2c device structure
576 static void cdns_i2c_mrecv(struct cdns_i2c *id)
578 unsigned int ctrl_reg;
579 unsigned int isr_status;
581 id->p_recv_buf = id->p_msg->buf;
582 id->recv_count = id->p_msg->len;
584 /* Put the controller in master receive mode and clear the FIFO */
585 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
586 ctrl_reg |= CDNS_I2C_CR_RW | CDNS_I2C_CR_CLR_FIFO;
588 if (id->p_msg->flags & I2C_M_RECV_LEN)
589 id->recv_count = I2C_SMBUS_BLOCK_MAX + 1;
591 id->curr_recv_count = id->recv_count;
594 * Check for the message size against FIFO depth and set the
595 * 'hold bus' bit if it is greater than FIFO depth.
597 if (id->recv_count > CDNS_I2C_FIFO_DEPTH)
598 ctrl_reg |= CDNS_I2C_CR_HOLD;
600 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
602 /* Clear the interrupts in interrupt status register */
603 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
604 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
607 * The no. of bytes to receive is checked against the limit of
608 * max transfer size. Set transfer size register with no of bytes
609 * receive if it is less than transfer size and transfer size if
610 * it is more. Enable the interrupts.
612 if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) {
613 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,
614 CDNS_I2C_XFER_SIZE_OFFSET);
615 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
617 cdns_i2c_writereg(id->recv_count, CDNS_I2C_XFER_SIZE_OFFSET);
620 /* Set the slave address in address register - triggers operation */
621 cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,
622 CDNS_I2C_ADDR_OFFSET);
623 /* Clear the bus hold flag if bytes to receive is less than FIFO size */
624 if (!id->bus_hold_flag &&
625 ((id->p_msg->flags & I2C_M_RECV_LEN) != I2C_M_RECV_LEN) &&
626 (id->recv_count <= CDNS_I2C_FIFO_DEPTH))
627 cdns_i2c_clear_bus_hold(id);
628 cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET);
632 * cdns_i2c_msend - Prepare and start a master send operation
633 * @id: pointer to the i2c device
635 static void cdns_i2c_msend(struct cdns_i2c *id)
637 unsigned int avail_bytes;
638 unsigned int bytes_to_send;
639 unsigned int ctrl_reg;
640 unsigned int isr_status;
642 id->p_recv_buf = NULL;
643 id->p_send_buf = id->p_msg->buf;
644 id->send_count = id->p_msg->len;
646 /* Set the controller in Master transmit mode and clear the FIFO. */
647 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
648 ctrl_reg &= ~CDNS_I2C_CR_RW;
649 ctrl_reg |= CDNS_I2C_CR_CLR_FIFO;
652 * Check for the message size against FIFO depth and set the
653 * 'hold bus' bit if it is greater than FIFO depth.
655 if (id->send_count > CDNS_I2C_FIFO_DEPTH)
656 ctrl_reg |= CDNS_I2C_CR_HOLD;
657 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
659 /* Clear the interrupts in interrupt status register. */
660 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
661 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
664 * Calculate the space available in FIFO. Check the message length
665 * against the space available, and fill the FIFO accordingly.
666 * Enable the interrupts.
668 avail_bytes = CDNS_I2C_FIFO_DEPTH -
669 cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
671 if (id->send_count > avail_bytes)
672 bytes_to_send = avail_bytes;
674 bytes_to_send = id->send_count;
676 while (bytes_to_send--) {
677 cdns_i2c_writereg((*(id->p_send_buf)++), CDNS_I2C_DATA_OFFSET);
682 * Clear the bus hold flag if there is no more data
683 * and if it is the last message.
685 if (!id->bus_hold_flag && !id->send_count)
686 cdns_i2c_clear_bus_hold(id);
687 /* Set the slave address in address register - triggers operation. */
688 cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,
689 CDNS_I2C_ADDR_OFFSET);
691 cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET);
695 * cdns_i2c_master_reset - Reset the interface
696 * @adap: pointer to the i2c adapter driver instance
698 * This function cleanup the fifos, clear the hold bit and status
699 * and disable the interrupts.
701 static void cdns_i2c_master_reset(struct i2c_adapter *adap)
703 struct cdns_i2c *id = adap->algo_data;
706 /* Disable the interrupts */
707 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET);
708 /* Clear the hold bit and fifos */
709 regval = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
710 regval &= ~CDNS_I2C_CR_HOLD;
711 regval |= CDNS_I2C_CR_CLR_FIFO;
712 cdns_i2c_writereg(regval, CDNS_I2C_CR_OFFSET);
713 /* Update the transfercount register to zero */
714 cdns_i2c_writereg(0, CDNS_I2C_XFER_SIZE_OFFSET);
715 /* Clear the interrupt status register */
716 regval = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
717 cdns_i2c_writereg(regval, CDNS_I2C_ISR_OFFSET);
718 /* Clear the status register */
719 regval = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET);
720 cdns_i2c_writereg(regval, CDNS_I2C_SR_OFFSET);
723 static int cdns_i2c_process_msg(struct cdns_i2c *id, struct i2c_msg *msg,
724 struct i2c_adapter *adap)
726 unsigned long time_left;
731 reinit_completion(&id->xfer_done);
733 /* Check for the TEN Bit mode on each msg */
734 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
735 if (msg->flags & I2C_M_TEN) {
736 if (reg & CDNS_I2C_CR_NEA)
737 cdns_i2c_writereg(reg & ~CDNS_I2C_CR_NEA,
740 if (!(reg & CDNS_I2C_CR_NEA))
741 cdns_i2c_writereg(reg | CDNS_I2C_CR_NEA,
745 /* Check for the R/W flag on each msg */
746 if (msg->flags & I2C_M_RD)
751 /* Wait for the signal of completion */
752 time_left = wait_for_completion_timeout(&id->xfer_done, adap->timeout);
753 if (time_left == 0) {
754 cdns_i2c_master_reset(adap);
755 dev_err(id->adap.dev.parent,
756 "timeout waiting on completion\n");
760 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK,
761 CDNS_I2C_IDR_OFFSET);
763 /* If it is bus arbitration error, try again */
764 if (id->err_status & CDNS_I2C_IXR_ARB_LOST)
771 * cdns_i2c_master_xfer - The main i2c transfer function
772 * @adap: pointer to the i2c adapter driver instance
773 * @msgs: pointer to the i2c message structure
774 * @num: the number of messages to transfer
776 * Initiates the send/recv activity based on the transfer message received.
778 * Return: number of msgs processed on success, negative error otherwise
780 static int cdns_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
785 struct cdns_i2c *id = adap->algo_data;
787 #if IS_ENABLED(CONFIG_I2C_SLAVE)
788 bool change_role = false;
791 ret = pm_runtime_get_sync(id->dev);
795 #if IS_ENABLED(CONFIG_I2C_SLAVE)
796 /* Check i2c operating mode and switch if possible */
797 if (id->dev_mode == CDNS_I2C_MODE_SLAVE) {
798 if (id->slave_state != CDNS_I2C_SLAVE_STATE_IDLE)
801 /* Set mode to master */
802 cdns_i2c_set_mode(CDNS_I2C_MODE_MASTER, id);
804 /* Mark flag to change role once xfer is completed */
809 /* Check if the bus is free */
810 if (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) & CDNS_I2C_SR_BA) {
815 hold_quirk = !!(id->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
817 * Set the flag to one when multiple messages are to be
818 * processed with a repeated start.
822 * This controller does not give completion interrupt after a
823 * master receive message if HOLD bit is set (repeated start),
824 * resulting in SW timeout. Hence, if a receive message is
825 * followed by any other message, an error is returned
826 * indicating that this sequence is not supported.
828 for (count = 0; (count < num - 1 && hold_quirk); count++) {
829 if (msgs[count].flags & I2C_M_RD) {
830 dev_warn(adap->dev.parent,
831 "Can't do repeated start after a receive message\n");
836 id->bus_hold_flag = 1;
837 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
838 reg |= CDNS_I2C_CR_HOLD;
839 cdns_i2c_writereg(reg, CDNS_I2C_CR_OFFSET);
841 id->bus_hold_flag = 0;
844 /* Process the msg one by one */
845 for (count = 0; count < num; count++, msgs++) {
846 if (count == (num - 1))
847 id->bus_hold_flag = 0;
849 ret = cdns_i2c_process_msg(id, msgs, adap);
853 /* Report the other error interrupts to application */
854 if (id->err_status) {
855 cdns_i2c_master_reset(adap);
857 if (id->err_status & CDNS_I2C_IXR_NACK) {
870 #if IS_ENABLED(CONFIG_I2C_SLAVE)
871 /* Switch i2c mode to slave */
873 cdns_i2c_set_mode(CDNS_I2C_MODE_SLAVE, id);
876 pm_runtime_mark_last_busy(id->dev);
877 pm_runtime_put_autosuspend(id->dev);
882 * cdns_i2c_func - Returns the supported features of the I2C driver
883 * @adap: pointer to the i2c adapter structure
885 * Return: 32 bit value, each bit corresponding to a feature
887 static u32 cdns_i2c_func(struct i2c_adapter *adap)
889 u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR |
890 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
891 I2C_FUNC_SMBUS_BLOCK_DATA;
893 #if IS_ENABLED(CONFIG_I2C_SLAVE)
894 func |= I2C_FUNC_SLAVE;
900 #if IS_ENABLED(CONFIG_I2C_SLAVE)
901 static int cdns_reg_slave(struct i2c_client *slave)
904 struct cdns_i2c *id = container_of(slave->adapter, struct cdns_i2c,
910 if (slave->flags & I2C_CLIENT_TEN)
911 return -EAFNOSUPPORT;
913 ret = pm_runtime_get_sync(id->dev);
917 /* Store slave information */
920 /* Enable I2C slave */
921 cdns_i2c_set_mode(CDNS_I2C_MODE_SLAVE, id);
926 static int cdns_unreg_slave(struct i2c_client *slave)
928 struct cdns_i2c *id = container_of(slave->adapter, struct cdns_i2c,
931 pm_runtime_put(id->dev);
933 /* Remove slave information */
936 /* Enable I2C master */
937 cdns_i2c_set_mode(CDNS_I2C_MODE_MASTER, id);
943 static const struct i2c_algorithm cdns_i2c_algo = {
944 .master_xfer = cdns_i2c_master_xfer,
945 .functionality = cdns_i2c_func,
946 #if IS_ENABLED(CONFIG_I2C_SLAVE)
947 .reg_slave = cdns_reg_slave,
948 .unreg_slave = cdns_unreg_slave,
953 * cdns_i2c_calc_divs - Calculate clock dividers
954 * @f: I2C clock frequency
955 * @input_clk: Input clock frequency
956 * @a: First divider (return value)
957 * @b: Second divider (return value)
959 * f is used as input and output variable. As input it is used as target I2C
960 * frequency. On function exit f holds the actually resulting I2C frequency.
962 * Return: 0 on success, negative errno otherwise.
964 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk,
965 unsigned int *a, unsigned int *b)
967 unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp;
968 unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0;
969 unsigned int last_error, current_error;
971 /* calculate (divisor_a+1) x (divisor_b+1) */
972 temp = input_clk / (22 * fscl);
975 * If the calculated value is negative or 0, the fscl input is out of
976 * range. Return error.
978 if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX)))
982 for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) {
983 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1));
985 if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX))
989 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1));
991 if (actual_fscl > fscl)
994 current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) :
995 (fscl - actual_fscl));
997 if (last_error > current_error) {
1000 best_fscl = actual_fscl;
1001 last_error = current_error;
1013 * cdns_i2c_setclk - This function sets the serial clock rate for the I2C device
1014 * @clk_in: I2C clock input frequency in Hz
1015 * @id: Pointer to the I2C device structure
1017 * The device must be idle rather than busy transferring data before setting
1018 * these device options.
1019 * The data rate is set by values in the control register.
1020 * The formula for determining the correct register values is
1021 * Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
1022 * See the hardware data sheet for a full explanation of setting the serial
1023 * clock rate. The clock can not be faster than the input clock divide by 22.
1024 * The two most common clock rates are 100KHz and 400KHz.
1026 * Return: 0 on success, negative error otherwise
1028 static int cdns_i2c_setclk(unsigned long clk_in, struct cdns_i2c *id)
1030 unsigned int div_a, div_b;
1031 unsigned int ctrl_reg;
1033 unsigned long fscl = id->i2c_clk;
1035 ret = cdns_i2c_calc_divs(&fscl, clk_in, &div_a, &div_b);
1039 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
1040 ctrl_reg &= ~(CDNS_I2C_CR_DIVA_MASK | CDNS_I2C_CR_DIVB_MASK);
1041 ctrl_reg |= ((div_a << CDNS_I2C_CR_DIVA_SHIFT) |
1042 (div_b << CDNS_I2C_CR_DIVB_SHIFT));
1043 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
1044 #if IS_ENABLED(CONFIG_I2C_SLAVE)
1045 id->ctrl_reg_diva_divb = ctrl_reg & (CDNS_I2C_CR_DIVA_MASK |
1046 CDNS_I2C_CR_DIVB_MASK);
1052 * cdns_i2c_clk_notifier_cb - Clock rate change callback
1053 * @nb: Pointer to notifier block
1054 * @event: Notification reason
1055 * @data: Pointer to notification data object
1057 * This function is called when the cdns_i2c input clock frequency changes.
1058 * The callback checks whether a valid bus frequency can be generated after the
1059 * change. If so, the change is acknowledged, otherwise the change is aborted.
1060 * New dividers are written to the HW in the pre- or post change notification
1061 * depending on the scaling direction.
1063 * Return: NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK
1064 * to acknowledge the change, NOTIFY_DONE if the notification is
1065 * considered irrelevant.
1067 static int cdns_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long
1070 struct clk_notifier_data *ndata = data;
1071 struct cdns_i2c *id = to_cdns_i2c(nb);
1073 if (pm_runtime_suspended(id->dev))
1077 case PRE_RATE_CHANGE:
1079 unsigned long input_clk = ndata->new_rate;
1080 unsigned long fscl = id->i2c_clk;
1081 unsigned int div_a, div_b;
1084 ret = cdns_i2c_calc_divs(&fscl, input_clk, &div_a, &div_b);
1086 dev_warn(id->adap.dev.parent,
1087 "clock rate change rejected\n");
1092 if (ndata->new_rate > ndata->old_rate)
1093 cdns_i2c_setclk(ndata->new_rate, id);
1097 case POST_RATE_CHANGE:
1098 id->input_clk = ndata->new_rate;
1100 if (ndata->new_rate < ndata->old_rate)
1101 cdns_i2c_setclk(ndata->new_rate, id);
1103 case ABORT_RATE_CHANGE:
1105 if (ndata->new_rate > ndata->old_rate)
1106 cdns_i2c_setclk(ndata->old_rate, id);
1114 * cdns_i2c_runtime_suspend - Runtime suspend method for the driver
1115 * @dev: Address of the platform_device structure
1117 * Put the driver into low power mode.
1121 static int __maybe_unused cdns_i2c_runtime_suspend(struct device *dev)
1123 struct cdns_i2c *xi2c = dev_get_drvdata(dev);
1125 clk_disable(xi2c->clk);
1131 * cdns_i2c_runtime_resume - Runtime resume
1132 * @dev: Address of the platform_device structure
1134 * Runtime resume callback.
1136 * Return: 0 on success and error value on error
1138 static int __maybe_unused cdns_i2c_runtime_resume(struct device *dev)
1140 struct cdns_i2c *xi2c = dev_get_drvdata(dev);
1143 ret = clk_enable(xi2c->clk);
1145 dev_err(dev, "Cannot enable clock.\n");
1152 static const struct dev_pm_ops cdns_i2c_dev_pm_ops = {
1153 SET_RUNTIME_PM_OPS(cdns_i2c_runtime_suspend,
1154 cdns_i2c_runtime_resume, NULL)
1157 static const struct cdns_platform_data r1p10_i2c_def = {
1158 .quirks = CDNS_I2C_BROKEN_HOLD_BIT,
1161 static const struct of_device_id cdns_i2c_of_match[] = {
1162 { .compatible = "cdns,i2c-r1p10", .data = &r1p10_i2c_def },
1163 { .compatible = "cdns,i2c-r1p14",},
1164 { /* end of table */ }
1166 MODULE_DEVICE_TABLE(of, cdns_i2c_of_match);
1169 * cdns_i2c_probe - Platform registration call
1170 * @pdev: Handle to the platform device structure
1172 * This function does all the memory allocation and registration for the i2c
1173 * device. User can modify the address mode to 10 bit address mode using the
1174 * ioctl call with option I2C_TENBIT.
1176 * Return: 0 on success, negative error otherwise
1178 static int cdns_i2c_probe(struct platform_device *pdev)
1180 struct resource *r_mem;
1181 struct cdns_i2c *id;
1183 const struct of_device_id *match;
1185 id = devm_kzalloc(&pdev->dev, sizeof(*id), GFP_KERNEL);
1189 id->dev = &pdev->dev;
1190 platform_set_drvdata(pdev, id);
1192 match = of_match_node(cdns_i2c_of_match, pdev->dev.of_node);
1193 if (match && match->data) {
1194 const struct cdns_platform_data *data = match->data;
1195 id->quirks = data->quirks;
1198 id->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &r_mem);
1199 if (IS_ERR(id->membase))
1200 return PTR_ERR(id->membase);
1202 id->irq = platform_get_irq(pdev, 0);
1204 id->adap.owner = THIS_MODULE;
1205 id->adap.dev.of_node = pdev->dev.of_node;
1206 id->adap.algo = &cdns_i2c_algo;
1207 id->adap.timeout = CDNS_I2C_TIMEOUT;
1208 id->adap.retries = 3; /* Default retry value. */
1209 id->adap.algo_data = id;
1210 id->adap.dev.parent = &pdev->dev;
1211 init_completion(&id->xfer_done);
1212 snprintf(id->adap.name, sizeof(id->adap.name),
1213 "Cadence I2C at %08lx", (unsigned long)r_mem->start);
1215 id->clk = devm_clk_get(&pdev->dev, NULL);
1216 if (IS_ERR(id->clk)) {
1217 if (PTR_ERR(id->clk) != -EPROBE_DEFER)
1218 dev_err(&pdev->dev, "input clock not found.\n");
1219 return PTR_ERR(id->clk);
1221 ret = clk_prepare_enable(id->clk);
1223 dev_err(&pdev->dev, "Unable to enable clock.\n");
1225 pm_runtime_set_autosuspend_delay(id->dev, CNDS_I2C_PM_TIMEOUT);
1226 pm_runtime_use_autosuspend(id->dev);
1227 pm_runtime_set_active(id->dev);
1228 pm_runtime_enable(id->dev);
1230 id->clk_rate_change_nb.notifier_call = cdns_i2c_clk_notifier_cb;
1231 if (clk_notifier_register(id->clk, &id->clk_rate_change_nb))
1232 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1233 id->input_clk = clk_get_rate(id->clk);
1235 ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
1237 if (ret || (id->i2c_clk > I2C_MAX_FAST_MODE_FREQ))
1238 id->i2c_clk = I2C_MAX_STANDARD_MODE_FREQ;
1240 #if IS_ENABLED(CONFIG_I2C_SLAVE)
1241 /* Set initial mode to master */
1242 id->dev_mode = CDNS_I2C_MODE_MASTER;
1243 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
1245 cdns_i2c_writereg(CDNS_I2C_CR_MASTER_EN_MASK, CDNS_I2C_CR_OFFSET);
1247 ret = cdns_i2c_setclk(id->input_clk, id);
1249 dev_err(&pdev->dev, "invalid SCL clock: %u Hz\n", id->i2c_clk);
1254 ret = devm_request_irq(&pdev->dev, id->irq, cdns_i2c_isr, 0,
1257 dev_err(&pdev->dev, "cannot get irq %d\n", id->irq);
1262 * Cadence I2C controller has a bug wherein it generates
1263 * invalid read transaction after HW timeout in master receiver mode.
1264 * HW timeout is not used by this driver and the interrupt is disabled.
1265 * But the feature itself cannot be disabled. Hence maximum value
1266 * is written to this register to reduce the chances of error.
1268 cdns_i2c_writereg(CDNS_I2C_TIMEOUT_MAX, CDNS_I2C_TIME_OUT_OFFSET);
1270 ret = i2c_add_adapter(&id->adap);
1274 dev_info(&pdev->dev, "%u kHz mmio %08lx irq %d\n",
1275 id->i2c_clk / 1000, (unsigned long)r_mem->start, id->irq);
1280 clk_disable_unprepare(id->clk);
1281 pm_runtime_disable(&pdev->dev);
1282 pm_runtime_set_suspended(&pdev->dev);
1287 * cdns_i2c_remove - Unregister the device after releasing the resources
1288 * @pdev: Handle to the platform device structure
1290 * This function frees all the resources allocated to the device.
1294 static int cdns_i2c_remove(struct platform_device *pdev)
1296 struct cdns_i2c *id = platform_get_drvdata(pdev);
1298 pm_runtime_disable(&pdev->dev);
1299 pm_runtime_set_suspended(&pdev->dev);
1300 pm_runtime_dont_use_autosuspend(&pdev->dev);
1302 i2c_del_adapter(&id->adap);
1303 clk_notifier_unregister(id->clk, &id->clk_rate_change_nb);
1304 clk_disable_unprepare(id->clk);
1309 static struct platform_driver cdns_i2c_drv = {
1311 .name = DRIVER_NAME,
1312 .of_match_table = cdns_i2c_of_match,
1313 .pm = &cdns_i2c_dev_pm_ops,
1315 .probe = cdns_i2c_probe,
1316 .remove = cdns_i2c_remove,
1319 module_platform_driver(cdns_i2c_drv);
1321 MODULE_AUTHOR("Xilinx Inc.");
1322 MODULE_DESCRIPTION("Cadence I2C bus driver");
1323 MODULE_LICENSE("GPL");