drivers/i2c/busses/i2c-bcm-iproc.c

   1 /*
   2  * Copyright (C) 2014 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation version 2.
   7  *
   8  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
   9  * kind, whether express or implied; without even the implied warranty
  10  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/delay.h>
  15 #include <linux/i2c.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/kernel.h>
  19 #include <linux/module.h>
  20 #include <linux/of_device.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/slab.h>
  23
  24 #define IDM_CTRL_DIRECT_OFFSET       0x00
  25 #define CFG_OFFSET                   0x00
  26 #define CFG_RESET_SHIFT              31
  27 #define CFG_EN_SHIFT                 30
  28 #define CFG_SLAVE_ADDR_0_SHIFT       28
  29 #define CFG_M_RETRY_CNT_SHIFT        16
  30 #define CFG_M_RETRY_CNT_MASK         0x0f
  31
  32 #define TIM_CFG_OFFSET               0x04
  33 #define TIM_CFG_MODE_400_SHIFT       31
  34 #define TIM_RAND_SLAVE_STRETCH_SHIFT      24
  35 #define TIM_RAND_SLAVE_STRETCH_MASK       0x7f
  36 #define TIM_PERIODIC_SLAVE_STRETCH_SHIFT  16
  37 #define TIM_PERIODIC_SLAVE_STRETCH_MASK   0x7f
  38
  39 #define S_CFG_SMBUS_ADDR_OFFSET           0x08
  40 #define S_CFG_EN_NIC_SMB_ADDR3_SHIFT      31
  41 #define S_CFG_NIC_SMB_ADDR3_SHIFT         24
  42 #define S_CFG_NIC_SMB_ADDR3_MASK          0x7f
  43 #define S_CFG_EN_NIC_SMB_ADDR2_SHIFT      23
  44 #define S_CFG_NIC_SMB_ADDR2_SHIFT         16
  45 #define S_CFG_NIC_SMB_ADDR2_MASK          0x7f
  46 #define S_CFG_EN_NIC_SMB_ADDR1_SHIFT      15
  47 #define S_CFG_NIC_SMB_ADDR1_SHIFT         8
  48 #define S_CFG_NIC_SMB_ADDR1_MASK          0x7f
  49 #define S_CFG_EN_NIC_SMB_ADDR0_SHIFT      7
  50 #define S_CFG_NIC_SMB_ADDR0_SHIFT         0
  51 #define S_CFG_NIC_SMB_ADDR0_MASK          0x7f
  52
  53 #define M_FIFO_CTRL_OFFSET           0x0c
  54 #define M_FIFO_RX_FLUSH_SHIFT        31
  55 #define M_FIFO_TX_FLUSH_SHIFT        30
  56 #define M_FIFO_RX_CNT_SHIFT          16
  57 #define M_FIFO_RX_CNT_MASK           0x7f
  58 #define M_FIFO_RX_THLD_SHIFT         8
  59 #define M_FIFO_RX_THLD_MASK          0x3f
  60
  61 #define S_FIFO_CTRL_OFFSET           0x10
  62 #define S_FIFO_RX_FLUSH_SHIFT        31
  63 #define S_FIFO_TX_FLUSH_SHIFT        30
  64 #define S_FIFO_RX_CNT_SHIFT          16
  65 #define S_FIFO_RX_CNT_MASK           0x7f
  66 #define S_FIFO_RX_THLD_SHIFT         8
  67 #define S_FIFO_RX_THLD_MASK          0x3f
  68
  69 #define M_CMD_OFFSET                 0x30
  70 #define M_CMD_START_BUSY_SHIFT       31
  71 #define M_CMD_STATUS_SHIFT           25
  72 #define M_CMD_STATUS_MASK            0x07
  73 #define M_CMD_STATUS_SUCCESS         0x0
  74 #define M_CMD_STATUS_LOST_ARB        0x1
  75 #define M_CMD_STATUS_NACK_ADDR       0x2
  76 #define M_CMD_STATUS_NACK_DATA       0x3
  77 #define M_CMD_STATUS_TIMEOUT         0x4
  78 #define M_CMD_STATUS_FIFO_UNDERRUN   0x5
  79 #define M_CMD_STATUS_RX_FIFO_FULL    0x6
  80 #define M_CMD_PROTOCOL_SHIFT         9
  81 #define M_CMD_PROTOCOL_MASK          0xf
  82 #define M_CMD_PROTOCOL_QUICK         0x0
  83 #define M_CMD_PROTOCOL_BLK_WR        0x7
  84 #define M_CMD_PROTOCOL_BLK_RD        0x8
  85 #define M_CMD_PROTOCOL_PROCESS       0xa
  86 #define M_CMD_PEC_SHIFT              8
  87 #define M_CMD_RD_CNT_SHIFT           0
  88 #define M_CMD_RD_CNT_MASK            0xff
  89
  90 #define S_CMD_OFFSET                 0x34
  91 #define S_CMD_START_BUSY_SHIFT       31
  92 #define S_CMD_STATUS_SHIFT           23
  93 #define S_CMD_STATUS_MASK            0x07
  94 #define S_CMD_STATUS_SUCCESS         0x0
  95 #define S_CMD_STATUS_TIMEOUT         0x5
  96 #define S_CMD_STATUS_MASTER_ABORT    0x7
  97
  98 #define IE_OFFSET                    0x38
  99 #define IE_M_RX_FIFO_FULL_SHIFT      31
 100 #define IE_M_RX_THLD_SHIFT           30
 101 #define IE_M_START_BUSY_SHIFT        28
 102 #define IE_M_TX_UNDERRUN_SHIFT       27
 103 #define IE_S_RX_FIFO_FULL_SHIFT      26
 104 #define IE_S_RX_THLD_SHIFT           25
 105 #define IE_S_RX_EVENT_SHIFT          24
 106 #define IE_S_START_BUSY_SHIFT        23
 107 #define IE_S_TX_UNDERRUN_SHIFT       22
 108 #define IE_S_RD_EVENT_SHIFT          21
 109
 110 #define IS_OFFSET                    0x3c
 111 #define IS_M_RX_FIFO_FULL_SHIFT      31
 112 #define IS_M_RX_THLD_SHIFT           30
 113 #define IS_M_START_BUSY_SHIFT        28
 114 #define IS_M_TX_UNDERRUN_SHIFT       27
 115 #define IS_S_RX_FIFO_FULL_SHIFT      26
 116 #define IS_S_RX_THLD_SHIFT           25
 117 #define IS_S_RX_EVENT_SHIFT          24
 118 #define IS_S_START_BUSY_SHIFT        23
 119 #define IS_S_TX_UNDERRUN_SHIFT       22
 120 #define IS_S_RD_EVENT_SHIFT          21
 121
 122 #define M_TX_OFFSET                  0x40
 123 #define M_TX_WR_STATUS_SHIFT         31
 124 #define M_TX_DATA_SHIFT              0
 125 #define M_TX_DATA_MASK               0xff
 126
 127 #define M_RX_OFFSET                  0x44
 128 #define M_RX_STATUS_SHIFT            30
 129 #define M_RX_STATUS_MASK             0x03
 130 #define M_RX_PEC_ERR_SHIFT           29
 131 #define M_RX_DATA_SHIFT              0
 132 #define M_RX_DATA_MASK               0xff
 133
 134 #define S_TX_OFFSET                  0x48
 135 #define S_TX_WR_STATUS_SHIFT         31
 136 #define S_TX_DATA_SHIFT              0
 137 #define S_TX_DATA_MASK               0xff
 138
 139 #define S_RX_OFFSET                  0x4c
 140 #define S_RX_STATUS_SHIFT            30
 141 #define S_RX_STATUS_MASK             0x03
 142 #define S_RX_PEC_ERR_SHIFT           29
 143 #define S_RX_DATA_SHIFT              0
 144 #define S_RX_DATA_MASK               0xff
 145
 146 #define I2C_TIMEOUT_MSEC             50000
 147 #define M_TX_RX_FIFO_SIZE            64
 148 #define M_RX_FIFO_MAX_THLD_VALUE     (M_TX_RX_FIFO_SIZE - 1)
 149
 150 #define M_RX_MAX_READ_LEN            255
 151 #define M_RX_FIFO_THLD_VALUE         50
 152
 153 #define IE_M_ALL_INTERRUPT_SHIFT     27
 154 #define IE_M_ALL_INTERRUPT_MASK      0x1e
 155
 156 #define SLAVE_READ_WRITE_BIT_MASK    0x1
 157 #define SLAVE_READ_WRITE_BIT_SHIFT   0x1
 158 #define SLAVE_MAX_SIZE_TRANSACTION   64
 159 #define SLAVE_CLOCK_STRETCH_TIME     25
 160
 161 #define IE_S_ALL_INTERRUPT_SHIFT     21
 162 #define IE_S_ALL_INTERRUPT_MASK      0x3f
 163 /*
 164  * It takes ~18us to reading 10bytes of data, hence to keep tasklet
 165  * running for less time, max slave read per tasklet is set to 10 bytes.
 166  */
 167 #define MAX_SLAVE_RX_PER_INT         10
 168
 169 enum i2c_slave_read_status {
 170         I2C_SLAVE_RX_FIFO_EMPTY = 0,
 171         I2C_SLAVE_RX_START,
 172         I2C_SLAVE_RX_DATA,
 173         I2C_SLAVE_RX_END,
 174 };
 175
 176 enum bus_speed_index {
 177         I2C_SPD_100K = 0,
 178         I2C_SPD_400K,
 179 };
 180
 181 enum bcm_iproc_i2c_type {
 182         IPROC_I2C,
 183         IPROC_I2C_NIC
 184 };
 185
 186 struct bcm_iproc_i2c_dev {
 187         struct device *device;
 188         enum bcm_iproc_i2c_type type;
 189         int irq;
 190
 191         void __iomem *base;
 192         void __iomem *idm_base;
 193
 194         u32 ape_addr_mask;
 195
 196         /* lock for indirect access through IDM */
 197         spinlock_t idm_lock;
 198
 199         struct i2c_adapter adapter;
 200         unsigned int bus_speed;
 201
 202         struct completion done;
 203         int xfer_is_done;
 204
 205         struct i2c_msg *msg;
 206
 207         struct i2c_client *slave;
 208
 209         /* bytes that have been transferred */
 210         unsigned int tx_bytes;
 211         /* bytes that have been read */
 212         unsigned int rx_bytes;
 213         unsigned int thld_bytes;
 214
 215         bool slave_rx_only;
 216         bool rx_start_rcvd;
 217         bool slave_read_complete;
 218         u32 tx_underrun;
 219         u32 slave_int_mask;
 220         struct tasklet_struct slave_rx_tasklet;
 221 };
 222
 223 /* tasklet to process slave rx data */
 224 static void slave_rx_tasklet_fn(unsigned long);
 225
 226 /*
 227  * Can be expanded in the future if more interrupt status bits are utilized
 228  */
 229 #define ISR_MASK (BIT(IS_M_START_BUSY_SHIFT) | BIT(IS_M_TX_UNDERRUN_SHIFT)\
 230                 | BIT(IS_M_RX_THLD_SHIFT))
 231
 232 #define ISR_MASK_SLAVE (BIT(IS_S_START_BUSY_SHIFT)\
 233                 | BIT(IS_S_RX_EVENT_SHIFT) | BIT(IS_S_RD_EVENT_SHIFT)\
 234                 | BIT(IS_S_TX_UNDERRUN_SHIFT) | BIT(IS_S_RX_FIFO_FULL_SHIFT)\
 235                 | BIT(IS_S_RX_THLD_SHIFT))
 236
 237 static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave);
 238 static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave);
 239 static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c,
 240                                          bool enable);
 241
 242 static inline u32 iproc_i2c_rd_reg(struct bcm_iproc_i2c_dev *iproc_i2c,
 243                                    u32 offset)
 244 {
 245         u32 val;
 246
 247         if (iproc_i2c->idm_base) {
 248                 spin_lock(&iproc_i2c->idm_lock);
 249                 writel(iproc_i2c->ape_addr_mask,
 250                        iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET);
 251                 val = readl(iproc_i2c->base + offset);
 252                 spin_unlock(&iproc_i2c->idm_lock);
 253         } else {
 254                 val = readl(iproc_i2c->base + offset);
 255         }
 256
 257         return val;
 258 }
 259
 260 static inline void iproc_i2c_wr_reg(struct bcm_iproc_i2c_dev *iproc_i2c,
 261                                     u32 offset, u32 val)
 262 {
 263         if (iproc_i2c->idm_base) {
 264                 spin_lock(&iproc_i2c->idm_lock);
 265                 writel(iproc_i2c->ape_addr_mask,
 266                        iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET);
 267                 writel(val, iproc_i2c->base + offset);
 268                 spin_unlock(&iproc_i2c->idm_lock);
 269         } else {
 270                 writel(val, iproc_i2c->base + offset);
 271         }
 272 }
 273
 274 static void bcm_iproc_i2c_slave_init(
 275         struct bcm_iproc_i2c_dev *iproc_i2c, bool need_reset)
 276 {
 277         u32 val;
 278
 279         iproc_i2c->tx_underrun = 0;
 280         if (need_reset) {
 281                 /* put controller in reset */
 282                 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
 283                 val |= BIT(CFG_RESET_SHIFT);
 284                 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
 285
 286                 /* wait 100 usec per spec */
 287                 udelay(100);
 288
 289                 /* bring controller out of reset */
 290                 val &= ~(BIT(CFG_RESET_SHIFT));
 291                 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
 292         }
 293
 294         /* flush TX/RX FIFOs */
 295         val = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT));
 296         iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val);
 297
 298         /* Maximum slave stretch time */
 299         val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
 300         val &= ~(TIM_RAND_SLAVE_STRETCH_MASK << TIM_RAND_SLAVE_STRETCH_SHIFT);
 301         val |= (SLAVE_CLOCK_STRETCH_TIME << TIM_RAND_SLAVE_STRETCH_SHIFT);
 302         iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
 303
 304         /* Configure the slave address */
 305         val = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET);
 306         val |= BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);
 307         val &= ~(S_CFG_NIC_SMB_ADDR3_MASK << S_CFG_NIC_SMB_ADDR3_SHIFT);
 308         val |= (iproc_i2c->slave->addr << S_CFG_NIC_SMB_ADDR3_SHIFT);
 309         iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, val);
 310
 311         /* clear all pending slave interrupts */
 312         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE);
 313
 314         /* Enable interrupt register to indicate a valid byte in receive fifo */
 315         val = BIT(IE_S_RX_EVENT_SHIFT);
 316         /* Enable interrupt register to indicate a Master read transaction */
 317         val |= BIT(IE_S_RD_EVENT_SHIFT);
 318         /* Enable interrupt register for the Slave BUSY command */
 319         val |= BIT(IE_S_START_BUSY_SHIFT);
 320         iproc_i2c->slave_int_mask = val;
 321         iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
 322 }
 323
 324 static void bcm_iproc_i2c_check_slave_status(
 325         struct bcm_iproc_i2c_dev *iproc_i2c)
 326 {
 327         u32 val;
 328
 329         val = iproc_i2c_rd_reg(iproc_i2c, S_CMD_OFFSET);
 330         /* status is valid only when START_BUSY is cleared after it was set */
 331         if (val & BIT(S_CMD_START_BUSY_SHIFT))
 332                 return;
 333
 334         val = (val >> S_CMD_STATUS_SHIFT) & S_CMD_STATUS_MASK;
 335         if (val == S_CMD_STATUS_TIMEOUT || val == S_CMD_STATUS_MASTER_ABORT) {
 336                 dev_err(iproc_i2c->device, (val == S_CMD_STATUS_TIMEOUT) ?
 337                         "slave random stretch time timeout\n" :
 338                         "Master aborted read transaction\n");
 339                 /* re-initialize i2c for recovery */
 340                 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
 341                 bcm_iproc_i2c_slave_init(iproc_i2c, true);
 342                 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
 343         }
 344 }
 345
 346 static void bcm_iproc_i2c_slave_read(struct bcm_iproc_i2c_dev *iproc_i2c)
 347 {
 348         u8 rx_data, rx_status;
 349         u32 rx_bytes = 0;
 350         u32 val;
 351
 352         while (rx_bytes < MAX_SLAVE_RX_PER_INT) {
 353                 val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);
 354                 rx_status = (val >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK;
 355                 rx_data = ((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK);
 356
 357                 if (rx_status == I2C_SLAVE_RX_START) {
 358                         /* Start of SMBUS Master write */
 359                         i2c_slave_event(iproc_i2c->slave,
 360                                         I2C_SLAVE_WRITE_REQUESTED, &rx_data);
 361                         iproc_i2c->rx_start_rcvd = true;
 362                         iproc_i2c->slave_read_complete = false;
 363                 } else if (rx_status == I2C_SLAVE_RX_DATA &&
 364                            iproc_i2c->rx_start_rcvd) {
 365                         /* Middle of SMBUS Master write */
 366                         i2c_slave_event(iproc_i2c->slave,
 367                                         I2C_SLAVE_WRITE_RECEIVED, &rx_data);
 368                 } else if (rx_status == I2C_SLAVE_RX_END &&
 369                            iproc_i2c->rx_start_rcvd) {
 370                         /* End of SMBUS Master write */
 371                         if (iproc_i2c->slave_rx_only)
 372                                 i2c_slave_event(iproc_i2c->slave,
 373                                                 I2C_SLAVE_WRITE_RECEIVED,
 374                                                 &rx_data);
 375
 376                         i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP,
 377                                         &rx_data);
 378                 } else if (rx_status == I2C_SLAVE_RX_FIFO_EMPTY) {
 379                         iproc_i2c->rx_start_rcvd = false;
 380                         iproc_i2c->slave_read_complete = true;
 381                         break;
 382                 }
 383
 384                 rx_bytes++;
 385         }
 386 }
 387
 388 static void slave_rx_tasklet_fn(unsigned long data)
 389 {
 390         struct bcm_iproc_i2c_dev *iproc_i2c = (struct bcm_iproc_i2c_dev *)data;
 391         u32 int_clr;
 392
 393         bcm_iproc_i2c_slave_read(iproc_i2c);
 394
 395         /* clear pending IS_S_RX_EVENT_SHIFT interrupt */
 396         int_clr = BIT(IS_S_RX_EVENT_SHIFT);
 397
 398         if (!iproc_i2c->slave_rx_only && iproc_i2c->slave_read_complete) {
 399                 /*
 400                  * In case of single byte master-read request,
 401                  * IS_S_TX_UNDERRUN_SHIFT event is generated before
 402                  * IS_S_START_BUSY_SHIFT event. Hence start slave data send
 403                  * from first IS_S_TX_UNDERRUN_SHIFT event.
 404                  *
 405                  * This means don't send any data from slave when
 406                  * IS_S_RD_EVENT_SHIFT event is generated else it will increment
 407                  * eeprom or other backend slave driver read pointer twice.
 408                  */
 409                 iproc_i2c->tx_underrun = 0;
 410                 iproc_i2c->slave_int_mask |= BIT(IE_S_TX_UNDERRUN_SHIFT);
 411
 412                 /* clear IS_S_RD_EVENT_SHIFT interrupt */
 413                 int_clr |= BIT(IS_S_RD_EVENT_SHIFT);
 414         }
 415
 416         /* clear slave interrupt */
 417         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, int_clr);
 418         /* enable slave interrupts */
 419         iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, iproc_i2c->slave_int_mask);
 420 }
 421
 422 static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c,
 423                                     u32 status)
 424 {
 425         u32 val;
 426         u8 value;
 427
 428         /*
 429          * Slave events in case of master-write, master-write-read and,
 430          * master-read
 431          *
 432          * Master-write     : only IS_S_RX_EVENT_SHIFT event
 433          * Master-write-read: both IS_S_RX_EVENT_SHIFT and IS_S_RD_EVENT_SHIFT
 434          *                    events
 435          * Master-read      : both IS_S_RX_EVENT_SHIFT and IS_S_RD_EVENT_SHIFT
 436          *                    events or only IS_S_RD_EVENT_SHIFT
 437          */
 438         if (status & BIT(IS_S_RX_EVENT_SHIFT) ||
 439             status & BIT(IS_S_RD_EVENT_SHIFT)) {
 440                 /* disable slave interrupts */
 441                 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 442                 val &= ~iproc_i2c->slave_int_mask;
 443                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
 444
 445                 if (status & BIT(IS_S_RD_EVENT_SHIFT))
 446                         /* Master-write-read request */
 447                         iproc_i2c->slave_rx_only = false;
 448                 else
 449                         /* Master-write request only */
 450                         iproc_i2c->slave_rx_only = true;
 451
 452                 /* schedule tasklet to read data later */
 453                 tasklet_schedule(&iproc_i2c->slave_rx_tasklet);
 454
 455                 /* clear only IS_S_RX_EVENT_SHIFT interrupt */
 456                 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET,
 457                                  BIT(IS_S_RX_EVENT_SHIFT));
 458         }
 459
 460         if (status & BIT(IS_S_TX_UNDERRUN_SHIFT)) {
 461                 iproc_i2c->tx_underrun++;
 462                 if (iproc_i2c->tx_underrun == 1)
 463                         /* Start of SMBUS for Master Read */
 464                         i2c_slave_event(iproc_i2c->slave,
 465                                         I2C_SLAVE_READ_REQUESTED,
 466                                         &value);
 467                 else
 468                         /* Master read other than start */
 469                         i2c_slave_event(iproc_i2c->slave,
 470                                         I2C_SLAVE_READ_PROCESSED,
 471                                         &value);
 472
 473                 iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value);
 474                 /* start transfer */
 475                 val = BIT(S_CMD_START_BUSY_SHIFT);
 476                 iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
 477
 478                 /* clear interrupt */
 479                 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET,
 480                                  BIT(IS_S_TX_UNDERRUN_SHIFT));
 481         }
 482
 483         /* Stop received from master in case of master read transaction */
 484         if (status & BIT(IS_S_START_BUSY_SHIFT)) {
 485                 /*
 486                  * Disable interrupt for TX FIFO becomes empty and
 487                  * less than PKT_LENGTH bytes were output on the SMBUS
 488                  */
 489                 iproc_i2c->slave_int_mask &= ~BIT(IE_S_TX_UNDERRUN_SHIFT);
 490                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET,
 491                                  iproc_i2c->slave_int_mask);
 492
 493                 /* End of SMBUS for Master Read */
 494                 val = BIT(S_TX_WR_STATUS_SHIFT);
 495                 iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, val);
 496
 497                 val = BIT(S_CMD_START_BUSY_SHIFT);
 498                 iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
 499
 500                 /* flush TX FIFOs */
 501                 val = iproc_i2c_rd_reg(iproc_i2c, S_FIFO_CTRL_OFFSET);
 502                 val |= (BIT(S_FIFO_TX_FLUSH_SHIFT));
 503                 iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val);
 504
 505                 i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP, &value);
 506
 507                 /* clear interrupt */
 508                 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET,
 509                                  BIT(IS_S_START_BUSY_SHIFT));
 510         }
 511
 512         /* check slave transmit status only if slave is transmitting */
 513         if (!iproc_i2c->slave_rx_only)
 514                 bcm_iproc_i2c_check_slave_status(iproc_i2c);
 515
 516         return true;
 517 }
 518
 519 static void bcm_iproc_i2c_read_valid_bytes(struct bcm_iproc_i2c_dev *iproc_i2c)
 520 {
 521         struct i2c_msg *msg = iproc_i2c->msg;
 522         uint32_t val;
 523
 524         /* Read valid data from RX FIFO */
 525         while (iproc_i2c->rx_bytes < msg->len) {
 526                 val = iproc_i2c_rd_reg(iproc_i2c, M_RX_OFFSET);
 527
 528                 /* rx fifo empty */
 529                 if (!((val >> M_RX_STATUS_SHIFT) & M_RX_STATUS_MASK))
 530                         break;
 531
 532                 msg->buf[iproc_i2c->rx_bytes] =
 533                         (val >> M_RX_DATA_SHIFT) & M_RX_DATA_MASK;
 534                 iproc_i2c->rx_bytes++;
 535         }
 536 }
 537
 538 static void bcm_iproc_i2c_send(struct bcm_iproc_i2c_dev *iproc_i2c)
 539 {
 540         struct i2c_msg *msg = iproc_i2c->msg;
 541         unsigned int tx_bytes = msg->len - iproc_i2c->tx_bytes;
 542         unsigned int i;
 543         u32 val;
 544
 545         /* can only fill up to the FIFO size */
 546         tx_bytes = min_t(unsigned int, tx_bytes, M_TX_RX_FIFO_SIZE);
 547         for (i = 0; i < tx_bytes; i++) {
 548                 /* start from where we left over */
 549                 unsigned int idx = iproc_i2c->tx_bytes + i;
 550
 551                 val = msg->buf[idx];
 552
 553                 /* mark the last byte */
 554                 if (idx == msg->len - 1) {
 555                         val |= BIT(M_TX_WR_STATUS_SHIFT);
 556
 557                         if (iproc_i2c->irq) {
 558                                 u32 tmp;
 559
 560                                 /*
 561                                  * Since this is the last byte, we should now
 562                                  * disable TX FIFO underrun interrupt
 563                                  */
 564                                 tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 565                                 tmp &= ~BIT(IE_M_TX_UNDERRUN_SHIFT);
 566                                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET,
 567                                                  tmp);
 568                         }
 569                 }
 570
 571                 /* load data into TX FIFO */
 572                 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
 573         }
 574
 575         /* update number of transferred bytes */
 576         iproc_i2c->tx_bytes += tx_bytes;
 577 }
 578
 579 static void bcm_iproc_i2c_read(struct bcm_iproc_i2c_dev *iproc_i2c)
 580 {
 581         struct i2c_msg *msg = iproc_i2c->msg;
 582         u32 bytes_left, val;
 583
 584         bcm_iproc_i2c_read_valid_bytes(iproc_i2c);
 585         bytes_left = msg->len - iproc_i2c->rx_bytes;
 586         if (bytes_left == 0) {
 587                 if (iproc_i2c->irq) {
 588                         /* finished reading all data, disable rx thld event */
 589                         val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 590                         val &= ~BIT(IS_M_RX_THLD_SHIFT);
 591                         iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
 592                 }
 593         } else if (bytes_left < iproc_i2c->thld_bytes) {
 594                 /* set bytes left as threshold */
 595                 val = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET);
 596                 val &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
 597                 val |= (bytes_left << M_FIFO_RX_THLD_SHIFT);
 598                 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
 599                 iproc_i2c->thld_bytes = bytes_left;
 600         }
 601         /*
 602          * bytes_left >= iproc_i2c->thld_bytes,
 603          * hence no need to change the THRESHOLD SET.
 604          * It will remain as iproc_i2c->thld_bytes itself
 605          */
 606 }
 607
 608 static void bcm_iproc_i2c_process_m_event(struct bcm_iproc_i2c_dev *iproc_i2c,
 609                                           u32 status)
 610 {
 611         /* TX FIFO is empty and we have more data to send */
 612         if (status & BIT(IS_M_TX_UNDERRUN_SHIFT))
 613                 bcm_iproc_i2c_send(iproc_i2c);
 614
 615         /* RX FIFO threshold is reached and data needs to be read out */
 616         if (status & BIT(IS_M_RX_THLD_SHIFT))
 617                 bcm_iproc_i2c_read(iproc_i2c);
 618
 619         /* transfer is done */
 620         if (status & BIT(IS_M_START_BUSY_SHIFT)) {
 621                 iproc_i2c->xfer_is_done = 1;
 622                 if (iproc_i2c->irq)
 623                         complete(&iproc_i2c->done);
 624         }
 625 }
 626
 627 static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data)
 628 {
 629         struct bcm_iproc_i2c_dev *iproc_i2c = data;
 630         u32 slave_status;
 631         u32 status;
 632         bool ret;
 633
 634         status = iproc_i2c_rd_reg(iproc_i2c, IS_OFFSET);
 635         /* process only slave interrupt which are enabled */
 636         slave_status = status & iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET) &
 637                        ISR_MASK_SLAVE;
 638
 639         if (slave_status) {
 640                 ret = bcm_iproc_i2c_slave_isr(iproc_i2c, slave_status);
 641                 if (ret)
 642                         return IRQ_HANDLED;
 643                 else
 644                         return IRQ_NONE;
 645         }
 646
 647         status &= ISR_MASK;
 648         if (!status)
 649                 return IRQ_NONE;
 650
 651         /* process all master based events */
 652         bcm_iproc_i2c_process_m_event(iproc_i2c, status);
 653         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
 654
 655         return IRQ_HANDLED;
 656 }
 657
 658 static int bcm_iproc_i2c_init(struct bcm_iproc_i2c_dev *iproc_i2c)
 659 {
 660         u32 val;
 661
 662         /* put controller in reset */
 663         val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
 664         val |= BIT(CFG_RESET_SHIFT);
 665         val &= ~(BIT(CFG_EN_SHIFT));
 666         iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
 667
 668         /* wait 100 usec per spec */
 669         udelay(100);
 670
 671         /* bring controller out of reset */
 672         val &= ~(BIT(CFG_RESET_SHIFT));
 673         iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
 674
 675         /* flush TX/RX FIFOs and set RX FIFO threshold to zero */
 676         val = (BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT));
 677         iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
 678         /* disable all interrupts */
 679         val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 680         val &= ~(IE_M_ALL_INTERRUPT_MASK <<
 681                         IE_M_ALL_INTERRUPT_SHIFT);
 682         iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
 683
 684         /* clear all pending interrupts */
 685         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, 0xffffffff);
 686
 687         return 0;
 688 }
 689
 690 static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c,
 691                                          bool enable)
 692 {
 693         u32 val;
 694
 695         val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
 696         if (enable)
 697                 val |= BIT(CFG_EN_SHIFT);
 698         else
 699                 val &= ~BIT(CFG_EN_SHIFT);
 700         iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
 701 }
 702
 703 static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c,
 704                                       struct i2c_msg *msg)
 705 {
 706         u32 val;
 707
 708         val = iproc_i2c_rd_reg(iproc_i2c, M_CMD_OFFSET);
 709         val = (val >> M_CMD_STATUS_SHIFT) & M_CMD_STATUS_MASK;
 710
 711         switch (val) {
 712         case M_CMD_STATUS_SUCCESS:
 713                 return 0;
 714
 715         case M_CMD_STATUS_LOST_ARB:
 716                 dev_dbg(iproc_i2c->device, "lost bus arbitration\n");
 717                 return -EAGAIN;
 718
 719         case M_CMD_STATUS_NACK_ADDR:
 720                 dev_dbg(iproc_i2c->device, "NAK addr:0x%02x\n", msg->addr);
 721                 return -ENXIO;
 722
 723         case M_CMD_STATUS_NACK_DATA:
 724                 dev_dbg(iproc_i2c->device, "NAK data\n");
 725                 return -ENXIO;
 726
 727         case M_CMD_STATUS_TIMEOUT:
 728                 dev_dbg(iproc_i2c->device, "bus timeout\n");
 729                 return -ETIMEDOUT;
 730
 731         case M_CMD_STATUS_FIFO_UNDERRUN:
 732                 dev_dbg(iproc_i2c->device, "FIFO under-run\n");
 733                 return -ENXIO;
 734
 735         case M_CMD_STATUS_RX_FIFO_FULL:
 736                 dev_dbg(iproc_i2c->device, "RX FIFO full\n");
 737                 return -ETIMEDOUT;
 738
 739         default:
 740                 dev_dbg(iproc_i2c->device, "unknown error code=%d\n", val);
 741
 742                 /* re-initialize i2c for recovery */
 743                 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
 744                 bcm_iproc_i2c_init(iproc_i2c);
 745                 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
 746
 747                 return -EIO;
 748         }
 749 }
 750
 751 static int bcm_iproc_i2c_xfer_wait(struct bcm_iproc_i2c_dev *iproc_i2c,
 752                                    struct i2c_msg *msg,
 753                                    u32 cmd)
 754 {
 755         unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT_MSEC);
 756         u32 val, status;
 757         int ret;
 758
 759         iproc_i2c_wr_reg(iproc_i2c, M_CMD_OFFSET, cmd);
 760
 761         if (iproc_i2c->irq) {
 762                 time_left = wait_for_completion_timeout(&iproc_i2c->done,
 763                                                         time_left);
 764                 /* disable all interrupts */
 765                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
 766                 /* read it back to flush the write */
 767                 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 768                 /* make sure the interrupt handler isn't running */
 769                 synchronize_irq(iproc_i2c->irq);
 770
 771         } else { /* polling mode */
 772                 unsigned long timeout = jiffies + time_left;
 773
 774                 do {
 775                         status = iproc_i2c_rd_reg(iproc_i2c,
 776                                                   IS_OFFSET) & ISR_MASK;
 777                         bcm_iproc_i2c_process_m_event(iproc_i2c, status);
 778                         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
 779
 780                         if (time_after(jiffies, timeout)) {
 781                                 time_left = 0;
 782                                 break;
 783                         }
 784
 785                         cpu_relax();
 786                         cond_resched();
 787                 } while (!iproc_i2c->xfer_is_done);
 788         }
 789
 790         if (!time_left && !iproc_i2c->xfer_is_done) {
 791                 dev_err(iproc_i2c->device, "transaction timed out\n");
 792
 793                 /* flush both TX/RX FIFOs */
 794                 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
 795                 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
 796                 return -ETIMEDOUT;
 797         }
 798
 799         ret = bcm_iproc_i2c_check_status(iproc_i2c, msg);
 800         if (ret) {
 801                 /* flush both TX/RX FIFOs */
 802                 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
 803                 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
 804                 return ret;
 805         }
 806
 807         return 0;
 808 }
 809
 810 /*
 811  * If 'process_call' is true, then this is a multi-msg transfer that requires
 812  * a repeated start between the messages.
 813  * More specifically, it must be a write (reg) followed by a read (data).
 814  * The i2c quirks are set to enforce this rule.
 815  */
 816 static int bcm_iproc_i2c_xfer_internal(struct bcm_iproc_i2c_dev *iproc_i2c,
 817                                         struct i2c_msg *msgs, bool process_call)
 818 {
 819         int i;
 820         u8 addr;
 821         u32 val, tmp, val_intr_en;
 822         unsigned int tx_bytes;
 823         struct i2c_msg *msg = &msgs[0];
 824
 825         /* check if bus is busy */
 826         if (!!(iproc_i2c_rd_reg(iproc_i2c,
 827                                 M_CMD_OFFSET) & BIT(M_CMD_START_BUSY_SHIFT))) {
 828                 dev_warn(iproc_i2c->device, "bus is busy\n");
 829                 return -EBUSY;
 830         }
 831
 832         iproc_i2c->msg = msg;
 833
 834         /* format and load slave address into the TX FIFO */
 835         addr = i2c_8bit_addr_from_msg(msg);
 836         iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, addr);
 837
 838         /*
 839          * For a write transaction, load data into the TX FIFO. Only allow
 840          * loading up to TX FIFO size - 1 bytes of data since the first byte
 841          * has been used up by the slave address
 842          */
 843         tx_bytes = min_t(unsigned int, msg->len, M_TX_RX_FIFO_SIZE - 1);
 844         if (!(msg->flags & I2C_M_RD)) {
 845                 for (i = 0; i < tx_bytes; i++) {
 846                         val = msg->buf[i];
 847
 848                         /* mark the last byte */
 849                         if (!process_call && (i == msg->len - 1))
 850                                 val |= BIT(M_TX_WR_STATUS_SHIFT);
 851
 852                         iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
 853                 }
 854                 iproc_i2c->tx_bytes = tx_bytes;
 855         }
 856
 857         /* Process the read message if this is process call */
 858         if (process_call) {
 859                 msg++;
 860                 iproc_i2c->msg = msg;  /* point to second msg */
 861
 862                 /*
 863                  * The last byte to be sent out should be a slave
 864                  * address with read operation
 865                  */
 866                 addr = i2c_8bit_addr_from_msg(msg);
 867                 /* mark it the last byte out */
 868                 val = addr | BIT(M_TX_WR_STATUS_SHIFT);
 869                 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
 870         }
 871
 872         /* mark as incomplete before starting the transaction */
 873         if (iproc_i2c->irq)
 874                 reinit_completion(&iproc_i2c->done);
 875
 876         iproc_i2c->xfer_is_done = 0;
 877
 878         /*
 879          * Enable the "start busy" interrupt, which will be triggered after the
 880          * transaction is done, i.e., the internal start_busy bit, transitions
 881          * from 1 to 0.
 882          */
 883         val_intr_en = BIT(IE_M_START_BUSY_SHIFT);
 884
 885         /*
 886          * If TX data size is larger than the TX FIFO, need to enable TX
 887          * underrun interrupt, which will be triggerred when the TX FIFO is
 888          * empty. When that happens we can then pump more data into the FIFO
 889          */
 890         if (!process_call && !(msg->flags & I2C_M_RD) &&
 891             msg->len > iproc_i2c->tx_bytes)
 892                 val_intr_en |= BIT(IE_M_TX_UNDERRUN_SHIFT);
 893
 894         /*
 895          * Now we can activate the transfer. For a read operation, specify the
 896          * number of bytes to read
 897          */
 898         val = BIT(M_CMD_START_BUSY_SHIFT);
 899
 900         if (msg->len == 0) {
 901                 /* SMBUS QUICK Command (Read/Write) */
 902                 val |= (M_CMD_PROTOCOL_QUICK << M_CMD_PROTOCOL_SHIFT);
 903         } else if (msg->flags & I2C_M_RD) {
 904                 u32 protocol;
 905
 906                 iproc_i2c->rx_bytes = 0;
 907                 if (msg->len > M_RX_FIFO_MAX_THLD_VALUE)
 908                         iproc_i2c->thld_bytes = M_RX_FIFO_THLD_VALUE;
 909                 else
 910                         iproc_i2c->thld_bytes = msg->len;
 911
 912                 /* set threshold value */
 913                 tmp = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET);
 914                 tmp &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
 915                 tmp |= iproc_i2c->thld_bytes << M_FIFO_RX_THLD_SHIFT;
 916                 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, tmp);
 917
 918                 /* enable the RX threshold interrupt */
 919                 val_intr_en |= BIT(IE_M_RX_THLD_SHIFT);
 920
 921                 protocol = process_call ?
 922                                 M_CMD_PROTOCOL_PROCESS : M_CMD_PROTOCOL_BLK_RD;
 923
 924                 val |= (protocol << M_CMD_PROTOCOL_SHIFT) |
 925                        (msg->len << M_CMD_RD_CNT_SHIFT);
 926         } else {
 927                 val |= (M_CMD_PROTOCOL_BLK_WR << M_CMD_PROTOCOL_SHIFT);
 928         }
 929
 930         if (iproc_i2c->irq)
 931                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val_intr_en);
 932
 933         return bcm_iproc_i2c_xfer_wait(iproc_i2c, msg, val);
 934 }
 935
 936 static int bcm_iproc_i2c_xfer(struct i2c_adapter *adapter,
 937                               struct i2c_msg msgs[], int num)
 938 {
 939         struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(adapter);
 940         bool process_call = false;
 941         int ret;
 942
 943         if (num == 2) {
 944                 /* Repeated start, use process call */
 945                 process_call = true;
 946                 if (msgs[1].flags & I2C_M_NOSTART) {
 947                         dev_err(iproc_i2c->device, "Invalid repeated start\n");
 948                         return -EOPNOTSUPP;
 949                 }
 950         }
 951
 952         ret = bcm_iproc_i2c_xfer_internal(iproc_i2c, msgs, process_call);
 953         if (ret) {
 954                 dev_dbg(iproc_i2c->device, "xfer failed\n");
 955                 return ret;
 956         }
 957
 958         return num;
 959 }
 960
 961 static uint32_t bcm_iproc_i2c_functionality(struct i2c_adapter *adap)
 962 {
 963         u32 val;
 964
 965         val = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 966
 967         if (adap->algo->reg_slave)
 968                 val |= I2C_FUNC_SLAVE;
 969
 970         return val;
 971 }
 972
 973 static struct i2c_algorithm bcm_iproc_algo = {
 974         .master_xfer = bcm_iproc_i2c_xfer,
 975         .functionality = bcm_iproc_i2c_functionality,
 976         .reg_slave = bcm_iproc_i2c_reg_slave,
 977         .unreg_slave = bcm_iproc_i2c_unreg_slave,
 978 };
 979
 980 static const struct i2c_adapter_quirks bcm_iproc_i2c_quirks = {
 981         .flags = I2C_AQ_COMB_WRITE_THEN_READ,
 982         .max_comb_1st_msg_len = M_TX_RX_FIFO_SIZE,
 983         .max_read_len = M_RX_MAX_READ_LEN,
 984 };
 985
 986 static int bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev *iproc_i2c)
 987 {
 988         unsigned int bus_speed;
 989         u32 val;
 990         int ret = of_property_read_u32(iproc_i2c->device->of_node,
 991                                        "clock-frequency", &bus_speed);
 992         if (ret < 0) {
 993                 dev_info(iproc_i2c->device,
 994                         "unable to interpret clock-frequency DT property\n");
 995                 bus_speed = I2C_MAX_STANDARD_MODE_FREQ;
 996         }
 997
 998         if (bus_speed < I2C_MAX_STANDARD_MODE_FREQ) {
 999                 dev_err(iproc_i2c->device, "%d Hz bus speed not supported\n",
1000                         bus_speed);
1001                 dev_err(iproc_i2c->device,
1002                         "valid speeds are 100khz and 400khz\n");
1003                 return -EINVAL;
1004         } else if (bus_speed < I2C_MAX_FAST_MODE_FREQ) {
1005                 bus_speed = I2C_MAX_STANDARD_MODE_FREQ;
1006         } else {
1007                 bus_speed = I2C_MAX_FAST_MODE_FREQ;
1008         }
1009
1010         iproc_i2c->bus_speed = bus_speed;
1011         val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
1012         val &= ~BIT(TIM_CFG_MODE_400_SHIFT);
1013         val |= (bus_speed == I2C_MAX_FAST_MODE_FREQ) << TIM_CFG_MODE_400_SHIFT;
1014         iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
1015
1016         dev_info(iproc_i2c->device, "bus set to %u Hz\n", bus_speed);
1017
1018         return 0;
1019 }
1020
1021 static int bcm_iproc_i2c_probe(struct platform_device *pdev)
1022 {
1023         int irq, ret = 0;
1024         struct bcm_iproc_i2c_dev *iproc_i2c;
1025         struct i2c_adapter *adap;
1026         struct resource *res;
1027
1028         iproc_i2c = devm_kzalloc(&pdev->dev, sizeof(*iproc_i2c),
1029                                  GFP_KERNEL);
1030         if (!iproc_i2c)
1031                 return -ENOMEM;
1032
1033         platform_set_drvdata(pdev, iproc_i2c);
1034         iproc_i2c->device = &pdev->dev;
1035         iproc_i2c->type =
1036                 (enum bcm_iproc_i2c_type)of_device_get_match_data(&pdev->dev);
1037         init_completion(&iproc_i2c->done);
1038
1039         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1040         iproc_i2c->base = devm_ioremap_resource(iproc_i2c->device, res);
1041         if (IS_ERR(iproc_i2c->base))
1042                 return PTR_ERR(iproc_i2c->base);
1043
1044         if (iproc_i2c->type == IPROC_I2C_NIC) {
1045                 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1046                 iproc_i2c->idm_base = devm_ioremap_resource(iproc_i2c->device,
1047                                                             res);
1048                 if (IS_ERR(iproc_i2c->idm_base))
1049                         return PTR_ERR(iproc_i2c->idm_base);
1050
1051                 ret = of_property_read_u32(iproc_i2c->device->of_node,
1052                                            "brcm,ape-hsls-addr-mask",
1053                                            &iproc_i2c->ape_addr_mask);
1054                 if (ret < 0) {
1055                         dev_err(iproc_i2c->device,
1056                                 "'brcm,ape-hsls-addr-mask' missing\n");
1057                         return -EINVAL;
1058                 }
1059
1060                 spin_lock_init(&iproc_i2c->idm_lock);
1061
1062                 /* no slave support */
1063                 bcm_iproc_algo.reg_slave = NULL;
1064                 bcm_iproc_algo.unreg_slave = NULL;
1065         }
1066
1067         ret = bcm_iproc_i2c_init(iproc_i2c);
1068         if (ret)
1069                 return ret;
1070
1071         ret = bcm_iproc_i2c_cfg_speed(iproc_i2c);
1072         if (ret)
1073                 return ret;
1074
1075         irq = platform_get_irq(pdev, 0);
1076         if (irq > 0) {
1077                 ret = devm_request_irq(iproc_i2c->device, irq,
1078                                        bcm_iproc_i2c_isr, 0, pdev->name,
1079                                        iproc_i2c);
1080                 if (ret < 0) {
1081                         dev_err(iproc_i2c->device,
1082                                 "unable to request irq %i\n", irq);
1083                         return ret;
1084                 }
1085
1086                 iproc_i2c->irq = irq;
1087         } else {
1088                 dev_warn(iproc_i2c->device,
1089                          "no irq resource, falling back to poll mode\n");
1090         }
1091
1092         bcm_iproc_i2c_enable_disable(iproc_i2c, true);
1093
1094         adap = &iproc_i2c->adapter;
1095         i2c_set_adapdata(adap, iproc_i2c);
1096         snprintf(adap->name, sizeof(adap->name),
1097                 "Broadcom iProc (%s)",
1098                 of_node_full_name(iproc_i2c->device->of_node));
1099         adap->algo = &bcm_iproc_algo;
1100         adap->quirks = &bcm_iproc_i2c_quirks;
1101         adap->dev.parent = &pdev->dev;
1102         adap->dev.of_node = pdev->dev.of_node;
1103
1104         return i2c_add_adapter(adap);
1105 }
1106
1107 static int bcm_iproc_i2c_remove(struct platform_device *pdev)
1108 {
1109         struct bcm_iproc_i2c_dev *iproc_i2c = platform_get_drvdata(pdev);
1110
1111         if (iproc_i2c->irq) {
1112                 /*
1113                  * Make sure there's no pending interrupt when we remove the
1114                  * adapter
1115                  */
1116                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
1117                 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
1118                 synchronize_irq(iproc_i2c->irq);
1119         }
1120
1121         i2c_del_adapter(&iproc_i2c->adapter);
1122         bcm_iproc_i2c_enable_disable(iproc_i2c, false);
1123
1124         return 0;
1125 }
1126
1127 #ifdef CONFIG_PM_SLEEP
1128
1129 static int bcm_iproc_i2c_suspend(struct device *dev)
1130 {
1131         struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev);
1132
1133         if (iproc_i2c->irq) {
1134                 /*
1135                  * Make sure there's no pending interrupt when we go into
1136                  * suspend
1137                  */
1138                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
1139                 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
1140                 synchronize_irq(iproc_i2c->irq);
1141         }
1142
1143         /* now disable the controller */
1144         bcm_iproc_i2c_enable_disable(iproc_i2c, false);
1145
1146         return 0;
1147 }
1148
1149 static int bcm_iproc_i2c_resume(struct device *dev)
1150 {
1151         struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev);
1152         int ret;
1153         u32 val;
1154
1155         /*
1156          * Power domain could have been shut off completely in system deep
1157          * sleep, so re-initialize the block here
1158          */
1159         ret = bcm_iproc_i2c_init(iproc_i2c);
1160         if (ret)
1161                 return ret;
1162
1163         /* configure to the desired bus speed */
1164         val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
1165         val &= ~BIT(TIM_CFG_MODE_400_SHIFT);
1166         val |= (iproc_i2c->bus_speed == I2C_MAX_FAST_MODE_FREQ) << TIM_CFG_MODE_400_SHIFT;
1167         iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
1168
1169         bcm_iproc_i2c_enable_disable(iproc_i2c, true);
1170
1171         return 0;
1172 }
1173
1174 static const struct dev_pm_ops bcm_iproc_i2c_pm_ops = {
1175         .suspend_late = &bcm_iproc_i2c_suspend,
1176         .resume_early = &bcm_iproc_i2c_resume
1177 };
1178
1179 #define BCM_IPROC_I2C_PM_OPS (&bcm_iproc_i2c_pm_ops)
1180 #else
1181 #define BCM_IPROC_I2C_PM_OPS NULL
1182 #endif /* CONFIG_PM_SLEEP */
1183
1184
1185 static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave)
1186 {
1187         struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter);
1188
1189         if (iproc_i2c->slave)
1190                 return -EBUSY;
1191
1192         if (slave->flags & I2C_CLIENT_TEN)
1193                 return -EAFNOSUPPORT;
1194
1195         iproc_i2c->slave = slave;
1196
1197         tasklet_init(&iproc_i2c->slave_rx_tasklet, slave_rx_tasklet_fn,
1198                      (unsigned long)iproc_i2c);
1199
1200         bcm_iproc_i2c_slave_init(iproc_i2c, false);
1201         return 0;
1202 }
1203
1204 static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave)
1205 {
1206         u32 tmp;
1207         struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter);
1208
1209         if (!iproc_i2c->slave)
1210                 return -EINVAL;
1211
1212         disable_irq(iproc_i2c->irq);
1213
1214         /* disable all slave interrupts */
1215         tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
1216         tmp &= ~(IE_S_ALL_INTERRUPT_MASK <<
1217                         IE_S_ALL_INTERRUPT_SHIFT);
1218         iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, tmp);
1219
1220         tasklet_kill(&iproc_i2c->slave_rx_tasklet);
1221
1222         /* Erase the slave address programmed */
1223         tmp = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET);
1224         tmp &= ~BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);
1225         iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, tmp);
1226
1227         /* flush TX/RX FIFOs */
1228         tmp = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT));
1229         iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, tmp);
1230
1231         /* clear all pending slave interrupts */
1232         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE);
1233
1234         iproc_i2c->slave = NULL;
1235
1236         enable_irq(iproc_i2c->irq);
1237
1238         return 0;
1239 }
1240
1241 static const struct of_device_id bcm_iproc_i2c_of_match[] = {
1242         {
1243                 .compatible = "brcm,iproc-i2c",
1244                 .data = (int *)IPROC_I2C,
1245         }, {
1246                 .compatible = "brcm,iproc-nic-i2c",
1247                 .data = (int *)IPROC_I2C_NIC,
1248         },
1249         { /* sentinel */ }
1250 };
1251 MODULE_DEVICE_TABLE(of, bcm_iproc_i2c_of_match);
1252
1253 static struct platform_driver bcm_iproc_i2c_driver = {
1254         .driver = {
1255                 .name = "bcm-iproc-i2c",
1256                 .of_match_table = bcm_iproc_i2c_of_match,
1257                 .pm = BCM_IPROC_I2C_PM_OPS,
1258         },
1259         .probe = bcm_iproc_i2c_probe,
1260         .remove = bcm_iproc_i2c_remove,
1261 };
1262 module_platform_driver(bcm_iproc_i2c_driver);
1263
1264 MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
1265 MODULE_DESCRIPTION("Broadcom iProc I2C Driver");
1266 MODULE_LICENSE("GPL v2");