drivers/i2c/busses/i2c-bcm-iproc.c

   1 /*
   2  * Copyright (C) 2014 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation version 2.
   7  *
   8  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
   9  * kind, whether express or implied; without even the implied warranty
  10  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/delay.h>
  15 #include <linux/i2c.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/kernel.h>
  19 #include <linux/module.h>
  20 #include <linux/of_device.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/slab.h>
  23
  24 #define IDM_CTRL_DIRECT_OFFSET       0x00
  25 #define CFG_OFFSET                   0x00
  26 #define CFG_RESET_SHIFT              31
  27 #define CFG_EN_SHIFT                 30
  28 #define CFG_SLAVE_ADDR_0_SHIFT       28
  29 #define CFG_M_RETRY_CNT_SHIFT        16
  30 #define CFG_M_RETRY_CNT_MASK         0x0f
  31
  32 #define TIM_CFG_OFFSET               0x04
  33 #define TIM_CFG_MODE_400_SHIFT       31
  34 #define TIM_RAND_SLAVE_STRETCH_SHIFT      24
  35 #define TIM_RAND_SLAVE_STRETCH_MASK       0x7f
  36 #define TIM_PERIODIC_SLAVE_STRETCH_SHIFT  16
  37 #define TIM_PERIODIC_SLAVE_STRETCH_MASK   0x7f
  38
  39 #define S_CFG_SMBUS_ADDR_OFFSET           0x08
  40 #define S_CFG_EN_NIC_SMB_ADDR3_SHIFT      31
  41 #define S_CFG_NIC_SMB_ADDR3_SHIFT         24
  42 #define S_CFG_NIC_SMB_ADDR3_MASK          0x7f
  43 #define S_CFG_EN_NIC_SMB_ADDR2_SHIFT      23
  44 #define S_CFG_NIC_SMB_ADDR2_SHIFT         16
  45 #define S_CFG_NIC_SMB_ADDR2_MASK          0x7f
  46 #define S_CFG_EN_NIC_SMB_ADDR1_SHIFT      15
  47 #define S_CFG_NIC_SMB_ADDR1_SHIFT         8
  48 #define S_CFG_NIC_SMB_ADDR1_MASK          0x7f
  49 #define S_CFG_EN_NIC_SMB_ADDR0_SHIFT      7
  50 #define S_CFG_NIC_SMB_ADDR0_SHIFT         0
  51 #define S_CFG_NIC_SMB_ADDR0_MASK          0x7f
  52
  53 #define M_FIFO_CTRL_OFFSET           0x0c
  54 #define M_FIFO_RX_FLUSH_SHIFT        31
  55 #define M_FIFO_TX_FLUSH_SHIFT        30
  56 #define M_FIFO_RX_CNT_SHIFT          16
  57 #define M_FIFO_RX_CNT_MASK           0x7f
  58 #define M_FIFO_RX_THLD_SHIFT         8
  59 #define M_FIFO_RX_THLD_MASK          0x3f
  60
  61 #define S_FIFO_CTRL_OFFSET           0x10
  62 #define S_FIFO_RX_FLUSH_SHIFT        31
  63 #define S_FIFO_TX_FLUSH_SHIFT        30
  64 #define S_FIFO_RX_CNT_SHIFT          16
  65 #define S_FIFO_RX_CNT_MASK           0x7f
  66 #define S_FIFO_RX_THLD_SHIFT         8
  67 #define S_FIFO_RX_THLD_MASK          0x3f
  68
  69 #define M_CMD_OFFSET                 0x30
  70 #define M_CMD_START_BUSY_SHIFT       31
  71 #define M_CMD_STATUS_SHIFT           25
  72 #define M_CMD_STATUS_MASK            0x07
  73 #define M_CMD_STATUS_SUCCESS         0x0
  74 #define M_CMD_STATUS_LOST_ARB        0x1
  75 #define M_CMD_STATUS_NACK_ADDR       0x2
  76 #define M_CMD_STATUS_NACK_DATA       0x3
  77 #define M_CMD_STATUS_TIMEOUT         0x4
  78 #define M_CMD_STATUS_FIFO_UNDERRUN   0x5
  79 #define M_CMD_STATUS_RX_FIFO_FULL    0x6
  80 #define M_CMD_PROTOCOL_SHIFT         9
  81 #define M_CMD_PROTOCOL_MASK          0xf
  82 #define M_CMD_PROTOCOL_QUICK         0x0
  83 #define M_CMD_PROTOCOL_BLK_WR        0x7
  84 #define M_CMD_PROTOCOL_BLK_RD        0x8
  85 #define M_CMD_PROTOCOL_PROCESS       0xa
  86 #define M_CMD_PEC_SHIFT              8
  87 #define M_CMD_RD_CNT_SHIFT           0
  88 #define M_CMD_RD_CNT_MASK            0xff
  89
  90 #define S_CMD_OFFSET                 0x34
  91 #define S_CMD_START_BUSY_SHIFT       31
  92 #define S_CMD_STATUS_SHIFT           23
  93 #define S_CMD_STATUS_MASK            0x07
  94 #define S_CMD_STATUS_SUCCESS         0x0
  95 #define S_CMD_STATUS_TIMEOUT         0x5
  96 #define S_CMD_STATUS_MASTER_ABORT    0x7
  97
  98 #define IE_OFFSET                    0x38
  99 #define IE_M_RX_FIFO_FULL_SHIFT      31
 100 #define IE_M_RX_THLD_SHIFT           30
 101 #define IE_M_START_BUSY_SHIFT        28
 102 #define IE_M_TX_UNDERRUN_SHIFT       27
 103 #define IE_S_RX_FIFO_FULL_SHIFT      26
 104 #define IE_S_RX_THLD_SHIFT           25
 105 #define IE_S_RX_EVENT_SHIFT          24
 106 #define IE_S_START_BUSY_SHIFT        23
 107 #define IE_S_TX_UNDERRUN_SHIFT       22
 108 #define IE_S_RD_EVENT_SHIFT          21
 109
 110 #define IS_OFFSET                    0x3c
 111 #define IS_M_RX_FIFO_FULL_SHIFT      31
 112 #define IS_M_RX_THLD_SHIFT           30
 113 #define IS_M_START_BUSY_SHIFT        28
 114 #define IS_M_TX_UNDERRUN_SHIFT       27
 115 #define IS_S_RX_FIFO_FULL_SHIFT      26
 116 #define IS_S_RX_THLD_SHIFT           25
 117 #define IS_S_RX_EVENT_SHIFT          24
 118 #define IS_S_START_BUSY_SHIFT        23
 119 #define IS_S_TX_UNDERRUN_SHIFT       22
 120 #define IS_S_RD_EVENT_SHIFT          21
 121
 122 #define M_TX_OFFSET                  0x40
 123 #define M_TX_WR_STATUS_SHIFT         31
 124 #define M_TX_DATA_SHIFT              0
 125 #define M_TX_DATA_MASK               0xff
 126
 127 #define M_RX_OFFSET                  0x44
 128 #define M_RX_STATUS_SHIFT            30
 129 #define M_RX_STATUS_MASK             0x03
 130 #define M_RX_PEC_ERR_SHIFT           29
 131 #define M_RX_DATA_SHIFT              0
 132 #define M_RX_DATA_MASK               0xff
 133
 134 #define S_TX_OFFSET                  0x48
 135 #define S_TX_WR_STATUS_SHIFT         31
 136 #define S_TX_DATA_SHIFT              0
 137 #define S_TX_DATA_MASK               0xff
 138
 139 #define S_RX_OFFSET                  0x4c
 140 #define S_RX_STATUS_SHIFT            30
 141 #define S_RX_STATUS_MASK             0x03
 142 #define S_RX_PEC_ERR_SHIFT           29
 143 #define S_RX_DATA_SHIFT              0
 144 #define S_RX_DATA_MASK               0xff
 145
 146 #define I2C_TIMEOUT_MSEC             50000
 147 #define M_TX_RX_FIFO_SIZE            64
 148 #define M_RX_FIFO_MAX_THLD_VALUE     (M_TX_RX_FIFO_SIZE - 1)
 149
 150 #define M_RX_MAX_READ_LEN            255
 151 #define M_RX_FIFO_THLD_VALUE         50
 152
 153 #define IE_M_ALL_INTERRUPT_SHIFT     27
 154 #define IE_M_ALL_INTERRUPT_MASK      0x1e
 155
 156 #define SLAVE_READ_WRITE_BIT_MASK    0x1
 157 #define SLAVE_READ_WRITE_BIT_SHIFT   0x1
 158 #define SLAVE_MAX_SIZE_TRANSACTION   64
 159 #define SLAVE_CLOCK_STRETCH_TIME     25
 160
 161 #define IE_S_ALL_INTERRUPT_SHIFT     21
 162 #define IE_S_ALL_INTERRUPT_MASK      0x3f
 163
 164 enum i2c_slave_read_status {
 165         I2C_SLAVE_RX_FIFO_EMPTY = 0,
 166         I2C_SLAVE_RX_START,
 167         I2C_SLAVE_RX_DATA,
 168         I2C_SLAVE_RX_END,
 169 };
 170
 171 enum bus_speed_index {
 172         I2C_SPD_100K = 0,
 173         I2C_SPD_400K,
 174 };
 175
 176 enum bcm_iproc_i2c_type {
 177         IPROC_I2C,
 178         IPROC_I2C_NIC
 179 };
 180
 181 struct bcm_iproc_i2c_dev {
 182         struct device *device;
 183         enum bcm_iproc_i2c_type type;
 184         int irq;
 185
 186         void __iomem *base;
 187         void __iomem *idm_base;
 188
 189         u32 ape_addr_mask;
 190
 191         /* lock for indirect access through IDM */
 192         spinlock_t idm_lock;
 193
 194         struct i2c_adapter adapter;
 195         unsigned int bus_speed;
 196
 197         struct completion done;
 198         int xfer_is_done;
 199
 200         struct i2c_msg *msg;
 201
 202         struct i2c_client *slave;
 203
 204         /* bytes that have been transferred */
 205         unsigned int tx_bytes;
 206         /* bytes that have been read */
 207         unsigned int rx_bytes;
 208         unsigned int thld_bytes;
 209 };
 210
 211 /*
 212  * Can be expanded in the future if more interrupt status bits are utilized
 213  */
 214 #define ISR_MASK (BIT(IS_M_START_BUSY_SHIFT) | BIT(IS_M_TX_UNDERRUN_SHIFT)\
 215                 | BIT(IS_M_RX_THLD_SHIFT))
 216
 217 #define ISR_MASK_SLAVE (BIT(IS_S_START_BUSY_SHIFT)\
 218                 | BIT(IS_S_RX_EVENT_SHIFT) | BIT(IS_S_RD_EVENT_SHIFT)\
 219                 | BIT(IS_S_TX_UNDERRUN_SHIFT) | BIT(IS_S_RX_FIFO_FULL_SHIFT)\
 220                 | BIT(IS_S_RX_THLD_SHIFT))
 221
 222 static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave);
 223 static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave);
 224 static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c,
 225                                          bool enable);
 226
 227 static inline u32 iproc_i2c_rd_reg(struct bcm_iproc_i2c_dev *iproc_i2c,
 228                                    u32 offset)
 229 {
 230         u32 val;
 231
 232         if (iproc_i2c->idm_base) {
 233                 spin_lock(&iproc_i2c->idm_lock);
 234                 writel(iproc_i2c->ape_addr_mask,
 235                        iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET);
 236                 val = readl(iproc_i2c->base + offset);
 237                 spin_unlock(&iproc_i2c->idm_lock);
 238         } else {
 239                 val = readl(iproc_i2c->base + offset);
 240         }
 241
 242         return val;
 243 }
 244
 245 static inline void iproc_i2c_wr_reg(struct bcm_iproc_i2c_dev *iproc_i2c,
 246                                     u32 offset, u32 val)
 247 {
 248         if (iproc_i2c->idm_base) {
 249                 spin_lock(&iproc_i2c->idm_lock);
 250                 writel(iproc_i2c->ape_addr_mask,
 251                        iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET);
 252                 writel(val, iproc_i2c->base + offset);
 253                 spin_unlock(&iproc_i2c->idm_lock);
 254         } else {
 255                 writel(val, iproc_i2c->base + offset);
 256         }
 257 }
 258
 259 static void bcm_iproc_i2c_slave_init(
 260         struct bcm_iproc_i2c_dev *iproc_i2c, bool need_reset)
 261 {
 262         u32 val;
 263
 264         if (need_reset) {
 265                 /* put controller in reset */
 266                 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
 267                 val |= BIT(CFG_RESET_SHIFT);
 268                 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
 269
 270                 /* wait 100 usec per spec */
 271                 udelay(100);
 272
 273                 /* bring controller out of reset */
 274                 val &= ~(BIT(CFG_RESET_SHIFT));
 275                 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
 276         }
 277
 278         /* flush TX/RX FIFOs */
 279         val = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT));
 280         iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val);
 281
 282         /* Maximum slave stretch time */
 283         val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
 284         val &= ~(TIM_RAND_SLAVE_STRETCH_MASK << TIM_RAND_SLAVE_STRETCH_SHIFT);
 285         val |= (SLAVE_CLOCK_STRETCH_TIME << TIM_RAND_SLAVE_STRETCH_SHIFT);
 286         iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
 287
 288         /* Configure the slave address */
 289         val = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET);
 290         val |= BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);
 291         val &= ~(S_CFG_NIC_SMB_ADDR3_MASK << S_CFG_NIC_SMB_ADDR3_SHIFT);
 292         val |= (iproc_i2c->slave->addr << S_CFG_NIC_SMB_ADDR3_SHIFT);
 293         iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, val);
 294
 295         /* clear all pending slave interrupts */
 296         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE);
 297
 298         /* Enable interrupt register to indicate a valid byte in receive fifo */
 299         val = BIT(IE_S_RX_EVENT_SHIFT);
 300         /* Enable interrupt register for the Slave BUSY command */
 301         val |= BIT(IE_S_START_BUSY_SHIFT);
 302         iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
 303 }
 304
 305 static void bcm_iproc_i2c_check_slave_status(
 306         struct bcm_iproc_i2c_dev *iproc_i2c)
 307 {
 308         u32 val;
 309
 310         val = iproc_i2c_rd_reg(iproc_i2c, S_CMD_OFFSET);
 311         /* status is valid only when START_BUSY is cleared after it was set */
 312         if (val & BIT(S_CMD_START_BUSY_SHIFT))
 313                 return;
 314
 315         val = (val >> S_CMD_STATUS_SHIFT) & S_CMD_STATUS_MASK;
 316         if (val == S_CMD_STATUS_TIMEOUT || val == S_CMD_STATUS_MASTER_ABORT) {
 317                 dev_err(iproc_i2c->device, (val == S_CMD_STATUS_TIMEOUT) ?
 318                         "slave random stretch time timeout\n" :
 319                         "Master aborted read transaction\n");
 320                 /* re-initialize i2c for recovery */
 321                 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
 322                 bcm_iproc_i2c_slave_init(iproc_i2c, true);
 323                 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
 324         }
 325 }
 326
 327 static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c,
 328                                     u32 status)
 329 {
 330         u32 val;
 331         u8 value, rx_status;
 332
 333         /* Slave RX byte receive */
 334         if (status & BIT(IS_S_RX_EVENT_SHIFT)) {
 335                 val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);
 336                 rx_status = (val >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK;
 337                 if (rx_status == I2C_SLAVE_RX_START) {
 338                         /* Start of SMBUS for Master write */
 339                         i2c_slave_event(iproc_i2c->slave,
 340                                         I2C_SLAVE_WRITE_REQUESTED, &value);
 341
 342                         val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);
 343                         value = (u8)((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK);
 344                         i2c_slave_event(iproc_i2c->slave,
 345                                         I2C_SLAVE_WRITE_RECEIVED, &value);
 346                 } else if (status & BIT(IS_S_RD_EVENT_SHIFT)) {
 347                         /* Start of SMBUS for Master Read */
 348                         i2c_slave_event(iproc_i2c->slave,
 349                                         I2C_SLAVE_READ_REQUESTED, &value);
 350                         iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value);
 351
 352                         val = BIT(S_CMD_START_BUSY_SHIFT);
 353                         iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
 354
 355                         /*
 356                          * Enable interrupt for TX FIFO becomes empty and
 357                          * less than PKT_LENGTH bytes were output on the SMBUS
 358                          */
 359                         val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 360                         val |= BIT(IE_S_TX_UNDERRUN_SHIFT);
 361                         iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
 362                 } else {
 363                         /* Master write other than start */
 364                         value = (u8)((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK);
 365                         i2c_slave_event(iproc_i2c->slave,
 366                                         I2C_SLAVE_WRITE_RECEIVED, &value);
 367                         if (rx_status == I2C_SLAVE_RX_END)
 368                                 i2c_slave_event(iproc_i2c->slave,
 369                                                 I2C_SLAVE_STOP, &value);
 370                 }
 371         } else if (status & BIT(IS_S_TX_UNDERRUN_SHIFT)) {
 372                 /* Master read other than start */
 373                 i2c_slave_event(iproc_i2c->slave,
 374                                 I2C_SLAVE_READ_PROCESSED, &value);
 375
 376                 iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value);
 377                 val = BIT(S_CMD_START_BUSY_SHIFT);
 378                 iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
 379         }
 380
 381         /* Stop */
 382         if (status & BIT(IS_S_START_BUSY_SHIFT)) {
 383                 i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP, &value);
 384                 /*
 385                  * Disable interrupt for TX FIFO becomes empty and
 386                  * less than PKT_LENGTH bytes were output on the SMBUS
 387                  */
 388                 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 389                 val &= ~BIT(IE_S_TX_UNDERRUN_SHIFT);
 390                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
 391         }
 392
 393         /* clear interrupt status */
 394         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
 395
 396         bcm_iproc_i2c_check_slave_status(iproc_i2c);
 397         return true;
 398 }
 399
 400 static void bcm_iproc_i2c_read_valid_bytes(struct bcm_iproc_i2c_dev *iproc_i2c)
 401 {
 402         struct i2c_msg *msg = iproc_i2c->msg;
 403         uint32_t val;
 404
 405         /* Read valid data from RX FIFO */
 406         while (iproc_i2c->rx_bytes < msg->len) {
 407                 val = iproc_i2c_rd_reg(iproc_i2c, M_RX_OFFSET);
 408
 409                 /* rx fifo empty */
 410                 if (!((val >> M_RX_STATUS_SHIFT) & M_RX_STATUS_MASK))
 411                         break;
 412
 413                 msg->buf[iproc_i2c->rx_bytes] =
 414                         (val >> M_RX_DATA_SHIFT) & M_RX_DATA_MASK;
 415                 iproc_i2c->rx_bytes++;
 416         }
 417 }
 418
 419 static void bcm_iproc_i2c_send(struct bcm_iproc_i2c_dev *iproc_i2c)
 420 {
 421         struct i2c_msg *msg = iproc_i2c->msg;
 422         unsigned int tx_bytes = msg->len - iproc_i2c->tx_bytes;
 423         unsigned int i;
 424         u32 val;
 425
 426         /* can only fill up to the FIFO size */
 427         tx_bytes = min_t(unsigned int, tx_bytes, M_TX_RX_FIFO_SIZE);
 428         for (i = 0; i < tx_bytes; i++) {
 429                 /* start from where we left over */
 430                 unsigned int idx = iproc_i2c->tx_bytes + i;
 431
 432                 val = msg->buf[idx];
 433
 434                 /* mark the last byte */
 435                 if (idx == msg->len - 1) {
 436                         val |= BIT(M_TX_WR_STATUS_SHIFT);
 437
 438                         if (iproc_i2c->irq) {
 439                                 u32 tmp;
 440
 441                                 /*
 442                                  * Since this is the last byte, we should now
 443                                  * disable TX FIFO underrun interrupt
 444                                  */
 445                                 tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 446                                 tmp &= ~BIT(IE_M_TX_UNDERRUN_SHIFT);
 447                                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET,
 448                                                  tmp);
 449                         }
 450                 }
 451
 452                 /* load data into TX FIFO */
 453                 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
 454         }
 455
 456         /* update number of transferred bytes */
 457         iproc_i2c->tx_bytes += tx_bytes;
 458 }
 459
 460 static void bcm_iproc_i2c_read(struct bcm_iproc_i2c_dev *iproc_i2c)
 461 {
 462         struct i2c_msg *msg = iproc_i2c->msg;
 463         u32 bytes_left, val;
 464
 465         bcm_iproc_i2c_read_valid_bytes(iproc_i2c);
 466         bytes_left = msg->len - iproc_i2c->rx_bytes;
 467         if (bytes_left == 0) {
 468                 if (iproc_i2c->irq) {
 469                         /* finished reading all data, disable rx thld event */
 470                         val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 471                         val &= ~BIT(IS_M_RX_THLD_SHIFT);
 472                         iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
 473                 }
 474         } else if (bytes_left < iproc_i2c->thld_bytes) {
 475                 /* set bytes left as threshold */
 476                 val = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET);
 477                 val &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
 478                 val |= (bytes_left << M_FIFO_RX_THLD_SHIFT);
 479                 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
 480                 iproc_i2c->thld_bytes = bytes_left;
 481         }
 482         /*
 483          * bytes_left >= iproc_i2c->thld_bytes,
 484          * hence no need to change the THRESHOLD SET.
 485          * It will remain as iproc_i2c->thld_bytes itself
 486          */
 487 }
 488
 489 static void bcm_iproc_i2c_process_m_event(struct bcm_iproc_i2c_dev *iproc_i2c,
 490                                           u32 status)
 491 {
 492         /* TX FIFO is empty and we have more data to send */
 493         if (status & BIT(IS_M_TX_UNDERRUN_SHIFT))
 494                 bcm_iproc_i2c_send(iproc_i2c);
 495
 496         /* RX FIFO threshold is reached and data needs to be read out */
 497         if (status & BIT(IS_M_RX_THLD_SHIFT))
 498                 bcm_iproc_i2c_read(iproc_i2c);
 499
 500         /* transfer is done */
 501         if (status & BIT(IS_M_START_BUSY_SHIFT)) {
 502                 iproc_i2c->xfer_is_done = 1;
 503                 if (iproc_i2c->irq)
 504                         complete(&iproc_i2c->done);
 505         }
 506 }
 507
 508 static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data)
 509 {
 510         struct bcm_iproc_i2c_dev *iproc_i2c = data;
 511         u32 slave_status;
 512         u32 status;
 513         bool ret;
 514
 515         status = iproc_i2c_rd_reg(iproc_i2c, IS_OFFSET);
 516         /* process only slave interrupt which are enabled */
 517         slave_status = status & iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET) &
 518                        ISR_MASK_SLAVE;
 519
 520         if (slave_status) {
 521                 ret = bcm_iproc_i2c_slave_isr(iproc_i2c, slave_status);
 522                 if (ret)
 523                         return IRQ_HANDLED;
 524                 else
 525                         return IRQ_NONE;
 526         }
 527
 528         status &= ISR_MASK;
 529         if (!status)
 530                 return IRQ_NONE;
 531
 532         /* process all master based events */
 533         bcm_iproc_i2c_process_m_event(iproc_i2c, status);
 534         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
 535
 536         return IRQ_HANDLED;
 537 }
 538
 539 static int bcm_iproc_i2c_init(struct bcm_iproc_i2c_dev *iproc_i2c)
 540 {
 541         u32 val;
 542
 543         /* put controller in reset */
 544         val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
 545         val |= BIT(CFG_RESET_SHIFT);
 546         val &= ~(BIT(CFG_EN_SHIFT));
 547         iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
 548
 549         /* wait 100 usec per spec */
 550         udelay(100);
 551
 552         /* bring controller out of reset */
 553         val &= ~(BIT(CFG_RESET_SHIFT));
 554         iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
 555
 556         /* flush TX/RX FIFOs and set RX FIFO threshold to zero */
 557         val = (BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT));
 558         iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
 559         /* disable all interrupts */
 560         val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 561         val &= ~(IE_M_ALL_INTERRUPT_MASK <<
 562                         IE_M_ALL_INTERRUPT_SHIFT);
 563         iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
 564
 565         /* clear all pending interrupts */
 566         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, 0xffffffff);
 567
 568         return 0;
 569 }
 570
 571 static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c,
 572                                          bool enable)
 573 {
 574         u32 val;
 575
 576         val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
 577         if (enable)
 578                 val |= BIT(CFG_EN_SHIFT);
 579         else
 580                 val &= ~BIT(CFG_EN_SHIFT);
 581         iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
 582 }
 583
 584 static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c,
 585                                       struct i2c_msg *msg)
 586 {
 587         u32 val;
 588
 589         val = iproc_i2c_rd_reg(iproc_i2c, M_CMD_OFFSET);
 590         val = (val >> M_CMD_STATUS_SHIFT) & M_CMD_STATUS_MASK;
 591
 592         switch (val) {
 593         case M_CMD_STATUS_SUCCESS:
 594                 return 0;
 595
 596         case M_CMD_STATUS_LOST_ARB:
 597                 dev_dbg(iproc_i2c->device, "lost bus arbitration\n");
 598                 return -EAGAIN;
 599
 600         case M_CMD_STATUS_NACK_ADDR:
 601                 dev_dbg(iproc_i2c->device, "NAK addr:0x%02x\n", msg->addr);
 602                 return -ENXIO;
 603
 604         case M_CMD_STATUS_NACK_DATA:
 605                 dev_dbg(iproc_i2c->device, "NAK data\n");
 606                 return -ENXIO;
 607
 608         case M_CMD_STATUS_TIMEOUT:
 609                 dev_dbg(iproc_i2c->device, "bus timeout\n");
 610                 return -ETIMEDOUT;
 611
 612         case M_CMD_STATUS_FIFO_UNDERRUN:
 613                 dev_dbg(iproc_i2c->device, "FIFO under-run\n");
 614                 return -ENXIO;
 615
 616         case M_CMD_STATUS_RX_FIFO_FULL:
 617                 dev_dbg(iproc_i2c->device, "RX FIFO full\n");
 618                 return -ETIMEDOUT;
 619
 620         default:
 621                 dev_dbg(iproc_i2c->device, "unknown error code=%d\n", val);
 622
 623                 /* re-initialize i2c for recovery */
 624                 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
 625                 bcm_iproc_i2c_init(iproc_i2c);
 626                 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
 627
 628                 return -EIO;
 629         }
 630 }
 631
 632 static int bcm_iproc_i2c_xfer_wait(struct bcm_iproc_i2c_dev *iproc_i2c,
 633                                    struct i2c_msg *msg,
 634                                    u32 cmd)
 635 {
 636         unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT_MSEC);
 637         u32 val, status;
 638         int ret;
 639
 640         iproc_i2c_wr_reg(iproc_i2c, M_CMD_OFFSET, cmd);
 641
 642         if (iproc_i2c->irq) {
 643                 time_left = wait_for_completion_timeout(&iproc_i2c->done,
 644                                                         time_left);
 645                 /* disable all interrupts */
 646                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
 647                 /* read it back to flush the write */
 648                 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 649                 /* make sure the interrupt handler isn't running */
 650                 synchronize_irq(iproc_i2c->irq);
 651
 652         } else { /* polling mode */
 653                 unsigned long timeout = jiffies + time_left;
 654
 655                 do {
 656                         status = iproc_i2c_rd_reg(iproc_i2c,
 657                                                   IS_OFFSET) & ISR_MASK;
 658                         bcm_iproc_i2c_process_m_event(iproc_i2c, status);
 659                         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
 660
 661                         if (time_after(jiffies, timeout)) {
 662                                 time_left = 0;
 663                                 break;
 664                         }
 665
 666                         cpu_relax();
 667                         cond_resched();
 668                 } while (!iproc_i2c->xfer_is_done);
 669         }
 670
 671         if (!time_left && !iproc_i2c->xfer_is_done) {
 672                 dev_err(iproc_i2c->device, "transaction timed out\n");
 673
 674                 /* flush both TX/RX FIFOs */
 675                 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
 676                 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
 677                 return -ETIMEDOUT;
 678         }
 679
 680         ret = bcm_iproc_i2c_check_status(iproc_i2c, msg);
 681         if (ret) {
 682                 /* flush both TX/RX FIFOs */
 683                 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
 684                 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
 685                 return ret;
 686         }
 687
 688         return 0;
 689 }
 690
 691 /*
 692  * If 'process_call' is true, then this is a multi-msg transfer that requires
 693  * a repeated start between the messages.
 694  * More specifically, it must be a write (reg) followed by a read (data).
 695  * The i2c quirks are set to enforce this rule.
 696  */
 697 static int bcm_iproc_i2c_xfer_internal(struct bcm_iproc_i2c_dev *iproc_i2c,
 698                                         struct i2c_msg *msgs, bool process_call)
 699 {
 700         int i;
 701         u8 addr;
 702         u32 val, tmp, val_intr_en;
 703         unsigned int tx_bytes;
 704         struct i2c_msg *msg = &msgs[0];
 705
 706         /* check if bus is busy */
 707         if (!!(iproc_i2c_rd_reg(iproc_i2c,
 708                                 M_CMD_OFFSET) & BIT(M_CMD_START_BUSY_SHIFT))) {
 709                 dev_warn(iproc_i2c->device, "bus is busy\n");
 710                 return -EBUSY;
 711         }
 712
 713         iproc_i2c->msg = msg;
 714
 715         /* format and load slave address into the TX FIFO */
 716         addr = i2c_8bit_addr_from_msg(msg);
 717         iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, addr);
 718
 719         /*
 720          * For a write transaction, load data into the TX FIFO. Only allow
 721          * loading up to TX FIFO size - 1 bytes of data since the first byte
 722          * has been used up by the slave address
 723          */
 724         tx_bytes = min_t(unsigned int, msg->len, M_TX_RX_FIFO_SIZE - 1);
 725         if (!(msg->flags & I2C_M_RD)) {
 726                 for (i = 0; i < tx_bytes; i++) {
 727                         val = msg->buf[i];
 728
 729                         /* mark the last byte */
 730                         if (!process_call && (i == msg->len - 1))
 731                                 val |= BIT(M_TX_WR_STATUS_SHIFT);
 732
 733                         iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
 734                 }
 735                 iproc_i2c->tx_bytes = tx_bytes;
 736         }
 737
 738         /* Process the read message if this is process call */
 739         if (process_call) {
 740                 msg++;
 741                 iproc_i2c->msg = msg;  /* point to second msg */
 742
 743                 /*
 744                  * The last byte to be sent out should be a slave
 745                  * address with read operation
 746                  */
 747                 addr = i2c_8bit_addr_from_msg(msg);
 748                 /* mark it the last byte out */
 749                 val = addr | BIT(M_TX_WR_STATUS_SHIFT);
 750                 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
 751         }
 752
 753         /* mark as incomplete before starting the transaction */
 754         if (iproc_i2c->irq)
 755                 reinit_completion(&iproc_i2c->done);
 756
 757         iproc_i2c->xfer_is_done = 0;
 758
 759         /*
 760          * Enable the "start busy" interrupt, which will be triggered after the
 761          * transaction is done, i.e., the internal start_busy bit, transitions
 762          * from 1 to 0.
 763          */
 764         val_intr_en = BIT(IE_M_START_BUSY_SHIFT);
 765
 766         /*
 767          * If TX data size is larger than the TX FIFO, need to enable TX
 768          * underrun interrupt, which will be triggerred when the TX FIFO is
 769          * empty. When that happens we can then pump more data into the FIFO
 770          */
 771         if (!process_call && !(msg->flags & I2C_M_RD) &&
 772             msg->len > iproc_i2c->tx_bytes)
 773                 val_intr_en |= BIT(IE_M_TX_UNDERRUN_SHIFT);
 774
 775         /*
 776          * Now we can activate the transfer. For a read operation, specify the
 777          * number of bytes to read
 778          */
 779         val = BIT(M_CMD_START_BUSY_SHIFT);
 780
 781         if (msg->len == 0) {
 782                 /* SMBUS QUICK Command (Read/Write) */
 783                 val |= (M_CMD_PROTOCOL_QUICK << M_CMD_PROTOCOL_SHIFT);
 784         } else if (msg->flags & I2C_M_RD) {
 785                 u32 protocol;
 786
 787                 iproc_i2c->rx_bytes = 0;
 788                 if (msg->len > M_RX_FIFO_MAX_THLD_VALUE)
 789                         iproc_i2c->thld_bytes = M_RX_FIFO_THLD_VALUE;
 790                 else
 791                         iproc_i2c->thld_bytes = msg->len;
 792
 793                 /* set threshold value */
 794                 tmp = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET);
 795                 tmp &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
 796                 tmp |= iproc_i2c->thld_bytes << M_FIFO_RX_THLD_SHIFT;
 797                 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, tmp);
 798
 799                 /* enable the RX threshold interrupt */
 800                 val_intr_en |= BIT(IE_M_RX_THLD_SHIFT);
 801
 802                 protocol = process_call ?
 803                                 M_CMD_PROTOCOL_PROCESS : M_CMD_PROTOCOL_BLK_RD;
 804
 805                 val |= (protocol << M_CMD_PROTOCOL_SHIFT) |
 806                        (msg->len << M_CMD_RD_CNT_SHIFT);
 807         } else {
 808                 val |= (M_CMD_PROTOCOL_BLK_WR << M_CMD_PROTOCOL_SHIFT);
 809         }
 810
 811         if (iproc_i2c->irq)
 812                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val_intr_en);
 813
 814         return bcm_iproc_i2c_xfer_wait(iproc_i2c, msg, val);
 815 }
 816
 817 static int bcm_iproc_i2c_xfer(struct i2c_adapter *adapter,
 818                               struct i2c_msg msgs[], int num)
 819 {
 820         struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(adapter);
 821         bool process_call = false;
 822         int ret;
 823
 824         if (num == 2) {
 825                 /* Repeated start, use process call */
 826                 process_call = true;
 827                 if (msgs[1].flags & I2C_M_NOSTART) {
 828                         dev_err(iproc_i2c->device, "Invalid repeated start\n");
 829                         return -EOPNOTSUPP;
 830                 }
 831         }
 832
 833         ret = bcm_iproc_i2c_xfer_internal(iproc_i2c, msgs, process_call);
 834         if (ret) {
 835                 dev_dbg(iproc_i2c->device, "xfer failed\n");
 836                 return ret;
 837         }
 838
 839         return num;
 840 }
 841
 842 static uint32_t bcm_iproc_i2c_functionality(struct i2c_adapter *adap)
 843 {
 844         u32 val;
 845
 846         val = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 847
 848         if (adap->algo->reg_slave)
 849                 val |= I2C_FUNC_SLAVE;
 850
 851         return val;
 852 }
 853
 854 static struct i2c_algorithm bcm_iproc_algo = {
 855         .master_xfer = bcm_iproc_i2c_xfer,
 856         .functionality = bcm_iproc_i2c_functionality,
 857         .reg_slave = bcm_iproc_i2c_reg_slave,
 858         .unreg_slave = bcm_iproc_i2c_unreg_slave,
 859 };
 860
 861 static const struct i2c_adapter_quirks bcm_iproc_i2c_quirks = {
 862         .flags = I2C_AQ_COMB_WRITE_THEN_READ,
 863         .max_comb_1st_msg_len = M_TX_RX_FIFO_SIZE,
 864         .max_read_len = M_RX_MAX_READ_LEN,
 865 };
 866
 867 static int bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev *iproc_i2c)
 868 {
 869         unsigned int bus_speed;
 870         u32 val;
 871         int ret = of_property_read_u32(iproc_i2c->device->of_node,
 872                                        "clock-frequency", &bus_speed);
 873         if (ret < 0) {
 874                 dev_info(iproc_i2c->device,
 875                         "unable to interpret clock-frequency DT property\n");
 876                 bus_speed = I2C_MAX_STANDARD_MODE_FREQ;
 877         }
 878
 879         if (bus_speed < I2C_MAX_STANDARD_MODE_FREQ) {
 880                 dev_err(iproc_i2c->device, "%d Hz bus speed not supported\n",
 881                         bus_speed);
 882                 dev_err(iproc_i2c->device,
 883                         "valid speeds are 100khz and 400khz\n");
 884                 return -EINVAL;
 885         } else if (bus_speed < I2C_MAX_FAST_MODE_FREQ) {
 886                 bus_speed = I2C_MAX_STANDARD_MODE_FREQ;
 887         } else {
 888                 bus_speed = I2C_MAX_FAST_MODE_FREQ;
 889         }
 890
 891         iproc_i2c->bus_speed = bus_speed;
 892         val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
 893         val &= ~BIT(TIM_CFG_MODE_400_SHIFT);
 894         val |= (bus_speed == I2C_MAX_FAST_MODE_FREQ) << TIM_CFG_MODE_400_SHIFT;
 895         iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
 896
 897         dev_info(iproc_i2c->device, "bus set to %u Hz\n", bus_speed);
 898
 899         return 0;
 900 }
 901
 902 static int bcm_iproc_i2c_probe(struct platform_device *pdev)
 903 {
 904         int irq, ret = 0;
 905         struct bcm_iproc_i2c_dev *iproc_i2c;
 906         struct i2c_adapter *adap;
 907         struct resource *res;
 908
 909         iproc_i2c = devm_kzalloc(&pdev->dev, sizeof(*iproc_i2c),
 910                                  GFP_KERNEL);
 911         if (!iproc_i2c)
 912                 return -ENOMEM;
 913
 914         platform_set_drvdata(pdev, iproc_i2c);
 915         iproc_i2c->device = &pdev->dev;
 916         iproc_i2c->type =
 917                 (enum bcm_iproc_i2c_type)of_device_get_match_data(&pdev->dev);
 918         init_completion(&iproc_i2c->done);
 919
 920         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 921         iproc_i2c->base = devm_ioremap_resource(iproc_i2c->device, res);
 922         if (IS_ERR(iproc_i2c->base))
 923                 return PTR_ERR(iproc_i2c->base);
 924
 925         if (iproc_i2c->type == IPROC_I2C_NIC) {
 926                 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 927                 iproc_i2c->idm_base = devm_ioremap_resource(iproc_i2c->device,
 928                                                             res);
 929                 if (IS_ERR(iproc_i2c->idm_base))
 930                         return PTR_ERR(iproc_i2c->idm_base);
 931
 932                 ret = of_property_read_u32(iproc_i2c->device->of_node,
 933                                            "brcm,ape-hsls-addr-mask",
 934                                            &iproc_i2c->ape_addr_mask);
 935                 if (ret < 0) {
 936                         dev_err(iproc_i2c->device,
 937                                 "'brcm,ape-hsls-addr-mask' missing\n");
 938                         return -EINVAL;
 939                 }
 940
 941                 spin_lock_init(&iproc_i2c->idm_lock);
 942
 943                 /* no slave support */
 944                 bcm_iproc_algo.reg_slave = NULL;
 945                 bcm_iproc_algo.unreg_slave = NULL;
 946         }
 947
 948         ret = bcm_iproc_i2c_init(iproc_i2c);
 949         if (ret)
 950                 return ret;
 951
 952         ret = bcm_iproc_i2c_cfg_speed(iproc_i2c);
 953         if (ret)
 954                 return ret;
 955
 956         irq = platform_get_irq(pdev, 0);
 957         if (irq > 0) {
 958                 ret = devm_request_irq(iproc_i2c->device, irq,
 959                                        bcm_iproc_i2c_isr, 0, pdev->name,
 960                                        iproc_i2c);
 961                 if (ret < 0) {
 962                         dev_err(iproc_i2c->device,
 963                                 "unable to request irq %i\n", irq);
 964                         return ret;
 965                 }
 966
 967                 iproc_i2c->irq = irq;
 968         } else {
 969                 dev_warn(iproc_i2c->device,
 970                          "no irq resource, falling back to poll mode\n");
 971         }
 972
 973         bcm_iproc_i2c_enable_disable(iproc_i2c, true);
 974
 975         adap = &iproc_i2c->adapter;
 976         i2c_set_adapdata(adap, iproc_i2c);
 977         snprintf(adap->name, sizeof(adap->name),
 978                 "Broadcom iProc (%s)",
 979                 of_node_full_name(iproc_i2c->device->of_node));
 980         adap->algo = &bcm_iproc_algo;
 981         adap->quirks = &bcm_iproc_i2c_quirks;
 982         adap->dev.parent = &pdev->dev;
 983         adap->dev.of_node = pdev->dev.of_node;
 984
 985         return i2c_add_adapter(adap);
 986 }
 987
 988 static int bcm_iproc_i2c_remove(struct platform_device *pdev)
 989 {
 990         struct bcm_iproc_i2c_dev *iproc_i2c = platform_get_drvdata(pdev);
 991
 992         if (iproc_i2c->irq) {
 993                 /*
 994                  * Make sure there's no pending interrupt when we remove the
 995                  * adapter
 996                  */
 997                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
 998                 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 999                 synchronize_irq(iproc_i2c->irq);
1000         }
1001
1002         i2c_del_adapter(&iproc_i2c->adapter);
1003         bcm_iproc_i2c_enable_disable(iproc_i2c, false);
1004
1005         return 0;
1006 }
1007
1008 #ifdef CONFIG_PM_SLEEP
1009
1010 static int bcm_iproc_i2c_suspend(struct device *dev)
1011 {
1012         struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev);
1013
1014         if (iproc_i2c->irq) {
1015                 /*
1016                  * Make sure there's no pending interrupt when we go into
1017                  * suspend
1018                  */
1019                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
1020                 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
1021                 synchronize_irq(iproc_i2c->irq);
1022         }
1023
1024         /* now disable the controller */
1025         bcm_iproc_i2c_enable_disable(iproc_i2c, false);
1026
1027         return 0;
1028 }
1029
1030 static int bcm_iproc_i2c_resume(struct device *dev)
1031 {
1032         struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev);
1033         int ret;
1034         u32 val;
1035
1036         /*
1037          * Power domain could have been shut off completely in system deep
1038          * sleep, so re-initialize the block here
1039          */
1040         ret = bcm_iproc_i2c_init(iproc_i2c);
1041         if (ret)
1042                 return ret;
1043
1044         /* configure to the desired bus speed */
1045         val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
1046         val &= ~BIT(TIM_CFG_MODE_400_SHIFT);
1047         val |= (iproc_i2c->bus_speed == I2C_MAX_FAST_MODE_FREQ) << TIM_CFG_MODE_400_SHIFT;
1048         iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
1049
1050         bcm_iproc_i2c_enable_disable(iproc_i2c, true);
1051
1052         return 0;
1053 }
1054
1055 static const struct dev_pm_ops bcm_iproc_i2c_pm_ops = {
1056         .suspend_late = &bcm_iproc_i2c_suspend,
1057         .resume_early = &bcm_iproc_i2c_resume
1058 };
1059
1060 #define BCM_IPROC_I2C_PM_OPS (&bcm_iproc_i2c_pm_ops)
1061 #else
1062 #define BCM_IPROC_I2C_PM_OPS NULL
1063 #endif /* CONFIG_PM_SLEEP */
1064
1065
1066 static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave)
1067 {
1068         struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter);
1069
1070         if (iproc_i2c->slave)
1071                 return -EBUSY;
1072
1073         if (slave->flags & I2C_CLIENT_TEN)
1074                 return -EAFNOSUPPORT;
1075
1076         iproc_i2c->slave = slave;
1077         bcm_iproc_i2c_slave_init(iproc_i2c, false);
1078         return 0;
1079 }
1080
1081 static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave)
1082 {
1083         u32 tmp;
1084         struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter);
1085
1086         if (!iproc_i2c->slave)
1087                 return -EINVAL;
1088
1089         disable_irq(iproc_i2c->irq);
1090
1091         /* disable all slave interrupts */
1092         tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
1093         tmp &= ~(IE_S_ALL_INTERRUPT_MASK <<
1094                         IE_S_ALL_INTERRUPT_SHIFT);
1095         iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, tmp);
1096
1097         /* Erase the slave address programmed */
1098         tmp = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET);
1099         tmp &= ~BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);
1100         iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, tmp);
1101
1102         /* flush TX/RX FIFOs */
1103         tmp = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT));
1104         iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, tmp);
1105
1106         /* clear all pending slave interrupts */
1107         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE);
1108
1109         iproc_i2c->slave = NULL;
1110
1111         enable_irq(iproc_i2c->irq);
1112
1113         return 0;
1114 }
1115
1116 static const struct of_device_id bcm_iproc_i2c_of_match[] = {
1117         {
1118                 .compatible = "brcm,iproc-i2c",
1119                 .data = (int *)IPROC_I2C,
1120         }, {
1121                 .compatible = "brcm,iproc-nic-i2c",
1122                 .data = (int *)IPROC_I2C_NIC,
1123         },
1124         { /* sentinel */ }
1125 };
1126 MODULE_DEVICE_TABLE(of, bcm_iproc_i2c_of_match);
1127
1128 static struct platform_driver bcm_iproc_i2c_driver = {
1129         .driver = {
1130                 .name = "bcm-iproc-i2c",
1131                 .of_match_table = bcm_iproc_i2c_of_match,
1132                 .pm = BCM_IPROC_I2C_PM_OPS,
1133         },
1134         .probe = bcm_iproc_i2c_probe,
1135         .remove = bcm_iproc_i2c_remove,
1136 };
1137 module_platform_driver(bcm_iproc_i2c_driver);
1138
1139 MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
1140 MODULE_DESCRIPTION("Broadcom iProc I2C Driver");
1141 MODULE_LICENSE("GPL v2");