drivers/i2c/busses/i2c-bcm-iproc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 // Copyright (C) 2014 Broadcom Corporation
   3
   4 #include <linux/delay.h>
   5 #include <linux/i2c.h>
   6 #include <linux/interrupt.h>
   7 #include <linux/io.h>
   8 #include <linux/kernel.h>
   9 #include <linux/module.h>
  10 #include <linux/of_device.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/slab.h>
  13
  14 #define IDM_CTRL_DIRECT_OFFSET       0x00
  15 #define CFG_OFFSET                   0x00
  16 #define CFG_RESET_SHIFT              31
  17 #define CFG_EN_SHIFT                 30
  18 #define CFG_SLAVE_ADDR_0_SHIFT       28
  19 #define CFG_M_RETRY_CNT_SHIFT        16
  20 #define CFG_M_RETRY_CNT_MASK         0x0f
  21
  22 #define TIM_CFG_OFFSET               0x04
  23 #define TIM_CFG_MODE_400_SHIFT       31
  24 #define TIM_RAND_SLAVE_STRETCH_SHIFT      24
  25 #define TIM_RAND_SLAVE_STRETCH_MASK       0x7f
  26 #define TIM_PERIODIC_SLAVE_STRETCH_SHIFT  16
  27 #define TIM_PERIODIC_SLAVE_STRETCH_MASK   0x7f
  28
  29 #define S_CFG_SMBUS_ADDR_OFFSET           0x08
  30 #define S_CFG_EN_NIC_SMB_ADDR3_SHIFT      31
  31 #define S_CFG_NIC_SMB_ADDR3_SHIFT         24
  32 #define S_CFG_NIC_SMB_ADDR3_MASK          0x7f
  33 #define S_CFG_EN_NIC_SMB_ADDR2_SHIFT      23
  34 #define S_CFG_NIC_SMB_ADDR2_SHIFT         16
  35 #define S_CFG_NIC_SMB_ADDR2_MASK          0x7f
  36 #define S_CFG_EN_NIC_SMB_ADDR1_SHIFT      15
  37 #define S_CFG_NIC_SMB_ADDR1_SHIFT         8
  38 #define S_CFG_NIC_SMB_ADDR1_MASK          0x7f
  39 #define S_CFG_EN_NIC_SMB_ADDR0_SHIFT      7
  40 #define S_CFG_NIC_SMB_ADDR0_SHIFT         0
  41 #define S_CFG_NIC_SMB_ADDR0_MASK          0x7f
  42
  43 #define M_FIFO_CTRL_OFFSET           0x0c
  44 #define M_FIFO_RX_FLUSH_SHIFT        31
  45 #define M_FIFO_TX_FLUSH_SHIFT        30
  46 #define M_FIFO_RX_CNT_SHIFT          16
  47 #define M_FIFO_RX_CNT_MASK           0x7f
  48 #define M_FIFO_RX_THLD_SHIFT         8
  49 #define M_FIFO_RX_THLD_MASK          0x3f
  50
  51 #define S_FIFO_CTRL_OFFSET           0x10
  52 #define S_FIFO_RX_FLUSH_SHIFT        31
  53 #define S_FIFO_TX_FLUSH_SHIFT        30
  54 #define S_FIFO_RX_CNT_SHIFT          16
  55 #define S_FIFO_RX_CNT_MASK           0x7f
  56 #define S_FIFO_RX_THLD_SHIFT         8
  57 #define S_FIFO_RX_THLD_MASK          0x3f
  58
  59 #define M_CMD_OFFSET                 0x30
  60 #define M_CMD_START_BUSY_SHIFT       31
  61 #define M_CMD_STATUS_SHIFT           25
  62 #define M_CMD_STATUS_MASK            0x07
  63 #define M_CMD_STATUS_SUCCESS         0x0
  64 #define M_CMD_STATUS_LOST_ARB        0x1
  65 #define M_CMD_STATUS_NACK_ADDR       0x2
  66 #define M_CMD_STATUS_NACK_DATA       0x3
  67 #define M_CMD_STATUS_TIMEOUT         0x4
  68 #define M_CMD_STATUS_FIFO_UNDERRUN   0x5
  69 #define M_CMD_STATUS_RX_FIFO_FULL    0x6
  70 #define M_CMD_PROTOCOL_SHIFT         9
  71 #define M_CMD_PROTOCOL_MASK          0xf
  72 #define M_CMD_PROTOCOL_QUICK         0x0
  73 #define M_CMD_PROTOCOL_BLK_WR        0x7
  74 #define M_CMD_PROTOCOL_BLK_RD        0x8
  75 #define M_CMD_PROTOCOL_PROCESS       0xa
  76 #define M_CMD_PEC_SHIFT              8
  77 #define M_CMD_RD_CNT_SHIFT           0
  78 #define M_CMD_RD_CNT_MASK            0xff
  79
  80 #define S_CMD_OFFSET                 0x34
  81 #define S_CMD_START_BUSY_SHIFT       31
  82 #define S_CMD_STATUS_SHIFT           23
  83 #define S_CMD_STATUS_MASK            0x07
  84 #define S_CMD_STATUS_SUCCESS         0x0
  85 #define S_CMD_STATUS_TIMEOUT         0x5
  86 #define S_CMD_STATUS_MASTER_ABORT    0x7
  87
  88 #define IE_OFFSET                    0x38
  89 #define IE_M_RX_FIFO_FULL_SHIFT      31
  90 #define IE_M_RX_THLD_SHIFT           30
  91 #define IE_M_START_BUSY_SHIFT        28
  92 #define IE_M_TX_UNDERRUN_SHIFT       27
  93 #define IE_S_RX_FIFO_FULL_SHIFT      26
  94 #define IE_S_RX_THLD_SHIFT           25
  95 #define IE_S_RX_EVENT_SHIFT          24
  96 #define IE_S_START_BUSY_SHIFT        23
  97 #define IE_S_TX_UNDERRUN_SHIFT       22
  98 #define IE_S_RD_EVENT_SHIFT          21
  99
 100 #define IS_OFFSET                    0x3c
 101 #define IS_M_RX_FIFO_FULL_SHIFT      31
 102 #define IS_M_RX_THLD_SHIFT           30
 103 #define IS_M_START_BUSY_SHIFT        28
 104 #define IS_M_TX_UNDERRUN_SHIFT       27
 105 #define IS_S_RX_FIFO_FULL_SHIFT      26
 106 #define IS_S_RX_THLD_SHIFT           25
 107 #define IS_S_RX_EVENT_SHIFT          24
 108 #define IS_S_START_BUSY_SHIFT        23
 109 #define IS_S_TX_UNDERRUN_SHIFT       22
 110 #define IS_S_RD_EVENT_SHIFT          21
 111
 112 #define M_TX_OFFSET                  0x40
 113 #define M_TX_WR_STATUS_SHIFT         31
 114 #define M_TX_DATA_SHIFT              0
 115 #define M_TX_DATA_MASK               0xff
 116
 117 #define M_RX_OFFSET                  0x44
 118 #define M_RX_STATUS_SHIFT            30
 119 #define M_RX_STATUS_MASK             0x03
 120 #define M_RX_PEC_ERR_SHIFT           29
 121 #define M_RX_DATA_SHIFT              0
 122 #define M_RX_DATA_MASK               0xff
 123
 124 #define S_TX_OFFSET                  0x48
 125 #define S_TX_WR_STATUS_SHIFT         31
 126 #define S_TX_DATA_SHIFT              0
 127 #define S_TX_DATA_MASK               0xff
 128
 129 #define S_RX_OFFSET                  0x4c
 130 #define S_RX_STATUS_SHIFT            30
 131 #define S_RX_STATUS_MASK             0x03
 132 #define S_RX_PEC_ERR_SHIFT           29
 133 #define S_RX_DATA_SHIFT              0
 134 #define S_RX_DATA_MASK               0xff
 135
 136 #define I2C_TIMEOUT_MSEC             50000
 137 #define M_TX_RX_FIFO_SIZE            64
 138 #define M_RX_FIFO_MAX_THLD_VALUE     (M_TX_RX_FIFO_SIZE - 1)
 139
 140 #define M_RX_MAX_READ_LEN            255
 141 #define M_RX_FIFO_THLD_VALUE         50
 142
 143 #define IE_M_ALL_INTERRUPT_SHIFT     27
 144 #define IE_M_ALL_INTERRUPT_MASK      0x1e
 145
 146 #define SLAVE_READ_WRITE_BIT_MASK    0x1
 147 #define SLAVE_READ_WRITE_BIT_SHIFT   0x1
 148 #define SLAVE_MAX_SIZE_TRANSACTION   64
 149 #define SLAVE_CLOCK_STRETCH_TIME     25
 150
 151 #define IE_S_ALL_INTERRUPT_SHIFT     21
 152 #define IE_S_ALL_INTERRUPT_MASK      0x3f
 153 /*
 154  * It takes ~18us to reading 10bytes of data, hence to keep tasklet
 155  * running for less time, max slave read per tasklet is set to 10 bytes.
 156  */
 157 #define MAX_SLAVE_RX_PER_INT         10
 158
 159 enum i2c_slave_read_status {
 160         I2C_SLAVE_RX_FIFO_EMPTY = 0,
 161         I2C_SLAVE_RX_START,
 162         I2C_SLAVE_RX_DATA,
 163         I2C_SLAVE_RX_END,
 164 };
 165
 166 enum bus_speed_index {
 167         I2C_SPD_100K = 0,
 168         I2C_SPD_400K,
 169 };
 170
 171 enum bcm_iproc_i2c_type {
 172         IPROC_I2C,
 173         IPROC_I2C_NIC
 174 };
 175
 176 struct bcm_iproc_i2c_dev {
 177         struct device *device;
 178         enum bcm_iproc_i2c_type type;
 179         int irq;
 180
 181         void __iomem *base;
 182         void __iomem *idm_base;
 183
 184         u32 ape_addr_mask;
 185
 186         /* lock for indirect access through IDM */
 187         spinlock_t idm_lock;
 188
 189         struct i2c_adapter adapter;
 190         unsigned int bus_speed;
 191
 192         struct completion done;
 193         int xfer_is_done;
 194
 195         struct i2c_msg *msg;
 196
 197         struct i2c_client *slave;
 198
 199         /* bytes that have been transferred */
 200         unsigned int tx_bytes;
 201         /* bytes that have been read */
 202         unsigned int rx_bytes;
 203         unsigned int thld_bytes;
 204
 205         bool slave_rx_only;
 206         bool rx_start_rcvd;
 207         bool slave_read_complete;
 208         u32 tx_underrun;
 209         u32 slave_int_mask;
 210         struct tasklet_struct slave_rx_tasklet;
 211 };
 212
 213 /* tasklet to process slave rx data */
 214 static void slave_rx_tasklet_fn(unsigned long);
 215
 216 /*
 217  * Can be expanded in the future if more interrupt status bits are utilized
 218  */
 219 #define ISR_MASK (BIT(IS_M_START_BUSY_SHIFT) | BIT(IS_M_TX_UNDERRUN_SHIFT)\
 220                 | BIT(IS_M_RX_THLD_SHIFT))
 221
 222 #define ISR_MASK_SLAVE (BIT(IS_S_START_BUSY_SHIFT)\
 223                 | BIT(IS_S_RX_EVENT_SHIFT) | BIT(IS_S_RD_EVENT_SHIFT)\
 224                 | BIT(IS_S_TX_UNDERRUN_SHIFT) | BIT(IS_S_RX_FIFO_FULL_SHIFT)\
 225                 | BIT(IS_S_RX_THLD_SHIFT))
 226
 227 static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave);
 228 static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave);
 229 static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c,
 230                                          bool enable);
 231
 232 static inline u32 iproc_i2c_rd_reg(struct bcm_iproc_i2c_dev *iproc_i2c,
 233                                    u32 offset)
 234 {
 235         u32 val;
 236
 237         if (iproc_i2c->idm_base) {
 238                 spin_lock(&iproc_i2c->idm_lock);
 239                 writel(iproc_i2c->ape_addr_mask,
 240                        iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET);
 241                 val = readl(iproc_i2c->base + offset);
 242                 spin_unlock(&iproc_i2c->idm_lock);
 243         } else {
 244                 val = readl(iproc_i2c->base + offset);
 245         }
 246
 247         return val;
 248 }
 249
 250 static inline void iproc_i2c_wr_reg(struct bcm_iproc_i2c_dev *iproc_i2c,
 251                                     u32 offset, u32 val)
 252 {
 253         if (iproc_i2c->idm_base) {
 254                 spin_lock(&iproc_i2c->idm_lock);
 255                 writel(iproc_i2c->ape_addr_mask,
 256                        iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET);
 257                 writel(val, iproc_i2c->base + offset);
 258                 spin_unlock(&iproc_i2c->idm_lock);
 259         } else {
 260                 writel(val, iproc_i2c->base + offset);
 261         }
 262 }
 263
 264 static void bcm_iproc_i2c_slave_init(
 265         struct bcm_iproc_i2c_dev *iproc_i2c, bool need_reset)
 266 {
 267         u32 val;
 268
 269         iproc_i2c->tx_underrun = 0;
 270         if (need_reset) {
 271                 /* put controller in reset */
 272                 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
 273                 val |= BIT(CFG_RESET_SHIFT);
 274                 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
 275
 276                 /* wait 100 usec per spec */
 277                 udelay(100);
 278
 279                 /* bring controller out of reset */
 280                 val &= ~(BIT(CFG_RESET_SHIFT));
 281                 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
 282         }
 283
 284         /* flush TX/RX FIFOs */
 285         val = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT));
 286         iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val);
 287
 288         /* Maximum slave stretch time */
 289         val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
 290         val &= ~(TIM_RAND_SLAVE_STRETCH_MASK << TIM_RAND_SLAVE_STRETCH_SHIFT);
 291         val |= (SLAVE_CLOCK_STRETCH_TIME << TIM_RAND_SLAVE_STRETCH_SHIFT);
 292         iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
 293
 294         /* Configure the slave address */
 295         val = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET);
 296         val |= BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);
 297         val &= ~(S_CFG_NIC_SMB_ADDR3_MASK << S_CFG_NIC_SMB_ADDR3_SHIFT);
 298         val |= (iproc_i2c->slave->addr << S_CFG_NIC_SMB_ADDR3_SHIFT);
 299         iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, val);
 300
 301         /* clear all pending slave interrupts */
 302         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE);
 303
 304         /* Enable interrupt register to indicate a valid byte in receive fifo */
 305         val = BIT(IE_S_RX_EVENT_SHIFT);
 306         /* Enable interrupt register to indicate Slave Rx FIFO Full */
 307         val |= BIT(IE_S_RX_FIFO_FULL_SHIFT);
 308         /* Enable interrupt register to indicate a Master read transaction */
 309         val |= BIT(IE_S_RD_EVENT_SHIFT);
 310         /* Enable interrupt register for the Slave BUSY command */
 311         val |= BIT(IE_S_START_BUSY_SHIFT);
 312         iproc_i2c->slave_int_mask = val;
 313         iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
 314 }
 315
 316 static void bcm_iproc_i2c_check_slave_status(
 317         struct bcm_iproc_i2c_dev *iproc_i2c)
 318 {
 319         u32 val;
 320
 321         val = iproc_i2c_rd_reg(iproc_i2c, S_CMD_OFFSET);
 322         /* status is valid only when START_BUSY is cleared after it was set */
 323         if (val & BIT(S_CMD_START_BUSY_SHIFT))
 324                 return;
 325
 326         val = (val >> S_CMD_STATUS_SHIFT) & S_CMD_STATUS_MASK;
 327         if (val == S_CMD_STATUS_TIMEOUT || val == S_CMD_STATUS_MASTER_ABORT) {
 328                 dev_err(iproc_i2c->device, (val == S_CMD_STATUS_TIMEOUT) ?
 329                         "slave random stretch time timeout\n" :
 330                         "Master aborted read transaction\n");
 331                 /* re-initialize i2c for recovery */
 332                 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
 333                 bcm_iproc_i2c_slave_init(iproc_i2c, true);
 334                 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
 335         }
 336 }
 337
 338 static void bcm_iproc_i2c_slave_read(struct bcm_iproc_i2c_dev *iproc_i2c)
 339 {
 340         u8 rx_data, rx_status;
 341         u32 rx_bytes = 0;
 342         u32 val;
 343
 344         while (rx_bytes < MAX_SLAVE_RX_PER_INT) {
 345                 val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);
 346                 rx_status = (val >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK;
 347                 rx_data = ((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK);
 348
 349                 if (rx_status == I2C_SLAVE_RX_START) {
 350                         /* Start of SMBUS Master write */
 351                         i2c_slave_event(iproc_i2c->slave,
 352                                         I2C_SLAVE_WRITE_REQUESTED, &rx_data);
 353                         iproc_i2c->rx_start_rcvd = true;
 354                         iproc_i2c->slave_read_complete = false;
 355                 } else if (rx_status == I2C_SLAVE_RX_DATA &&
 356                            iproc_i2c->rx_start_rcvd) {
 357                         /* Middle of SMBUS Master write */
 358                         i2c_slave_event(iproc_i2c->slave,
 359                                         I2C_SLAVE_WRITE_RECEIVED, &rx_data);
 360                 } else if (rx_status == I2C_SLAVE_RX_END &&
 361                            iproc_i2c->rx_start_rcvd) {
 362                         /* End of SMBUS Master write */
 363                         if (iproc_i2c->slave_rx_only)
 364                                 i2c_slave_event(iproc_i2c->slave,
 365                                                 I2C_SLAVE_WRITE_RECEIVED,
 366                                                 &rx_data);
 367
 368                         i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP,
 369                                         &rx_data);
 370                 } else if (rx_status == I2C_SLAVE_RX_FIFO_EMPTY) {
 371                         iproc_i2c->rx_start_rcvd = false;
 372                         iproc_i2c->slave_read_complete = true;
 373                         break;
 374                 }
 375
 376                 rx_bytes++;
 377         }
 378 }
 379
 380 static void slave_rx_tasklet_fn(unsigned long data)
 381 {
 382         struct bcm_iproc_i2c_dev *iproc_i2c = (struct bcm_iproc_i2c_dev *)data;
 383         u32 int_clr;
 384
 385         bcm_iproc_i2c_slave_read(iproc_i2c);
 386
 387         /* clear pending IS_S_RX_EVENT_SHIFT interrupt */
 388         int_clr = BIT(IS_S_RX_EVENT_SHIFT);
 389
 390         if (!iproc_i2c->slave_rx_only && iproc_i2c->slave_read_complete) {
 391                 /*
 392                  * In case of single byte master-read request,
 393                  * IS_S_TX_UNDERRUN_SHIFT event is generated before
 394                  * IS_S_START_BUSY_SHIFT event. Hence start slave data send
 395                  * from first IS_S_TX_UNDERRUN_SHIFT event.
 396                  *
 397                  * This means don't send any data from slave when
 398                  * IS_S_RD_EVENT_SHIFT event is generated else it will increment
 399                  * eeprom or other backend slave driver read pointer twice.
 400                  */
 401                 iproc_i2c->tx_underrun = 0;
 402                 iproc_i2c->slave_int_mask |= BIT(IE_S_TX_UNDERRUN_SHIFT);
 403
 404                 /* clear IS_S_RD_EVENT_SHIFT interrupt */
 405                 int_clr |= BIT(IS_S_RD_EVENT_SHIFT);
 406         }
 407
 408         /* clear slave interrupt */
 409         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, int_clr);
 410         /* enable slave interrupts */
 411         iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, iproc_i2c->slave_int_mask);
 412 }
 413
 414 static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c,
 415                                     u32 status)
 416 {
 417         u32 val;
 418         u8 value;
 419
 420         /*
 421          * Slave events in case of master-write, master-write-read and,
 422          * master-read
 423          *
 424          * Master-write     : only IS_S_RX_EVENT_SHIFT event
 425          * Master-write-read: both IS_S_RX_EVENT_SHIFT and IS_S_RD_EVENT_SHIFT
 426          *                    events
 427          * Master-read      : both IS_S_RX_EVENT_SHIFT and IS_S_RD_EVENT_SHIFT
 428          *                    events or only IS_S_RD_EVENT_SHIFT
 429          *
 430          * iproc has a slave rx fifo size of 64 bytes. Rx fifo full interrupt
 431          * (IS_S_RX_FIFO_FULL_SHIFT) will be generated when RX fifo becomes
 432          * full. This can happen if Master issues write requests of more than
 433          * 64 bytes.
 434          */
 435         if (status & BIT(IS_S_RX_EVENT_SHIFT) ||
 436             status & BIT(IS_S_RD_EVENT_SHIFT) ||
 437             status & BIT(IS_S_RX_FIFO_FULL_SHIFT)) {
 438                 /* disable slave interrupts */
 439                 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 440                 val &= ~iproc_i2c->slave_int_mask;
 441                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
 442
 443                 if (status & BIT(IS_S_RD_EVENT_SHIFT))
 444                         /* Master-write-read request */
 445                         iproc_i2c->slave_rx_only = false;
 446                 else
 447                         /* Master-write request only */
 448                         iproc_i2c->slave_rx_only = true;
 449
 450                 /* schedule tasklet to read data later */
 451                 tasklet_schedule(&iproc_i2c->slave_rx_tasklet);
 452
 453                 /*
 454                  * clear only IS_S_RX_EVENT_SHIFT and
 455                  * IS_S_RX_FIFO_FULL_SHIFT interrupt.
 456                  */
 457                 val = BIT(IS_S_RX_EVENT_SHIFT);
 458                 if (status & BIT(IS_S_RX_FIFO_FULL_SHIFT))
 459                         val |= BIT(IS_S_RX_FIFO_FULL_SHIFT);
 460                 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, val);
 461         }
 462
 463         if (status & BIT(IS_S_TX_UNDERRUN_SHIFT)) {
 464                 iproc_i2c->tx_underrun++;
 465                 if (iproc_i2c->tx_underrun == 1)
 466                         /* Start of SMBUS for Master Read */
 467                         i2c_slave_event(iproc_i2c->slave,
 468                                         I2C_SLAVE_READ_REQUESTED,
 469                                         &value);
 470                 else
 471                         /* Master read other than start */
 472                         i2c_slave_event(iproc_i2c->slave,
 473                                         I2C_SLAVE_READ_PROCESSED,
 474                                         &value);
 475
 476                 iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value);
 477                 /* start transfer */
 478                 val = BIT(S_CMD_START_BUSY_SHIFT);
 479                 iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
 480
 481                 /* clear interrupt */
 482                 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET,
 483                                  BIT(IS_S_TX_UNDERRUN_SHIFT));
 484         }
 485
 486         /* Stop received from master in case of master read transaction */
 487         if (status & BIT(IS_S_START_BUSY_SHIFT)) {
 488                 /*
 489                  * Disable interrupt for TX FIFO becomes empty and
 490                  * less than PKT_LENGTH bytes were output on the SMBUS
 491                  */
 492                 iproc_i2c->slave_int_mask &= ~BIT(IE_S_TX_UNDERRUN_SHIFT);
 493                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET,
 494                                  iproc_i2c->slave_int_mask);
 495
 496                 /* End of SMBUS for Master Read */
 497                 val = BIT(S_TX_WR_STATUS_SHIFT);
 498                 iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, val);
 499
 500                 val = BIT(S_CMD_START_BUSY_SHIFT);
 501                 iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
 502
 503                 /* flush TX FIFOs */
 504                 val = iproc_i2c_rd_reg(iproc_i2c, S_FIFO_CTRL_OFFSET);
 505                 val |= (BIT(S_FIFO_TX_FLUSH_SHIFT));
 506                 iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val);
 507
 508                 i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP, &value);
 509
 510                 /* clear interrupt */
 511                 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET,
 512                                  BIT(IS_S_START_BUSY_SHIFT));
 513         }
 514
 515         /* check slave transmit status only if slave is transmitting */
 516         if (!iproc_i2c->slave_rx_only)
 517                 bcm_iproc_i2c_check_slave_status(iproc_i2c);
 518
 519         return true;
 520 }
 521
 522 static void bcm_iproc_i2c_read_valid_bytes(struct bcm_iproc_i2c_dev *iproc_i2c)
 523 {
 524         struct i2c_msg *msg = iproc_i2c->msg;
 525         uint32_t val;
 526
 527         /* Read valid data from RX FIFO */
 528         while (iproc_i2c->rx_bytes < msg->len) {
 529                 val = iproc_i2c_rd_reg(iproc_i2c, M_RX_OFFSET);
 530
 531                 /* rx fifo empty */
 532                 if (!((val >> M_RX_STATUS_SHIFT) & M_RX_STATUS_MASK))
 533                         break;
 534
 535                 msg->buf[iproc_i2c->rx_bytes] =
 536                         (val >> M_RX_DATA_SHIFT) & M_RX_DATA_MASK;
 537                 iproc_i2c->rx_bytes++;
 538         }
 539 }
 540
 541 static void bcm_iproc_i2c_send(struct bcm_iproc_i2c_dev *iproc_i2c)
 542 {
 543         struct i2c_msg *msg = iproc_i2c->msg;
 544         unsigned int tx_bytes = msg->len - iproc_i2c->tx_bytes;
 545         unsigned int i;
 546         u32 val;
 547
 548         /* can only fill up to the FIFO size */
 549         tx_bytes = min_t(unsigned int, tx_bytes, M_TX_RX_FIFO_SIZE);
 550         for (i = 0; i < tx_bytes; i++) {
 551                 /* start from where we left over */
 552                 unsigned int idx = iproc_i2c->tx_bytes + i;
 553
 554                 val = msg->buf[idx];
 555
 556                 /* mark the last byte */
 557                 if (idx == msg->len - 1) {
 558                         val |= BIT(M_TX_WR_STATUS_SHIFT);
 559
 560                         if (iproc_i2c->irq) {
 561                                 u32 tmp;
 562
 563                                 /*
 564                                  * Since this is the last byte, we should now
 565                                  * disable TX FIFO underrun interrupt
 566                                  */
 567                                 tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 568                                 tmp &= ~BIT(IE_M_TX_UNDERRUN_SHIFT);
 569                                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET,
 570                                                  tmp);
 571                         }
 572                 }
 573
 574                 /* load data into TX FIFO */
 575                 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
 576         }
 577
 578         /* update number of transferred bytes */
 579         iproc_i2c->tx_bytes += tx_bytes;
 580 }
 581
 582 static void bcm_iproc_i2c_read(struct bcm_iproc_i2c_dev *iproc_i2c)
 583 {
 584         struct i2c_msg *msg = iproc_i2c->msg;
 585         u32 bytes_left, val;
 586
 587         bcm_iproc_i2c_read_valid_bytes(iproc_i2c);
 588         bytes_left = msg->len - iproc_i2c->rx_bytes;
 589         if (bytes_left == 0) {
 590                 if (iproc_i2c->irq) {
 591                         /* finished reading all data, disable rx thld event */
 592                         val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 593                         val &= ~BIT(IS_M_RX_THLD_SHIFT);
 594                         iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
 595                 }
 596         } else if (bytes_left < iproc_i2c->thld_bytes) {
 597                 /* set bytes left as threshold */
 598                 val = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET);
 599                 val &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
 600                 val |= (bytes_left << M_FIFO_RX_THLD_SHIFT);
 601                 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
 602                 iproc_i2c->thld_bytes = bytes_left;
 603         }
 604         /*
 605          * bytes_left >= iproc_i2c->thld_bytes,
 606          * hence no need to change the THRESHOLD SET.
 607          * It will remain as iproc_i2c->thld_bytes itself
 608          */
 609 }
 610
 611 static void bcm_iproc_i2c_process_m_event(struct bcm_iproc_i2c_dev *iproc_i2c,
 612                                           u32 status)
 613 {
 614         /* TX FIFO is empty and we have more data to send */
 615         if (status & BIT(IS_M_TX_UNDERRUN_SHIFT))
 616                 bcm_iproc_i2c_send(iproc_i2c);
 617
 618         /* RX FIFO threshold is reached and data needs to be read out */
 619         if (status & BIT(IS_M_RX_THLD_SHIFT))
 620                 bcm_iproc_i2c_read(iproc_i2c);
 621
 622         /* transfer is done */
 623         if (status & BIT(IS_M_START_BUSY_SHIFT)) {
 624                 iproc_i2c->xfer_is_done = 1;
 625                 if (iproc_i2c->irq)
 626                         complete(&iproc_i2c->done);
 627         }
 628 }
 629
 630 static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data)
 631 {
 632         struct bcm_iproc_i2c_dev *iproc_i2c = data;
 633         u32 slave_status;
 634         u32 status;
 635         bool ret;
 636
 637         status = iproc_i2c_rd_reg(iproc_i2c, IS_OFFSET);
 638         /* process only slave interrupt which are enabled */
 639         slave_status = status & iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET) &
 640                        ISR_MASK_SLAVE;
 641
 642         if (slave_status) {
 643                 ret = bcm_iproc_i2c_slave_isr(iproc_i2c, slave_status);
 644                 if (ret)
 645                         return IRQ_HANDLED;
 646                 else
 647                         return IRQ_NONE;
 648         }
 649
 650         status &= ISR_MASK;
 651         if (!status)
 652                 return IRQ_NONE;
 653
 654         /* process all master based events */
 655         bcm_iproc_i2c_process_m_event(iproc_i2c, status);
 656         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
 657
 658         return IRQ_HANDLED;
 659 }
 660
 661 static int bcm_iproc_i2c_init(struct bcm_iproc_i2c_dev *iproc_i2c)
 662 {
 663         u32 val;
 664
 665         /* put controller in reset */
 666         val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
 667         val |= BIT(CFG_RESET_SHIFT);
 668         val &= ~(BIT(CFG_EN_SHIFT));
 669         iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
 670
 671         /* wait 100 usec per spec */
 672         udelay(100);
 673
 674         /* bring controller out of reset */
 675         val &= ~(BIT(CFG_RESET_SHIFT));
 676         iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
 677
 678         /* flush TX/RX FIFOs and set RX FIFO threshold to zero */
 679         val = (BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT));
 680         iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
 681         /* disable all interrupts */
 682         val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 683         val &= ~(IE_M_ALL_INTERRUPT_MASK <<
 684                         IE_M_ALL_INTERRUPT_SHIFT);
 685         iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
 686
 687         /* clear all pending interrupts */
 688         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, 0xffffffff);
 689
 690         return 0;
 691 }
 692
 693 static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c,
 694                                          bool enable)
 695 {
 696         u32 val;
 697
 698         val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
 699         if (enable)
 700                 val |= BIT(CFG_EN_SHIFT);
 701         else
 702                 val &= ~BIT(CFG_EN_SHIFT);
 703         iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
 704 }
 705
 706 static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c,
 707                                       struct i2c_msg *msg)
 708 {
 709         u32 val;
 710
 711         val = iproc_i2c_rd_reg(iproc_i2c, M_CMD_OFFSET);
 712         val = (val >> M_CMD_STATUS_SHIFT) & M_CMD_STATUS_MASK;
 713
 714         switch (val) {
 715         case M_CMD_STATUS_SUCCESS:
 716                 return 0;
 717
 718         case M_CMD_STATUS_LOST_ARB:
 719                 dev_dbg(iproc_i2c->device, "lost bus arbitration\n");
 720                 return -EAGAIN;
 721
 722         case M_CMD_STATUS_NACK_ADDR:
 723                 dev_dbg(iproc_i2c->device, "NAK addr:0x%02x\n", msg->addr);
 724                 return -ENXIO;
 725
 726         case M_CMD_STATUS_NACK_DATA:
 727                 dev_dbg(iproc_i2c->device, "NAK data\n");
 728                 return -ENXIO;
 729
 730         case M_CMD_STATUS_TIMEOUT:
 731                 dev_dbg(iproc_i2c->device, "bus timeout\n");
 732                 return -ETIMEDOUT;
 733
 734         case M_CMD_STATUS_FIFO_UNDERRUN:
 735                 dev_dbg(iproc_i2c->device, "FIFO under-run\n");
 736                 return -ENXIO;
 737
 738         case M_CMD_STATUS_RX_FIFO_FULL:
 739                 dev_dbg(iproc_i2c->device, "RX FIFO full\n");
 740                 return -ETIMEDOUT;
 741
 742         default:
 743                 dev_dbg(iproc_i2c->device, "unknown error code=%d\n", val);
 744
 745                 /* re-initialize i2c for recovery */
 746                 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
 747                 bcm_iproc_i2c_init(iproc_i2c);
 748                 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
 749
 750                 return -EIO;
 751         }
 752 }
 753
 754 static int bcm_iproc_i2c_xfer_wait(struct bcm_iproc_i2c_dev *iproc_i2c,
 755                                    struct i2c_msg *msg,
 756                                    u32 cmd)
 757 {
 758         unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT_MSEC);
 759         u32 val, status;
 760         int ret;
 761
 762         iproc_i2c_wr_reg(iproc_i2c, M_CMD_OFFSET, cmd);
 763
 764         if (iproc_i2c->irq) {
 765                 time_left = wait_for_completion_timeout(&iproc_i2c->done,
 766                                                         time_left);
 767                 /* disable all interrupts */
 768                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
 769                 /* read it back to flush the write */
 770                 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 771                 /* make sure the interrupt handler isn't running */
 772                 synchronize_irq(iproc_i2c->irq);
 773
 774         } else { /* polling mode */
 775                 unsigned long timeout = jiffies + time_left;
 776
 777                 do {
 778                         status = iproc_i2c_rd_reg(iproc_i2c,
 779                                                   IS_OFFSET) & ISR_MASK;
 780                         bcm_iproc_i2c_process_m_event(iproc_i2c, status);
 781                         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
 782
 783                         if (time_after(jiffies, timeout)) {
 784                                 time_left = 0;
 785                                 break;
 786                         }
 787
 788                         cpu_relax();
 789                         cond_resched();
 790                 } while (!iproc_i2c->xfer_is_done);
 791         }
 792
 793         if (!time_left && !iproc_i2c->xfer_is_done) {
 794                 dev_err(iproc_i2c->device, "transaction timed out\n");
 795
 796                 /* flush both TX/RX FIFOs */
 797                 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
 798                 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
 799                 return -ETIMEDOUT;
 800         }
 801
 802         ret = bcm_iproc_i2c_check_status(iproc_i2c, msg);
 803         if (ret) {
 804                 /* flush both TX/RX FIFOs */
 805                 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
 806                 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
 807                 return ret;
 808         }
 809
 810         return 0;
 811 }
 812
 813 /*
 814  * If 'process_call' is true, then this is a multi-msg transfer that requires
 815  * a repeated start between the messages.
 816  * More specifically, it must be a write (reg) followed by a read (data).
 817  * The i2c quirks are set to enforce this rule.
 818  */
 819 static int bcm_iproc_i2c_xfer_internal(struct bcm_iproc_i2c_dev *iproc_i2c,
 820                                         struct i2c_msg *msgs, bool process_call)
 821 {
 822         int i;
 823         u8 addr;
 824         u32 val, tmp, val_intr_en;
 825         unsigned int tx_bytes;
 826         struct i2c_msg *msg = &msgs[0];
 827
 828         /* check if bus is busy */
 829         if (!!(iproc_i2c_rd_reg(iproc_i2c,
 830                                 M_CMD_OFFSET) & BIT(M_CMD_START_BUSY_SHIFT))) {
 831                 dev_warn(iproc_i2c->device, "bus is busy\n");
 832                 return -EBUSY;
 833         }
 834
 835         iproc_i2c->msg = msg;
 836
 837         /* format and load slave address into the TX FIFO */
 838         addr = i2c_8bit_addr_from_msg(msg);
 839         iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, addr);
 840
 841         /*
 842          * For a write transaction, load data into the TX FIFO. Only allow
 843          * loading up to TX FIFO size - 1 bytes of data since the first byte
 844          * has been used up by the slave address
 845          */
 846         tx_bytes = min_t(unsigned int, msg->len, M_TX_RX_FIFO_SIZE - 1);
 847         if (!(msg->flags & I2C_M_RD)) {
 848                 for (i = 0; i < tx_bytes; i++) {
 849                         val = msg->buf[i];
 850
 851                         /* mark the last byte */
 852                         if (!process_call && (i == msg->len - 1))
 853                                 val |= BIT(M_TX_WR_STATUS_SHIFT);
 854
 855                         iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
 856                 }
 857                 iproc_i2c->tx_bytes = tx_bytes;
 858         }
 859
 860         /* Process the read message if this is process call */
 861         if (process_call) {
 862                 msg++;
 863                 iproc_i2c->msg = msg;  /* point to second msg */
 864
 865                 /*
 866                  * The last byte to be sent out should be a slave
 867                  * address with read operation
 868                  */
 869                 addr = i2c_8bit_addr_from_msg(msg);
 870                 /* mark it the last byte out */
 871                 val = addr | BIT(M_TX_WR_STATUS_SHIFT);
 872                 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
 873         }
 874
 875         /* mark as incomplete before starting the transaction */
 876         if (iproc_i2c->irq)
 877                 reinit_completion(&iproc_i2c->done);
 878
 879         iproc_i2c->xfer_is_done = 0;
 880
 881         /*
 882          * Enable the "start busy" interrupt, which will be triggered after the
 883          * transaction is done, i.e., the internal start_busy bit, transitions
 884          * from 1 to 0.
 885          */
 886         val_intr_en = BIT(IE_M_START_BUSY_SHIFT);
 887
 888         /*
 889          * If TX data size is larger than the TX FIFO, need to enable TX
 890          * underrun interrupt, which will be triggerred when the TX FIFO is
 891          * empty. When that happens we can then pump more data into the FIFO
 892          */
 893         if (!process_call && !(msg->flags & I2C_M_RD) &&
 894             msg->len > iproc_i2c->tx_bytes)
 895                 val_intr_en |= BIT(IE_M_TX_UNDERRUN_SHIFT);
 896
 897         /*
 898          * Now we can activate the transfer. For a read operation, specify the
 899          * number of bytes to read
 900          */
 901         val = BIT(M_CMD_START_BUSY_SHIFT);
 902
 903         if (msg->len == 0) {
 904                 /* SMBUS QUICK Command (Read/Write) */
 905                 val |= (M_CMD_PROTOCOL_QUICK << M_CMD_PROTOCOL_SHIFT);
 906         } else if (msg->flags & I2C_M_RD) {
 907                 u32 protocol;
 908
 909                 iproc_i2c->rx_bytes = 0;
 910                 if (msg->len > M_RX_FIFO_MAX_THLD_VALUE)
 911                         iproc_i2c->thld_bytes = M_RX_FIFO_THLD_VALUE;
 912                 else
 913                         iproc_i2c->thld_bytes = msg->len;
 914
 915                 /* set threshold value */
 916                 tmp = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET);
 917                 tmp &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
 918                 tmp |= iproc_i2c->thld_bytes << M_FIFO_RX_THLD_SHIFT;
 919                 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, tmp);
 920
 921                 /* enable the RX threshold interrupt */
 922                 val_intr_en |= BIT(IE_M_RX_THLD_SHIFT);
 923
 924                 protocol = process_call ?
 925                                 M_CMD_PROTOCOL_PROCESS : M_CMD_PROTOCOL_BLK_RD;
 926
 927                 val |= (protocol << M_CMD_PROTOCOL_SHIFT) |
 928                        (msg->len << M_CMD_RD_CNT_SHIFT);
 929         } else {
 930                 val |= (M_CMD_PROTOCOL_BLK_WR << M_CMD_PROTOCOL_SHIFT);
 931         }
 932
 933         if (iproc_i2c->irq)
 934                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val_intr_en);
 935
 936         return bcm_iproc_i2c_xfer_wait(iproc_i2c, msg, val);
 937 }
 938
 939 static int bcm_iproc_i2c_xfer(struct i2c_adapter *adapter,
 940                               struct i2c_msg msgs[], int num)
 941 {
 942         struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(adapter);
 943         bool process_call = false;
 944         int ret;
 945
 946         if (num == 2) {
 947                 /* Repeated start, use process call */
 948                 process_call = true;
 949                 if (msgs[1].flags & I2C_M_NOSTART) {
 950                         dev_err(iproc_i2c->device, "Invalid repeated start\n");
 951                         return -EOPNOTSUPP;
 952                 }
 953         }
 954
 955         ret = bcm_iproc_i2c_xfer_internal(iproc_i2c, msgs, process_call);
 956         if (ret) {
 957                 dev_dbg(iproc_i2c->device, "xfer failed\n");
 958                 return ret;
 959         }
 960
 961         return num;
 962 }
 963
 964 static uint32_t bcm_iproc_i2c_functionality(struct i2c_adapter *adap)
 965 {
 966         u32 val;
 967
 968         val = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 969
 970         if (adap->algo->reg_slave)
 971                 val |= I2C_FUNC_SLAVE;
 972
 973         return val;
 974 }
 975
 976 static struct i2c_algorithm bcm_iproc_algo = {
 977         .master_xfer = bcm_iproc_i2c_xfer,
 978         .functionality = bcm_iproc_i2c_functionality,
 979         .reg_slave = bcm_iproc_i2c_reg_slave,
 980         .unreg_slave = bcm_iproc_i2c_unreg_slave,
 981 };
 982
 983 static const struct i2c_adapter_quirks bcm_iproc_i2c_quirks = {
 984         .flags = I2C_AQ_COMB_WRITE_THEN_READ,
 985         .max_comb_1st_msg_len = M_TX_RX_FIFO_SIZE,
 986         .max_read_len = M_RX_MAX_READ_LEN,
 987 };
 988
 989 static int bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev *iproc_i2c)
 990 {
 991         unsigned int bus_speed;
 992         u32 val;
 993         int ret = of_property_read_u32(iproc_i2c->device->of_node,
 994                                        "clock-frequency", &bus_speed);
 995         if (ret < 0) {
 996                 dev_info(iproc_i2c->device,
 997                         "unable to interpret clock-frequency DT property\n");
 998                 bus_speed = I2C_MAX_STANDARD_MODE_FREQ;
 999         }
1000
1001         if (bus_speed < I2C_MAX_STANDARD_MODE_FREQ) {
1002                 dev_err(iproc_i2c->device, "%d Hz bus speed not supported\n",
1003                         bus_speed);
1004                 dev_err(iproc_i2c->device,
1005                         "valid speeds are 100khz and 400khz\n");
1006                 return -EINVAL;
1007         } else if (bus_speed < I2C_MAX_FAST_MODE_FREQ) {
1008                 bus_speed = I2C_MAX_STANDARD_MODE_FREQ;
1009         } else {
1010                 bus_speed = I2C_MAX_FAST_MODE_FREQ;
1011         }
1012
1013         iproc_i2c->bus_speed = bus_speed;
1014         val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
1015         val &= ~BIT(TIM_CFG_MODE_400_SHIFT);
1016         val |= (bus_speed == I2C_MAX_FAST_MODE_FREQ) << TIM_CFG_MODE_400_SHIFT;
1017         iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
1018
1019         dev_info(iproc_i2c->device, "bus set to %u Hz\n", bus_speed);
1020
1021         return 0;
1022 }
1023
1024 static int bcm_iproc_i2c_probe(struct platform_device *pdev)
1025 {
1026         int irq, ret = 0;
1027         struct bcm_iproc_i2c_dev *iproc_i2c;
1028         struct i2c_adapter *adap;
1029         struct resource *res;
1030
1031         iproc_i2c = devm_kzalloc(&pdev->dev, sizeof(*iproc_i2c),
1032                                  GFP_KERNEL);
1033         if (!iproc_i2c)
1034                 return -ENOMEM;
1035
1036         platform_set_drvdata(pdev, iproc_i2c);
1037         iproc_i2c->device = &pdev->dev;
1038         iproc_i2c->type =
1039                 (enum bcm_iproc_i2c_type)of_device_get_match_data(&pdev->dev);
1040         init_completion(&iproc_i2c->done);
1041
1042         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1043         iproc_i2c->base = devm_ioremap_resource(iproc_i2c->device, res);
1044         if (IS_ERR(iproc_i2c->base))
1045                 return PTR_ERR(iproc_i2c->base);
1046
1047         if (iproc_i2c->type == IPROC_I2C_NIC) {
1048                 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1049                 iproc_i2c->idm_base = devm_ioremap_resource(iproc_i2c->device,
1050                                                             res);
1051                 if (IS_ERR(iproc_i2c->idm_base))
1052                         return PTR_ERR(iproc_i2c->idm_base);
1053
1054                 ret = of_property_read_u32(iproc_i2c->device->of_node,
1055                                            "brcm,ape-hsls-addr-mask",
1056                                            &iproc_i2c->ape_addr_mask);
1057                 if (ret < 0) {
1058                         dev_err(iproc_i2c->device,
1059                                 "'brcm,ape-hsls-addr-mask' missing\n");
1060                         return -EINVAL;
1061                 }
1062
1063                 spin_lock_init(&iproc_i2c->idm_lock);
1064
1065                 /* no slave support */
1066                 bcm_iproc_algo.reg_slave = NULL;
1067                 bcm_iproc_algo.unreg_slave = NULL;
1068         }
1069
1070         ret = bcm_iproc_i2c_init(iproc_i2c);
1071         if (ret)
1072                 return ret;
1073
1074         ret = bcm_iproc_i2c_cfg_speed(iproc_i2c);
1075         if (ret)
1076                 return ret;
1077
1078         irq = platform_get_irq(pdev, 0);
1079         if (irq > 0) {
1080                 ret = devm_request_irq(iproc_i2c->device, irq,
1081                                        bcm_iproc_i2c_isr, 0, pdev->name,
1082                                        iproc_i2c);
1083                 if (ret < 0) {
1084                         dev_err(iproc_i2c->device,
1085                                 "unable to request irq %i\n", irq);
1086                         return ret;
1087                 }
1088
1089                 iproc_i2c->irq = irq;
1090         } else {
1091                 dev_warn(iproc_i2c->device,
1092                          "no irq resource, falling back to poll mode\n");
1093         }
1094
1095         bcm_iproc_i2c_enable_disable(iproc_i2c, true);
1096
1097         adap = &iproc_i2c->adapter;
1098         i2c_set_adapdata(adap, iproc_i2c);
1099         snprintf(adap->name, sizeof(adap->name),
1100                 "Broadcom iProc (%s)",
1101                 of_node_full_name(iproc_i2c->device->of_node));
1102         adap->algo = &bcm_iproc_algo;
1103         adap->quirks = &bcm_iproc_i2c_quirks;
1104         adap->dev.parent = &pdev->dev;
1105         adap->dev.of_node = pdev->dev.of_node;
1106
1107         return i2c_add_adapter(adap);
1108 }
1109
1110 static void bcm_iproc_i2c_remove(struct platform_device *pdev)
1111 {
1112         struct bcm_iproc_i2c_dev *iproc_i2c = platform_get_drvdata(pdev);
1113
1114         if (iproc_i2c->irq) {
1115                 /*
1116                  * Make sure there's no pending interrupt when we remove the
1117                  * adapter
1118                  */
1119                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
1120                 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
1121                 synchronize_irq(iproc_i2c->irq);
1122         }
1123
1124         i2c_del_adapter(&iproc_i2c->adapter);
1125         bcm_iproc_i2c_enable_disable(iproc_i2c, false);
1126 }
1127
1128 #ifdef CONFIG_PM_SLEEP
1129
1130 static int bcm_iproc_i2c_suspend(struct device *dev)
1131 {
1132         struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev);
1133
1134         if (iproc_i2c->irq) {
1135                 /*
1136                  * Make sure there's no pending interrupt when we go into
1137                  * suspend
1138                  */
1139                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
1140                 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
1141                 synchronize_irq(iproc_i2c->irq);
1142         }
1143
1144         /* now disable the controller */
1145         bcm_iproc_i2c_enable_disable(iproc_i2c, false);
1146
1147         return 0;
1148 }
1149
1150 static int bcm_iproc_i2c_resume(struct device *dev)
1151 {
1152         struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev);
1153         int ret;
1154         u32 val;
1155
1156         /*
1157          * Power domain could have been shut off completely in system deep
1158          * sleep, so re-initialize the block here
1159          */
1160         ret = bcm_iproc_i2c_init(iproc_i2c);
1161         if (ret)
1162                 return ret;
1163
1164         /* configure to the desired bus speed */
1165         val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
1166         val &= ~BIT(TIM_CFG_MODE_400_SHIFT);
1167         val |= (iproc_i2c->bus_speed == I2C_MAX_FAST_MODE_FREQ) << TIM_CFG_MODE_400_SHIFT;
1168         iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
1169
1170         bcm_iproc_i2c_enable_disable(iproc_i2c, true);
1171
1172         return 0;
1173 }
1174
1175 static const struct dev_pm_ops bcm_iproc_i2c_pm_ops = {
1176         .suspend_late = &bcm_iproc_i2c_suspend,
1177         .resume_early = &bcm_iproc_i2c_resume
1178 };
1179
1180 #define BCM_IPROC_I2C_PM_OPS (&bcm_iproc_i2c_pm_ops)
1181 #else
1182 #define BCM_IPROC_I2C_PM_OPS NULL
1183 #endif /* CONFIG_PM_SLEEP */
1184
1185
1186 static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave)
1187 {
1188         struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter);
1189
1190         if (iproc_i2c->slave)
1191                 return -EBUSY;
1192
1193         if (slave->flags & I2C_CLIENT_TEN)
1194                 return -EAFNOSUPPORT;
1195
1196         iproc_i2c->slave = slave;
1197
1198         tasklet_init(&iproc_i2c->slave_rx_tasklet, slave_rx_tasklet_fn,
1199                      (unsigned long)iproc_i2c);
1200
1201         bcm_iproc_i2c_slave_init(iproc_i2c, false);
1202         return 0;
1203 }
1204
1205 static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave)
1206 {
1207         u32 tmp;
1208         struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter);
1209
1210         if (!iproc_i2c->slave)
1211                 return -EINVAL;
1212
1213         disable_irq(iproc_i2c->irq);
1214
1215         tasklet_kill(&iproc_i2c->slave_rx_tasklet);
1216
1217         /* disable all slave interrupts */
1218         tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
1219         tmp &= ~(IE_S_ALL_INTERRUPT_MASK <<
1220                         IE_S_ALL_INTERRUPT_SHIFT);
1221         iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, tmp);
1222
1223         /* Erase the slave address programmed */
1224         tmp = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET);
1225         tmp &= ~BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);
1226         iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, tmp);
1227
1228         /* flush TX/RX FIFOs */
1229         tmp = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT));
1230         iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, tmp);
1231
1232         /* clear all pending slave interrupts */
1233         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE);
1234
1235         iproc_i2c->slave = NULL;
1236
1237         enable_irq(iproc_i2c->irq);
1238
1239         return 0;
1240 }
1241
1242 static const struct of_device_id bcm_iproc_i2c_of_match[] = {
1243         {
1244                 .compatible = "brcm,iproc-i2c",
1245                 .data = (int *)IPROC_I2C,
1246         }, {
1247                 .compatible = "brcm,iproc-nic-i2c",
1248                 .data = (int *)IPROC_I2C_NIC,
1249         },
1250         { /* sentinel */ }
1251 };
1252 MODULE_DEVICE_TABLE(of, bcm_iproc_i2c_of_match);
1253
1254 static struct platform_driver bcm_iproc_i2c_driver = {
1255         .driver = {
1256                 .name = "bcm-iproc-i2c",
1257                 .of_match_table = bcm_iproc_i2c_of_match,
1258                 .pm = BCM_IPROC_I2C_PM_OPS,
1259         },
1260         .probe = bcm_iproc_i2c_probe,
1261         .remove_new = bcm_iproc_i2c_remove,
1262 };
1263 module_platform_driver(bcm_iproc_i2c_driver);
1264
1265 MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
1266 MODULE_DESCRIPTION("Broadcom iProc I2C Driver");
1267 MODULE_LICENSE("GPL v2");