drivers/i2c/busses/i2c-bcm-iproc.c

   1 /*
   2  * Copyright (C) 2014 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation version 2.
   7  *
   8  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
   9  * kind, whether express or implied; without even the implied warranty
  10  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/delay.h>
  15 #include <linux/i2c.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/kernel.h>
  19 #include <linux/module.h>
  20 #include <linux/of_device.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/slab.h>
  23
  24 #define IDM_CTRL_DIRECT_OFFSET       0x00
  25 #define CFG_OFFSET                   0x00
  26 #define CFG_RESET_SHIFT              31
  27 #define CFG_EN_SHIFT                 30
  28 #define CFG_SLAVE_ADDR_0_SHIFT       28
  29 #define CFG_M_RETRY_CNT_SHIFT        16
  30 #define CFG_M_RETRY_CNT_MASK         0x0f
  31
  32 #define TIM_CFG_OFFSET               0x04
  33 #define TIM_CFG_MODE_400_SHIFT       31
  34 #define TIM_RAND_SLAVE_STRETCH_SHIFT      24
  35 #define TIM_RAND_SLAVE_STRETCH_MASK       0x7f
  36 #define TIM_PERIODIC_SLAVE_STRETCH_SHIFT  16
  37 #define TIM_PERIODIC_SLAVE_STRETCH_MASK   0x7f
  38
  39 #define S_CFG_SMBUS_ADDR_OFFSET           0x08
  40 #define S_CFG_EN_NIC_SMB_ADDR3_SHIFT      31
  41 #define S_CFG_NIC_SMB_ADDR3_SHIFT         24
  42 #define S_CFG_NIC_SMB_ADDR3_MASK          0x7f
  43 #define S_CFG_EN_NIC_SMB_ADDR2_SHIFT      23
  44 #define S_CFG_NIC_SMB_ADDR2_SHIFT         16
  45 #define S_CFG_NIC_SMB_ADDR2_MASK          0x7f
  46 #define S_CFG_EN_NIC_SMB_ADDR1_SHIFT      15
  47 #define S_CFG_NIC_SMB_ADDR1_SHIFT         8
  48 #define S_CFG_NIC_SMB_ADDR1_MASK          0x7f
  49 #define S_CFG_EN_NIC_SMB_ADDR0_SHIFT      7
  50 #define S_CFG_NIC_SMB_ADDR0_SHIFT         0
  51 #define S_CFG_NIC_SMB_ADDR0_MASK          0x7f
  52
  53 #define M_FIFO_CTRL_OFFSET           0x0c
  54 #define M_FIFO_RX_FLUSH_SHIFT        31
  55 #define M_FIFO_TX_FLUSH_SHIFT        30
  56 #define M_FIFO_RX_CNT_SHIFT          16
  57 #define M_FIFO_RX_CNT_MASK           0x7f
  58 #define M_FIFO_RX_THLD_SHIFT         8
  59 #define M_FIFO_RX_THLD_MASK          0x3f
  60
  61 #define S_FIFO_CTRL_OFFSET           0x10
  62 #define S_FIFO_RX_FLUSH_SHIFT        31
  63 #define S_FIFO_TX_FLUSH_SHIFT        30
  64 #define S_FIFO_RX_CNT_SHIFT          16
  65 #define S_FIFO_RX_CNT_MASK           0x7f
  66 #define S_FIFO_RX_THLD_SHIFT         8
  67 #define S_FIFO_RX_THLD_MASK          0x3f
  68
  69 #define M_CMD_OFFSET                 0x30
  70 #define M_CMD_START_BUSY_SHIFT       31
  71 #define M_CMD_STATUS_SHIFT           25
  72 #define M_CMD_STATUS_MASK            0x07
  73 #define M_CMD_STATUS_SUCCESS         0x0
  74 #define M_CMD_STATUS_LOST_ARB        0x1
  75 #define M_CMD_STATUS_NACK_ADDR       0x2
  76 #define M_CMD_STATUS_NACK_DATA       0x3
  77 #define M_CMD_STATUS_TIMEOUT         0x4
  78 #define M_CMD_STATUS_FIFO_UNDERRUN   0x5
  79 #define M_CMD_STATUS_RX_FIFO_FULL    0x6
  80 #define M_CMD_PROTOCOL_SHIFT         9
  81 #define M_CMD_PROTOCOL_MASK          0xf
  82 #define M_CMD_PROTOCOL_QUICK         0x0
  83 #define M_CMD_PROTOCOL_BLK_WR        0x7
  84 #define M_CMD_PROTOCOL_BLK_RD        0x8
  85 #define M_CMD_PROTOCOL_PROCESS       0xa
  86 #define M_CMD_PEC_SHIFT              8
  87 #define M_CMD_RD_CNT_SHIFT           0
  88 #define M_CMD_RD_CNT_MASK            0xff
  89
  90 #define S_CMD_OFFSET                 0x34
  91 #define S_CMD_START_BUSY_SHIFT       31
  92 #define S_CMD_STATUS_SHIFT           23
  93 #define S_CMD_STATUS_MASK            0x07
  94 #define S_CMD_STATUS_SUCCESS         0x0
  95 #define S_CMD_STATUS_TIMEOUT         0x5
  96
  97 #define IE_OFFSET                    0x38
  98 #define IE_M_RX_FIFO_FULL_SHIFT      31
  99 #define IE_M_RX_THLD_SHIFT           30
 100 #define IE_M_START_BUSY_SHIFT        28
 101 #define IE_M_TX_UNDERRUN_SHIFT       27
 102 #define IE_S_RX_FIFO_FULL_SHIFT      26
 103 #define IE_S_RX_THLD_SHIFT           25
 104 #define IE_S_RX_EVENT_SHIFT          24
 105 #define IE_S_START_BUSY_SHIFT        23
 106 #define IE_S_TX_UNDERRUN_SHIFT       22
 107 #define IE_S_RD_EVENT_SHIFT          21
 108
 109 #define IS_OFFSET                    0x3c
 110 #define IS_M_RX_FIFO_FULL_SHIFT      31
 111 #define IS_M_RX_THLD_SHIFT           30
 112 #define IS_M_START_BUSY_SHIFT        28
 113 #define IS_M_TX_UNDERRUN_SHIFT       27
 114 #define IS_S_RX_FIFO_FULL_SHIFT      26
 115 #define IS_S_RX_THLD_SHIFT           25
 116 #define IS_S_RX_EVENT_SHIFT          24
 117 #define IS_S_START_BUSY_SHIFT        23
 118 #define IS_S_TX_UNDERRUN_SHIFT       22
 119 #define IS_S_RD_EVENT_SHIFT          21
 120
 121 #define M_TX_OFFSET                  0x40
 122 #define M_TX_WR_STATUS_SHIFT         31
 123 #define M_TX_DATA_SHIFT              0
 124 #define M_TX_DATA_MASK               0xff
 125
 126 #define M_RX_OFFSET                  0x44
 127 #define M_RX_STATUS_SHIFT            30
 128 #define M_RX_STATUS_MASK             0x03
 129 #define M_RX_PEC_ERR_SHIFT           29
 130 #define M_RX_DATA_SHIFT              0
 131 #define M_RX_DATA_MASK               0xff
 132
 133 #define S_TX_OFFSET                  0x48
 134 #define S_TX_WR_STATUS_SHIFT         31
 135 #define S_TX_DATA_SHIFT              0
 136 #define S_TX_DATA_MASK               0xff
 137
 138 #define S_RX_OFFSET                  0x4c
 139 #define S_RX_STATUS_SHIFT            30
 140 #define S_RX_STATUS_MASK             0x03
 141 #define S_RX_PEC_ERR_SHIFT           29
 142 #define S_RX_DATA_SHIFT              0
 143 #define S_RX_DATA_MASK               0xff
 144
 145 #define I2C_TIMEOUT_MSEC             50000
 146 #define M_TX_RX_FIFO_SIZE            64
 147 #define M_RX_FIFO_MAX_THLD_VALUE     (M_TX_RX_FIFO_SIZE - 1)
 148
 149 #define M_RX_MAX_READ_LEN            255
 150 #define M_RX_FIFO_THLD_VALUE         50
 151
 152 #define IE_M_ALL_INTERRUPT_SHIFT     27
 153 #define IE_M_ALL_INTERRUPT_MASK      0x1e
 154
 155 #define SLAVE_READ_WRITE_BIT_MASK    0x1
 156 #define SLAVE_READ_WRITE_BIT_SHIFT   0x1
 157 #define SLAVE_MAX_SIZE_TRANSACTION   64
 158 #define SLAVE_CLOCK_STRETCH_TIME     25
 159
 160 #define IE_S_ALL_INTERRUPT_SHIFT     21
 161 #define IE_S_ALL_INTERRUPT_MASK      0x3f
 162
 163 enum i2c_slave_read_status {
 164         I2C_SLAVE_RX_FIFO_EMPTY = 0,
 165         I2C_SLAVE_RX_START,
 166         I2C_SLAVE_RX_DATA,
 167         I2C_SLAVE_RX_END,
 168 };
 169
 170 enum bus_speed_index {
 171         I2C_SPD_100K = 0,
 172         I2C_SPD_400K,
 173 };
 174
 175 enum bcm_iproc_i2c_type {
 176         IPROC_I2C,
 177         IPROC_I2C_NIC
 178 };
 179
 180 struct bcm_iproc_i2c_dev {
 181         struct device *device;
 182         enum bcm_iproc_i2c_type type;
 183         int irq;
 184
 185         void __iomem *base;
 186         void __iomem *idm_base;
 187
 188         u32 ape_addr_mask;
 189
 190         /* lock for indirect access through IDM */
 191         spinlock_t idm_lock;
 192
 193         struct i2c_adapter adapter;
 194         unsigned int bus_speed;
 195
 196         struct completion done;
 197         int xfer_is_done;
 198
 199         struct i2c_msg *msg;
 200
 201         struct i2c_client *slave;
 202
 203         /* bytes that have been transferred */
 204         unsigned int tx_bytes;
 205         /* bytes that have been read */
 206         unsigned int rx_bytes;
 207         unsigned int thld_bytes;
 208 };
 209
 210 /*
 211  * Can be expanded in the future if more interrupt status bits are utilized
 212  */
 213 #define ISR_MASK (BIT(IS_M_START_BUSY_SHIFT) | BIT(IS_M_TX_UNDERRUN_SHIFT)\
 214                 | BIT(IS_M_RX_THLD_SHIFT))
 215
 216 #define ISR_MASK_SLAVE (BIT(IS_S_START_BUSY_SHIFT)\
 217                 | BIT(IS_S_RX_EVENT_SHIFT) | BIT(IS_S_RD_EVENT_SHIFT)\
 218                 | BIT(IS_S_TX_UNDERRUN_SHIFT))
 219
 220 static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave);
 221 static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave);
 222 static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c,
 223                                          bool enable);
 224
 225 static inline u32 iproc_i2c_rd_reg(struct bcm_iproc_i2c_dev *iproc_i2c,
 226                                    u32 offset)
 227 {
 228         u32 val;
 229
 230         if (iproc_i2c->idm_base) {
 231                 spin_lock(&iproc_i2c->idm_lock);
 232                 writel(iproc_i2c->ape_addr_mask,
 233                        iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET);
 234                 val = readl(iproc_i2c->base + offset);
 235                 spin_unlock(&iproc_i2c->idm_lock);
 236         } else {
 237                 val = readl(iproc_i2c->base + offset);
 238         }
 239
 240         return val;
 241 }
 242
 243 static inline void iproc_i2c_wr_reg(struct bcm_iproc_i2c_dev *iproc_i2c,
 244                                     u32 offset, u32 val)
 245 {
 246         if (iproc_i2c->idm_base) {
 247                 spin_lock(&iproc_i2c->idm_lock);
 248                 writel(iproc_i2c->ape_addr_mask,
 249                        iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET);
 250                 writel(val, iproc_i2c->base + offset);
 251                 spin_unlock(&iproc_i2c->idm_lock);
 252         } else {
 253                 writel(val, iproc_i2c->base + offset);
 254         }
 255 }
 256
 257 static void bcm_iproc_i2c_slave_init(
 258         struct bcm_iproc_i2c_dev *iproc_i2c, bool need_reset)
 259 {
 260         u32 val;
 261
 262         if (need_reset) {
 263                 /* put controller in reset */
 264                 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
 265                 val |= BIT(CFG_RESET_SHIFT);
 266                 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
 267
 268                 /* wait 100 usec per spec */
 269                 udelay(100);
 270
 271                 /* bring controller out of reset */
 272                 val &= ~(BIT(CFG_RESET_SHIFT));
 273                 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
 274         }
 275
 276         /* flush TX/RX FIFOs */
 277         val = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT));
 278         iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val);
 279
 280         /* Maximum slave stretch time */
 281         val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
 282         val &= ~(TIM_RAND_SLAVE_STRETCH_MASK << TIM_RAND_SLAVE_STRETCH_SHIFT);
 283         val |= (SLAVE_CLOCK_STRETCH_TIME << TIM_RAND_SLAVE_STRETCH_SHIFT);
 284         iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
 285
 286         /* Configure the slave address */
 287         val = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET);
 288         val |= BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);
 289         val &= ~(S_CFG_NIC_SMB_ADDR3_MASK << S_CFG_NIC_SMB_ADDR3_SHIFT);
 290         val |= (iproc_i2c->slave->addr << S_CFG_NIC_SMB_ADDR3_SHIFT);
 291         iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, val);
 292
 293         /* clear all pending slave interrupts */
 294         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE);
 295
 296         /* Enable interrupt register to indicate a valid byte in receive fifo */
 297         val = BIT(IE_S_RX_EVENT_SHIFT);
 298         /* Enable interrupt register for the Slave BUSY command */
 299         val |= BIT(IE_S_START_BUSY_SHIFT);
 300         iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
 301 }
 302
 303 static void bcm_iproc_i2c_check_slave_status(
 304         struct bcm_iproc_i2c_dev *iproc_i2c)
 305 {
 306         u32 val;
 307
 308         val = iproc_i2c_rd_reg(iproc_i2c, S_CMD_OFFSET);
 309         /* status is valid only when START_BUSY is cleared after it was set */
 310         if (val & BIT(S_CMD_START_BUSY_SHIFT))
 311                 return;
 312
 313         val = (val >> S_CMD_STATUS_SHIFT) & S_CMD_STATUS_MASK;
 314         if (val == S_CMD_STATUS_TIMEOUT) {
 315                 dev_err(iproc_i2c->device, "slave random stretch time timeout\n");
 316
 317                 /* re-initialize i2c for recovery */
 318                 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
 319                 bcm_iproc_i2c_slave_init(iproc_i2c, true);
 320                 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
 321         }
 322 }
 323
 324 static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c,
 325                                     u32 status)
 326 {
 327         u32 val;
 328         u8 value, rx_status;
 329
 330         /* Slave RX byte receive */
 331         if (status & BIT(IS_S_RX_EVENT_SHIFT)) {
 332                 val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);
 333                 rx_status = (val >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK;
 334                 if (rx_status == I2C_SLAVE_RX_START) {
 335                         /* Start of SMBUS for Master write */
 336                         i2c_slave_event(iproc_i2c->slave,
 337                                         I2C_SLAVE_WRITE_REQUESTED, &value);
 338
 339                         val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);
 340                         value = (u8)((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK);
 341                         i2c_slave_event(iproc_i2c->slave,
 342                                         I2C_SLAVE_WRITE_RECEIVED, &value);
 343                 } else if (status & BIT(IS_S_RD_EVENT_SHIFT)) {
 344                         /* Start of SMBUS for Master Read */
 345                         i2c_slave_event(iproc_i2c->slave,
 346                                         I2C_SLAVE_READ_REQUESTED, &value);
 347                         iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value);
 348
 349                         val = BIT(S_CMD_START_BUSY_SHIFT);
 350                         iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
 351
 352                         /*
 353                          * Enable interrupt for TX FIFO becomes empty and
 354                          * less than PKT_LENGTH bytes were output on the SMBUS
 355                          */
 356                         val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 357                         val |= BIT(IE_S_TX_UNDERRUN_SHIFT);
 358                         iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
 359                 } else {
 360                         /* Master write other than start */
 361                         value = (u8)((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK);
 362                         i2c_slave_event(iproc_i2c->slave,
 363                                         I2C_SLAVE_WRITE_RECEIVED, &value);
 364                         if (rx_status == I2C_SLAVE_RX_END)
 365                                 i2c_slave_event(iproc_i2c->slave,
 366                                                 I2C_SLAVE_STOP, &value);
 367                 }
 368         } else if (status & BIT(IS_S_TX_UNDERRUN_SHIFT)) {
 369                 /* Master read other than start */
 370                 i2c_slave_event(iproc_i2c->slave,
 371                                 I2C_SLAVE_READ_PROCESSED, &value);
 372
 373                 iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value);
 374                 val = BIT(S_CMD_START_BUSY_SHIFT);
 375                 iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
 376         }
 377
 378         /* Stop */
 379         if (status & BIT(IS_S_START_BUSY_SHIFT)) {
 380                 i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP, &value);
 381                 /*
 382                  * Enable interrupt for TX FIFO becomes empty and
 383                  * less than PKT_LENGTH bytes were output on the SMBUS
 384                  */
 385                 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 386                 val &= ~BIT(IE_S_TX_UNDERRUN_SHIFT);
 387                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
 388         }
 389
 390         /* clear interrupt status */
 391         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
 392
 393         bcm_iproc_i2c_check_slave_status(iproc_i2c);
 394         return true;
 395 }
 396
 397 static void bcm_iproc_i2c_read_valid_bytes(struct bcm_iproc_i2c_dev *iproc_i2c)
 398 {
 399         struct i2c_msg *msg = iproc_i2c->msg;
 400         uint32_t val;
 401
 402         /* Read valid data from RX FIFO */
 403         while (iproc_i2c->rx_bytes < msg->len) {
 404                 val = iproc_i2c_rd_reg(iproc_i2c, M_RX_OFFSET);
 405
 406                 /* rx fifo empty */
 407                 if (!((val >> M_RX_STATUS_SHIFT) & M_RX_STATUS_MASK))
 408                         break;
 409
 410                 msg->buf[iproc_i2c->rx_bytes] =
 411                         (val >> M_RX_DATA_SHIFT) & M_RX_DATA_MASK;
 412                 iproc_i2c->rx_bytes++;
 413         }
 414 }
 415
 416 static void bcm_iproc_i2c_send(struct bcm_iproc_i2c_dev *iproc_i2c)
 417 {
 418         struct i2c_msg *msg = iproc_i2c->msg;
 419         unsigned int tx_bytes = msg->len - iproc_i2c->tx_bytes;
 420         unsigned int i;
 421         u32 val;
 422
 423         /* can only fill up to the FIFO size */
 424         tx_bytes = min_t(unsigned int, tx_bytes, M_TX_RX_FIFO_SIZE);
 425         for (i = 0; i < tx_bytes; i++) {
 426                 /* start from where we left over */
 427                 unsigned int idx = iproc_i2c->tx_bytes + i;
 428
 429                 val = msg->buf[idx];
 430
 431                 /* mark the last byte */
 432                 if (idx == msg->len - 1) {
 433                         val |= BIT(M_TX_WR_STATUS_SHIFT);
 434
 435                         if (iproc_i2c->irq) {
 436                                 u32 tmp;
 437
 438                                 /*
 439                                  * Since this is the last byte, we should now
 440                                  * disable TX FIFO underrun interrupt
 441                                  */
 442                                 tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 443                                 tmp &= ~BIT(IE_M_TX_UNDERRUN_SHIFT);
 444                                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET,
 445                                                  tmp);
 446                         }
 447                 }
 448
 449                 /* load data into TX FIFO */
 450                 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
 451         }
 452
 453         /* update number of transferred bytes */
 454         iproc_i2c->tx_bytes += tx_bytes;
 455 }
 456
 457 static void bcm_iproc_i2c_read(struct bcm_iproc_i2c_dev *iproc_i2c)
 458 {
 459         struct i2c_msg *msg = iproc_i2c->msg;
 460         u32 bytes_left, val;
 461
 462         bcm_iproc_i2c_read_valid_bytes(iproc_i2c);
 463         bytes_left = msg->len - iproc_i2c->rx_bytes;
 464         if (bytes_left == 0) {
 465                 if (iproc_i2c->irq) {
 466                         /* finished reading all data, disable rx thld event */
 467                         val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 468                         val &= ~BIT(IS_M_RX_THLD_SHIFT);
 469                         iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
 470                 }
 471         } else if (bytes_left < iproc_i2c->thld_bytes) {
 472                 /* set bytes left as threshold */
 473                 val = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET);
 474                 val &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
 475                 val |= (bytes_left << M_FIFO_RX_THLD_SHIFT);
 476                 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
 477                 iproc_i2c->thld_bytes = bytes_left;
 478         }
 479         /*
 480          * bytes_left >= iproc_i2c->thld_bytes,
 481          * hence no need to change the THRESHOLD SET.
 482          * It will remain as iproc_i2c->thld_bytes itself
 483          */
 484 }
 485
 486 static void bcm_iproc_i2c_process_m_event(struct bcm_iproc_i2c_dev *iproc_i2c,
 487                                           u32 status)
 488 {
 489         /* TX FIFO is empty and we have more data to send */
 490         if (status & BIT(IS_M_TX_UNDERRUN_SHIFT))
 491                 bcm_iproc_i2c_send(iproc_i2c);
 492
 493         /* RX FIFO threshold is reached and data needs to be read out */
 494         if (status & BIT(IS_M_RX_THLD_SHIFT))
 495                 bcm_iproc_i2c_read(iproc_i2c);
 496
 497         /* transfer is done */
 498         if (status & BIT(IS_M_START_BUSY_SHIFT)) {
 499                 iproc_i2c->xfer_is_done = 1;
 500                 if (iproc_i2c->irq)
 501                         complete(&iproc_i2c->done);
 502         }
 503 }
 504
 505 static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data)
 506 {
 507         struct bcm_iproc_i2c_dev *iproc_i2c = data;
 508         u32 status = iproc_i2c_rd_reg(iproc_i2c, IS_OFFSET);
 509         bool ret;
 510         u32 sl_status = status & ISR_MASK_SLAVE;
 511
 512         if (sl_status) {
 513                 ret = bcm_iproc_i2c_slave_isr(iproc_i2c, sl_status);
 514                 if (ret)
 515                         return IRQ_HANDLED;
 516                 else
 517                         return IRQ_NONE;
 518         }
 519
 520         status &= ISR_MASK;
 521         if (!status)
 522                 return IRQ_NONE;
 523
 524         /* process all master based events */
 525         bcm_iproc_i2c_process_m_event(iproc_i2c, status);
 526         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
 527
 528         return IRQ_HANDLED;
 529 }
 530
 531 static int bcm_iproc_i2c_init(struct bcm_iproc_i2c_dev *iproc_i2c)
 532 {
 533         u32 val;
 534
 535         /* put controller in reset */
 536         val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
 537         val |= BIT(CFG_RESET_SHIFT);
 538         val &= ~(BIT(CFG_EN_SHIFT));
 539         iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
 540
 541         /* wait 100 usec per spec */
 542         udelay(100);
 543
 544         /* bring controller out of reset */
 545         val &= ~(BIT(CFG_RESET_SHIFT));
 546         iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
 547
 548         /* flush TX/RX FIFOs and set RX FIFO threshold to zero */
 549         val = (BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT));
 550         iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
 551         /* disable all interrupts */
 552         val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 553         val &= ~(IE_M_ALL_INTERRUPT_MASK <<
 554                         IE_M_ALL_INTERRUPT_SHIFT);
 555         iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
 556
 557         /* clear all pending interrupts */
 558         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, 0xffffffff);
 559
 560         return 0;
 561 }
 562
 563 static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c,
 564                                          bool enable)
 565 {
 566         u32 val;
 567
 568         val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
 569         if (enable)
 570                 val |= BIT(CFG_EN_SHIFT);
 571         else
 572                 val &= ~BIT(CFG_EN_SHIFT);
 573         iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
 574 }
 575
 576 static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c,
 577                                       struct i2c_msg *msg)
 578 {
 579         u32 val;
 580
 581         val = iproc_i2c_rd_reg(iproc_i2c, M_CMD_OFFSET);
 582         val = (val >> M_CMD_STATUS_SHIFT) & M_CMD_STATUS_MASK;
 583
 584         switch (val) {
 585         case M_CMD_STATUS_SUCCESS:
 586                 return 0;
 587
 588         case M_CMD_STATUS_LOST_ARB:
 589                 dev_dbg(iproc_i2c->device, "lost bus arbitration\n");
 590                 return -EAGAIN;
 591
 592         case M_CMD_STATUS_NACK_ADDR:
 593                 dev_dbg(iproc_i2c->device, "NAK addr:0x%02x\n", msg->addr);
 594                 return -ENXIO;
 595
 596         case M_CMD_STATUS_NACK_DATA:
 597                 dev_dbg(iproc_i2c->device, "NAK data\n");
 598                 return -ENXIO;
 599
 600         case M_CMD_STATUS_TIMEOUT:
 601                 dev_dbg(iproc_i2c->device, "bus timeout\n");
 602                 return -ETIMEDOUT;
 603
 604         case M_CMD_STATUS_FIFO_UNDERRUN:
 605                 dev_dbg(iproc_i2c->device, "FIFO under-run\n");
 606                 return -ENXIO;
 607
 608         case M_CMD_STATUS_RX_FIFO_FULL:
 609                 dev_dbg(iproc_i2c->device, "RX FIFO full\n");
 610                 return -ETIMEDOUT;
 611
 612         default:
 613                 dev_dbg(iproc_i2c->device, "unknown error code=%d\n", val);
 614
 615                 /* re-initialize i2c for recovery */
 616                 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
 617                 bcm_iproc_i2c_init(iproc_i2c);
 618                 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
 619
 620                 return -EIO;
 621         }
 622 }
 623
 624 static int bcm_iproc_i2c_xfer_wait(struct bcm_iproc_i2c_dev *iproc_i2c,
 625                                    struct i2c_msg *msg,
 626                                    u32 cmd)
 627 {
 628         unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT_MSEC);
 629         u32 val, status;
 630         int ret;
 631
 632         iproc_i2c_wr_reg(iproc_i2c, M_CMD_OFFSET, cmd);
 633
 634         if (iproc_i2c->irq) {
 635                 time_left = wait_for_completion_timeout(&iproc_i2c->done,
 636                                                         time_left);
 637                 /* disable all interrupts */
 638                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
 639                 /* read it back to flush the write */
 640                 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 641                 /* make sure the interrupt handler isn't running */
 642                 synchronize_irq(iproc_i2c->irq);
 643
 644         } else { /* polling mode */
 645                 unsigned long timeout = jiffies + time_left;
 646
 647                 do {
 648                         status = iproc_i2c_rd_reg(iproc_i2c,
 649                                                   IS_OFFSET) & ISR_MASK;
 650                         bcm_iproc_i2c_process_m_event(iproc_i2c, status);
 651                         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
 652
 653                         if (time_after(jiffies, timeout)) {
 654                                 time_left = 0;
 655                                 break;
 656                         }
 657
 658                         cpu_relax();
 659                         cond_resched();
 660                 } while (!iproc_i2c->xfer_is_done);
 661         }
 662
 663         if (!time_left && !iproc_i2c->xfer_is_done) {
 664                 dev_err(iproc_i2c->device, "transaction timed out\n");
 665
 666                 /* flush both TX/RX FIFOs */
 667                 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
 668                 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
 669                 return -ETIMEDOUT;
 670         }
 671
 672         ret = bcm_iproc_i2c_check_status(iproc_i2c, msg);
 673         if (ret) {
 674                 /* flush both TX/RX FIFOs */
 675                 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
 676                 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
 677                 return ret;
 678         }
 679
 680         return 0;
 681 }
 682
 683 /*
 684  * If 'process_call' is true, then this is a multi-msg transfer that requires
 685  * a repeated start between the messages.
 686  * More specifically, it must be a write (reg) followed by a read (data).
 687  * The i2c quirks are set to enforce this rule.
 688  */
 689 static int bcm_iproc_i2c_xfer_internal(struct bcm_iproc_i2c_dev *iproc_i2c,
 690                                         struct i2c_msg *msgs, bool process_call)
 691 {
 692         int i;
 693         u8 addr;
 694         u32 val, tmp, val_intr_en;
 695         unsigned int tx_bytes;
 696         struct i2c_msg *msg = &msgs[0];
 697
 698         /* check if bus is busy */
 699         if (!!(iproc_i2c_rd_reg(iproc_i2c,
 700                                 M_CMD_OFFSET) & BIT(M_CMD_START_BUSY_SHIFT))) {
 701                 dev_warn(iproc_i2c->device, "bus is busy\n");
 702                 return -EBUSY;
 703         }
 704
 705         iproc_i2c->msg = msg;
 706
 707         /* format and load slave address into the TX FIFO */
 708         addr = i2c_8bit_addr_from_msg(msg);
 709         iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, addr);
 710
 711         /*
 712          * For a write transaction, load data into the TX FIFO. Only allow
 713          * loading up to TX FIFO size - 1 bytes of data since the first byte
 714          * has been used up by the slave address
 715          */
 716         tx_bytes = min_t(unsigned int, msg->len, M_TX_RX_FIFO_SIZE - 1);
 717         if (!(msg->flags & I2C_M_RD)) {
 718                 for (i = 0; i < tx_bytes; i++) {
 719                         val = msg->buf[i];
 720
 721                         /* mark the last byte */
 722                         if (!process_call && (i == msg->len - 1))
 723                                 val |= BIT(M_TX_WR_STATUS_SHIFT);
 724
 725                         iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
 726                 }
 727                 iproc_i2c->tx_bytes = tx_bytes;
 728         }
 729
 730         /* Process the read message if this is process call */
 731         if (process_call) {
 732                 msg++;
 733                 iproc_i2c->msg = msg;  /* point to second msg */
 734
 735                 /*
 736                  * The last byte to be sent out should be a slave
 737                  * address with read operation
 738                  */
 739                 addr = i2c_8bit_addr_from_msg(msg);
 740                 /* mark it the last byte out */
 741                 val = addr | BIT(M_TX_WR_STATUS_SHIFT);
 742                 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
 743         }
 744
 745         /* mark as incomplete before starting the transaction */
 746         if (iproc_i2c->irq)
 747                 reinit_completion(&iproc_i2c->done);
 748
 749         iproc_i2c->xfer_is_done = 0;
 750
 751         /*
 752          * Enable the "start busy" interrupt, which will be triggered after the
 753          * transaction is done, i.e., the internal start_busy bit, transitions
 754          * from 1 to 0.
 755          */
 756         val_intr_en = BIT(IE_M_START_BUSY_SHIFT);
 757
 758         /*
 759          * If TX data size is larger than the TX FIFO, need to enable TX
 760          * underrun interrupt, which will be triggerred when the TX FIFO is
 761          * empty. When that happens we can then pump more data into the FIFO
 762          */
 763         if (!process_call && !(msg->flags & I2C_M_RD) &&
 764             msg->len > iproc_i2c->tx_bytes)
 765                 val_intr_en |= BIT(IE_M_TX_UNDERRUN_SHIFT);
 766
 767         /*
 768          * Now we can activate the transfer. For a read operation, specify the
 769          * number of bytes to read
 770          */
 771         val = BIT(M_CMD_START_BUSY_SHIFT);
 772
 773         if (msg->len == 0) {
 774                 /* SMBUS QUICK Command (Read/Write) */
 775                 val |= (M_CMD_PROTOCOL_QUICK << M_CMD_PROTOCOL_SHIFT);
 776         } else if (msg->flags & I2C_M_RD) {
 777                 u32 protocol;
 778
 779                 iproc_i2c->rx_bytes = 0;
 780                 if (msg->len > M_RX_FIFO_MAX_THLD_VALUE)
 781                         iproc_i2c->thld_bytes = M_RX_FIFO_THLD_VALUE;
 782                 else
 783                         iproc_i2c->thld_bytes = msg->len;
 784
 785                 /* set threshold value */
 786                 tmp = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET);
 787                 tmp &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
 788                 tmp |= iproc_i2c->thld_bytes << M_FIFO_RX_THLD_SHIFT;
 789                 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, tmp);
 790
 791                 /* enable the RX threshold interrupt */
 792                 val_intr_en |= BIT(IE_M_RX_THLD_SHIFT);
 793
 794                 protocol = process_call ?
 795                                 M_CMD_PROTOCOL_PROCESS : M_CMD_PROTOCOL_BLK_RD;
 796
 797                 val |= (protocol << M_CMD_PROTOCOL_SHIFT) |
 798                        (msg->len << M_CMD_RD_CNT_SHIFT);
 799         } else {
 800                 val |= (M_CMD_PROTOCOL_BLK_WR << M_CMD_PROTOCOL_SHIFT);
 801         }
 802
 803         if (iproc_i2c->irq)
 804                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val_intr_en);
 805
 806         return bcm_iproc_i2c_xfer_wait(iproc_i2c, msg, val);
 807 }
 808
 809 static int bcm_iproc_i2c_xfer(struct i2c_adapter *adapter,
 810                               struct i2c_msg msgs[], int num)
 811 {
 812         struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(adapter);
 813         bool process_call = false;
 814         int ret;
 815
 816         if (num == 2) {
 817                 /* Repeated start, use process call */
 818                 process_call = true;
 819                 if (msgs[1].flags & I2C_M_NOSTART) {
 820                         dev_err(iproc_i2c->device, "Invalid repeated start\n");
 821                         return -EOPNOTSUPP;
 822                 }
 823         }
 824
 825         ret = bcm_iproc_i2c_xfer_internal(iproc_i2c, msgs, process_call);
 826         if (ret) {
 827                 dev_dbg(iproc_i2c->device, "xfer failed\n");
 828                 return ret;
 829         }
 830
 831         return num;
 832 }
 833
 834 static uint32_t bcm_iproc_i2c_functionality(struct i2c_adapter *adap)
 835 {
 836         u32 val;
 837
 838         val = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 839
 840         if (adap->algo->reg_slave)
 841                 val |= I2C_FUNC_SLAVE;
 842
 843         return val;
 844 }
 845
 846 static struct i2c_algorithm bcm_iproc_algo = {
 847         .master_xfer = bcm_iproc_i2c_xfer,
 848         .functionality = bcm_iproc_i2c_functionality,
 849         .reg_slave = bcm_iproc_i2c_reg_slave,
 850         .unreg_slave = bcm_iproc_i2c_unreg_slave,
 851 };
 852
 853 static const struct i2c_adapter_quirks bcm_iproc_i2c_quirks = {
 854         .flags = I2C_AQ_COMB_WRITE_THEN_READ,
 855         .max_comb_1st_msg_len = M_TX_RX_FIFO_SIZE,
 856         .max_read_len = M_RX_MAX_READ_LEN,
 857 };
 858
 859 static int bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev *iproc_i2c)
 860 {
 861         unsigned int bus_speed;
 862         u32 val;
 863         int ret = of_property_read_u32(iproc_i2c->device->of_node,
 864                                        "clock-frequency", &bus_speed);
 865         if (ret < 0) {
 866                 dev_info(iproc_i2c->device,
 867                         "unable to interpret clock-frequency DT property\n");
 868                 bus_speed = I2C_MAX_STANDARD_MODE_FREQ;
 869         }
 870
 871         if (bus_speed < I2C_MAX_STANDARD_MODE_FREQ) {
 872                 dev_err(iproc_i2c->device, "%d Hz bus speed not supported\n",
 873                         bus_speed);
 874                 dev_err(iproc_i2c->device,
 875                         "valid speeds are 100khz and 400khz\n");
 876                 return -EINVAL;
 877         } else if (bus_speed < I2C_MAX_FAST_MODE_FREQ) {
 878                 bus_speed = I2C_MAX_STANDARD_MODE_FREQ;
 879         } else {
 880                 bus_speed = I2C_MAX_FAST_MODE_FREQ;
 881         }
 882
 883         iproc_i2c->bus_speed = bus_speed;
 884         val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
 885         val &= ~BIT(TIM_CFG_MODE_400_SHIFT);
 886         val |= (bus_speed == I2C_MAX_FAST_MODE_FREQ) << TIM_CFG_MODE_400_SHIFT;
 887         iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
 888
 889         dev_info(iproc_i2c->device, "bus set to %u Hz\n", bus_speed);
 890
 891         return 0;
 892 }
 893
 894 static int bcm_iproc_i2c_probe(struct platform_device *pdev)
 895 {
 896         int irq, ret = 0;
 897         struct bcm_iproc_i2c_dev *iproc_i2c;
 898         struct i2c_adapter *adap;
 899         struct resource *res;
 900
 901         iproc_i2c = devm_kzalloc(&pdev->dev, sizeof(*iproc_i2c),
 902                                  GFP_KERNEL);
 903         if (!iproc_i2c)
 904                 return -ENOMEM;
 905
 906         platform_set_drvdata(pdev, iproc_i2c);
 907         iproc_i2c->device = &pdev->dev;
 908         iproc_i2c->type =
 909                 (enum bcm_iproc_i2c_type)of_device_get_match_data(&pdev->dev);
 910         init_completion(&iproc_i2c->done);
 911
 912         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 913         iproc_i2c->base = devm_ioremap_resource(iproc_i2c->device, res);
 914         if (IS_ERR(iproc_i2c->base))
 915                 return PTR_ERR(iproc_i2c->base);
 916
 917         if (iproc_i2c->type == IPROC_I2C_NIC) {
 918                 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 919                 iproc_i2c->idm_base = devm_ioremap_resource(iproc_i2c->device,
 920                                                             res);
 921                 if (IS_ERR(iproc_i2c->idm_base))
 922                         return PTR_ERR(iproc_i2c->idm_base);
 923
 924                 ret = of_property_read_u32(iproc_i2c->device->of_node,
 925                                            "brcm,ape-hsls-addr-mask",
 926                                            &iproc_i2c->ape_addr_mask);
 927                 if (ret < 0) {
 928                         dev_err(iproc_i2c->device,
 929                                 "'brcm,ape-hsls-addr-mask' missing\n");
 930                         return -EINVAL;
 931                 }
 932
 933                 spin_lock_init(&iproc_i2c->idm_lock);
 934
 935                 /* no slave support */
 936                 bcm_iproc_algo.reg_slave = NULL;
 937                 bcm_iproc_algo.unreg_slave = NULL;
 938         }
 939
 940         ret = bcm_iproc_i2c_init(iproc_i2c);
 941         if (ret)
 942                 return ret;
 943
 944         ret = bcm_iproc_i2c_cfg_speed(iproc_i2c);
 945         if (ret)
 946                 return ret;
 947
 948         irq = platform_get_irq(pdev, 0);
 949         if (irq > 0) {
 950                 ret = devm_request_irq(iproc_i2c->device, irq,
 951                                        bcm_iproc_i2c_isr, 0, pdev->name,
 952                                        iproc_i2c);
 953                 if (ret < 0) {
 954                         dev_err(iproc_i2c->device,
 955                                 "unable to request irq %i\n", irq);
 956                         return ret;
 957                 }
 958
 959                 iproc_i2c->irq = irq;
 960         } else {
 961                 dev_warn(iproc_i2c->device,
 962                          "no irq resource, falling back to poll mode\n");
 963         }
 964
 965         bcm_iproc_i2c_enable_disable(iproc_i2c, true);
 966
 967         adap = &iproc_i2c->adapter;
 968         i2c_set_adapdata(adap, iproc_i2c);
 969         snprintf(adap->name, sizeof(adap->name),
 970                 "Broadcom iProc (%s)",
 971                 of_node_full_name(iproc_i2c->device->of_node));
 972         adap->algo = &bcm_iproc_algo;
 973         adap->quirks = &bcm_iproc_i2c_quirks;
 974         adap->dev.parent = &pdev->dev;
 975         adap->dev.of_node = pdev->dev.of_node;
 976
 977         return i2c_add_adapter(adap);
 978 }
 979
 980 static int bcm_iproc_i2c_remove(struct platform_device *pdev)
 981 {
 982         struct bcm_iproc_i2c_dev *iproc_i2c = platform_get_drvdata(pdev);
 983
 984         if (iproc_i2c->irq) {
 985                 /*
 986                  * Make sure there's no pending interrupt when we remove the
 987                  * adapter
 988                  */
 989                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
 990                 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 991                 synchronize_irq(iproc_i2c->irq);
 992         }
 993
 994         i2c_del_adapter(&iproc_i2c->adapter);
 995         bcm_iproc_i2c_enable_disable(iproc_i2c, false);
 996
 997         return 0;
 998 }
 999
1000 #ifdef CONFIG_PM_SLEEP
1001
1002 static int bcm_iproc_i2c_suspend(struct device *dev)
1003 {
1004         struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev);
1005
1006         if (iproc_i2c->irq) {
1007                 /*
1008                  * Make sure there's no pending interrupt when we go into
1009                  * suspend
1010                  */
1011                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
1012                 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
1013                 synchronize_irq(iproc_i2c->irq);
1014         }
1015
1016         /* now disable the controller */
1017         bcm_iproc_i2c_enable_disable(iproc_i2c, false);
1018
1019         return 0;
1020 }
1021
1022 static int bcm_iproc_i2c_resume(struct device *dev)
1023 {
1024         struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev);
1025         int ret;
1026         u32 val;
1027
1028         /*
1029          * Power domain could have been shut off completely in system deep
1030          * sleep, so re-initialize the block here
1031          */
1032         ret = bcm_iproc_i2c_init(iproc_i2c);
1033         if (ret)
1034                 return ret;
1035
1036         /* configure to the desired bus speed */
1037         val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
1038         val &= ~BIT(TIM_CFG_MODE_400_SHIFT);
1039         val |= (iproc_i2c->bus_speed == I2C_MAX_FAST_MODE_FREQ) << TIM_CFG_MODE_400_SHIFT;
1040         iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
1041
1042         bcm_iproc_i2c_enable_disable(iproc_i2c, true);
1043
1044         return 0;
1045 }
1046
1047 static const struct dev_pm_ops bcm_iproc_i2c_pm_ops = {
1048         .suspend_late = &bcm_iproc_i2c_suspend,
1049         .resume_early = &bcm_iproc_i2c_resume
1050 };
1051
1052 #define BCM_IPROC_I2C_PM_OPS (&bcm_iproc_i2c_pm_ops)
1053 #else
1054 #define BCM_IPROC_I2C_PM_OPS NULL
1055 #endif /* CONFIG_PM_SLEEP */
1056
1057
1058 static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave)
1059 {
1060         struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter);
1061
1062         if (iproc_i2c->slave)
1063                 return -EBUSY;
1064
1065         if (slave->flags & I2C_CLIENT_TEN)
1066                 return -EAFNOSUPPORT;
1067
1068         iproc_i2c->slave = slave;
1069         bcm_iproc_i2c_slave_init(iproc_i2c, false);
1070         return 0;
1071 }
1072
1073 static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave)
1074 {
1075         u32 tmp;
1076         struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter);
1077
1078         if (!iproc_i2c->slave)
1079                 return -EINVAL;
1080
1081         disable_irq(iproc_i2c->irq);
1082
1083         /* disable all slave interrupts */
1084         tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
1085         tmp &= ~(IE_S_ALL_INTERRUPT_MASK <<
1086                         IE_S_ALL_INTERRUPT_SHIFT);
1087         iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, tmp);
1088
1089         /* Erase the slave address programmed */
1090         tmp = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET);
1091         tmp &= ~BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);
1092         iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, tmp);
1093
1094         /* flush TX/RX FIFOs */
1095         tmp = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT));
1096         iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, tmp);
1097
1098         /* clear all pending slave interrupts */
1099         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE);
1100
1101         iproc_i2c->slave = NULL;
1102
1103         enable_irq(iproc_i2c->irq);
1104
1105         return 0;
1106 }
1107
1108 static const struct of_device_id bcm_iproc_i2c_of_match[] = {
1109         {
1110                 .compatible = "brcm,iproc-i2c",
1111                 .data = (int *)IPROC_I2C,
1112         }, {
1113                 .compatible = "brcm,iproc-nic-i2c",
1114                 .data = (int *)IPROC_I2C_NIC,
1115         },
1116         { /* sentinel */ }
1117 };
1118 MODULE_DEVICE_TABLE(of, bcm_iproc_i2c_of_match);
1119
1120 static struct platform_driver bcm_iproc_i2c_driver = {
1121         .driver = {
1122                 .name = "bcm-iproc-i2c",
1123                 .of_match_table = bcm_iproc_i2c_of_match,
1124                 .pm = BCM_IPROC_I2C_PM_OPS,
1125         },
1126         .probe = bcm_iproc_i2c_probe,
1127         .remove = bcm_iproc_i2c_remove,
1128 };
1129 module_platform_driver(bcm_iproc_i2c_driver);
1130
1131 MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
1132 MODULE_DESCRIPTION("Broadcom iProc I2C Driver");
1133 MODULE_LICENSE("GPL v2");