drivers/i2c/busses/i2c-bcm-iproc.c

   1 /*
   2  * Copyright (C) 2014 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation version 2.
   7  *
   8  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
   9  * kind, whether express or implied; without even the implied warranty
  10  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/delay.h>
  15 #include <linux/i2c.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/kernel.h>
  19 #include <linux/module.h>
  20 #include <linux/of_device.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/slab.h>
  23
  24 #define IDM_CTRL_DIRECT_OFFSET       0x00
  25 #define CFG_OFFSET                   0x00
  26 #define CFG_RESET_SHIFT              31
  27 #define CFG_EN_SHIFT                 30
  28 #define CFG_SLAVE_ADDR_0_SHIFT       28
  29 #define CFG_M_RETRY_CNT_SHIFT        16
  30 #define CFG_M_RETRY_CNT_MASK         0x0f
  31
  32 #define TIM_CFG_OFFSET               0x04
  33 #define TIM_CFG_MODE_400_SHIFT       31
  34 #define TIM_RAND_SLAVE_STRETCH_SHIFT      24
  35 #define TIM_RAND_SLAVE_STRETCH_MASK       0x7f
  36 #define TIM_PERIODIC_SLAVE_STRETCH_SHIFT  16
  37 #define TIM_PERIODIC_SLAVE_STRETCH_MASK   0x7f
  38
  39 #define S_CFG_SMBUS_ADDR_OFFSET           0x08
  40 #define S_CFG_EN_NIC_SMB_ADDR3_SHIFT      31
  41 #define S_CFG_NIC_SMB_ADDR3_SHIFT         24
  42 #define S_CFG_NIC_SMB_ADDR3_MASK          0x7f
  43 #define S_CFG_EN_NIC_SMB_ADDR2_SHIFT      23
  44 #define S_CFG_NIC_SMB_ADDR2_SHIFT         16
  45 #define S_CFG_NIC_SMB_ADDR2_MASK          0x7f
  46 #define S_CFG_EN_NIC_SMB_ADDR1_SHIFT      15
  47 #define S_CFG_NIC_SMB_ADDR1_SHIFT         8
  48 #define S_CFG_NIC_SMB_ADDR1_MASK          0x7f
  49 #define S_CFG_EN_NIC_SMB_ADDR0_SHIFT      7
  50 #define S_CFG_NIC_SMB_ADDR0_SHIFT         0
  51 #define S_CFG_NIC_SMB_ADDR0_MASK          0x7f
  52
  53 #define M_FIFO_CTRL_OFFSET           0x0c
  54 #define M_FIFO_RX_FLUSH_SHIFT        31
  55 #define M_FIFO_TX_FLUSH_SHIFT        30
  56 #define M_FIFO_RX_CNT_SHIFT          16
  57 #define M_FIFO_RX_CNT_MASK           0x7f
  58 #define M_FIFO_RX_THLD_SHIFT         8
  59 #define M_FIFO_RX_THLD_MASK          0x3f
  60
  61 #define S_FIFO_CTRL_OFFSET           0x10
  62 #define S_FIFO_RX_FLUSH_SHIFT        31
  63 #define S_FIFO_TX_FLUSH_SHIFT        30
  64 #define S_FIFO_RX_CNT_SHIFT          16
  65 #define S_FIFO_RX_CNT_MASK           0x7f
  66 #define S_FIFO_RX_THLD_SHIFT         8
  67 #define S_FIFO_RX_THLD_MASK          0x3f
  68
  69 #define M_CMD_OFFSET                 0x30
  70 #define M_CMD_START_BUSY_SHIFT       31
  71 #define M_CMD_STATUS_SHIFT           25
  72 #define M_CMD_STATUS_MASK            0x07
  73 #define M_CMD_STATUS_SUCCESS         0x0
  74 #define M_CMD_STATUS_LOST_ARB        0x1
  75 #define M_CMD_STATUS_NACK_ADDR       0x2
  76 #define M_CMD_STATUS_NACK_DATA       0x3
  77 #define M_CMD_STATUS_TIMEOUT         0x4
  78 #define M_CMD_STATUS_FIFO_UNDERRUN   0x5
  79 #define M_CMD_STATUS_RX_FIFO_FULL    0x6
  80 #define M_CMD_PROTOCOL_SHIFT         9
  81 #define M_CMD_PROTOCOL_MASK          0xf
  82 #define M_CMD_PROTOCOL_BLK_WR        0x7
  83 #define M_CMD_PROTOCOL_BLK_RD        0x8
  84 #define M_CMD_PROTOCOL_PROCESS       0xa
  85 #define M_CMD_PEC_SHIFT              8
  86 #define M_CMD_RD_CNT_SHIFT           0
  87 #define M_CMD_RD_CNT_MASK            0xff
  88
  89 #define S_CMD_OFFSET                 0x34
  90 #define S_CMD_START_BUSY_SHIFT       31
  91 #define S_CMD_STATUS_SHIFT           23
  92 #define S_CMD_STATUS_MASK            0x07
  93 #define S_CMD_STATUS_SUCCESS         0x0
  94 #define S_CMD_STATUS_TIMEOUT         0x5
  95
  96 #define IE_OFFSET                    0x38
  97 #define IE_M_RX_FIFO_FULL_SHIFT      31
  98 #define IE_M_RX_THLD_SHIFT           30
  99 #define IE_M_START_BUSY_SHIFT        28
 100 #define IE_M_TX_UNDERRUN_SHIFT       27
 101 #define IE_S_RX_FIFO_FULL_SHIFT      26
 102 #define IE_S_RX_THLD_SHIFT           25
 103 #define IE_S_RX_EVENT_SHIFT          24
 104 #define IE_S_START_BUSY_SHIFT        23
 105 #define IE_S_TX_UNDERRUN_SHIFT       22
 106 #define IE_S_RD_EVENT_SHIFT          21
 107
 108 #define IS_OFFSET                    0x3c
 109 #define IS_M_RX_FIFO_FULL_SHIFT      31
 110 #define IS_M_RX_THLD_SHIFT           30
 111 #define IS_M_START_BUSY_SHIFT        28
 112 #define IS_M_TX_UNDERRUN_SHIFT       27
 113 #define IS_S_RX_FIFO_FULL_SHIFT      26
 114 #define IS_S_RX_THLD_SHIFT           25
 115 #define IS_S_RX_EVENT_SHIFT          24
 116 #define IS_S_START_BUSY_SHIFT        23
 117 #define IS_S_TX_UNDERRUN_SHIFT       22
 118 #define IS_S_RD_EVENT_SHIFT          21
 119
 120 #define M_TX_OFFSET                  0x40
 121 #define M_TX_WR_STATUS_SHIFT         31
 122 #define M_TX_DATA_SHIFT              0
 123 #define M_TX_DATA_MASK               0xff
 124
 125 #define M_RX_OFFSET                  0x44
 126 #define M_RX_STATUS_SHIFT            30
 127 #define M_RX_STATUS_MASK             0x03
 128 #define M_RX_PEC_ERR_SHIFT           29
 129 #define M_RX_DATA_SHIFT              0
 130 #define M_RX_DATA_MASK               0xff
 131
 132 #define S_TX_OFFSET                  0x48
 133 #define S_TX_WR_STATUS_SHIFT         31
 134 #define S_TX_DATA_SHIFT              0
 135 #define S_TX_DATA_MASK               0xff
 136
 137 #define S_RX_OFFSET                  0x4c
 138 #define S_RX_STATUS_SHIFT            30
 139 #define S_RX_STATUS_MASK             0x03
 140 #define S_RX_PEC_ERR_SHIFT           29
 141 #define S_RX_DATA_SHIFT              0
 142 #define S_RX_DATA_MASK               0xff
 143
 144 #define I2C_TIMEOUT_MSEC             50000
 145 #define M_TX_RX_FIFO_SIZE            64
 146 #define M_RX_FIFO_MAX_THLD_VALUE     (M_TX_RX_FIFO_SIZE - 1)
 147
 148 #define M_RX_MAX_READ_LEN            255
 149 #define M_RX_FIFO_THLD_VALUE         50
 150
 151 #define IE_M_ALL_INTERRUPT_SHIFT     27
 152 #define IE_M_ALL_INTERRUPT_MASK      0x1e
 153
 154 #define SLAVE_READ_WRITE_BIT_MASK    0x1
 155 #define SLAVE_READ_WRITE_BIT_SHIFT   0x1
 156 #define SLAVE_MAX_SIZE_TRANSACTION   64
 157 #define SLAVE_CLOCK_STRETCH_TIME     25
 158
 159 #define IE_S_ALL_INTERRUPT_SHIFT     21
 160 #define IE_S_ALL_INTERRUPT_MASK      0x3f
 161
 162 enum i2c_slave_read_status {
 163         I2C_SLAVE_RX_FIFO_EMPTY = 0,
 164         I2C_SLAVE_RX_START,
 165         I2C_SLAVE_RX_DATA,
 166         I2C_SLAVE_RX_END,
 167 };
 168
 169 enum bus_speed_index {
 170         I2C_SPD_100K = 0,
 171         I2C_SPD_400K,
 172 };
 173
 174 enum bcm_iproc_i2c_type {
 175         IPROC_I2C,
 176         IPROC_I2C_NIC
 177 };
 178
 179 struct bcm_iproc_i2c_dev {
 180         struct device *device;
 181         enum bcm_iproc_i2c_type type;
 182         int irq;
 183
 184         void __iomem *base;
 185         void __iomem *idm_base;
 186
 187         u32 ape_addr_mask;
 188
 189         /* lock for indirect access through IDM */
 190         spinlock_t idm_lock;
 191
 192         struct i2c_adapter adapter;
 193         unsigned int bus_speed;
 194
 195         struct completion done;
 196         int xfer_is_done;
 197
 198         struct i2c_msg *msg;
 199
 200         struct i2c_client *slave;
 201
 202         /* bytes that have been transferred */
 203         unsigned int tx_bytes;
 204         /* bytes that have been read */
 205         unsigned int rx_bytes;
 206         unsigned int thld_bytes;
 207 };
 208
 209 /*
 210  * Can be expanded in the future if more interrupt status bits are utilized
 211  */
 212 #define ISR_MASK (BIT(IS_M_START_BUSY_SHIFT) | BIT(IS_M_TX_UNDERRUN_SHIFT)\
 213                 | BIT(IS_M_RX_THLD_SHIFT))
 214
 215 #define ISR_MASK_SLAVE (BIT(IS_S_START_BUSY_SHIFT)\
 216                 | BIT(IS_S_RX_EVENT_SHIFT) | BIT(IS_S_RD_EVENT_SHIFT)\
 217                 | BIT(IS_S_TX_UNDERRUN_SHIFT))
 218
 219 static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave);
 220 static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave);
 221 static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c,
 222                                          bool enable);
 223
 224 static inline u32 iproc_i2c_rd_reg(struct bcm_iproc_i2c_dev *iproc_i2c,
 225                                    u32 offset)
 226 {
 227         u32 val;
 228
 229         if (iproc_i2c->idm_base) {
 230                 spin_lock(&iproc_i2c->idm_lock);
 231                 writel(iproc_i2c->ape_addr_mask,
 232                        iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET);
 233                 val = readl(iproc_i2c->base + offset);
 234                 spin_unlock(&iproc_i2c->idm_lock);
 235         } else {
 236                 val = readl(iproc_i2c->base + offset);
 237         }
 238
 239         return val;
 240 }
 241
 242 static inline void iproc_i2c_wr_reg(struct bcm_iproc_i2c_dev *iproc_i2c,
 243                                     u32 offset, u32 val)
 244 {
 245         if (iproc_i2c->idm_base) {
 246                 spin_lock(&iproc_i2c->idm_lock);
 247                 writel(iproc_i2c->ape_addr_mask,
 248                        iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET);
 249                 writel(val, iproc_i2c->base + offset);
 250                 spin_unlock(&iproc_i2c->idm_lock);
 251         } else {
 252                 writel(val, iproc_i2c->base + offset);
 253         }
 254 }
 255
 256 static void bcm_iproc_i2c_slave_init(
 257         struct bcm_iproc_i2c_dev *iproc_i2c, bool need_reset)
 258 {
 259         u32 val;
 260
 261         if (need_reset) {
 262                 /* put controller in reset */
 263                 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
 264                 val |= BIT(CFG_RESET_SHIFT);
 265                 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
 266
 267                 /* wait 100 usec per spec */
 268                 udelay(100);
 269
 270                 /* bring controller out of reset */
 271                 val &= ~(BIT(CFG_RESET_SHIFT));
 272                 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
 273         }
 274
 275         /* flush TX/RX FIFOs */
 276         val = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT));
 277         iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val);
 278
 279         /* Maximum slave stretch time */
 280         val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
 281         val &= ~(TIM_RAND_SLAVE_STRETCH_MASK << TIM_RAND_SLAVE_STRETCH_SHIFT);
 282         val |= (SLAVE_CLOCK_STRETCH_TIME << TIM_RAND_SLAVE_STRETCH_SHIFT);
 283         iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
 284
 285         /* Configure the slave address */
 286         val = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET);
 287         val |= BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);
 288         val &= ~(S_CFG_NIC_SMB_ADDR3_MASK << S_CFG_NIC_SMB_ADDR3_SHIFT);
 289         val |= (iproc_i2c->slave->addr << S_CFG_NIC_SMB_ADDR3_SHIFT);
 290         iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, val);
 291
 292         /* clear all pending slave interrupts */
 293         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE);
 294
 295         /* Enable interrupt register to indicate a valid byte in receive fifo */
 296         val = BIT(IE_S_RX_EVENT_SHIFT);
 297         /* Enable interrupt register for the Slave BUSY command */
 298         val |= BIT(IE_S_START_BUSY_SHIFT);
 299         iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
 300 }
 301
 302 static void bcm_iproc_i2c_check_slave_status(
 303         struct bcm_iproc_i2c_dev *iproc_i2c)
 304 {
 305         u32 val;
 306
 307         val = iproc_i2c_rd_reg(iproc_i2c, S_CMD_OFFSET);
 308         /* status is valid only when START_BUSY is cleared after it was set */
 309         if (val & BIT(S_CMD_START_BUSY_SHIFT))
 310                 return;
 311
 312         val = (val >> S_CMD_STATUS_SHIFT) & S_CMD_STATUS_MASK;
 313         if (val == S_CMD_STATUS_TIMEOUT) {
 314                 dev_err(iproc_i2c->device, "slave random stretch time timeout\n");
 315
 316                 /* re-initialize i2c for recovery */
 317                 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
 318                 bcm_iproc_i2c_slave_init(iproc_i2c, true);
 319                 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
 320         }
 321 }
 322
 323 static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c,
 324                                     u32 status)
 325 {
 326         u32 val;
 327         u8 value, rx_status;
 328
 329         /* Slave RX byte receive */
 330         if (status & BIT(IS_S_RX_EVENT_SHIFT)) {
 331                 val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);
 332                 rx_status = (val >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK;
 333                 if (rx_status == I2C_SLAVE_RX_START) {
 334                         /* Start of SMBUS for Master write */
 335                         i2c_slave_event(iproc_i2c->slave,
 336                                         I2C_SLAVE_WRITE_REQUESTED, &value);
 337
 338                         val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);
 339                         value = (u8)((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK);
 340                         i2c_slave_event(iproc_i2c->slave,
 341                                         I2C_SLAVE_WRITE_RECEIVED, &value);
 342                 } else if (status & BIT(IS_S_RD_EVENT_SHIFT)) {
 343                         /* Start of SMBUS for Master Read */
 344                         i2c_slave_event(iproc_i2c->slave,
 345                                         I2C_SLAVE_READ_REQUESTED, &value);
 346                         iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value);
 347
 348                         val = BIT(S_CMD_START_BUSY_SHIFT);
 349                         iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
 350
 351                         /*
 352                          * Enable interrupt for TX FIFO becomes empty and
 353                          * less than PKT_LENGTH bytes were output on the SMBUS
 354                          */
 355                         val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 356                         val |= BIT(IE_S_TX_UNDERRUN_SHIFT);
 357                         iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
 358                 } else {
 359                         /* Master write other than start */
 360                         value = (u8)((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK);
 361                         i2c_slave_event(iproc_i2c->slave,
 362                                         I2C_SLAVE_WRITE_RECEIVED, &value);
 363                 }
 364         } else if (status & BIT(IS_S_TX_UNDERRUN_SHIFT)) {
 365                 /* Master read other than start */
 366                 i2c_slave_event(iproc_i2c->slave,
 367                                 I2C_SLAVE_READ_PROCESSED, &value);
 368
 369                 iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value);
 370                 val = BIT(S_CMD_START_BUSY_SHIFT);
 371                 iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
 372         }
 373
 374         /* Stop */
 375         if (status & BIT(IS_S_START_BUSY_SHIFT)) {
 376                 i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP, &value);
 377                 /*
 378                  * Enable interrupt for TX FIFO becomes empty and
 379                  * less than PKT_LENGTH bytes were output on the SMBUS
 380                  */
 381                 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 382                 val &= ~BIT(IE_S_TX_UNDERRUN_SHIFT);
 383                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
 384         }
 385
 386         /* clear interrupt status */
 387         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
 388
 389         bcm_iproc_i2c_check_slave_status(iproc_i2c);
 390         return true;
 391 }
 392
 393 static void bcm_iproc_i2c_read_valid_bytes(struct bcm_iproc_i2c_dev *iproc_i2c)
 394 {
 395         struct i2c_msg *msg = iproc_i2c->msg;
 396         uint32_t val;
 397
 398         /* Read valid data from RX FIFO */
 399         while (iproc_i2c->rx_bytes < msg->len) {
 400                 val = iproc_i2c_rd_reg(iproc_i2c, M_RX_OFFSET);
 401
 402                 /* rx fifo empty */
 403                 if (!((val >> M_RX_STATUS_SHIFT) & M_RX_STATUS_MASK))
 404                         break;
 405
 406                 msg->buf[iproc_i2c->rx_bytes] =
 407                         (val >> M_RX_DATA_SHIFT) & M_RX_DATA_MASK;
 408                 iproc_i2c->rx_bytes++;
 409         }
 410 }
 411
 412 static void bcm_iproc_i2c_send(struct bcm_iproc_i2c_dev *iproc_i2c)
 413 {
 414         struct i2c_msg *msg = iproc_i2c->msg;
 415         unsigned int tx_bytes = msg->len - iproc_i2c->tx_bytes;
 416         unsigned int i;
 417         u32 val;
 418
 419         /* can only fill up to the FIFO size */
 420         tx_bytes = min_t(unsigned int, tx_bytes, M_TX_RX_FIFO_SIZE);
 421         for (i = 0; i < tx_bytes; i++) {
 422                 /* start from where we left over */
 423                 unsigned int idx = iproc_i2c->tx_bytes + i;
 424
 425                 val = msg->buf[idx];
 426
 427                 /* mark the last byte */
 428                 if (idx == msg->len - 1) {
 429                         val |= BIT(M_TX_WR_STATUS_SHIFT);
 430
 431                         if (iproc_i2c->irq) {
 432                                 u32 tmp;
 433
 434                                 /*
 435                                  * Since this is the last byte, we should now
 436                                  * disable TX FIFO underrun interrupt
 437                                  */
 438                                 tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 439                                 tmp &= ~BIT(IE_M_TX_UNDERRUN_SHIFT);
 440                                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET,
 441                                                  tmp);
 442                         }
 443                 }
 444
 445                 /* load data into TX FIFO */
 446                 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
 447         }
 448
 449         /* update number of transferred bytes */
 450         iproc_i2c->tx_bytes += tx_bytes;
 451 }
 452
 453 static void bcm_iproc_i2c_read(struct bcm_iproc_i2c_dev *iproc_i2c)
 454 {
 455         struct i2c_msg *msg = iproc_i2c->msg;
 456         u32 bytes_left, val;
 457
 458         bcm_iproc_i2c_read_valid_bytes(iproc_i2c);
 459         bytes_left = msg->len - iproc_i2c->rx_bytes;
 460         if (bytes_left == 0) {
 461                 if (iproc_i2c->irq) {
 462                         /* finished reading all data, disable rx thld event */
 463                         val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 464                         val &= ~BIT(IS_M_RX_THLD_SHIFT);
 465                         iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
 466                 }
 467         } else if (bytes_left < iproc_i2c->thld_bytes) {
 468                 /* set bytes left as threshold */
 469                 val = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET);
 470                 val &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
 471                 val |= (bytes_left << M_FIFO_RX_THLD_SHIFT);
 472                 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
 473                 iproc_i2c->thld_bytes = bytes_left;
 474         }
 475         /*
 476          * bytes_left >= iproc_i2c->thld_bytes,
 477          * hence no need to change the THRESHOLD SET.
 478          * It will remain as iproc_i2c->thld_bytes itself
 479          */
 480 }
 481
 482 static void bcm_iproc_i2c_process_m_event(struct bcm_iproc_i2c_dev *iproc_i2c,
 483                                           u32 status)
 484 {
 485         /* TX FIFO is empty and we have more data to send */
 486         if (status & BIT(IS_M_TX_UNDERRUN_SHIFT))
 487                 bcm_iproc_i2c_send(iproc_i2c);
 488
 489         /* RX FIFO threshold is reached and data needs to be read out */
 490         if (status & BIT(IS_M_RX_THLD_SHIFT))
 491                 bcm_iproc_i2c_read(iproc_i2c);
 492
 493         /* transfer is done */
 494         if (status & BIT(IS_M_START_BUSY_SHIFT)) {
 495                 iproc_i2c->xfer_is_done = 1;
 496                 if (iproc_i2c->irq)
 497                         complete(&iproc_i2c->done);
 498         }
 499 }
 500
 501 static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data)
 502 {
 503         struct bcm_iproc_i2c_dev *iproc_i2c = data;
 504         u32 status = iproc_i2c_rd_reg(iproc_i2c, IS_OFFSET);
 505         bool ret;
 506         u32 sl_status = status & ISR_MASK_SLAVE;
 507
 508         if (sl_status) {
 509                 ret = bcm_iproc_i2c_slave_isr(iproc_i2c, sl_status);
 510                 if (ret)
 511                         return IRQ_HANDLED;
 512                 else
 513                         return IRQ_NONE;
 514         }
 515
 516         status &= ISR_MASK;
 517         if (!status)
 518                 return IRQ_NONE;
 519
 520         /* process all master based events */
 521         bcm_iproc_i2c_process_m_event(iproc_i2c, status);
 522         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
 523
 524         return IRQ_HANDLED;
 525 }
 526
 527 static int bcm_iproc_i2c_init(struct bcm_iproc_i2c_dev *iproc_i2c)
 528 {
 529         u32 val;
 530
 531         /* put controller in reset */
 532         val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
 533         val |= BIT(CFG_RESET_SHIFT);
 534         val &= ~(BIT(CFG_EN_SHIFT));
 535         iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
 536
 537         /* wait 100 usec per spec */
 538         udelay(100);
 539
 540         /* bring controller out of reset */
 541         val &= ~(BIT(CFG_RESET_SHIFT));
 542         iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
 543
 544         /* flush TX/RX FIFOs and set RX FIFO threshold to zero */
 545         val = (BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT));
 546         iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
 547         /* disable all interrupts */
 548         val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 549         val &= ~(IE_M_ALL_INTERRUPT_MASK <<
 550                         IE_M_ALL_INTERRUPT_SHIFT);
 551         iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
 552
 553         /* clear all pending interrupts */
 554         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, 0xffffffff);
 555
 556         return 0;
 557 }
 558
 559 static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c,
 560                                          bool enable)
 561 {
 562         u32 val;
 563
 564         val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
 565         if (enable)
 566                 val |= BIT(CFG_EN_SHIFT);
 567         else
 568                 val &= ~BIT(CFG_EN_SHIFT);
 569         iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
 570 }
 571
 572 static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c,
 573                                       struct i2c_msg *msg)
 574 {
 575         u32 val;
 576
 577         val = iproc_i2c_rd_reg(iproc_i2c, M_CMD_OFFSET);
 578         val = (val >> M_CMD_STATUS_SHIFT) & M_CMD_STATUS_MASK;
 579
 580         switch (val) {
 581         case M_CMD_STATUS_SUCCESS:
 582                 return 0;
 583
 584         case M_CMD_STATUS_LOST_ARB:
 585                 dev_dbg(iproc_i2c->device, "lost bus arbitration\n");
 586                 return -EAGAIN;
 587
 588         case M_CMD_STATUS_NACK_ADDR:
 589                 dev_dbg(iproc_i2c->device, "NAK addr:0x%02x\n", msg->addr);
 590                 return -ENXIO;
 591
 592         case M_CMD_STATUS_NACK_DATA:
 593                 dev_dbg(iproc_i2c->device, "NAK data\n");
 594                 return -ENXIO;
 595
 596         case M_CMD_STATUS_TIMEOUT:
 597                 dev_dbg(iproc_i2c->device, "bus timeout\n");
 598                 return -ETIMEDOUT;
 599
 600         case M_CMD_STATUS_FIFO_UNDERRUN:
 601                 dev_dbg(iproc_i2c->device, "FIFO under-run\n");
 602                 return -ENXIO;
 603
 604         case M_CMD_STATUS_RX_FIFO_FULL:
 605                 dev_dbg(iproc_i2c->device, "RX FIFO full\n");
 606                 return -ETIMEDOUT;
 607
 608         default:
 609                 dev_dbg(iproc_i2c->device, "unknown error code=%d\n", val);
 610
 611                 /* re-initialize i2c for recovery */
 612                 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
 613                 bcm_iproc_i2c_init(iproc_i2c);
 614                 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
 615
 616                 return -EIO;
 617         }
 618 }
 619
 620 static int bcm_iproc_i2c_xfer_wait(struct bcm_iproc_i2c_dev *iproc_i2c,
 621                                    struct i2c_msg *msg,
 622                                    u32 cmd)
 623 {
 624         unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT_MSEC);
 625         u32 val, status;
 626         int ret;
 627
 628         iproc_i2c_wr_reg(iproc_i2c, M_CMD_OFFSET, cmd);
 629
 630         if (iproc_i2c->irq) {
 631                 time_left = wait_for_completion_timeout(&iproc_i2c->done,
 632                                                         time_left);
 633                 /* disable all interrupts */
 634                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
 635                 /* read it back to flush the write */
 636                 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 637                 /* make sure the interrupt handler isn't running */
 638                 synchronize_irq(iproc_i2c->irq);
 639
 640         } else { /* polling mode */
 641                 unsigned long timeout = jiffies + time_left;
 642
 643                 do {
 644                         status = iproc_i2c_rd_reg(iproc_i2c,
 645                                                   IS_OFFSET) & ISR_MASK;
 646                         bcm_iproc_i2c_process_m_event(iproc_i2c, status);
 647                         iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
 648
 649                         if (time_after(jiffies, timeout)) {
 650                                 time_left = 0;
 651                                 break;
 652                         }
 653
 654                         cpu_relax();
 655                         cond_resched();
 656                 } while (!iproc_i2c->xfer_is_done);
 657         }
 658
 659         if (!time_left && !iproc_i2c->xfer_is_done) {
 660                 dev_err(iproc_i2c->device, "transaction timed out\n");
 661
 662                 /* flush both TX/RX FIFOs */
 663                 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
 664                 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
 665                 return -ETIMEDOUT;
 666         }
 667
 668         ret = bcm_iproc_i2c_check_status(iproc_i2c, msg);
 669         if (ret) {
 670                 /* flush both TX/RX FIFOs */
 671                 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
 672                 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
 673                 return ret;
 674         }
 675
 676         return 0;
 677 }
 678
 679 /*
 680  * If 'process_call' is true, then this is a multi-msg transfer that requires
 681  * a repeated start between the messages.
 682  * More specifically, it must be a write (reg) followed by a read (data).
 683  * The i2c quirks are set to enforce this rule.
 684  */
 685 static int bcm_iproc_i2c_xfer_internal(struct bcm_iproc_i2c_dev *iproc_i2c,
 686                                         struct i2c_msg *msgs, bool process_call)
 687 {
 688         int i;
 689         u8 addr;
 690         u32 val, tmp, val_intr_en;
 691         unsigned int tx_bytes;
 692         struct i2c_msg *msg = &msgs[0];
 693
 694         /* check if bus is busy */
 695         if (!!(iproc_i2c_rd_reg(iproc_i2c,
 696                                 M_CMD_OFFSET) & BIT(M_CMD_START_BUSY_SHIFT))) {
 697                 dev_warn(iproc_i2c->device, "bus is busy\n");
 698                 return -EBUSY;
 699         }
 700
 701         iproc_i2c->msg = msg;
 702
 703         /* format and load slave address into the TX FIFO */
 704         addr = i2c_8bit_addr_from_msg(msg);
 705         iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, addr);
 706
 707         /*
 708          * For a write transaction, load data into the TX FIFO. Only allow
 709          * loading up to TX FIFO size - 1 bytes of data since the first byte
 710          * has been used up by the slave address
 711          */
 712         tx_bytes = min_t(unsigned int, msg->len, M_TX_RX_FIFO_SIZE - 1);
 713         if (!(msg->flags & I2C_M_RD)) {
 714                 for (i = 0; i < tx_bytes; i++) {
 715                         val = msg->buf[i];
 716
 717                         /* mark the last byte */
 718                         if (!process_call && (i == msg->len - 1))
 719                                 val |= 1 << M_TX_WR_STATUS_SHIFT;
 720
 721                         iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
 722                 }
 723                 iproc_i2c->tx_bytes = tx_bytes;
 724         }
 725
 726         /* Process the read message if this is process call */
 727         if (process_call) {
 728                 msg++;
 729                 iproc_i2c->msg = msg;  /* point to second msg */
 730
 731                 /*
 732                  * The last byte to be sent out should be a slave
 733                  * address with read operation
 734                  */
 735                 addr = i2c_8bit_addr_from_msg(msg);
 736                 /* mark it the last byte out */
 737                 val = addr | (1 << M_TX_WR_STATUS_SHIFT);
 738                 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
 739         }
 740
 741         /* mark as incomplete before starting the transaction */
 742         if (iproc_i2c->irq)
 743                 reinit_completion(&iproc_i2c->done);
 744
 745         iproc_i2c->xfer_is_done = 0;
 746
 747         /*
 748          * Enable the "start busy" interrupt, which will be triggered after the
 749          * transaction is done, i.e., the internal start_busy bit, transitions
 750          * from 1 to 0.
 751          */
 752         val_intr_en = BIT(IE_M_START_BUSY_SHIFT);
 753
 754         /*
 755          * If TX data size is larger than the TX FIFO, need to enable TX
 756          * underrun interrupt, which will be triggerred when the TX FIFO is
 757          * empty. When that happens we can then pump more data into the FIFO
 758          */
 759         if (!process_call && !(msg->flags & I2C_M_RD) &&
 760             msg->len > iproc_i2c->tx_bytes)
 761                 val_intr_en |= BIT(IE_M_TX_UNDERRUN_SHIFT);
 762
 763         /*
 764          * Now we can activate the transfer. For a read operation, specify the
 765          * number of bytes to read
 766          */
 767         val = BIT(M_CMD_START_BUSY_SHIFT);
 768         if (msg->flags & I2C_M_RD) {
 769                 u32 protocol;
 770
 771                 iproc_i2c->rx_bytes = 0;
 772                 if (msg->len > M_RX_FIFO_MAX_THLD_VALUE)
 773                         iproc_i2c->thld_bytes = M_RX_FIFO_THLD_VALUE;
 774                 else
 775                         iproc_i2c->thld_bytes = msg->len;
 776
 777                 /* set threshold value */
 778                 tmp = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET);
 779                 tmp &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
 780                 tmp |= iproc_i2c->thld_bytes << M_FIFO_RX_THLD_SHIFT;
 781                 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, tmp);
 782
 783                 /* enable the RX threshold interrupt */
 784                 val_intr_en |= BIT(IE_M_RX_THLD_SHIFT);
 785
 786                 protocol = process_call ?
 787                                 M_CMD_PROTOCOL_PROCESS : M_CMD_PROTOCOL_BLK_RD;
 788
 789                 val |= (protocol << M_CMD_PROTOCOL_SHIFT) |
 790                        (msg->len << M_CMD_RD_CNT_SHIFT);
 791         } else {
 792                 val |= (M_CMD_PROTOCOL_BLK_WR << M_CMD_PROTOCOL_SHIFT);
 793         }
 794
 795         if (iproc_i2c->irq)
 796                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val_intr_en);
 797
 798         return bcm_iproc_i2c_xfer_wait(iproc_i2c, msg, val);
 799 }
 800
 801 static int bcm_iproc_i2c_xfer(struct i2c_adapter *adapter,
 802                               struct i2c_msg msgs[], int num)
 803 {
 804         struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(adapter);
 805         bool process_call = false;
 806         int ret;
 807
 808         if (num == 2) {
 809                 /* Repeated start, use process call */
 810                 process_call = true;
 811                 if (msgs[1].flags & I2C_M_NOSTART) {
 812                         dev_err(iproc_i2c->device, "Invalid repeated start\n");
 813                         return -EOPNOTSUPP;
 814                 }
 815         }
 816
 817         ret = bcm_iproc_i2c_xfer_internal(iproc_i2c, msgs, process_call);
 818         if (ret) {
 819                 dev_dbg(iproc_i2c->device, "xfer failed\n");
 820                 return ret;
 821         }
 822
 823         return num;
 824 }
 825
 826 static uint32_t bcm_iproc_i2c_functionality(struct i2c_adapter *adap)
 827 {
 828         u32 val;
 829
 830         /* We do not support the SMBUS Quick command */
 831         val = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 832
 833         if (adap->algo->reg_slave)
 834                 val |= I2C_FUNC_SLAVE;
 835
 836         return val;
 837 }
 838
 839 static struct i2c_algorithm bcm_iproc_algo = {
 840         .master_xfer = bcm_iproc_i2c_xfer,
 841         .functionality = bcm_iproc_i2c_functionality,
 842         .reg_slave = bcm_iproc_i2c_reg_slave,
 843         .unreg_slave = bcm_iproc_i2c_unreg_slave,
 844 };
 845
 846 static const struct i2c_adapter_quirks bcm_iproc_i2c_quirks = {
 847         .flags = I2C_AQ_COMB_WRITE_THEN_READ,
 848         .max_comb_1st_msg_len = M_TX_RX_FIFO_SIZE,
 849         .max_read_len = M_RX_MAX_READ_LEN,
 850 };
 851
 852 static int bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev *iproc_i2c)
 853 {
 854         unsigned int bus_speed;
 855         u32 val;
 856         int ret = of_property_read_u32(iproc_i2c->device->of_node,
 857                                        "clock-frequency", &bus_speed);
 858         if (ret < 0) {
 859                 dev_info(iproc_i2c->device,
 860                         "unable to interpret clock-frequency DT property\n");
 861                 bus_speed = 100000;
 862         }
 863
 864         if (bus_speed < 100000) {
 865                 dev_err(iproc_i2c->device, "%d Hz bus speed not supported\n",
 866                         bus_speed);
 867                 dev_err(iproc_i2c->device,
 868                         "valid speeds are 100khz and 400khz\n");
 869                 return -EINVAL;
 870         } else if (bus_speed < 400000) {
 871                 bus_speed = 100000;
 872         } else {
 873                 bus_speed = 400000;
 874         }
 875
 876         iproc_i2c->bus_speed = bus_speed;
 877         val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
 878         val &= ~BIT(TIM_CFG_MODE_400_SHIFT);
 879         val |= (bus_speed == 400000) << TIM_CFG_MODE_400_SHIFT;
 880         iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
 881
 882         dev_info(iproc_i2c->device, "bus set to %u Hz\n", bus_speed);
 883
 884         return 0;
 885 }
 886
 887 static int bcm_iproc_i2c_probe(struct platform_device *pdev)
 888 {
 889         int irq, ret = 0;
 890         struct bcm_iproc_i2c_dev *iproc_i2c;
 891         struct i2c_adapter *adap;
 892         struct resource *res;
 893
 894         iproc_i2c = devm_kzalloc(&pdev->dev, sizeof(*iproc_i2c),
 895                                  GFP_KERNEL);
 896         if (!iproc_i2c)
 897                 return -ENOMEM;
 898
 899         platform_set_drvdata(pdev, iproc_i2c);
 900         iproc_i2c->device = &pdev->dev;
 901         iproc_i2c->type =
 902                 (enum bcm_iproc_i2c_type)of_device_get_match_data(&pdev->dev);
 903         init_completion(&iproc_i2c->done);
 904
 905         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 906         iproc_i2c->base = devm_ioremap_resource(iproc_i2c->device, res);
 907         if (IS_ERR(iproc_i2c->base))
 908                 return PTR_ERR(iproc_i2c->base);
 909
 910         if (iproc_i2c->type == IPROC_I2C_NIC) {
 911                 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 912                 iproc_i2c->idm_base = devm_ioremap_resource(iproc_i2c->device,
 913                                                             res);
 914                 if (IS_ERR(iproc_i2c->idm_base))
 915                         return PTR_ERR(iproc_i2c->idm_base);
 916
 917                 ret = of_property_read_u32(iproc_i2c->device->of_node,
 918                                            "brcm,ape-hsls-addr-mask",
 919                                            &iproc_i2c->ape_addr_mask);
 920                 if (ret < 0) {
 921                         dev_err(iproc_i2c->device,
 922                                 "'brcm,ape-hsls-addr-mask' missing\n");
 923                         return -EINVAL;
 924                 }
 925
 926                 spin_lock_init(&iproc_i2c->idm_lock);
 927
 928                 /* no slave support */
 929                 bcm_iproc_algo.reg_slave = NULL;
 930                 bcm_iproc_algo.unreg_slave = NULL;
 931         }
 932
 933         ret = bcm_iproc_i2c_init(iproc_i2c);
 934         if (ret)
 935                 return ret;
 936
 937         ret = bcm_iproc_i2c_cfg_speed(iproc_i2c);
 938         if (ret)
 939                 return ret;
 940
 941         irq = platform_get_irq(pdev, 0);
 942         if (irq > 0) {
 943                 ret = devm_request_irq(iproc_i2c->device, irq,
 944                                        bcm_iproc_i2c_isr, 0, pdev->name,
 945                                        iproc_i2c);
 946                 if (ret < 0) {
 947                         dev_err(iproc_i2c->device,
 948                                 "unable to request irq %i\n", irq);
 949                         return ret;
 950                 }
 951
 952                 iproc_i2c->irq = irq;
 953         } else {
 954                 dev_warn(iproc_i2c->device,
 955                          "no irq resource, falling back to poll mode\n");
 956         }
 957
 958         bcm_iproc_i2c_enable_disable(iproc_i2c, true);
 959
 960         adap = &iproc_i2c->adapter;
 961         i2c_set_adapdata(adap, iproc_i2c);
 962         snprintf(adap->name, sizeof(adap->name),
 963                 "Broadcom iProc (%s)",
 964                 of_node_full_name(iproc_i2c->device->of_node));
 965         adap->algo = &bcm_iproc_algo;
 966         adap->quirks = &bcm_iproc_i2c_quirks;
 967         adap->dev.parent = &pdev->dev;
 968         adap->dev.of_node = pdev->dev.of_node;
 969
 970         return i2c_add_adapter(adap);
 971 }
 972
 973 static int bcm_iproc_i2c_remove(struct platform_device *pdev)
 974 {
 975         struct bcm_iproc_i2c_dev *iproc_i2c = platform_get_drvdata(pdev);
 976
 977         if (iproc_i2c->irq) {
 978                 /*
 979                  * Make sure there's no pending interrupt when we remove the
 980                  * adapter
 981                  */
 982                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
 983                 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
 984                 synchronize_irq(iproc_i2c->irq);
 985         }
 986
 987         i2c_del_adapter(&iproc_i2c->adapter);
 988         bcm_iproc_i2c_enable_disable(iproc_i2c, false);
 989
 990         return 0;
 991 }
 992
 993 #ifdef CONFIG_PM_SLEEP
 994
 995 static int bcm_iproc_i2c_suspend(struct device *dev)
 996 {
 997         struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev);
 998
 999         if (iproc_i2c->irq) {
1000                 /*
1001                  * Make sure there's no pending interrupt when we go into
1002                  * suspend
1003                  */
1004                 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
1005                 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
1006                 synchronize_irq(iproc_i2c->irq);
1007         }
1008
1009         /* now disable the controller */
1010         bcm_iproc_i2c_enable_disable(iproc_i2c, false);
1011
1012         return 0;
1013 }
1014
1015 static int bcm_iproc_i2c_resume(struct device *dev)
1016 {
1017         struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev);
1018         int ret;
1019         u32 val;
1020
1021         /*
1022          * Power domain could have been shut off completely in system deep
1023          * sleep, so re-initialize the block here
1024          */
1025         ret = bcm_iproc_i2c_init(iproc_i2c);
1026         if (ret)
1027                 return ret;
1028
1029         /* configure to the desired bus speed */
1030         val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
1031         val &= ~BIT(TIM_CFG_MODE_400_SHIFT);
1032         val |= (iproc_i2c->bus_speed == 400000) << TIM_CFG_MODE_400_SHIFT;
1033         iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
1034
1035         bcm_iproc_i2c_enable_disable(iproc_i2c, true);
1036
1037         return 0;
1038 }
1039
1040 static const struct dev_pm_ops bcm_iproc_i2c_pm_ops = {
1041         .suspend_late = &bcm_iproc_i2c_suspend,
1042         .resume_early = &bcm_iproc_i2c_resume
1043 };
1044
1045 #define BCM_IPROC_I2C_PM_OPS (&bcm_iproc_i2c_pm_ops)
1046 #else
1047 #define BCM_IPROC_I2C_PM_OPS NULL
1048 #endif /* CONFIG_PM_SLEEP */
1049
1050
1051 static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave)
1052 {
1053         struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter);
1054
1055         if (iproc_i2c->slave)
1056                 return -EBUSY;
1057
1058         if (slave->flags & I2C_CLIENT_TEN)
1059                 return -EAFNOSUPPORT;
1060
1061         iproc_i2c->slave = slave;
1062         bcm_iproc_i2c_slave_init(iproc_i2c, false);
1063         return 0;
1064 }
1065
1066 static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave)
1067 {
1068         u32 tmp;
1069         struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter);
1070
1071         if (!iproc_i2c->slave)
1072                 return -EINVAL;
1073
1074         iproc_i2c->slave = NULL;
1075
1076         /* disable all slave interrupts */
1077         tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
1078         tmp &= ~(IE_S_ALL_INTERRUPT_MASK <<
1079                         IE_S_ALL_INTERRUPT_SHIFT);
1080         iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, tmp);
1081
1082         /* Erase the slave address programmed */
1083         tmp = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET);
1084         tmp &= ~BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);
1085         iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, tmp);
1086
1087         return 0;
1088 }
1089
1090 static const struct of_device_id bcm_iproc_i2c_of_match[] = {
1091         {
1092                 .compatible = "brcm,iproc-i2c",
1093                 .data = (int *)IPROC_I2C,
1094         }, {
1095                 .compatible = "brcm,iproc-nic-i2c",
1096                 .data = (int *)IPROC_I2C_NIC,
1097         },
1098         { /* sentinel */ }
1099 };
1100 MODULE_DEVICE_TABLE(of, bcm_iproc_i2c_of_match);
1101
1102 static struct platform_driver bcm_iproc_i2c_driver = {
1103         .driver = {
1104                 .name = "bcm-iproc-i2c",
1105                 .of_match_table = bcm_iproc_i2c_of_match,
1106                 .pm = BCM_IPROC_I2C_PM_OPS,
1107         },
1108         .probe = bcm_iproc_i2c_probe,
1109         .remove = bcm_iproc_i2c_remove,
1110 };
1111 module_platform_driver(bcm_iproc_i2c_driver);
1112
1113 MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
1114 MODULE_DESCRIPTION("Broadcom iProc I2C Driver");
1115 MODULE_LICENSE("GPL v2");