1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
6 #ifndef _CORESIGHT_CORESIGHT_TPDA_H
7 #define _CORESIGHT_CORESIGHT_TPDA_H
9 #define TPDA_CR (0x000)
10 #define TPDA_Pn_CR(n) (0x004 + (n * 4))
11 /* Aggregator port enable bit */
12 #define TPDA_Pn_CR_ENA BIT(0)
13 /* Aggregator port CMB data set element size bit */
14 #define TPDA_Pn_CR_CMBSIZE GENMASK(7, 6)
15 /* Aggregator port DSB data set element size bit */
16 #define TPDA_Pn_CR_DSBSIZE BIT(8)
18 #define TPDA_MAX_INPORTS 32
20 /* Bits 6 ~ 12 is for atid value */
21 #define TPDA_CR_ATID GENMASK(12, 6)
24 * struct tpda_drvdata - specifics associated to an TPDA component
25 * @base: memory mapped base address for this component.
26 * @dev: The device entity associated to this component.
27 * @csdev: component vitals needed by the framework.
28 * @spinlock: lock for the drvdata value.
29 * @enable: enable status of the component.
30 * @dsb_esize Record the DSB element size.
31 * @cmb_esize Record the CMB element size.
36 struct coresight_device *csdev;
43 #endif /* _CORESIGHT_CORESIGHT_TPDA_H */