drivers/hwtracing/coresight/coresight-tmc-core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright (c) 2012, The Linux Foundation. All rights reserved.
   3  *
   4  * Description: CoreSight Trace Memory Controller driver
   5  */
   6
   7 #include <linux/kernel.h>
   8 #include <linux/init.h>
   9 #include <linux/types.h>
  10 #include <linux/device.h>
  11 #include <linux/idr.h>
  12 #include <linux/io.h>
  13 #include <linux/err.h>
  14 #include <linux/fs.h>
  15 #include <linux/miscdevice.h>
  16 #include <linux/mutex.h>
  17 #include <linux/property.h>
  18 #include <linux/uaccess.h>
  19 #include <linux/slab.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/pm_runtime.h>
  23 #include <linux/of.h>
  24 #include <linux/coresight.h>
  25 #include <linux/amba/bus.h>
  26
  27 #include "coresight-priv.h"
  28 #include "coresight-tmc.h"
  29
  30 DEFINE_CORESIGHT_DEVLIST(etb_devs, "tmc_etb");
  31 DEFINE_CORESIGHT_DEVLIST(etf_devs, "tmc_etf");
  32 DEFINE_CORESIGHT_DEVLIST(etr_devs, "tmc_etr");
  33
  34 int tmc_wait_for_tmcready(struct tmc_drvdata *drvdata)
  35 {
  36         struct coresight_device *csdev = drvdata->csdev;
  37         struct csdev_access *csa = &csdev->access;
  38
  39         /* Ensure formatter, unformatter and hardware fifo are empty */
  40         if (coresight_timeout(csa, TMC_STS, TMC_STS_TMCREADY_BIT, 1)) {
  41                 dev_err(&csdev->dev,
  42                         "timeout while waiting for TMC to be Ready\n");
  43                 return -EBUSY;
  44         }
  45         return 0;
  46 }
  47
  48 void tmc_flush_and_stop(struct tmc_drvdata *drvdata)
  49 {
  50         struct coresight_device *csdev = drvdata->csdev;
  51         struct csdev_access *csa = &csdev->access;
  52         u32 ffcr;
  53
  54         ffcr = readl_relaxed(drvdata->base + TMC_FFCR);
  55         ffcr |= TMC_FFCR_STOP_ON_FLUSH;
  56         writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
  57         ffcr |= BIT(TMC_FFCR_FLUSHMAN_BIT);
  58         writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
  59         /* Ensure flush completes */
  60         if (coresight_timeout(csa, TMC_FFCR, TMC_FFCR_FLUSHMAN_BIT, 0)) {
  61                 dev_err(&csdev->dev,
  62                 "timeout while waiting for completion of Manual Flush\n");
  63         }
  64
  65         tmc_wait_for_tmcready(drvdata);
  66 }
  67
  68 void tmc_enable_hw(struct tmc_drvdata *drvdata)
  69 {
  70         writel_relaxed(TMC_CTL_CAPT_EN, drvdata->base + TMC_CTL);
  71 }
  72
  73 void tmc_disable_hw(struct tmc_drvdata *drvdata)
  74 {
  75         writel_relaxed(0x0, drvdata->base + TMC_CTL);
  76 }
  77
  78 u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata)
  79 {
  80         u32 mask = 0;
  81
  82         /*
  83          * When moving RRP or an offset address forward, the new values must
  84          * be byte-address aligned to the width of the trace memory databus
  85          * _and_ to a frame boundary (16 byte), whichever is the biggest. For
  86          * example, for 32-bit, 64-bit and 128-bit wide trace memory, the four
  87          * LSBs must be 0s. For 256-bit wide trace memory, the five LSBs must
  88          * be 0s.
  89          */
  90         switch (drvdata->memwidth) {
  91         case TMC_MEM_INTF_WIDTH_32BITS:
  92         case TMC_MEM_INTF_WIDTH_64BITS:
  93         case TMC_MEM_INTF_WIDTH_128BITS:
  94                 mask = GENMASK(31, 4);
  95                 break;
  96         case TMC_MEM_INTF_WIDTH_256BITS:
  97                 mask = GENMASK(31, 5);
  98                 break;
  99         }
 100
 101         return mask;
 102 }
 103
 104 static int tmc_read_prepare(struct tmc_drvdata *drvdata)
 105 {
 106         int ret = 0;
 107
 108         switch (drvdata->config_type) {
 109         case TMC_CONFIG_TYPE_ETB:
 110         case TMC_CONFIG_TYPE_ETF:
 111                 ret = tmc_read_prepare_etb(drvdata);
 112                 break;
 113         case TMC_CONFIG_TYPE_ETR:
 114                 ret = tmc_read_prepare_etr(drvdata);
 115                 break;
 116         default:
 117                 ret = -EINVAL;
 118         }
 119
 120         if (!ret)
 121                 dev_dbg(&drvdata->csdev->dev, "TMC read start\n");
 122
 123         return ret;
 124 }
 125
 126 static int tmc_read_unprepare(struct tmc_drvdata *drvdata)
 127 {
 128         int ret = 0;
 129
 130         switch (drvdata->config_type) {
 131         case TMC_CONFIG_TYPE_ETB:
 132         case TMC_CONFIG_TYPE_ETF:
 133                 ret = tmc_read_unprepare_etb(drvdata);
 134                 break;
 135         case TMC_CONFIG_TYPE_ETR:
 136                 ret = tmc_read_unprepare_etr(drvdata);
 137                 break;
 138         default:
 139                 ret = -EINVAL;
 140         }
 141
 142         if (!ret)
 143                 dev_dbg(&drvdata->csdev->dev, "TMC read end\n");
 144
 145         return ret;
 146 }
 147
 148 static int tmc_open(struct inode *inode, struct file *file)
 149 {
 150         int ret;
 151         struct tmc_drvdata *drvdata = container_of(file->private_data,
 152                                                    struct tmc_drvdata, miscdev);
 153
 154         ret = tmc_read_prepare(drvdata);
 155         if (ret)
 156                 return ret;
 157
 158         nonseekable_open(inode, file);
 159
 160         dev_dbg(&drvdata->csdev->dev, "%s: successfully opened\n", __func__);
 161         return 0;
 162 }
 163
 164 static inline ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata,
 165                                           loff_t pos, size_t len, char **bufpp)
 166 {
 167         switch (drvdata->config_type) {
 168         case TMC_CONFIG_TYPE_ETB:
 169         case TMC_CONFIG_TYPE_ETF:
 170                 return tmc_etb_get_sysfs_trace(drvdata, pos, len, bufpp);
 171         case TMC_CONFIG_TYPE_ETR:
 172                 return tmc_etr_get_sysfs_trace(drvdata, pos, len, bufpp);
 173         }
 174
 175         return -EINVAL;
 176 }
 177
 178 static ssize_t tmc_read(struct file *file, char __user *data, size_t len,
 179                         loff_t *ppos)
 180 {
 181         char *bufp;
 182         ssize_t actual;
 183         struct tmc_drvdata *drvdata = container_of(file->private_data,
 184                                                    struct tmc_drvdata, miscdev);
 185         actual = tmc_get_sysfs_trace(drvdata, *ppos, len, &bufp);
 186         if (actual <= 0)
 187                 return 0;
 188
 189         if (copy_to_user(data, bufp, actual)) {
 190                 dev_dbg(&drvdata->csdev->dev,
 191                         "%s: copy_to_user failed\n", __func__);
 192                 return -EFAULT;
 193         }
 194
 195         *ppos += actual;
 196         dev_dbg(&drvdata->csdev->dev, "%zu bytes copied\n", actual);
 197
 198         return actual;
 199 }
 200
 201 static int tmc_release(struct inode *inode, struct file *file)
 202 {
 203         int ret;
 204         struct tmc_drvdata *drvdata = container_of(file->private_data,
 205                                                    struct tmc_drvdata, miscdev);
 206
 207         ret = tmc_read_unprepare(drvdata);
 208         if (ret)
 209                 return ret;
 210
 211         dev_dbg(&drvdata->csdev->dev, "%s: released\n", __func__);
 212         return 0;
 213 }
 214
 215 static const struct file_operations tmc_fops = {
 216         .owner          = THIS_MODULE,
 217         .open           = tmc_open,
 218         .read           = tmc_read,
 219         .release        = tmc_release,
 220         .llseek         = no_llseek,
 221 };
 222
 223 static enum tmc_mem_intf_width tmc_get_memwidth(u32 devid)
 224 {
 225         enum tmc_mem_intf_width memwidth;
 226
 227         /*
 228          * Excerpt from the TRM:
 229          *
 230          * DEVID::MEMWIDTH[10:8]
 231          * 0x2 Memory interface databus is 32 bits wide.
 232          * 0x3 Memory interface databus is 64 bits wide.
 233          * 0x4 Memory interface databus is 128 bits wide.
 234          * 0x5 Memory interface databus is 256 bits wide.
 235          */
 236         switch (BMVAL(devid, 8, 10)) {
 237         case 0x2:
 238                 memwidth = TMC_MEM_INTF_WIDTH_32BITS;
 239                 break;
 240         case 0x3:
 241                 memwidth = TMC_MEM_INTF_WIDTH_64BITS;
 242                 break;
 243         case 0x4:
 244                 memwidth = TMC_MEM_INTF_WIDTH_128BITS;
 245                 break;
 246         case 0x5:
 247                 memwidth = TMC_MEM_INTF_WIDTH_256BITS;
 248                 break;
 249         default:
 250                 memwidth = 0;
 251         }
 252
 253         return memwidth;
 254 }
 255
 256 static struct attribute *coresight_tmc_mgmt_attrs[] = {
 257         coresight_simple_reg32(rsz, TMC_RSZ),
 258         coresight_simple_reg32(sts, TMC_STS),
 259         coresight_simple_reg64(rrp, TMC_RRP, TMC_RRPHI),
 260         coresight_simple_reg64(rwp, TMC_RWP, TMC_RWPHI),
 261         coresight_simple_reg32(trg, TMC_TRG),
 262         coresight_simple_reg32(ctl, TMC_CTL),
 263         coresight_simple_reg32(ffsr, TMC_FFSR),
 264         coresight_simple_reg32(ffcr, TMC_FFCR),
 265         coresight_simple_reg32(mode, TMC_MODE),
 266         coresight_simple_reg32(pscr, TMC_PSCR),
 267         coresight_simple_reg32(devid, CORESIGHT_DEVID),
 268         coresight_simple_reg64(dba, TMC_DBALO, TMC_DBAHI),
 269         coresight_simple_reg32(axictl, TMC_AXICTL),
 270         coresight_simple_reg32(authstatus, TMC_AUTHSTATUS),
 271         NULL,
 272 };
 273
 274 static ssize_t trigger_cntr_show(struct device *dev,
 275                                  struct device_attribute *attr, char *buf)
 276 {
 277         struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
 278         unsigned long val = drvdata->trigger_cntr;
 279
 280         return sprintf(buf, "%#lx\n", val);
 281 }
 282
 283 static ssize_t trigger_cntr_store(struct device *dev,
 284                              struct device_attribute *attr,
 285                              const char *buf, size_t size)
 286 {
 287         int ret;
 288         unsigned long val;
 289         struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
 290
 291         ret = kstrtoul(buf, 16, &val);
 292         if (ret)
 293                 return ret;
 294
 295         drvdata->trigger_cntr = val;
 296         return size;
 297 }
 298 static DEVICE_ATTR_RW(trigger_cntr);
 299
 300 static ssize_t buffer_size_show(struct device *dev,
 301                                 struct device_attribute *attr, char *buf)
 302 {
 303         struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
 304
 305         return sprintf(buf, "%#x\n", drvdata->size);
 306 }
 307
 308 static ssize_t buffer_size_store(struct device *dev,
 309                                  struct device_attribute *attr,
 310                                  const char *buf, size_t size)
 311 {
 312         int ret;
 313         unsigned long val;
 314         struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
 315
 316         /* Only permitted for TMC-ETRs */
 317         if (drvdata->config_type != TMC_CONFIG_TYPE_ETR)
 318                 return -EPERM;
 319
 320         ret = kstrtoul(buf, 0, &val);
 321         if (ret)
 322                 return ret;
 323         /* The buffer size should be page aligned */
 324         if (val & (PAGE_SIZE - 1))
 325                 return -EINVAL;
 326         drvdata->size = val;
 327         return size;
 328 }
 329
 330 static DEVICE_ATTR_RW(buffer_size);
 331
 332 static struct attribute *coresight_tmc_attrs[] = {
 333         &dev_attr_trigger_cntr.attr,
 334         &dev_attr_buffer_size.attr,
 335         NULL,
 336 };
 337
 338 static const struct attribute_group coresight_tmc_group = {
 339         .attrs = coresight_tmc_attrs,
 340 };
 341
 342 static const struct attribute_group coresight_tmc_mgmt_group = {
 343         .attrs = coresight_tmc_mgmt_attrs,
 344         .name = "mgmt",
 345 };
 346
 347 static const struct attribute_group *coresight_tmc_groups[] = {
 348         &coresight_tmc_group,
 349         &coresight_tmc_mgmt_group,
 350         NULL,
 351 };
 352
 353 static inline bool tmc_etr_can_use_sg(struct device *dev)
 354 {
 355         return fwnode_property_present(dev->fwnode, "arm,scatter-gather");
 356 }
 357
 358 static inline bool tmc_etr_has_non_secure_access(struct tmc_drvdata *drvdata)
 359 {
 360         u32 auth = readl_relaxed(drvdata->base + TMC_AUTHSTATUS);
 361
 362         return (auth & TMC_AUTH_NSID_MASK) == 0x3;
 363 }
 364
 365 /* Detect and initialise the capabilities of a TMC ETR */
 366 static int tmc_etr_setup_caps(struct device *parent, u32 devid, void *dev_caps)
 367 {
 368         int rc;
 369         u32 dma_mask = 0;
 370         struct tmc_drvdata *drvdata = dev_get_drvdata(parent);
 371
 372         if (!tmc_etr_has_non_secure_access(drvdata))
 373                 return -EACCES;
 374
 375         /* Set the unadvertised capabilities */
 376         tmc_etr_init_caps(drvdata, (u32)(unsigned long)dev_caps);
 377
 378         if (!(devid & TMC_DEVID_NOSCAT) && tmc_etr_can_use_sg(parent))
 379                 tmc_etr_set_cap(drvdata, TMC_ETR_SG);
 380
 381         /* Check if the AXI address width is available */
 382         if (devid & TMC_DEVID_AXIAW_VALID)
 383                 dma_mask = ((devid >> TMC_DEVID_AXIAW_SHIFT) &
 384                                 TMC_DEVID_AXIAW_MASK);
 385
 386         /*
 387          * Unless specified in the device configuration, ETR uses a 40-bit
 388          * AXI master in place of the embedded SRAM of ETB/ETF.
 389          */
 390         switch (dma_mask) {
 391         case 32:
 392         case 40:
 393         case 44:
 394         case 48:
 395         case 52:
 396                 dev_info(parent, "Detected dma mask %dbits\n", dma_mask);
 397                 break;
 398         default:
 399                 dma_mask = 40;
 400         }
 401
 402         rc = dma_set_mask_and_coherent(parent, DMA_BIT_MASK(dma_mask));
 403         if (rc)
 404                 dev_err(parent, "Failed to setup DMA mask: %d\n", rc);
 405         return rc;
 406 }
 407
 408 static u32 tmc_etr_get_default_buffer_size(struct device *dev)
 409 {
 410         u32 size;
 411
 412         if (fwnode_property_read_u32(dev->fwnode, "arm,buffer-size", &size))
 413                 size = SZ_1M;
 414         return size;
 415 }
 416
 417 static u32 tmc_etr_get_max_burst_size(struct device *dev)
 418 {
 419         u32 burst_size;
 420
 421         if (fwnode_property_read_u32(dev->fwnode, "arm,max-burst-size",
 422                                      &burst_size))
 423                 return TMC_AXICTL_WR_BURST_16;
 424
 425         /* Only permissible values are 0 to 15 */
 426         if (burst_size > 0xF)
 427                 burst_size = TMC_AXICTL_WR_BURST_16;
 428
 429         return burst_size;
 430 }
 431
 432 static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
 433 {
 434         int ret = 0;
 435         u32 devid;
 436         void __iomem *base;
 437         struct device *dev = &adev->dev;
 438         struct coresight_platform_data *pdata = NULL;
 439         struct tmc_drvdata *drvdata;
 440         struct resource *res = &adev->res;
 441         struct coresight_desc desc = { 0 };
 442         struct coresight_dev_list *dev_list = NULL;
 443
 444         ret = -ENOMEM;
 445         drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
 446         if (!drvdata)
 447                 goto out;
 448
 449         dev_set_drvdata(dev, drvdata);
 450
 451         /* Validity for the resource is already checked by the AMBA core */
 452         base = devm_ioremap_resource(dev, res);
 453         if (IS_ERR(base)) {
 454                 ret = PTR_ERR(base);
 455                 goto out;
 456         }
 457
 458         drvdata->base = base;
 459         desc.access = CSDEV_ACCESS_IOMEM(base);
 460
 461         spin_lock_init(&drvdata->spinlock);
 462
 463         devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
 464         drvdata->config_type = BMVAL(devid, 6, 7);
 465         drvdata->memwidth = tmc_get_memwidth(devid);
 466         /* This device is not associated with a session */
 467         drvdata->pid = -1;
 468
 469         if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
 470                 drvdata->size = tmc_etr_get_default_buffer_size(dev);
 471                 drvdata->max_burst_size = tmc_etr_get_max_burst_size(dev);
 472         } else {
 473                 drvdata->size = readl_relaxed(drvdata->base + TMC_RSZ) * 4;
 474         }
 475
 476         desc.dev = dev;
 477         desc.groups = coresight_tmc_groups;
 478
 479         switch (drvdata->config_type) {
 480         case TMC_CONFIG_TYPE_ETB:
 481                 desc.type = CORESIGHT_DEV_TYPE_SINK;
 482                 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
 483                 desc.ops = &tmc_etb_cs_ops;
 484                 dev_list = &etb_devs;
 485                 break;
 486         case TMC_CONFIG_TYPE_ETR:
 487                 desc.type = CORESIGHT_DEV_TYPE_SINK;
 488                 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM;
 489                 desc.ops = &tmc_etr_cs_ops;
 490                 ret = tmc_etr_setup_caps(dev, devid,
 491                                          coresight_get_uci_data(id));
 492                 if (ret)
 493                         goto out;
 494                 idr_init(&drvdata->idr);
 495                 mutex_init(&drvdata->idr_mutex);
 496                 dev_list = &etr_devs;
 497                 break;
 498         case TMC_CONFIG_TYPE_ETF:
 499                 desc.type = CORESIGHT_DEV_TYPE_LINKSINK;
 500                 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
 501                 desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO;
 502                 desc.ops = &tmc_etf_cs_ops;
 503                 dev_list = &etf_devs;
 504                 break;
 505         default:
 506                 pr_err("%s: Unsupported TMC config\n", desc.name);
 507                 ret = -EINVAL;
 508                 goto out;
 509         }
 510
 511         desc.name = coresight_alloc_device_name(dev_list, dev);
 512         if (!desc.name) {
 513                 ret = -ENOMEM;
 514                 goto out;
 515         }
 516
 517         pdata = coresight_get_platform_data(dev);
 518         if (IS_ERR(pdata)) {
 519                 ret = PTR_ERR(pdata);
 520                 goto out;
 521         }
 522         adev->dev.platform_data = pdata;
 523         desc.pdata = pdata;
 524
 525         drvdata->csdev = coresight_register(&desc);
 526         if (IS_ERR(drvdata->csdev)) {
 527                 ret = PTR_ERR(drvdata->csdev);
 528                 goto out;
 529         }
 530
 531         drvdata->miscdev.name = desc.name;
 532         drvdata->miscdev.minor = MISC_DYNAMIC_MINOR;
 533         drvdata->miscdev.fops = &tmc_fops;
 534         ret = misc_register(&drvdata->miscdev);
 535         if (ret)
 536                 coresight_unregister(drvdata->csdev);
 537         else
 538                 pm_runtime_put(&adev->dev);
 539 out:
 540         return ret;
 541 }
 542
 543 static void tmc_shutdown(struct amba_device *adev)
 544 {
 545         unsigned long flags;
 546         struct tmc_drvdata *drvdata = amba_get_drvdata(adev);
 547
 548         spin_lock_irqsave(&drvdata->spinlock, flags);
 549
 550         if (drvdata->mode == CS_MODE_DISABLED)
 551                 goto out;
 552
 553         if (drvdata->config_type == TMC_CONFIG_TYPE_ETR)
 554                 tmc_etr_disable_hw(drvdata);
 555
 556         /*
 557          * We do not care about coresight unregister here unlike remove
 558          * callback which is required for making coresight modular since
 559          * the system is going down after this.
 560          */
 561 out:
 562         spin_unlock_irqrestore(&drvdata->spinlock, flags);
 563 }
 564
 565 static void tmc_remove(struct amba_device *adev)
 566 {
 567         struct tmc_drvdata *drvdata = dev_get_drvdata(&adev->dev);
 568
 569         /*
 570          * Since misc_open() holds a refcount on the f_ops, which is
 571          * etb fops in this case, device is there until last file
 572          * handler to this device is closed.
 573          */
 574         misc_deregister(&drvdata->miscdev);
 575         coresight_unregister(drvdata->csdev);
 576 }
 577
 578 static const struct amba_id tmc_ids[] = {
 579         CS_AMBA_ID(0x000bb961),
 580         /* Coresight SoC 600 TMC-ETR/ETS */
 581         CS_AMBA_ID_DATA(0x000bb9e8, (unsigned long)CORESIGHT_SOC_600_ETR_CAPS),
 582         /* Coresight SoC 600 TMC-ETB */
 583         CS_AMBA_ID(0x000bb9e9),
 584         /* Coresight SoC 600 TMC-ETF */
 585         CS_AMBA_ID(0x000bb9ea),
 586         { 0, 0},
 587 };
 588
 589 MODULE_DEVICE_TABLE(amba, tmc_ids);
 590
 591 static struct amba_driver tmc_driver = {
 592         .drv = {
 593                 .name   = "coresight-tmc",
 594                 .owner  = THIS_MODULE,
 595                 .suppress_bind_attrs = true,
 596         },
 597         .probe          = tmc_probe,
 598         .shutdown       = tmc_shutdown,
 599         .remove         = tmc_remove,
 600         .id_table       = tmc_ids,
 601 };
 602
 603 module_amba_driver(tmc_driver);
 604
 605 MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
 606 MODULE_DESCRIPTION("Arm CoreSight Trace Memory Controller driver");
 607 MODULE_LICENSE("GPL v2");