1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2012, The Linux Foundation. All rights reserved.
4 * Description: CoreSight Trace Memory Controller driver
7 #include <linux/kernel.h>
8 #include <linux/init.h>
9 #include <linux/types.h>
10 #include <linux/device.h>
11 #include <linux/idr.h>
13 #include <linux/iommu.h>
14 #include <linux/err.h>
16 #include <linux/miscdevice.h>
17 #include <linux/mutex.h>
18 #include <linux/property.h>
19 #include <linux/uaccess.h>
20 #include <linux/slab.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/spinlock.h>
23 #include <linux/pm_runtime.h>
25 #include <linux/coresight.h>
26 #include <linux/amba/bus.h>
28 #include "coresight-priv.h"
29 #include "coresight-tmc.h"
31 DEFINE_CORESIGHT_DEVLIST(etb_devs, "tmc_etb");
32 DEFINE_CORESIGHT_DEVLIST(etf_devs, "tmc_etf");
33 DEFINE_CORESIGHT_DEVLIST(etr_devs, "tmc_etr");
35 int tmc_wait_for_tmcready(struct tmc_drvdata *drvdata)
37 struct coresight_device *csdev = drvdata->csdev;
38 struct csdev_access *csa = &csdev->access;
40 /* Ensure formatter, unformatter and hardware fifo are empty */
41 if (coresight_timeout(csa, TMC_STS, TMC_STS_TMCREADY_BIT, 1)) {
43 "timeout while waiting for TMC to be Ready\n");
49 void tmc_flush_and_stop(struct tmc_drvdata *drvdata)
51 struct coresight_device *csdev = drvdata->csdev;
52 struct csdev_access *csa = &csdev->access;
55 ffcr = readl_relaxed(drvdata->base + TMC_FFCR);
56 ffcr |= TMC_FFCR_STOP_ON_FLUSH;
57 writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
58 ffcr |= BIT(TMC_FFCR_FLUSHMAN_BIT);
59 writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
60 /* Ensure flush completes */
61 if (coresight_timeout(csa, TMC_FFCR, TMC_FFCR_FLUSHMAN_BIT, 0)) {
63 "timeout while waiting for completion of Manual Flush\n");
66 tmc_wait_for_tmcready(drvdata);
69 void tmc_enable_hw(struct tmc_drvdata *drvdata)
71 writel_relaxed(TMC_CTL_CAPT_EN, drvdata->base + TMC_CTL);
74 void tmc_disable_hw(struct tmc_drvdata *drvdata)
76 writel_relaxed(0x0, drvdata->base + TMC_CTL);
79 u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata)
84 * When moving RRP or an offset address forward, the new values must
85 * be byte-address aligned to the width of the trace memory databus
86 * _and_ to a frame boundary (16 byte), whichever is the biggest. For
87 * example, for 32-bit, 64-bit and 128-bit wide trace memory, the four
88 * LSBs must be 0s. For 256-bit wide trace memory, the five LSBs must
91 switch (drvdata->memwidth) {
92 case TMC_MEM_INTF_WIDTH_32BITS:
93 case TMC_MEM_INTF_WIDTH_64BITS:
94 case TMC_MEM_INTF_WIDTH_128BITS:
95 mask = GENMASK(31, 4);
97 case TMC_MEM_INTF_WIDTH_256BITS:
98 mask = GENMASK(31, 5);
105 static int tmc_read_prepare(struct tmc_drvdata *drvdata)
109 switch (drvdata->config_type) {
110 case TMC_CONFIG_TYPE_ETB:
111 case TMC_CONFIG_TYPE_ETF:
112 ret = tmc_read_prepare_etb(drvdata);
114 case TMC_CONFIG_TYPE_ETR:
115 ret = tmc_read_prepare_etr(drvdata);
122 dev_dbg(&drvdata->csdev->dev, "TMC read start\n");
127 static int tmc_read_unprepare(struct tmc_drvdata *drvdata)
131 switch (drvdata->config_type) {
132 case TMC_CONFIG_TYPE_ETB:
133 case TMC_CONFIG_TYPE_ETF:
134 ret = tmc_read_unprepare_etb(drvdata);
136 case TMC_CONFIG_TYPE_ETR:
137 ret = tmc_read_unprepare_etr(drvdata);
144 dev_dbg(&drvdata->csdev->dev, "TMC read end\n");
149 static int tmc_open(struct inode *inode, struct file *file)
152 struct tmc_drvdata *drvdata = container_of(file->private_data,
153 struct tmc_drvdata, miscdev);
155 ret = tmc_read_prepare(drvdata);
159 nonseekable_open(inode, file);
161 dev_dbg(&drvdata->csdev->dev, "%s: successfully opened\n", __func__);
165 static inline ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata,
166 loff_t pos, size_t len, char **bufpp)
168 switch (drvdata->config_type) {
169 case TMC_CONFIG_TYPE_ETB:
170 case TMC_CONFIG_TYPE_ETF:
171 return tmc_etb_get_sysfs_trace(drvdata, pos, len, bufpp);
172 case TMC_CONFIG_TYPE_ETR:
173 return tmc_etr_get_sysfs_trace(drvdata, pos, len, bufpp);
179 static ssize_t tmc_read(struct file *file, char __user *data, size_t len,
184 struct tmc_drvdata *drvdata = container_of(file->private_data,
185 struct tmc_drvdata, miscdev);
186 actual = tmc_get_sysfs_trace(drvdata, *ppos, len, &bufp);
190 if (copy_to_user(data, bufp, actual)) {
191 dev_dbg(&drvdata->csdev->dev,
192 "%s: copy_to_user failed\n", __func__);
197 dev_dbg(&drvdata->csdev->dev, "%zu bytes copied\n", actual);
202 static int tmc_release(struct inode *inode, struct file *file)
205 struct tmc_drvdata *drvdata = container_of(file->private_data,
206 struct tmc_drvdata, miscdev);
208 ret = tmc_read_unprepare(drvdata);
212 dev_dbg(&drvdata->csdev->dev, "%s: released\n", __func__);
216 static const struct file_operations tmc_fops = {
217 .owner = THIS_MODULE,
220 .release = tmc_release,
224 static enum tmc_mem_intf_width tmc_get_memwidth(u32 devid)
226 enum tmc_mem_intf_width memwidth;
229 * Excerpt from the TRM:
231 * DEVID::MEMWIDTH[10:8]
232 * 0x2 Memory interface databus is 32 bits wide.
233 * 0x3 Memory interface databus is 64 bits wide.
234 * 0x4 Memory interface databus is 128 bits wide.
235 * 0x5 Memory interface databus is 256 bits wide.
237 switch (BMVAL(devid, 8, 10)) {
239 memwidth = TMC_MEM_INTF_WIDTH_32BITS;
242 memwidth = TMC_MEM_INTF_WIDTH_64BITS;
245 memwidth = TMC_MEM_INTF_WIDTH_128BITS;
248 memwidth = TMC_MEM_INTF_WIDTH_256BITS;
257 static struct attribute *coresight_tmc_mgmt_attrs[] = {
258 coresight_simple_reg32(rsz, TMC_RSZ),
259 coresight_simple_reg32(sts, TMC_STS),
260 coresight_simple_reg64(rrp, TMC_RRP, TMC_RRPHI),
261 coresight_simple_reg64(rwp, TMC_RWP, TMC_RWPHI),
262 coresight_simple_reg32(trg, TMC_TRG),
263 coresight_simple_reg32(ctl, TMC_CTL),
264 coresight_simple_reg32(ffsr, TMC_FFSR),
265 coresight_simple_reg32(ffcr, TMC_FFCR),
266 coresight_simple_reg32(mode, TMC_MODE),
267 coresight_simple_reg32(pscr, TMC_PSCR),
268 coresight_simple_reg32(devid, CORESIGHT_DEVID),
269 coresight_simple_reg64(dba, TMC_DBALO, TMC_DBAHI),
270 coresight_simple_reg32(axictl, TMC_AXICTL),
271 coresight_simple_reg32(authstatus, TMC_AUTHSTATUS),
275 static ssize_t trigger_cntr_show(struct device *dev,
276 struct device_attribute *attr, char *buf)
278 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
279 unsigned long val = drvdata->trigger_cntr;
281 return sprintf(buf, "%#lx\n", val);
284 static ssize_t trigger_cntr_store(struct device *dev,
285 struct device_attribute *attr,
286 const char *buf, size_t size)
290 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
292 ret = kstrtoul(buf, 16, &val);
296 drvdata->trigger_cntr = val;
299 static DEVICE_ATTR_RW(trigger_cntr);
301 static ssize_t buffer_size_show(struct device *dev,
302 struct device_attribute *attr, char *buf)
304 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
306 return sprintf(buf, "%#x\n", drvdata->size);
309 static ssize_t buffer_size_store(struct device *dev,
310 struct device_attribute *attr,
311 const char *buf, size_t size)
315 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
317 /* Only permitted for TMC-ETRs */
318 if (drvdata->config_type != TMC_CONFIG_TYPE_ETR)
321 ret = kstrtoul(buf, 0, &val);
324 /* The buffer size should be page aligned */
325 if (val & (PAGE_SIZE - 1))
331 static DEVICE_ATTR_RW(buffer_size);
333 static struct attribute *coresight_tmc_attrs[] = {
334 &dev_attr_trigger_cntr.attr,
335 &dev_attr_buffer_size.attr,
339 static const struct attribute_group coresight_tmc_group = {
340 .attrs = coresight_tmc_attrs,
343 static const struct attribute_group coresight_tmc_mgmt_group = {
344 .attrs = coresight_tmc_mgmt_attrs,
348 static const struct attribute_group *coresight_etf_groups[] = {
349 &coresight_tmc_group,
350 &coresight_tmc_mgmt_group,
354 static const struct attribute_group *coresight_etr_groups[] = {
355 &coresight_etr_group,
356 &coresight_tmc_group,
357 &coresight_tmc_mgmt_group,
361 static inline bool tmc_etr_can_use_sg(struct device *dev)
363 return fwnode_property_present(dev->fwnode, "arm,scatter-gather");
366 static inline bool tmc_etr_has_non_secure_access(struct tmc_drvdata *drvdata)
368 u32 auth = readl_relaxed(drvdata->base + TMC_AUTHSTATUS);
370 return (auth & TMC_AUTH_NSID_MASK) == 0x3;
373 /* Detect and initialise the capabilities of a TMC ETR */
374 static int tmc_etr_setup_caps(struct device *parent, u32 devid, void *dev_caps)
378 struct tmc_drvdata *drvdata = dev_get_drvdata(parent);
380 if (!tmc_etr_has_non_secure_access(drvdata))
383 /* Set the unadvertised capabilities */
384 tmc_etr_init_caps(drvdata, (u32)(unsigned long)dev_caps);
386 if (!(devid & TMC_DEVID_NOSCAT) && tmc_etr_can_use_sg(parent))
387 tmc_etr_set_cap(drvdata, TMC_ETR_SG);
389 /* Check if the AXI address width is available */
390 if (devid & TMC_DEVID_AXIAW_VALID)
391 dma_mask = ((devid >> TMC_DEVID_AXIAW_SHIFT) &
392 TMC_DEVID_AXIAW_MASK);
395 * Unless specified in the device configuration, ETR uses a 40-bit
396 * AXI master in place of the embedded SRAM of ETB/ETF.
404 dev_info(parent, "Detected dma mask %dbits\n", dma_mask);
410 rc = dma_set_mask_and_coherent(parent, DMA_BIT_MASK(dma_mask));
412 dev_err(parent, "Failed to setup DMA mask: %d\n", rc);
416 static u32 tmc_etr_get_default_buffer_size(struct device *dev)
420 if (fwnode_property_read_u32(dev->fwnode, "arm,buffer-size", &size))
425 static u32 tmc_etr_get_max_burst_size(struct device *dev)
429 if (fwnode_property_read_u32(dev->fwnode, "arm,max-burst-size",
431 return TMC_AXICTL_WR_BURST_16;
433 /* Only permissible values are 0 to 15 */
434 if (burst_size > 0xF)
435 burst_size = TMC_AXICTL_WR_BURST_16;
440 static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
445 struct device *dev = &adev->dev;
446 struct coresight_platform_data *pdata = NULL;
447 struct tmc_drvdata *drvdata;
448 struct resource *res = &adev->res;
449 struct coresight_desc desc = { 0 };
450 struct coresight_dev_list *dev_list = NULL;
453 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
457 dev_set_drvdata(dev, drvdata);
459 /* Validity for the resource is already checked by the AMBA core */
460 base = devm_ioremap_resource(dev, res);
466 drvdata->base = base;
467 desc.access = CSDEV_ACCESS_IOMEM(base);
469 spin_lock_init(&drvdata->spinlock);
471 devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
472 drvdata->config_type = BMVAL(devid, 6, 7);
473 drvdata->memwidth = tmc_get_memwidth(devid);
474 /* This device is not associated with a session */
476 drvdata->etr_mode = ETR_MODE_AUTO;
478 if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
479 drvdata->size = tmc_etr_get_default_buffer_size(dev);
480 drvdata->max_burst_size = tmc_etr_get_max_burst_size(dev);
482 drvdata->size = readl_relaxed(drvdata->base + TMC_RSZ) * 4;
487 switch (drvdata->config_type) {
488 case TMC_CONFIG_TYPE_ETB:
489 desc.groups = coresight_etf_groups;
490 desc.type = CORESIGHT_DEV_TYPE_SINK;
491 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
492 desc.ops = &tmc_etb_cs_ops;
493 dev_list = &etb_devs;
495 case TMC_CONFIG_TYPE_ETR:
496 desc.groups = coresight_etr_groups;
497 desc.type = CORESIGHT_DEV_TYPE_SINK;
498 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM;
499 desc.ops = &tmc_etr_cs_ops;
500 ret = tmc_etr_setup_caps(dev, devid,
501 coresight_get_uci_data(id));
504 idr_init(&drvdata->idr);
505 mutex_init(&drvdata->idr_mutex);
506 dev_list = &etr_devs;
508 case TMC_CONFIG_TYPE_ETF:
509 desc.groups = coresight_etf_groups;
510 desc.type = CORESIGHT_DEV_TYPE_LINKSINK;
511 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
512 desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO;
513 desc.ops = &tmc_etf_cs_ops;
514 dev_list = &etf_devs;
517 pr_err("%s: Unsupported TMC config\n", desc.name);
522 desc.name = coresight_alloc_device_name(dev_list, dev);
528 pdata = coresight_get_platform_data(dev);
530 ret = PTR_ERR(pdata);
533 adev->dev.platform_data = pdata;
536 drvdata->csdev = coresight_register(&desc);
537 if (IS_ERR(drvdata->csdev)) {
538 ret = PTR_ERR(drvdata->csdev);
542 drvdata->miscdev.name = desc.name;
543 drvdata->miscdev.minor = MISC_DYNAMIC_MINOR;
544 drvdata->miscdev.fops = &tmc_fops;
545 ret = misc_register(&drvdata->miscdev);
547 coresight_unregister(drvdata->csdev);
549 pm_runtime_put(&adev->dev);
554 static void tmc_shutdown(struct amba_device *adev)
557 struct tmc_drvdata *drvdata = amba_get_drvdata(adev);
559 spin_lock_irqsave(&drvdata->spinlock, flags);
561 if (drvdata->mode == CS_MODE_DISABLED)
564 if (drvdata->config_type == TMC_CONFIG_TYPE_ETR)
565 tmc_etr_disable_hw(drvdata);
568 * We do not care about coresight unregister here unlike remove
569 * callback which is required for making coresight modular since
570 * the system is going down after this.
573 spin_unlock_irqrestore(&drvdata->spinlock, flags);
576 static void tmc_remove(struct amba_device *adev)
578 struct tmc_drvdata *drvdata = dev_get_drvdata(&adev->dev);
581 * Since misc_open() holds a refcount on the f_ops, which is
582 * etb fops in this case, device is there until last file
583 * handler to this device is closed.
585 misc_deregister(&drvdata->miscdev);
586 coresight_unregister(drvdata->csdev);
589 static const struct amba_id tmc_ids[] = {
590 CS_AMBA_ID(0x000bb961),
591 /* Coresight SoC 600 TMC-ETR/ETS */
592 CS_AMBA_ID_DATA(0x000bb9e8, (unsigned long)CORESIGHT_SOC_600_ETR_CAPS),
593 /* Coresight SoC 600 TMC-ETB */
594 CS_AMBA_ID(0x000bb9e9),
595 /* Coresight SoC 600 TMC-ETF */
596 CS_AMBA_ID(0x000bb9ea),
600 MODULE_DEVICE_TABLE(amba, tmc_ids);
602 static struct amba_driver tmc_driver = {
604 .name = "coresight-tmc",
605 .owner = THIS_MODULE,
606 .suppress_bind_attrs = true,
609 .shutdown = tmc_shutdown,
610 .remove = tmc_remove,
614 module_amba_driver(tmc_driver);
616 MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
617 MODULE_DESCRIPTION("Arm CoreSight Trace Memory Controller driver");
618 MODULE_LICENSE("GPL v2");