1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
5 * Description: CoreSight System Trace Macrocell driver
7 * Initial implementation by Pratik Patel
8 * (C) 2014-2015 Pratik Patel <pratikp@codeaurora.org>
10 * Serious refactoring, code cleanup and upgrading to the Coresight upstream
11 * framework by Mathieu Poirier
12 * (C) 2015-2016 Mathieu Poirier <mathieu.poirier@linaro.org>
14 * Guaranteed timing and support for various packet type coming from the
15 * generic STM API by Chunyan Zhang
16 * (C) 2015-2016 Chunyan Zhang <zhang.chunyan@linaro.org>
18 #include <asm/local.h>
19 #include <linux/acpi.h>
20 #include <linux/amba/bus.h>
21 #include <linux/bitmap.h>
22 #include <linux/clk.h>
23 #include <linux/coresight.h>
24 #include <linux/coresight-stm.h>
25 #include <linux/err.h>
26 #include <linux/kernel.h>
27 #include <linux/moduleparam.h>
28 #include <linux/of_address.h>
29 #include <linux/perf_event.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/stm.h>
33 #include "coresight-priv.h"
35 #define STMDMASTARTR 0xc04
36 #define STMDMASTOPR 0xc08
37 #define STMDMASTATR 0xc0c
38 #define STMDMACTLR 0xc10
39 #define STMDMAIDR 0xcfc
41 #define STMHETER 0xd20
42 #define STMHEBSR 0xd60
43 #define STMHEMCR 0xd64
44 #define STMHEMASTR 0xdf4
45 #define STMHEFEAT1R 0xdf8
46 #define STMHEIDR 0xdfc
48 #define STMSPTER 0xe20
49 #define STMPRIVMASKR 0xe40
50 #define STMSPSCR 0xe60
51 #define STMSPMSCR 0xe64
52 #define STMSPOVERRIDER 0xe68
53 #define STMSPMOVERRIDER 0xe6c
54 #define STMSPTRIGCSR 0xe70
56 #define STMTSSTIMR 0xe84
57 #define STMTSFREQR 0xe8c
58 #define STMSYNCR 0xe90
59 #define STMAUXCR 0xe94
60 #define STMSPFEAT1R 0xea0
61 #define STMSPFEAT2R 0xea4
62 #define STMSPFEAT3R 0xea8
63 #define STMITTRIGGER 0xee8
64 #define STMITATBDATA0 0xeec
65 #define STMITATBCTR2 0xef0
66 #define STMITATBID 0xef4
67 #define STMITATBCTR0 0xef8
69 #define STM_32_CHANNEL 32
70 #define BYTES_PER_CHANNEL 256
71 #define STM_TRACE_BUF_SIZE 4096
72 #define STM_SW_MASTER_END 127
74 /* Register bit definition */
75 #define STMTCSR_BUSY_BIT 23
76 /* Reserve the first 10 channels for kernel usage */
77 #define STM_CHANNEL_OFFSET 0
80 STM_PKT_TYPE_DATA = 0x98,
81 STM_PKT_TYPE_FLAG = 0xE8,
82 STM_PKT_TYPE_TRIG = 0xF8,
85 #define stm_channel_addr(drvdata, ch) (drvdata->chs.base + \
86 (ch * BYTES_PER_CHANNEL))
87 #define stm_channel_off(type, opts) (type & ~opts)
89 static int boot_nr_channel;
92 * Not really modular but using module_param is the easiest way to
93 * remain consistent with existing use cases for now.
96 boot_nr_channel, boot_nr_channel, int, S_IRUGO
100 * struct channel_space - central management entity for extended ports
101 * @base: memory mapped base address where channels start.
102 * @phys: physical base address of channel region.
103 * @guaraneed: is the channel delivery guaranteed.
105 struct channel_space {
108 unsigned long *guaranteed;
111 DEFINE_CORESIGHT_DEVLIST(stm_devs, "stm");
114 * struct stm_drvdata - specifics associated to an STM component
115 * @base: memory mapped base address for this component.
116 * @atclk: optional clock for the core parts of the STM.
117 * @csdev: component vitals needed by the framework.
118 * @spinlock: only one at a time pls.
119 * @chs: the channels accociated to this STM.
120 * @stm: structure associated to the generic STM interface.
121 * @mode: this tracer's mode, i.e sysFS, or disabled.
122 * @traceid: value of the current ID for this component.
123 * @write_bytes: Maximus bytes this STM can write at a time.
124 * @stmsper: settings for register STMSPER.
125 * @stmspscr: settings for register STMSPSCR.
126 * @numsp: the total number of stimulus port support by this STM.
127 * @stmheer: settings for register STMHEER.
128 * @stmheter: settings for register STMHETER.
129 * @stmhebsr: settings for register STMHEBSR.
134 struct coresight_device *csdev;
136 struct channel_space chs;
149 static void stm_hwevent_enable_hw(struct stm_drvdata *drvdata)
151 CS_UNLOCK(drvdata->base);
153 writel_relaxed(drvdata->stmhebsr, drvdata->base + STMHEBSR);
154 writel_relaxed(drvdata->stmheter, drvdata->base + STMHETER);
155 writel_relaxed(drvdata->stmheer, drvdata->base + STMHEER);
156 writel_relaxed(0x01 | /* Enable HW event tracing */
157 0x04, /* Error detection on event tracing */
158 drvdata->base + STMHEMCR);
160 CS_LOCK(drvdata->base);
163 static void stm_port_enable_hw(struct stm_drvdata *drvdata)
165 CS_UNLOCK(drvdata->base);
166 /* ATB trigger enable on direct writes to TRIG locations */
168 drvdata->base + STMSPTRIGCSR);
169 writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR);
170 writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER);
172 CS_LOCK(drvdata->base);
175 static void stm_enable_hw(struct stm_drvdata *drvdata)
177 if (drvdata->stmheer)
178 stm_hwevent_enable_hw(drvdata);
180 stm_port_enable_hw(drvdata);
182 CS_UNLOCK(drvdata->base);
184 /* 4096 byte between synchronisation packets */
185 writel_relaxed(0xFFF, drvdata->base + STMSYNCR);
186 writel_relaxed((drvdata->traceid << 16 | /* trace id */
187 0x02 | /* timestamp enable */
188 0x01), /* global STM enable */
189 drvdata->base + STMTCSR);
191 CS_LOCK(drvdata->base);
194 static int stm_enable(struct coresight_device *csdev,
195 struct perf_event *event, u32 mode)
198 struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
200 if (mode != CS_MODE_SYSFS)
203 val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
205 /* Someone is already using the tracer */
209 pm_runtime_get_sync(csdev->dev.parent);
211 spin_lock(&drvdata->spinlock);
212 stm_enable_hw(drvdata);
213 spin_unlock(&drvdata->spinlock);
215 dev_dbg(&csdev->dev, "STM tracing enabled\n");
219 static void stm_hwevent_disable_hw(struct stm_drvdata *drvdata)
221 CS_UNLOCK(drvdata->base);
223 writel_relaxed(0x0, drvdata->base + STMHEMCR);
224 writel_relaxed(0x0, drvdata->base + STMHEER);
225 writel_relaxed(0x0, drvdata->base + STMHETER);
227 CS_LOCK(drvdata->base);
230 static void stm_port_disable_hw(struct stm_drvdata *drvdata)
232 CS_UNLOCK(drvdata->base);
234 writel_relaxed(0x0, drvdata->base + STMSPER);
235 writel_relaxed(0x0, drvdata->base + STMSPTRIGCSR);
237 CS_LOCK(drvdata->base);
240 static void stm_disable_hw(struct stm_drvdata *drvdata)
244 CS_UNLOCK(drvdata->base);
246 val = readl_relaxed(drvdata->base + STMTCSR);
247 val &= ~0x1; /* clear global STM enable [0] */
248 writel_relaxed(val, drvdata->base + STMTCSR);
250 CS_LOCK(drvdata->base);
252 stm_port_disable_hw(drvdata);
253 if (drvdata->stmheer)
254 stm_hwevent_disable_hw(drvdata);
257 static void stm_disable(struct coresight_device *csdev,
258 struct perf_event *event)
260 struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
261 struct csdev_access *csa = &csdev->access;
264 * For as long as the tracer isn't disabled another entity can't
265 * change its status. As such we can read the status here without
266 * fearing it will change under us.
268 if (local_read(&drvdata->mode) == CS_MODE_SYSFS) {
269 spin_lock(&drvdata->spinlock);
270 stm_disable_hw(drvdata);
271 spin_unlock(&drvdata->spinlock);
273 /* Wait until the engine has completely stopped */
274 coresight_timeout(csa, STMTCSR, STMTCSR_BUSY_BIT, 0);
276 pm_runtime_put(csdev->dev.parent);
278 local_set(&drvdata->mode, CS_MODE_DISABLED);
279 dev_dbg(&csdev->dev, "STM tracing disabled\n");
283 static int stm_trace_id(struct coresight_device *csdev)
285 struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
287 return drvdata->traceid;
290 static const struct coresight_ops_source stm_source_ops = {
291 .trace_id = stm_trace_id,
292 .enable = stm_enable,
293 .disable = stm_disable,
296 static const struct coresight_ops stm_cs_ops = {
297 .source_ops = &stm_source_ops,
300 static inline bool stm_addr_unaligned(const void *addr, u8 write_bytes)
302 return ((unsigned long)addr & (write_bytes - 1));
305 static void stm_send(void __iomem *addr, const void *data,
306 u32 size, u8 write_bytes)
310 if (stm_addr_unaligned(data, write_bytes)) {
311 memcpy(paload, data, size);
315 /* now we are 64bit/32bit aligned */
319 writeq_relaxed(*(u64 *)data, addr);
323 writel_relaxed(*(u32 *)data, addr);
326 writew_relaxed(*(u16 *)data, addr);
329 writeb_relaxed(*(u8 *)data, addr);
336 static int stm_generic_link(struct stm_data *stm_data,
337 unsigned int master, unsigned int channel)
339 struct stm_drvdata *drvdata = container_of(stm_data,
340 struct stm_drvdata, stm);
341 if (!drvdata || !drvdata->csdev)
344 return coresight_enable(drvdata->csdev);
347 static void stm_generic_unlink(struct stm_data *stm_data,
348 unsigned int master, unsigned int channel)
350 struct stm_drvdata *drvdata = container_of(stm_data,
351 struct stm_drvdata, stm);
352 if (!drvdata || !drvdata->csdev)
355 coresight_disable(drvdata->csdev);
359 stm_mmio_addr(struct stm_data *stm_data, unsigned int master,
360 unsigned int channel, unsigned int nr_chans)
362 struct stm_drvdata *drvdata = container_of(stm_data,
363 struct stm_drvdata, stm);
366 addr = drvdata->chs.phys + channel * BYTES_PER_CHANNEL;
368 if (offset_in_page(addr) ||
369 offset_in_page(nr_chans * BYTES_PER_CHANNEL))
375 static long stm_generic_set_options(struct stm_data *stm_data,
377 unsigned int channel,
378 unsigned int nr_chans,
379 unsigned long options)
381 struct stm_drvdata *drvdata = container_of(stm_data,
382 struct stm_drvdata, stm);
383 if (!(drvdata && local_read(&drvdata->mode)))
386 if (channel >= drvdata->numsp)
390 case STM_OPTION_GUARANTEED:
391 set_bit(channel, drvdata->chs.guaranteed);
394 case STM_OPTION_INVARIANT:
395 clear_bit(channel, drvdata->chs.guaranteed);
405 static ssize_t notrace stm_generic_packet(struct stm_data *stm_data,
407 unsigned int channel,
411 const unsigned char *payload)
413 void __iomem *ch_addr;
414 struct stm_drvdata *drvdata = container_of(stm_data,
415 struct stm_drvdata, stm);
416 unsigned int stm_flags;
418 if (!(drvdata && local_read(&drvdata->mode)))
421 if (channel >= drvdata->numsp)
424 ch_addr = stm_channel_addr(drvdata, channel);
426 stm_flags = (flags & STP_PACKET_TIMESTAMPED) ?
427 STM_FLAG_TIMESTAMPED : 0;
428 stm_flags |= test_bit(channel, drvdata->chs.guaranteed) ?
429 STM_FLAG_GUARANTEED : 0;
431 if (size > drvdata->write_bytes)
432 size = drvdata->write_bytes;
434 size = rounddown_pow_of_two(size);
437 case STP_PACKET_FLAG:
438 ch_addr += stm_channel_off(STM_PKT_TYPE_FLAG, stm_flags);
441 * The generic STM core sets a size of '0' on flag packets.
442 * As such send a flag packet of size '1' and tell the
445 stm_send(ch_addr, payload, 1, drvdata->write_bytes);
449 case STP_PACKET_DATA:
450 stm_flags |= (flags & STP_PACKET_MARKED) ? STM_FLAG_MARKED : 0;
451 ch_addr += stm_channel_off(STM_PKT_TYPE_DATA, stm_flags);
452 stm_send(ch_addr, payload, size,
453 drvdata->write_bytes);
463 static ssize_t hwevent_enable_show(struct device *dev,
464 struct device_attribute *attr, char *buf)
466 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
467 unsigned long val = drvdata->stmheer;
469 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
472 static ssize_t hwevent_enable_store(struct device *dev,
473 struct device_attribute *attr,
474 const char *buf, size_t size)
476 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
480 ret = kstrtoul(buf, 16, &val);
484 drvdata->stmheer = val;
485 /* HW event enable and trigger go hand in hand */
486 drvdata->stmheter = val;
490 static DEVICE_ATTR_RW(hwevent_enable);
492 static ssize_t hwevent_select_show(struct device *dev,
493 struct device_attribute *attr, char *buf)
495 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
496 unsigned long val = drvdata->stmhebsr;
498 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
501 static ssize_t hwevent_select_store(struct device *dev,
502 struct device_attribute *attr,
503 const char *buf, size_t size)
505 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
509 ret = kstrtoul(buf, 16, &val);
513 drvdata->stmhebsr = val;
517 static DEVICE_ATTR_RW(hwevent_select);
519 static ssize_t port_select_show(struct device *dev,
520 struct device_attribute *attr, char *buf)
522 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
525 if (!local_read(&drvdata->mode)) {
526 val = drvdata->stmspscr;
528 spin_lock(&drvdata->spinlock);
529 val = readl_relaxed(drvdata->base + STMSPSCR);
530 spin_unlock(&drvdata->spinlock);
533 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
536 static ssize_t port_select_store(struct device *dev,
537 struct device_attribute *attr,
538 const char *buf, size_t size)
540 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
541 unsigned long val, stmsper;
544 ret = kstrtoul(buf, 16, &val);
548 spin_lock(&drvdata->spinlock);
549 drvdata->stmspscr = val;
551 if (local_read(&drvdata->mode)) {
552 CS_UNLOCK(drvdata->base);
553 /* Process as per ARM's TRM recommendation */
554 stmsper = readl_relaxed(drvdata->base + STMSPER);
555 writel_relaxed(0x0, drvdata->base + STMSPER);
556 writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR);
557 writel_relaxed(stmsper, drvdata->base + STMSPER);
558 CS_LOCK(drvdata->base);
560 spin_unlock(&drvdata->spinlock);
564 static DEVICE_ATTR_RW(port_select);
566 static ssize_t port_enable_show(struct device *dev,
567 struct device_attribute *attr, char *buf)
569 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
572 if (!local_read(&drvdata->mode)) {
573 val = drvdata->stmsper;
575 spin_lock(&drvdata->spinlock);
576 val = readl_relaxed(drvdata->base + STMSPER);
577 spin_unlock(&drvdata->spinlock);
580 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
583 static ssize_t port_enable_store(struct device *dev,
584 struct device_attribute *attr,
585 const char *buf, size_t size)
587 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
591 ret = kstrtoul(buf, 16, &val);
595 spin_lock(&drvdata->spinlock);
596 drvdata->stmsper = val;
598 if (local_read(&drvdata->mode)) {
599 CS_UNLOCK(drvdata->base);
600 writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER);
601 CS_LOCK(drvdata->base);
603 spin_unlock(&drvdata->spinlock);
607 static DEVICE_ATTR_RW(port_enable);
609 static ssize_t traceid_show(struct device *dev,
610 struct device_attribute *attr, char *buf)
613 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
615 val = drvdata->traceid;
616 return sprintf(buf, "%#lx\n", val);
619 static ssize_t traceid_store(struct device *dev,
620 struct device_attribute *attr,
621 const char *buf, size_t size)
625 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
627 ret = kstrtoul(buf, 16, &val);
631 /* traceid field is 7bit wide on STM32 */
632 drvdata->traceid = val & 0x7f;
635 static DEVICE_ATTR_RW(traceid);
637 #define coresight_stm_reg(name, offset) \
638 coresight_simple_reg32(struct stm_drvdata, name, offset)
640 coresight_stm_reg(tcsr, STMTCSR);
641 coresight_stm_reg(tsfreqr, STMTSFREQR);
642 coresight_stm_reg(syncr, STMSYNCR);
643 coresight_stm_reg(sper, STMSPER);
644 coresight_stm_reg(spter, STMSPTER);
645 coresight_stm_reg(privmaskr, STMPRIVMASKR);
646 coresight_stm_reg(spscr, STMSPSCR);
647 coresight_stm_reg(spmscr, STMSPMSCR);
648 coresight_stm_reg(spfeat1r, STMSPFEAT1R);
649 coresight_stm_reg(spfeat2r, STMSPFEAT2R);
650 coresight_stm_reg(spfeat3r, STMSPFEAT3R);
651 coresight_stm_reg(devid, CORESIGHT_DEVID);
653 static struct attribute *coresight_stm_attrs[] = {
654 &dev_attr_hwevent_enable.attr,
655 &dev_attr_hwevent_select.attr,
656 &dev_attr_port_enable.attr,
657 &dev_attr_port_select.attr,
658 &dev_attr_traceid.attr,
662 static struct attribute *coresight_stm_mgmt_attrs[] = {
664 &dev_attr_tsfreqr.attr,
665 &dev_attr_syncr.attr,
667 &dev_attr_spter.attr,
668 &dev_attr_privmaskr.attr,
669 &dev_attr_spscr.attr,
670 &dev_attr_spmscr.attr,
671 &dev_attr_spfeat1r.attr,
672 &dev_attr_spfeat2r.attr,
673 &dev_attr_spfeat3r.attr,
674 &dev_attr_devid.attr,
678 static const struct attribute_group coresight_stm_group = {
679 .attrs = coresight_stm_attrs,
682 static const struct attribute_group coresight_stm_mgmt_group = {
683 .attrs = coresight_stm_mgmt_attrs,
687 static const struct attribute_group *coresight_stm_groups[] = {
688 &coresight_stm_group,
689 &coresight_stm_mgmt_group,
694 static int of_stm_get_stimulus_area(struct device *dev, struct resource *res)
696 const char *name = NULL;
697 int index = 0, found = 0;
698 struct device_node *np = dev->of_node;
700 while (!of_property_read_string_index(np, "reg-names", index, &name)) {
701 if (strcmp("stm-stimulus-base", name)) {
706 /* We have a match and @index is where it's at */
714 return of_address_to_resource(np, index, res);
717 static inline int of_stm_get_stimulus_area(struct device *dev,
718 struct resource *res)
725 static int acpi_stm_get_stimulus_area(struct device *dev, struct resource *res)
728 bool found_base = false;
729 struct resource_entry *rent;
732 struct acpi_device *adev = ACPI_COMPANION(dev);
734 rc = acpi_dev_get_resources(adev, &res_list, NULL, NULL);
739 * The stimulus base for STM device must be listed as the second memory
740 * resource, followed by the programming base address as described in
741 * "Section 2.3 Resources" in ACPI for CoreSightTM 1.0 Platform Design
742 * document (DEN0067).
745 list_for_each_entry(rent, &res_list, node) {
746 if (resource_type(rent->res) != IORESOURCE_MEM)
757 acpi_dev_free_resource_list(&res_list);
761 static inline int acpi_stm_get_stimulus_area(struct device *dev,
762 struct resource *res)
768 static int stm_get_stimulus_area(struct device *dev, struct resource *res)
770 struct fwnode_handle *fwnode = dev_fwnode(dev);
772 if (is_of_node(fwnode))
773 return of_stm_get_stimulus_area(dev, res);
774 else if (is_acpi_node(fwnode))
775 return acpi_stm_get_stimulus_area(dev, res);
779 static u32 stm_fundamental_data_size(struct stm_drvdata *drvdata)
783 if (!IS_ENABLED(CONFIG_64BIT))
786 stmspfeat2r = readl_relaxed(drvdata->base + STMSPFEAT2R);
789 * bit[15:12] represents the fundamental data size
793 return BMVAL(stmspfeat2r, 12, 15) ? 8 : 4;
796 static u32 stm_num_stimulus_port(struct stm_drvdata *drvdata)
800 numsp = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
802 * NUMPS in STMDEVID is 17 bit long and if equal to 0x0,
803 * 32 stimulus ports are supported.
807 numsp = STM_32_CHANNEL;
811 static void stm_init_default_data(struct stm_drvdata *drvdata)
813 /* Don't use port selection */
814 drvdata->stmspscr = 0x0;
816 * Enable all channel regardless of their number. When port
817 * selection isn't used (see above) STMSPER applies to all
818 * 32 channel group available, hence setting all 32 bits to 1
820 drvdata->stmsper = ~0x0;
823 * The trace ID value for *ETM* tracers start at CPU_ID * 2 + 0x10 and
824 * anything equal to or higher than 0x70 is reserved. Since 0x00 is
825 * also reserved the STM trace ID needs to be higher than 0x00 and
828 drvdata->traceid = 0x1;
830 /* Set invariant transaction timing on all channels */
831 bitmap_clear(drvdata->chs.guaranteed, 0, drvdata->numsp);
834 static void stm_init_generic_data(struct stm_drvdata *drvdata,
837 drvdata->stm.name = name;
840 * MasterIDs are assigned at HW design phase. As such the core is
841 * using a single master for interaction with this device.
843 drvdata->stm.sw_start = 1;
844 drvdata->stm.sw_end = 1;
845 drvdata->stm.hw_override = true;
846 drvdata->stm.sw_nchannels = drvdata->numsp;
847 drvdata->stm.sw_mmiosz = BYTES_PER_CHANNEL;
848 drvdata->stm.packet = stm_generic_packet;
849 drvdata->stm.mmio_addr = stm_mmio_addr;
850 drvdata->stm.link = stm_generic_link;
851 drvdata->stm.unlink = stm_generic_unlink;
852 drvdata->stm.set_options = stm_generic_set_options;
855 static int stm_probe(struct amba_device *adev, const struct amba_id *id)
859 unsigned long *guaranteed;
860 struct device *dev = &adev->dev;
861 struct coresight_platform_data *pdata = NULL;
862 struct stm_drvdata *drvdata;
863 struct resource *res = &adev->res;
864 struct resource ch_res;
866 struct coresight_desc desc = { 0 };
868 desc.name = coresight_alloc_device_name(&stm_devs, dev);
872 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
876 drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
877 if (!IS_ERR(drvdata->atclk)) {
878 ret = clk_prepare_enable(drvdata->atclk);
882 dev_set_drvdata(dev, drvdata);
884 base = devm_ioremap_resource(dev, res);
886 return PTR_ERR(base);
887 drvdata->base = base;
888 desc.access = CSDEV_ACCESS_IOMEM(base);
890 ret = stm_get_stimulus_area(dev, &ch_res);
893 drvdata->chs.phys = ch_res.start;
895 base = devm_ioremap_resource(dev, &ch_res);
897 return PTR_ERR(base);
898 drvdata->chs.base = base;
900 drvdata->write_bytes = stm_fundamental_data_size(drvdata);
903 drvdata->numsp = boot_nr_channel;
905 drvdata->numsp = stm_num_stimulus_port(drvdata);
907 bitmap_size = BITS_TO_LONGS(drvdata->numsp) * sizeof(long);
909 guaranteed = devm_kzalloc(dev, bitmap_size, GFP_KERNEL);
912 drvdata->chs.guaranteed = guaranteed;
914 spin_lock_init(&drvdata->spinlock);
916 stm_init_default_data(drvdata);
917 stm_init_generic_data(drvdata, desc.name);
919 if (stm_register_device(dev, &drvdata->stm, THIS_MODULE)) {
921 "%s : stm_register_device failed, probing deferred\n",
923 return -EPROBE_DEFER;
926 pdata = coresight_get_platform_data(dev);
928 ret = PTR_ERR(pdata);
931 adev->dev.platform_data = pdata;
933 desc.type = CORESIGHT_DEV_TYPE_SOURCE;
934 desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE;
935 desc.ops = &stm_cs_ops;
938 desc.groups = coresight_stm_groups;
939 drvdata->csdev = coresight_register(&desc);
940 if (IS_ERR(drvdata->csdev)) {
941 ret = PTR_ERR(drvdata->csdev);
945 pm_runtime_put(&adev->dev);
947 dev_info(&drvdata->csdev->dev, "%s initialized\n",
948 (char *)coresight_get_uci_data(id));
952 stm_unregister_device(&drvdata->stm);
956 static void stm_remove(struct amba_device *adev)
958 struct stm_drvdata *drvdata = dev_get_drvdata(&adev->dev);
960 coresight_unregister(drvdata->csdev);
962 stm_unregister_device(&drvdata->stm);
966 static int stm_runtime_suspend(struct device *dev)
968 struct stm_drvdata *drvdata = dev_get_drvdata(dev);
970 if (drvdata && !IS_ERR(drvdata->atclk))
971 clk_disable_unprepare(drvdata->atclk);
976 static int stm_runtime_resume(struct device *dev)
978 struct stm_drvdata *drvdata = dev_get_drvdata(dev);
980 if (drvdata && !IS_ERR(drvdata->atclk))
981 clk_prepare_enable(drvdata->atclk);
987 static const struct dev_pm_ops stm_dev_pm_ops = {
988 SET_RUNTIME_PM_OPS(stm_runtime_suspend, stm_runtime_resume, NULL)
991 static const struct amba_id stm_ids[] = {
992 CS_AMBA_ID_DATA(0x000bb962, "STM32"),
993 CS_AMBA_ID_DATA(0x000bb963, "STM500"),
997 MODULE_DEVICE_TABLE(amba, stm_ids);
999 static struct amba_driver stm_driver = {
1001 .name = "coresight-stm",
1002 .owner = THIS_MODULE,
1003 .pm = &stm_dev_pm_ops,
1004 .suppress_bind_attrs = true,
1007 .remove = stm_remove,
1008 .id_table = stm_ids,
1011 module_amba_driver(stm_driver);
1013 MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
1014 MODULE_DESCRIPTION("Arm CoreSight System Trace Macrocell driver");
1015 MODULE_LICENSE("GPL v2");