drivers/hwtracing/coresight/coresight-stm.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
   4  *
   5  * Description: CoreSight System Trace Macrocell driver
   6  *
   7  * Initial implementation by Pratik Patel
   8  * (C) 2014-2015 Pratik Patel <pratikp@codeaurora.org>
   9  *
  10  * Serious refactoring, code cleanup and upgrading to the Coresight upstream
  11  * framework by Mathieu Poirier
  12  * (C) 2015-2016 Mathieu Poirier <mathieu.poirier@linaro.org>
  13  *
  14  * Guaranteed timing and support for various packet type coming from the
  15  * generic STM API by Chunyan Zhang
  16  * (C) 2015-2016 Chunyan Zhang <zhang.chunyan@linaro.org>
  17  */
  18 #include <asm/local.h>
  19 #include <linux/acpi.h>
  20 #include <linux/amba/bus.h>
  21 #include <linux/bitmap.h>
  22 #include <linux/clk.h>
  23 #include <linux/coresight.h>
  24 #include <linux/coresight-stm.h>
  25 #include <linux/err.h>
  26 #include <linux/kernel.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/of_address.h>
  29 #include <linux/perf_event.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/stm.h>
  32
  33 #include "coresight-priv.h"
  34 #include "coresight-trace-id.h"
  35
  36 #define STMDMASTARTR                    0xc04
  37 #define STMDMASTOPR                     0xc08
  38 #define STMDMASTATR                     0xc0c
  39 #define STMDMACTLR                      0xc10
  40 #define STMDMAIDR                       0xcfc
  41 #define STMHEER                         0xd00
  42 #define STMHETER                        0xd20
  43 #define STMHEBSR                        0xd60
  44 #define STMHEMCR                        0xd64
  45 #define STMHEMASTR                      0xdf4
  46 #define STMHEFEAT1R                     0xdf8
  47 #define STMHEIDR                        0xdfc
  48 #define STMSPER                         0xe00
  49 #define STMSPTER                        0xe20
  50 #define STMPRIVMASKR                    0xe40
  51 #define STMSPSCR                        0xe60
  52 #define STMSPMSCR                       0xe64
  53 #define STMSPOVERRIDER                  0xe68
  54 #define STMSPMOVERRIDER                 0xe6c
  55 #define STMSPTRIGCSR                    0xe70
  56 #define STMTCSR                         0xe80
  57 #define STMTSSTIMR                      0xe84
  58 #define STMTSFREQR                      0xe8c
  59 #define STMSYNCR                        0xe90
  60 #define STMAUXCR                        0xe94
  61 #define STMSPFEAT1R                     0xea0
  62 #define STMSPFEAT2R                     0xea4
  63 #define STMSPFEAT3R                     0xea8
  64 #define STMITTRIGGER                    0xee8
  65 #define STMITATBDATA0                   0xeec
  66 #define STMITATBCTR2                    0xef0
  67 #define STMITATBID                      0xef4
  68 #define STMITATBCTR0                    0xef8
  69
  70 #define STM_32_CHANNEL                  32
  71 #define BYTES_PER_CHANNEL               256
  72 #define STM_TRACE_BUF_SIZE              4096
  73 #define STM_SW_MASTER_END               127
  74
  75 /* Register bit definition */
  76 #define STMTCSR_BUSY_BIT                23
  77 /* Reserve the first 10 channels for kernel usage */
  78 #define STM_CHANNEL_OFFSET              0
  79
  80 enum stm_pkt_type {
  81         STM_PKT_TYPE_DATA       = 0x98,
  82         STM_PKT_TYPE_FLAG       = 0xE8,
  83         STM_PKT_TYPE_TRIG       = 0xF8,
  84 };
  85
  86 #define stm_channel_addr(drvdata, ch)   (drvdata->chs.base +    \
  87                                         (ch * BYTES_PER_CHANNEL))
  88 #define stm_channel_off(type, opts)     (type & ~opts)
  89
  90 static int boot_nr_channel;
  91
  92 /*
  93  * Not really modular but using module_param is the easiest way to
  94  * remain consistent with existing use cases for now.
  95  */
  96 module_param_named(
  97         boot_nr_channel, boot_nr_channel, int, S_IRUGO
  98 );
  99
 100 /*
 101  * struct channel_space - central management entity for extended ports
 102  * @base:               memory mapped base address where channels start.
 103  * @phys:               physical base address of channel region.
 104  * @guaraneed:          is the channel delivery guaranteed.
 105  */
 106 struct channel_space {
 107         void __iomem            *base;
 108         phys_addr_t             phys;
 109         unsigned long           *guaranteed;
 110 };
 111
 112 DEFINE_CORESIGHT_DEVLIST(stm_devs, "stm");
 113
 114 /**
 115  * struct stm_drvdata - specifics associated to an STM component
 116  * @base:               memory mapped base address for this component.
 117  * @atclk:              optional clock for the core parts of the STM.
 118  * @csdev:              component vitals needed by the framework.
 119  * @spinlock:           only one at a time pls.
 120  * @chs:                the channels accociated to this STM.
 121  * @stm:                structure associated to the generic STM interface.
 122  * @traceid:            value of the current ID for this component.
 123  * @write_bytes:        Maximus bytes this STM can write at a time.
 124  * @stmsper:            settings for register STMSPER.
 125  * @stmspscr:           settings for register STMSPSCR.
 126  * @numsp:              the total number of stimulus port support by this STM.
 127  * @stmheer:            settings for register STMHEER.
 128  * @stmheter:           settings for register STMHETER.
 129  * @stmhebsr:           settings for register STMHEBSR.
 130  */
 131 struct stm_drvdata {
 132         void __iomem            *base;
 133         struct clk              *atclk;
 134         struct coresight_device *csdev;
 135         spinlock_t              spinlock;
 136         struct channel_space    chs;
 137         struct stm_data         stm;
 138         u8                      traceid;
 139         u32                     write_bytes;
 140         u32                     stmsper;
 141         u32                     stmspscr;
 142         u32                     numsp;
 143         u32                     stmheer;
 144         u32                     stmheter;
 145         u32                     stmhebsr;
 146 };
 147
 148 static void stm_hwevent_enable_hw(struct stm_drvdata *drvdata)
 149 {
 150         CS_UNLOCK(drvdata->base);
 151
 152         writel_relaxed(drvdata->stmhebsr, drvdata->base + STMHEBSR);
 153         writel_relaxed(drvdata->stmheter, drvdata->base + STMHETER);
 154         writel_relaxed(drvdata->stmheer, drvdata->base + STMHEER);
 155         writel_relaxed(0x01 |   /* Enable HW event tracing */
 156                        0x04,    /* Error detection on event tracing */
 157                        drvdata->base + STMHEMCR);
 158
 159         CS_LOCK(drvdata->base);
 160 }
 161
 162 static void stm_port_enable_hw(struct stm_drvdata *drvdata)
 163 {
 164         CS_UNLOCK(drvdata->base);
 165         /* ATB trigger enable on direct writes to TRIG locations */
 166         writel_relaxed(0x10,
 167                        drvdata->base + STMSPTRIGCSR);
 168         writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR);
 169         writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER);
 170
 171         CS_LOCK(drvdata->base);
 172 }
 173
 174 static void stm_enable_hw(struct stm_drvdata *drvdata)
 175 {
 176         if (drvdata->stmheer)
 177                 stm_hwevent_enable_hw(drvdata);
 178
 179         stm_port_enable_hw(drvdata);
 180
 181         CS_UNLOCK(drvdata->base);
 182
 183         /* 4096 byte between synchronisation packets */
 184         writel_relaxed(0xFFF, drvdata->base + STMSYNCR);
 185         writel_relaxed((drvdata->traceid << 16 | /* trace id */
 186                         0x02 |                   /* timestamp enable */
 187                         0x01),                   /* global STM enable */
 188                         drvdata->base + STMTCSR);
 189
 190         CS_LOCK(drvdata->base);
 191 }
 192
 193 static int stm_enable(struct coresight_device *csdev, struct perf_event *event,
 194                       enum cs_mode mode)
 195 {
 196         u32 val;
 197         struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 198
 199         if (mode != CS_MODE_SYSFS)
 200                 return -EINVAL;
 201
 202         val = local_cmpxchg(&csdev->mode, CS_MODE_DISABLED, mode);
 203
 204         /* Someone is already using the tracer */
 205         if (val)
 206                 return -EBUSY;
 207
 208         pm_runtime_get_sync(csdev->dev.parent);
 209
 210         spin_lock(&drvdata->spinlock);
 211         stm_enable_hw(drvdata);
 212         spin_unlock(&drvdata->spinlock);
 213
 214         dev_dbg(&csdev->dev, "STM tracing enabled\n");
 215         return 0;
 216 }
 217
 218 static void stm_hwevent_disable_hw(struct stm_drvdata *drvdata)
 219 {
 220         CS_UNLOCK(drvdata->base);
 221
 222         writel_relaxed(0x0, drvdata->base + STMHEMCR);
 223         writel_relaxed(0x0, drvdata->base + STMHEER);
 224         writel_relaxed(0x0, drvdata->base + STMHETER);
 225
 226         CS_LOCK(drvdata->base);
 227 }
 228
 229 static void stm_port_disable_hw(struct stm_drvdata *drvdata)
 230 {
 231         CS_UNLOCK(drvdata->base);
 232
 233         writel_relaxed(0x0, drvdata->base + STMSPER);
 234         writel_relaxed(0x0, drvdata->base + STMSPTRIGCSR);
 235
 236         CS_LOCK(drvdata->base);
 237 }
 238
 239 static void stm_disable_hw(struct stm_drvdata *drvdata)
 240 {
 241         u32 val;
 242
 243         CS_UNLOCK(drvdata->base);
 244
 245         val = readl_relaxed(drvdata->base + STMTCSR);
 246         val &= ~0x1; /* clear global STM enable [0] */
 247         writel_relaxed(val, drvdata->base + STMTCSR);
 248
 249         CS_LOCK(drvdata->base);
 250
 251         stm_port_disable_hw(drvdata);
 252         if (drvdata->stmheer)
 253                 stm_hwevent_disable_hw(drvdata);
 254 }
 255
 256 static void stm_disable(struct coresight_device *csdev,
 257                         struct perf_event *event)
 258 {
 259         struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 260         struct csdev_access *csa = &csdev->access;
 261
 262         /*
 263          * For as long as the tracer isn't disabled another entity can't
 264          * change its status.  As such we can read the status here without
 265          * fearing it will change under us.
 266          */
 267         if (local_read(&csdev->mode) == CS_MODE_SYSFS) {
 268                 spin_lock(&drvdata->spinlock);
 269                 stm_disable_hw(drvdata);
 270                 spin_unlock(&drvdata->spinlock);
 271
 272                 /* Wait until the engine has completely stopped */
 273                 coresight_timeout(csa, STMTCSR, STMTCSR_BUSY_BIT, 0);
 274
 275                 pm_runtime_put(csdev->dev.parent);
 276
 277                 local_set(&csdev->mode, CS_MODE_DISABLED);
 278                 dev_dbg(&csdev->dev, "STM tracing disabled\n");
 279         }
 280 }
 281
 282 static const struct coresight_ops_source stm_source_ops = {
 283         .enable         = stm_enable,
 284         .disable        = stm_disable,
 285 };
 286
 287 static const struct coresight_ops stm_cs_ops = {
 288         .source_ops     = &stm_source_ops,
 289 };
 290
 291 static inline bool stm_addr_unaligned(const void *addr, u8 write_bytes)
 292 {
 293         return ((unsigned long)addr & (write_bytes - 1));
 294 }
 295
 296 static void stm_send(void __iomem *addr, const void *data,
 297                      u32 size, u8 write_bytes)
 298 {
 299         u8 paload[8];
 300
 301         if (stm_addr_unaligned(data, write_bytes)) {
 302                 memcpy(paload, data, size);
 303                 data = paload;
 304         }
 305
 306         /* now we are 64bit/32bit aligned */
 307         switch (size) {
 308 #ifdef CONFIG_64BIT
 309         case 8:
 310                 writeq_relaxed(*(u64 *)data, addr);
 311                 break;
 312 #endif
 313         case 4:
 314                 writel_relaxed(*(u32 *)data, addr);
 315                 break;
 316         case 2:
 317                 writew_relaxed(*(u16 *)data, addr);
 318                 break;
 319         case 1:
 320                 writeb_relaxed(*(u8 *)data, addr);
 321                 break;
 322         default:
 323                 break;
 324         }
 325 }
 326
 327 static int stm_generic_link(struct stm_data *stm_data,
 328                             unsigned int master,  unsigned int channel)
 329 {
 330         struct stm_drvdata *drvdata = container_of(stm_data,
 331                                                    struct stm_drvdata, stm);
 332         if (!drvdata || !drvdata->csdev)
 333                 return -EINVAL;
 334
 335         return coresight_enable(drvdata->csdev);
 336 }
 337
 338 static void stm_generic_unlink(struct stm_data *stm_data,
 339                                unsigned int master,  unsigned int channel)
 340 {
 341         struct stm_drvdata *drvdata = container_of(stm_data,
 342                                                    struct stm_drvdata, stm);
 343         if (!drvdata || !drvdata->csdev)
 344                 return;
 345
 346         coresight_disable(drvdata->csdev);
 347 }
 348
 349 static phys_addr_t
 350 stm_mmio_addr(struct stm_data *stm_data, unsigned int master,
 351               unsigned int channel, unsigned int nr_chans)
 352 {
 353         struct stm_drvdata *drvdata = container_of(stm_data,
 354                                                    struct stm_drvdata, stm);
 355         phys_addr_t addr;
 356
 357         addr = drvdata->chs.phys + channel * BYTES_PER_CHANNEL;
 358
 359         if (offset_in_page(addr) ||
 360             offset_in_page(nr_chans * BYTES_PER_CHANNEL))
 361                 return 0;
 362
 363         return addr;
 364 }
 365
 366 static long stm_generic_set_options(struct stm_data *stm_data,
 367                                     unsigned int master,
 368                                     unsigned int channel,
 369                                     unsigned int nr_chans,
 370                                     unsigned long options)
 371 {
 372         struct stm_drvdata *drvdata = container_of(stm_data,
 373                                                    struct stm_drvdata, stm);
 374         if (!(drvdata && local_read(&drvdata->csdev->mode)))
 375                 return -EINVAL;
 376
 377         if (channel >= drvdata->numsp)
 378                 return -EINVAL;
 379
 380         switch (options) {
 381         case STM_OPTION_GUARANTEED:
 382                 set_bit(channel, drvdata->chs.guaranteed);
 383                 break;
 384
 385         case STM_OPTION_INVARIANT:
 386                 clear_bit(channel, drvdata->chs.guaranteed);
 387                 break;
 388
 389         default:
 390                 return -EINVAL;
 391         }
 392
 393         return 0;
 394 }
 395
 396 static ssize_t notrace stm_generic_packet(struct stm_data *stm_data,
 397                                   unsigned int master,
 398                                   unsigned int channel,
 399                                   unsigned int packet,
 400                                   unsigned int flags,
 401                                   unsigned int size,
 402                                   const unsigned char *payload)
 403 {
 404         void __iomem *ch_addr;
 405         struct stm_drvdata *drvdata = container_of(stm_data,
 406                                                    struct stm_drvdata, stm);
 407         unsigned int stm_flags;
 408
 409         if (!(drvdata && local_read(&drvdata->csdev->mode)))
 410                 return -EACCES;
 411
 412         if (channel >= drvdata->numsp)
 413                 return -EINVAL;
 414
 415         ch_addr = stm_channel_addr(drvdata, channel);
 416
 417         stm_flags = (flags & STP_PACKET_TIMESTAMPED) ?
 418                         STM_FLAG_TIMESTAMPED : 0;
 419         stm_flags |= test_bit(channel, drvdata->chs.guaranteed) ?
 420                            STM_FLAG_GUARANTEED : 0;
 421
 422         if (size > drvdata->write_bytes)
 423                 size = drvdata->write_bytes;
 424         else
 425                 size = rounddown_pow_of_two(size);
 426
 427         switch (packet) {
 428         case STP_PACKET_FLAG:
 429                 ch_addr += stm_channel_off(STM_PKT_TYPE_FLAG, stm_flags);
 430
 431                 /*
 432                  * The generic STM core sets a size of '0' on flag packets.
 433                  * As such send a flag packet of size '1' and tell the
 434                  * core we did so.
 435                  */
 436                 stm_send(ch_addr, payload, 1, drvdata->write_bytes);
 437                 size = 1;
 438                 break;
 439
 440         case STP_PACKET_DATA:
 441                 stm_flags |= (flags & STP_PACKET_MARKED) ? STM_FLAG_MARKED : 0;
 442                 ch_addr += stm_channel_off(STM_PKT_TYPE_DATA, stm_flags);
 443                 stm_send(ch_addr, payload, size,
 444                                 drvdata->write_bytes);
 445                 break;
 446
 447         default:
 448                 return -ENOTSUPP;
 449         }
 450
 451         return size;
 452 }
 453
 454 static ssize_t hwevent_enable_show(struct device *dev,
 455                                    struct device_attribute *attr, char *buf)
 456 {
 457         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 458         unsigned long val = drvdata->stmheer;
 459
 460         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 461 }
 462
 463 static ssize_t hwevent_enable_store(struct device *dev,
 464                                     struct device_attribute *attr,
 465                                     const char *buf, size_t size)
 466 {
 467         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 468         unsigned long val;
 469         int ret = 0;
 470
 471         ret = kstrtoul(buf, 16, &val);
 472         if (ret)
 473                 return -EINVAL;
 474
 475         drvdata->stmheer = val;
 476         /* HW event enable and trigger go hand in hand */
 477         drvdata->stmheter = val;
 478
 479         return size;
 480 }
 481 static DEVICE_ATTR_RW(hwevent_enable);
 482
 483 static ssize_t hwevent_select_show(struct device *dev,
 484                                    struct device_attribute *attr, char *buf)
 485 {
 486         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 487         unsigned long val = drvdata->stmhebsr;
 488
 489         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 490 }
 491
 492 static ssize_t hwevent_select_store(struct device *dev,
 493                                     struct device_attribute *attr,
 494                                     const char *buf, size_t size)
 495 {
 496         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 497         unsigned long val;
 498         int ret = 0;
 499
 500         ret = kstrtoul(buf, 16, &val);
 501         if (ret)
 502                 return -EINVAL;
 503
 504         drvdata->stmhebsr = val;
 505
 506         return size;
 507 }
 508 static DEVICE_ATTR_RW(hwevent_select);
 509
 510 static ssize_t port_select_show(struct device *dev,
 511                                 struct device_attribute *attr, char *buf)
 512 {
 513         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 514         unsigned long val;
 515
 516         if (!local_read(&drvdata->csdev->mode)) {
 517                 val = drvdata->stmspscr;
 518         } else {
 519                 spin_lock(&drvdata->spinlock);
 520                 val = readl_relaxed(drvdata->base + STMSPSCR);
 521                 spin_unlock(&drvdata->spinlock);
 522         }
 523
 524         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 525 }
 526
 527 static ssize_t port_select_store(struct device *dev,
 528                                  struct device_attribute *attr,
 529                                  const char *buf, size_t size)
 530 {
 531         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 532         unsigned long val, stmsper;
 533         int ret = 0;
 534
 535         ret = kstrtoul(buf, 16, &val);
 536         if (ret)
 537                 return ret;
 538
 539         spin_lock(&drvdata->spinlock);
 540         drvdata->stmspscr = val;
 541
 542         if (local_read(&drvdata->csdev->mode)) {
 543                 CS_UNLOCK(drvdata->base);
 544                 /* Process as per ARM's TRM recommendation */
 545                 stmsper = readl_relaxed(drvdata->base + STMSPER);
 546                 writel_relaxed(0x0, drvdata->base + STMSPER);
 547                 writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR);
 548                 writel_relaxed(stmsper, drvdata->base + STMSPER);
 549                 CS_LOCK(drvdata->base);
 550         }
 551         spin_unlock(&drvdata->spinlock);
 552
 553         return size;
 554 }
 555 static DEVICE_ATTR_RW(port_select);
 556
 557 static ssize_t port_enable_show(struct device *dev,
 558                                 struct device_attribute *attr, char *buf)
 559 {
 560         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 561         unsigned long val;
 562
 563         if (!local_read(&drvdata->csdev->mode)) {
 564                 val = drvdata->stmsper;
 565         } else {
 566                 spin_lock(&drvdata->spinlock);
 567                 val = readl_relaxed(drvdata->base + STMSPER);
 568                 spin_unlock(&drvdata->spinlock);
 569         }
 570
 571         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 572 }
 573
 574 static ssize_t port_enable_store(struct device *dev,
 575                                  struct device_attribute *attr,
 576                                  const char *buf, size_t size)
 577 {
 578         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 579         unsigned long val;
 580         int ret = 0;
 581
 582         ret = kstrtoul(buf, 16, &val);
 583         if (ret)
 584                 return ret;
 585
 586         spin_lock(&drvdata->spinlock);
 587         drvdata->stmsper = val;
 588
 589         if (local_read(&drvdata->csdev->mode)) {
 590                 CS_UNLOCK(drvdata->base);
 591                 writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER);
 592                 CS_LOCK(drvdata->base);
 593         }
 594         spin_unlock(&drvdata->spinlock);
 595
 596         return size;
 597 }
 598 static DEVICE_ATTR_RW(port_enable);
 599
 600 static ssize_t traceid_show(struct device *dev,
 601                             struct device_attribute *attr, char *buf)
 602 {
 603         unsigned long val;
 604         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 605
 606         val = drvdata->traceid;
 607         return sprintf(buf, "%#lx\n", val);
 608 }
 609 static DEVICE_ATTR_RO(traceid);
 610
 611 static struct attribute *coresight_stm_attrs[] = {
 612         &dev_attr_hwevent_enable.attr,
 613         &dev_attr_hwevent_select.attr,
 614         &dev_attr_port_enable.attr,
 615         &dev_attr_port_select.attr,
 616         &dev_attr_traceid.attr,
 617         NULL,
 618 };
 619
 620 static struct attribute *coresight_stm_mgmt_attrs[] = {
 621         coresight_simple_reg32(tcsr, STMTCSR),
 622         coresight_simple_reg32(tsfreqr, STMTSFREQR),
 623         coresight_simple_reg32(syncr, STMSYNCR),
 624         coresight_simple_reg32(sper, STMSPER),
 625         coresight_simple_reg32(spter, STMSPTER),
 626         coresight_simple_reg32(privmaskr, STMPRIVMASKR),
 627         coresight_simple_reg32(spscr, STMSPSCR),
 628         coresight_simple_reg32(spmscr, STMSPMSCR),
 629         coresight_simple_reg32(spfeat1r, STMSPFEAT1R),
 630         coresight_simple_reg32(spfeat2r, STMSPFEAT2R),
 631         coresight_simple_reg32(spfeat3r, STMSPFEAT3R),
 632         coresight_simple_reg32(devid, CORESIGHT_DEVID),
 633         NULL,
 634 };
 635
 636 static const struct attribute_group coresight_stm_group = {
 637         .attrs = coresight_stm_attrs,
 638 };
 639
 640 static const struct attribute_group coresight_stm_mgmt_group = {
 641         .attrs = coresight_stm_mgmt_attrs,
 642         .name = "mgmt",
 643 };
 644
 645 static const struct attribute_group *coresight_stm_groups[] = {
 646         &coresight_stm_group,
 647         &coresight_stm_mgmt_group,
 648         NULL,
 649 };
 650
 651 #ifdef CONFIG_OF
 652 static int of_stm_get_stimulus_area(struct device *dev, struct resource *res)
 653 {
 654         const char *name = NULL;
 655         int index = 0, found = 0;
 656         struct device_node *np = dev->of_node;
 657
 658         while (!of_property_read_string_index(np, "reg-names", index, &name)) {
 659                 if (strcmp("stm-stimulus-base", name)) {
 660                         index++;
 661                         continue;
 662                 }
 663
 664                 /* We have a match and @index is where it's at */
 665                 found = 1;
 666                 break;
 667         }
 668
 669         if (!found)
 670                 return -EINVAL;
 671
 672         return of_address_to_resource(np, index, res);
 673 }
 674 #else
 675 static inline int of_stm_get_stimulus_area(struct device *dev,
 676                                            struct resource *res)
 677 {
 678         return -ENOENT;
 679 }
 680 #endif
 681
 682 #ifdef CONFIG_ACPI
 683 static int acpi_stm_get_stimulus_area(struct device *dev, struct resource *res)
 684 {
 685         int rc;
 686         bool found_base = false;
 687         struct resource_entry *rent;
 688         LIST_HEAD(res_list);
 689
 690         struct acpi_device *adev = ACPI_COMPANION(dev);
 691
 692         rc = acpi_dev_get_resources(adev, &res_list, NULL, NULL);
 693         if (rc < 0)
 694                 return rc;
 695
 696         /*
 697          * The stimulus base for STM device must be listed as the second memory
 698          * resource, followed by the programming base address as described in
 699          * "Section 2.3 Resources" in ACPI for CoreSightTM 1.0 Platform Design
 700          * document (DEN0067).
 701          */
 702         rc = -ENOENT;
 703         list_for_each_entry(rent, &res_list, node) {
 704                 if (resource_type(rent->res) != IORESOURCE_MEM)
 705                         continue;
 706                 if (found_base) {
 707                         *res = *rent->res;
 708                         rc = 0;
 709                         break;
 710                 }
 711
 712                 found_base = true;
 713         }
 714
 715         acpi_dev_free_resource_list(&res_list);
 716         return rc;
 717 }
 718 #else
 719 static inline int acpi_stm_get_stimulus_area(struct device *dev,
 720                                              struct resource *res)
 721 {
 722         return -ENOENT;
 723 }
 724 #endif
 725
 726 static int stm_get_stimulus_area(struct device *dev, struct resource *res)
 727 {
 728         struct fwnode_handle *fwnode = dev_fwnode(dev);
 729
 730         if (is_of_node(fwnode))
 731                 return of_stm_get_stimulus_area(dev, res);
 732         else if (is_acpi_node(fwnode))
 733                 return acpi_stm_get_stimulus_area(dev, res);
 734         return -ENOENT;
 735 }
 736
 737 static u32 stm_fundamental_data_size(struct stm_drvdata *drvdata)
 738 {
 739         u32 stmspfeat2r;
 740
 741         if (!IS_ENABLED(CONFIG_64BIT))
 742                 return 4;
 743
 744         stmspfeat2r = readl_relaxed(drvdata->base + STMSPFEAT2R);
 745
 746         /*
 747          * bit[15:12] represents the fundamental data size
 748          * 0 - 32-bit data
 749          * 1 - 64-bit data
 750          */
 751         return BMVAL(stmspfeat2r, 12, 15) ? 8 : 4;
 752 }
 753
 754 static u32 stm_num_stimulus_port(struct stm_drvdata *drvdata)
 755 {
 756         u32 numsp;
 757
 758         numsp = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
 759         /*
 760          * NUMPS in STMDEVID is 17 bit long and if equal to 0x0,
 761          * 32 stimulus ports are supported.
 762          */
 763         numsp &= 0x1ffff;
 764         if (!numsp)
 765                 numsp = STM_32_CHANNEL;
 766         return numsp;
 767 }
 768
 769 static void stm_init_default_data(struct stm_drvdata *drvdata)
 770 {
 771         /* Don't use port selection */
 772         drvdata->stmspscr = 0x0;
 773         /*
 774          * Enable all channel regardless of their number.  When port
 775          * selection isn't used (see above) STMSPER applies to all
 776          * 32 channel group available, hence setting all 32 bits to 1
 777          */
 778         drvdata->stmsper = ~0x0;
 779
 780         /* Set invariant transaction timing on all channels */
 781         bitmap_clear(drvdata->chs.guaranteed, 0, drvdata->numsp);
 782 }
 783
 784 static void stm_init_generic_data(struct stm_drvdata *drvdata,
 785                                   const char *name)
 786 {
 787         drvdata->stm.name = name;
 788
 789         /*
 790          * MasterIDs are assigned at HW design phase. As such the core is
 791          * using a single master for interaction with this device.
 792          */
 793         drvdata->stm.sw_start = 1;
 794         drvdata->stm.sw_end = 1;
 795         drvdata->stm.hw_override = true;
 796         drvdata->stm.sw_nchannels = drvdata->numsp;
 797         drvdata->stm.sw_mmiosz = BYTES_PER_CHANNEL;
 798         drvdata->stm.packet = stm_generic_packet;
 799         drvdata->stm.mmio_addr = stm_mmio_addr;
 800         drvdata->stm.link = stm_generic_link;
 801         drvdata->stm.unlink = stm_generic_unlink;
 802         drvdata->stm.set_options = stm_generic_set_options;
 803 }
 804
 805 static int stm_probe(struct amba_device *adev, const struct amba_id *id)
 806 {
 807         int ret, trace_id;
 808         void __iomem *base;
 809         struct device *dev = &adev->dev;
 810         struct coresight_platform_data *pdata = NULL;
 811         struct stm_drvdata *drvdata;
 812         struct resource *res = &adev->res;
 813         struct resource ch_res;
 814         struct coresight_desc desc = { 0 };
 815
 816         desc.name = coresight_alloc_device_name(&stm_devs, dev);
 817         if (!desc.name)
 818                 return -ENOMEM;
 819
 820         drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
 821         if (!drvdata)
 822                 return -ENOMEM;
 823
 824         drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
 825         if (!IS_ERR(drvdata->atclk)) {
 826                 ret = clk_prepare_enable(drvdata->atclk);
 827                 if (ret)
 828                         return ret;
 829         }
 830         dev_set_drvdata(dev, drvdata);
 831
 832         base = devm_ioremap_resource(dev, res);
 833         if (IS_ERR(base))
 834                 return PTR_ERR(base);
 835         drvdata->base = base;
 836         desc.access = CSDEV_ACCESS_IOMEM(base);
 837
 838         ret = stm_get_stimulus_area(dev, &ch_res);
 839         if (ret)
 840                 return ret;
 841         drvdata->chs.phys = ch_res.start;
 842
 843         base = devm_ioremap_resource(dev, &ch_res);
 844         if (IS_ERR(base))
 845                 return PTR_ERR(base);
 846         drvdata->chs.base = base;
 847
 848         drvdata->write_bytes = stm_fundamental_data_size(drvdata);
 849
 850         if (boot_nr_channel)
 851                 drvdata->numsp = boot_nr_channel;
 852         else
 853                 drvdata->numsp = stm_num_stimulus_port(drvdata);
 854
 855         drvdata->chs.guaranteed = devm_bitmap_zalloc(dev, drvdata->numsp,
 856                                                      GFP_KERNEL);
 857         if (!drvdata->chs.guaranteed)
 858                 return -ENOMEM;
 859
 860         spin_lock_init(&drvdata->spinlock);
 861
 862         stm_init_default_data(drvdata);
 863         stm_init_generic_data(drvdata, desc.name);
 864
 865         if (stm_register_device(dev, &drvdata->stm, THIS_MODULE)) {
 866                 dev_info(dev,
 867                          "%s : stm_register_device failed, probing deferred\n",
 868                          desc.name);
 869                 return -EPROBE_DEFER;
 870         }
 871
 872         pdata = coresight_get_platform_data(dev);
 873         if (IS_ERR(pdata)) {
 874                 ret = PTR_ERR(pdata);
 875                 goto stm_unregister;
 876         }
 877         adev->dev.platform_data = pdata;
 878
 879         desc.type = CORESIGHT_DEV_TYPE_SOURCE;
 880         desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE;
 881         desc.ops = &stm_cs_ops;
 882         desc.pdata = pdata;
 883         desc.dev = dev;
 884         desc.groups = coresight_stm_groups;
 885         drvdata->csdev = coresight_register(&desc);
 886         if (IS_ERR(drvdata->csdev)) {
 887                 ret = PTR_ERR(drvdata->csdev);
 888                 goto stm_unregister;
 889         }
 890
 891         trace_id = coresight_trace_id_get_system_id();
 892         if (trace_id < 0) {
 893                 ret = trace_id;
 894                 goto cs_unregister;
 895         }
 896         drvdata->traceid = (u8)trace_id;
 897
 898         pm_runtime_put(&adev->dev);
 899
 900         dev_info(&drvdata->csdev->dev, "%s initialized\n",
 901                  (char *)coresight_get_uci_data(id));
 902         return 0;
 903
 904 cs_unregister:
 905         coresight_unregister(drvdata->csdev);
 906
 907 stm_unregister:
 908         stm_unregister_device(&drvdata->stm);
 909         return ret;
 910 }
 911
 912 static void stm_remove(struct amba_device *adev)
 913 {
 914         struct stm_drvdata *drvdata = dev_get_drvdata(&adev->dev);
 915
 916         coresight_trace_id_put_system_id(drvdata->traceid);
 917         coresight_unregister(drvdata->csdev);
 918
 919         stm_unregister_device(&drvdata->stm);
 920 }
 921
 922 #ifdef CONFIG_PM
 923 static int stm_runtime_suspend(struct device *dev)
 924 {
 925         struct stm_drvdata *drvdata = dev_get_drvdata(dev);
 926
 927         if (drvdata && !IS_ERR(drvdata->atclk))
 928                 clk_disable_unprepare(drvdata->atclk);
 929
 930         return 0;
 931 }
 932
 933 static int stm_runtime_resume(struct device *dev)
 934 {
 935         struct stm_drvdata *drvdata = dev_get_drvdata(dev);
 936
 937         if (drvdata && !IS_ERR(drvdata->atclk))
 938                 clk_prepare_enable(drvdata->atclk);
 939
 940         return 0;
 941 }
 942 #endif
 943
 944 static const struct dev_pm_ops stm_dev_pm_ops = {
 945         SET_RUNTIME_PM_OPS(stm_runtime_suspend, stm_runtime_resume, NULL)
 946 };
 947
 948 static const struct amba_id stm_ids[] = {
 949         CS_AMBA_ID_DATA(0x000bb962, "STM32"),
 950         CS_AMBA_ID_DATA(0x000bb963, "STM500"),
 951         { 0, 0, NULL },
 952 };
 953
 954 MODULE_DEVICE_TABLE(amba, stm_ids);
 955
 956 static struct amba_driver stm_driver = {
 957         .drv = {
 958                 .name   = "coresight-stm",
 959                 .owner  = THIS_MODULE,
 960                 .pm     = &stm_dev_pm_ops,
 961                 .suppress_bind_attrs = true,
 962         },
 963         .probe          = stm_probe,
 964         .remove         = stm_remove,
 965         .id_table       = stm_ids,
 966 };
 967
 968 module_amba_driver(stm_driver);
 969
 970 MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
 971 MODULE_DESCRIPTION("Arm CoreSight System Trace Macrocell driver");
 972 MODULE_LICENSE("GPL v2");