1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
5 * Description: CoreSight System Trace Macrocell driver
7 * Initial implementation by Pratik Patel
8 * (C) 2014-2015 Pratik Patel <pratikp@codeaurora.org>
10 * Serious refactoring, code cleanup and upgrading to the Coresight upstream
11 * framework by Mathieu Poirier
12 * (C) 2015-2016 Mathieu Poirier <mathieu.poirier@linaro.org>
14 * Guaranteed timing and support for various packet type coming from the
15 * generic STM API by Chunyan Zhang
16 * (C) 2015-2016 Chunyan Zhang <zhang.chunyan@linaro.org>
18 #include <asm/local.h>
19 #include <linux/amba/bus.h>
20 #include <linux/bitmap.h>
21 #include <linux/clk.h>
22 #include <linux/coresight.h>
23 #include <linux/coresight-stm.h>
24 #include <linux/err.h>
25 #include <linux/kernel.h>
26 #include <linux/moduleparam.h>
27 #include <linux/of_address.h>
28 #include <linux/perf_event.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/stm.h>
32 #include "coresight-priv.h"
34 #define STMDMASTARTR 0xc04
35 #define STMDMASTOPR 0xc08
36 #define STMDMASTATR 0xc0c
37 #define STMDMACTLR 0xc10
38 #define STMDMAIDR 0xcfc
40 #define STMHETER 0xd20
41 #define STMHEBSR 0xd60
42 #define STMHEMCR 0xd64
43 #define STMHEMASTR 0xdf4
44 #define STMHEFEAT1R 0xdf8
45 #define STMHEIDR 0xdfc
47 #define STMSPTER 0xe20
48 #define STMPRIVMASKR 0xe40
49 #define STMSPSCR 0xe60
50 #define STMSPMSCR 0xe64
51 #define STMSPOVERRIDER 0xe68
52 #define STMSPMOVERRIDER 0xe6c
53 #define STMSPTRIGCSR 0xe70
55 #define STMTSSTIMR 0xe84
56 #define STMTSFREQR 0xe8c
57 #define STMSYNCR 0xe90
58 #define STMAUXCR 0xe94
59 #define STMSPFEAT1R 0xea0
60 #define STMSPFEAT2R 0xea4
61 #define STMSPFEAT3R 0xea8
62 #define STMITTRIGGER 0xee8
63 #define STMITATBDATA0 0xeec
64 #define STMITATBCTR2 0xef0
65 #define STMITATBID 0xef4
66 #define STMITATBCTR0 0xef8
68 #define STM_32_CHANNEL 32
69 #define BYTES_PER_CHANNEL 256
70 #define STM_TRACE_BUF_SIZE 4096
71 #define STM_SW_MASTER_END 127
73 /* Register bit definition */
74 #define STMTCSR_BUSY_BIT 23
75 /* Reserve the first 10 channels for kernel usage */
76 #define STM_CHANNEL_OFFSET 0
79 STM_PKT_TYPE_DATA = 0x98,
80 STM_PKT_TYPE_FLAG = 0xE8,
81 STM_PKT_TYPE_TRIG = 0xF8,
84 #define stm_channel_addr(drvdata, ch) (drvdata->chs.base + \
85 (ch * BYTES_PER_CHANNEL))
86 #define stm_channel_off(type, opts) (type & ~opts)
88 static int boot_nr_channel;
91 * Not really modular but using module_param is the easiest way to
92 * remain consistent with existing use cases for now.
95 boot_nr_channel, boot_nr_channel, int, S_IRUGO
99 * struct channel_space - central management entity for extended ports
100 * @base: memory mapped base address where channels start.
101 * @phys: physical base address of channel region.
102 * @guaraneed: is the channel delivery guaranteed.
104 struct channel_space {
107 unsigned long *guaranteed;
111 * struct stm_drvdata - specifics associated to an STM component
112 * @base: memory mapped base address for this component.
113 * @atclk: optional clock for the core parts of the STM.
114 * @csdev: component vitals needed by the framework.
115 * @spinlock: only one at a time pls.
116 * @chs: the channels accociated to this STM.
117 * @stm: structure associated to the generic STM interface.
118 * @mode: this tracer's mode, i.e sysFS, or disabled.
119 * @traceid: value of the current ID for this component.
120 * @write_bytes: Maximus bytes this STM can write at a time.
121 * @stmsper: settings for register STMSPER.
122 * @stmspscr: settings for register STMSPSCR.
123 * @numsp: the total number of stimulus port support by this STM.
124 * @stmheer: settings for register STMHEER.
125 * @stmheter: settings for register STMHETER.
126 * @stmhebsr: settings for register STMHEBSR.
131 struct coresight_device *csdev;
133 struct channel_space chs;
146 static void stm_hwevent_enable_hw(struct stm_drvdata *drvdata)
148 CS_UNLOCK(drvdata->base);
150 writel_relaxed(drvdata->stmhebsr, drvdata->base + STMHEBSR);
151 writel_relaxed(drvdata->stmheter, drvdata->base + STMHETER);
152 writel_relaxed(drvdata->stmheer, drvdata->base + STMHEER);
153 writel_relaxed(0x01 | /* Enable HW event tracing */
154 0x04, /* Error detection on event tracing */
155 drvdata->base + STMHEMCR);
157 CS_LOCK(drvdata->base);
160 static void stm_port_enable_hw(struct stm_drvdata *drvdata)
162 CS_UNLOCK(drvdata->base);
163 /* ATB trigger enable on direct writes to TRIG locations */
165 drvdata->base + STMSPTRIGCSR);
166 writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR);
167 writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER);
169 CS_LOCK(drvdata->base);
172 static void stm_enable_hw(struct stm_drvdata *drvdata)
174 if (drvdata->stmheer)
175 stm_hwevent_enable_hw(drvdata);
177 stm_port_enable_hw(drvdata);
179 CS_UNLOCK(drvdata->base);
181 /* 4096 byte between synchronisation packets */
182 writel_relaxed(0xFFF, drvdata->base + STMSYNCR);
183 writel_relaxed((drvdata->traceid << 16 | /* trace id */
184 0x02 | /* timestamp enable */
185 0x01), /* global STM enable */
186 drvdata->base + STMTCSR);
188 CS_LOCK(drvdata->base);
191 static int stm_enable(struct coresight_device *csdev,
192 struct perf_event *event, u32 mode)
195 struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
197 if (mode != CS_MODE_SYSFS)
200 val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
202 /* Someone is already using the tracer */
206 pm_runtime_get_sync(csdev->dev.parent);
208 spin_lock(&drvdata->spinlock);
209 stm_enable_hw(drvdata);
210 spin_unlock(&drvdata->spinlock);
212 dev_dbg(&csdev->dev, "STM tracing enabled\n");
216 static void stm_hwevent_disable_hw(struct stm_drvdata *drvdata)
218 CS_UNLOCK(drvdata->base);
220 writel_relaxed(0x0, drvdata->base + STMHEMCR);
221 writel_relaxed(0x0, drvdata->base + STMHEER);
222 writel_relaxed(0x0, drvdata->base + STMHETER);
224 CS_LOCK(drvdata->base);
227 static void stm_port_disable_hw(struct stm_drvdata *drvdata)
229 CS_UNLOCK(drvdata->base);
231 writel_relaxed(0x0, drvdata->base + STMSPER);
232 writel_relaxed(0x0, drvdata->base + STMSPTRIGCSR);
234 CS_LOCK(drvdata->base);
237 static void stm_disable_hw(struct stm_drvdata *drvdata)
241 CS_UNLOCK(drvdata->base);
243 val = readl_relaxed(drvdata->base + STMTCSR);
244 val &= ~0x1; /* clear global STM enable [0] */
245 writel_relaxed(val, drvdata->base + STMTCSR);
247 CS_LOCK(drvdata->base);
249 stm_port_disable_hw(drvdata);
250 if (drvdata->stmheer)
251 stm_hwevent_disable_hw(drvdata);
254 static void stm_disable(struct coresight_device *csdev,
255 struct perf_event *event)
257 struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
260 * For as long as the tracer isn't disabled another entity can't
261 * change its status. As such we can read the status here without
262 * fearing it will change under us.
264 if (local_read(&drvdata->mode) == CS_MODE_SYSFS) {
265 spin_lock(&drvdata->spinlock);
266 stm_disable_hw(drvdata);
267 spin_unlock(&drvdata->spinlock);
269 /* Wait until the engine has completely stopped */
270 coresight_timeout(drvdata->base, STMTCSR, STMTCSR_BUSY_BIT, 0);
272 pm_runtime_put(csdev->dev.parent);
274 local_set(&drvdata->mode, CS_MODE_DISABLED);
275 dev_dbg(&csdev->dev, "STM tracing disabled\n");
279 static int stm_trace_id(struct coresight_device *csdev)
281 struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
283 return drvdata->traceid;
286 static const struct coresight_ops_source stm_source_ops = {
287 .trace_id = stm_trace_id,
288 .enable = stm_enable,
289 .disable = stm_disable,
292 static const struct coresight_ops stm_cs_ops = {
293 .source_ops = &stm_source_ops,
296 static inline bool stm_addr_unaligned(const void *addr, u8 write_bytes)
298 return ((unsigned long)addr & (write_bytes - 1));
301 static void stm_send(void __iomem *addr, const void *data,
302 u32 size, u8 write_bytes)
306 if (stm_addr_unaligned(data, write_bytes)) {
307 memcpy(paload, data, size);
311 /* now we are 64bit/32bit aligned */
315 writeq_relaxed(*(u64 *)data, addr);
319 writel_relaxed(*(u32 *)data, addr);
322 writew_relaxed(*(u16 *)data, addr);
325 writeb_relaxed(*(u8 *)data, addr);
332 static int stm_generic_link(struct stm_data *stm_data,
333 unsigned int master, unsigned int channel)
335 struct stm_drvdata *drvdata = container_of(stm_data,
336 struct stm_drvdata, stm);
337 if (!drvdata || !drvdata->csdev)
340 return coresight_enable(drvdata->csdev);
343 static void stm_generic_unlink(struct stm_data *stm_data,
344 unsigned int master, unsigned int channel)
346 struct stm_drvdata *drvdata = container_of(stm_data,
347 struct stm_drvdata, stm);
348 if (!drvdata || !drvdata->csdev)
351 coresight_disable(drvdata->csdev);
355 stm_mmio_addr(struct stm_data *stm_data, unsigned int master,
356 unsigned int channel, unsigned int nr_chans)
358 struct stm_drvdata *drvdata = container_of(stm_data,
359 struct stm_drvdata, stm);
362 addr = drvdata->chs.phys + channel * BYTES_PER_CHANNEL;
364 if (offset_in_page(addr) ||
365 offset_in_page(nr_chans * BYTES_PER_CHANNEL))
371 static long stm_generic_set_options(struct stm_data *stm_data,
373 unsigned int channel,
374 unsigned int nr_chans,
375 unsigned long options)
377 struct stm_drvdata *drvdata = container_of(stm_data,
378 struct stm_drvdata, stm);
379 if (!(drvdata && local_read(&drvdata->mode)))
382 if (channel >= drvdata->numsp)
386 case STM_OPTION_GUARANTEED:
387 set_bit(channel, drvdata->chs.guaranteed);
390 case STM_OPTION_INVARIANT:
391 clear_bit(channel, drvdata->chs.guaranteed);
401 static ssize_t notrace stm_generic_packet(struct stm_data *stm_data,
403 unsigned int channel,
407 const unsigned char *payload)
409 void __iomem *ch_addr;
410 struct stm_drvdata *drvdata = container_of(stm_data,
411 struct stm_drvdata, stm);
413 if (!(drvdata && local_read(&drvdata->mode)))
416 if (channel >= drvdata->numsp)
419 ch_addr = stm_channel_addr(drvdata, channel);
421 flags = (flags == STP_PACKET_TIMESTAMPED) ? STM_FLAG_TIMESTAMPED : 0;
422 flags |= test_bit(channel, drvdata->chs.guaranteed) ?
423 STM_FLAG_GUARANTEED : 0;
425 if (size > drvdata->write_bytes)
426 size = drvdata->write_bytes;
428 size = rounddown_pow_of_two(size);
431 case STP_PACKET_FLAG:
432 ch_addr += stm_channel_off(STM_PKT_TYPE_FLAG, flags);
435 * The generic STM core sets a size of '0' on flag packets.
436 * As such send a flag packet of size '1' and tell the
439 stm_send(ch_addr, payload, 1, drvdata->write_bytes);
443 case STP_PACKET_DATA:
444 ch_addr += stm_channel_off(STM_PKT_TYPE_DATA, flags);
445 stm_send(ch_addr, payload, size,
446 drvdata->write_bytes);
456 static ssize_t hwevent_enable_show(struct device *dev,
457 struct device_attribute *attr, char *buf)
459 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
460 unsigned long val = drvdata->stmheer;
462 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
465 static ssize_t hwevent_enable_store(struct device *dev,
466 struct device_attribute *attr,
467 const char *buf, size_t size)
469 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
473 ret = kstrtoul(buf, 16, &val);
477 drvdata->stmheer = val;
478 /* HW event enable and trigger go hand in hand */
479 drvdata->stmheter = val;
483 static DEVICE_ATTR_RW(hwevent_enable);
485 static ssize_t hwevent_select_show(struct device *dev,
486 struct device_attribute *attr, char *buf)
488 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
489 unsigned long val = drvdata->stmhebsr;
491 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
494 static ssize_t hwevent_select_store(struct device *dev,
495 struct device_attribute *attr,
496 const char *buf, size_t size)
498 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
502 ret = kstrtoul(buf, 16, &val);
506 drvdata->stmhebsr = val;
510 static DEVICE_ATTR_RW(hwevent_select);
512 static ssize_t port_select_show(struct device *dev,
513 struct device_attribute *attr, char *buf)
515 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
518 if (!local_read(&drvdata->mode)) {
519 val = drvdata->stmspscr;
521 spin_lock(&drvdata->spinlock);
522 val = readl_relaxed(drvdata->base + STMSPSCR);
523 spin_unlock(&drvdata->spinlock);
526 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
529 static ssize_t port_select_store(struct device *dev,
530 struct device_attribute *attr,
531 const char *buf, size_t size)
533 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
534 unsigned long val, stmsper;
537 ret = kstrtoul(buf, 16, &val);
541 spin_lock(&drvdata->spinlock);
542 drvdata->stmspscr = val;
544 if (local_read(&drvdata->mode)) {
545 CS_UNLOCK(drvdata->base);
546 /* Process as per ARM's TRM recommendation */
547 stmsper = readl_relaxed(drvdata->base + STMSPER);
548 writel_relaxed(0x0, drvdata->base + STMSPER);
549 writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR);
550 writel_relaxed(stmsper, drvdata->base + STMSPER);
551 CS_LOCK(drvdata->base);
553 spin_unlock(&drvdata->spinlock);
557 static DEVICE_ATTR_RW(port_select);
559 static ssize_t port_enable_show(struct device *dev,
560 struct device_attribute *attr, char *buf)
562 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
565 if (!local_read(&drvdata->mode)) {
566 val = drvdata->stmsper;
568 spin_lock(&drvdata->spinlock);
569 val = readl_relaxed(drvdata->base + STMSPER);
570 spin_unlock(&drvdata->spinlock);
573 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
576 static ssize_t port_enable_store(struct device *dev,
577 struct device_attribute *attr,
578 const char *buf, size_t size)
580 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
584 ret = kstrtoul(buf, 16, &val);
588 spin_lock(&drvdata->spinlock);
589 drvdata->stmsper = val;
591 if (local_read(&drvdata->mode)) {
592 CS_UNLOCK(drvdata->base);
593 writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER);
594 CS_LOCK(drvdata->base);
596 spin_unlock(&drvdata->spinlock);
600 static DEVICE_ATTR_RW(port_enable);
602 static ssize_t traceid_show(struct device *dev,
603 struct device_attribute *attr, char *buf)
606 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
608 val = drvdata->traceid;
609 return sprintf(buf, "%#lx\n", val);
612 static ssize_t traceid_store(struct device *dev,
613 struct device_attribute *attr,
614 const char *buf, size_t size)
618 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
620 ret = kstrtoul(buf, 16, &val);
624 /* traceid field is 7bit wide on STM32 */
625 drvdata->traceid = val & 0x7f;
628 static DEVICE_ATTR_RW(traceid);
630 #define coresight_stm_reg(name, offset) \
631 coresight_simple_reg32(struct stm_drvdata, name, offset)
633 coresight_stm_reg(tcsr, STMTCSR);
634 coresight_stm_reg(tsfreqr, STMTSFREQR);
635 coresight_stm_reg(syncr, STMSYNCR);
636 coresight_stm_reg(sper, STMSPER);
637 coresight_stm_reg(spter, STMSPTER);
638 coresight_stm_reg(privmaskr, STMPRIVMASKR);
639 coresight_stm_reg(spscr, STMSPSCR);
640 coresight_stm_reg(spmscr, STMSPMSCR);
641 coresight_stm_reg(spfeat1r, STMSPFEAT1R);
642 coresight_stm_reg(spfeat2r, STMSPFEAT2R);
643 coresight_stm_reg(spfeat3r, STMSPFEAT3R);
644 coresight_stm_reg(devid, CORESIGHT_DEVID);
646 static struct attribute *coresight_stm_attrs[] = {
647 &dev_attr_hwevent_enable.attr,
648 &dev_attr_hwevent_select.attr,
649 &dev_attr_port_enable.attr,
650 &dev_attr_port_select.attr,
651 &dev_attr_traceid.attr,
655 static struct attribute *coresight_stm_mgmt_attrs[] = {
657 &dev_attr_tsfreqr.attr,
658 &dev_attr_syncr.attr,
660 &dev_attr_spter.attr,
661 &dev_attr_privmaskr.attr,
662 &dev_attr_spscr.attr,
663 &dev_attr_spmscr.attr,
664 &dev_attr_spfeat1r.attr,
665 &dev_attr_spfeat2r.attr,
666 &dev_attr_spfeat3r.attr,
667 &dev_attr_devid.attr,
671 static const struct attribute_group coresight_stm_group = {
672 .attrs = coresight_stm_attrs,
675 static const struct attribute_group coresight_stm_mgmt_group = {
676 .attrs = coresight_stm_mgmt_attrs,
680 static const struct attribute_group *coresight_stm_groups[] = {
681 &coresight_stm_group,
682 &coresight_stm_mgmt_group,
687 static int of_stm_get_stimulus_area(struct device *dev, struct resource *res)
689 const char *name = NULL;
690 int index = 0, found = 0;
691 struct device_node *np = dev->of_node;
693 while (!of_property_read_string_index(np, "reg-names", index, &name)) {
694 if (strcmp("stm-stimulus-base", name)) {
699 /* We have a match and @index is where it's at */
707 return of_address_to_resource(np, index, res);
710 static inline int of_stm_get_stimulus_area(struct device *dev,
711 struct resource *res)
717 static int stm_get_stimulus_area(struct device *dev, struct resource *res)
719 if (is_of_node(dev_fwnode(dev)))
720 return of_stm_get_stimulus_area(dev, res);
724 static u32 stm_fundamental_data_size(struct stm_drvdata *drvdata)
728 if (!IS_ENABLED(CONFIG_64BIT))
731 stmspfeat2r = readl_relaxed(drvdata->base + STMSPFEAT2R);
734 * bit[15:12] represents the fundamental data size
738 return BMVAL(stmspfeat2r, 12, 15) ? 8 : 4;
741 static u32 stm_num_stimulus_port(struct stm_drvdata *drvdata)
745 numsp = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
747 * NUMPS in STMDEVID is 17 bit long and if equal to 0x0,
748 * 32 stimulus ports are supported.
752 numsp = STM_32_CHANNEL;
756 static void stm_init_default_data(struct stm_drvdata *drvdata)
758 /* Don't use port selection */
759 drvdata->stmspscr = 0x0;
761 * Enable all channel regardless of their number. When port
762 * selection isn't used (see above) STMSPER applies to all
763 * 32 channel group available, hence setting all 32 bits to 1
765 drvdata->stmsper = ~0x0;
768 * The trace ID value for *ETM* tracers start at CPU_ID * 2 + 0x10 and
769 * anything equal to or higher than 0x70 is reserved. Since 0x00 is
770 * also reserved the STM trace ID needs to be higher than 0x00 and
773 drvdata->traceid = 0x1;
775 /* Set invariant transaction timing on all channels */
776 bitmap_clear(drvdata->chs.guaranteed, 0, drvdata->numsp);
779 static void stm_init_generic_data(struct stm_drvdata *drvdata,
782 drvdata->stm.name = name;
785 * MasterIDs are assigned at HW design phase. As such the core is
786 * using a single master for interaction with this device.
788 drvdata->stm.sw_start = 1;
789 drvdata->stm.sw_end = 1;
790 drvdata->stm.hw_override = true;
791 drvdata->stm.sw_nchannels = drvdata->numsp;
792 drvdata->stm.sw_mmiosz = BYTES_PER_CHANNEL;
793 drvdata->stm.packet = stm_generic_packet;
794 drvdata->stm.mmio_addr = stm_mmio_addr;
795 drvdata->stm.link = stm_generic_link;
796 drvdata->stm.unlink = stm_generic_unlink;
797 drvdata->stm.set_options = stm_generic_set_options;
800 static int stm_probe(struct amba_device *adev, const struct amba_id *id)
804 unsigned long *guaranteed;
805 struct device *dev = &adev->dev;
806 struct coresight_platform_data *pdata = NULL;
807 struct stm_drvdata *drvdata;
808 struct resource *res = &adev->res;
809 struct resource ch_res;
811 struct coresight_desc desc = { 0 };
813 pdata = coresight_get_platform_data(dev);
815 return PTR_ERR(pdata);
816 adev->dev.platform_data = pdata;
817 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
821 drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
822 if (!IS_ERR(drvdata->atclk)) {
823 ret = clk_prepare_enable(drvdata->atclk);
827 dev_set_drvdata(dev, drvdata);
829 base = devm_ioremap_resource(dev, res);
831 return PTR_ERR(base);
832 drvdata->base = base;
834 ret = stm_get_stimulus_area(dev, &ch_res);
837 drvdata->chs.phys = ch_res.start;
839 base = devm_ioremap_resource(dev, &ch_res);
841 return PTR_ERR(base);
842 drvdata->chs.base = base;
844 drvdata->write_bytes = stm_fundamental_data_size(drvdata);
847 drvdata->numsp = boot_nr_channel;
849 drvdata->numsp = stm_num_stimulus_port(drvdata);
851 bitmap_size = BITS_TO_LONGS(drvdata->numsp) * sizeof(long);
853 guaranteed = devm_kzalloc(dev, bitmap_size, GFP_KERNEL);
856 drvdata->chs.guaranteed = guaranteed;
858 spin_lock_init(&drvdata->spinlock);
860 stm_init_default_data(drvdata);
861 stm_init_generic_data(drvdata, dev_name(dev));
863 if (stm_register_device(dev, &drvdata->stm, THIS_MODULE)) {
865 "stm_register_device failed, probing deferred\n");
866 return -EPROBE_DEFER;
869 desc.type = CORESIGHT_DEV_TYPE_SOURCE;
870 desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE;
871 desc.ops = &stm_cs_ops;
874 desc.name = dev_name(dev);
875 desc.groups = coresight_stm_groups;
876 drvdata->csdev = coresight_register(&desc);
877 if (IS_ERR(drvdata->csdev)) {
878 ret = PTR_ERR(drvdata->csdev);
882 pm_runtime_put(&adev->dev);
884 dev_info(&drvdata->csdev->dev, "%s initialized\n",
885 (char *)coresight_get_uci_data(id));
889 stm_unregister_device(&drvdata->stm);
894 static int stm_runtime_suspend(struct device *dev)
896 struct stm_drvdata *drvdata = dev_get_drvdata(dev);
898 if (drvdata && !IS_ERR(drvdata->atclk))
899 clk_disable_unprepare(drvdata->atclk);
904 static int stm_runtime_resume(struct device *dev)
906 struct stm_drvdata *drvdata = dev_get_drvdata(dev);
908 if (drvdata && !IS_ERR(drvdata->atclk))
909 clk_prepare_enable(drvdata->atclk);
915 static const struct dev_pm_ops stm_dev_pm_ops = {
916 SET_RUNTIME_PM_OPS(stm_runtime_suspend, stm_runtime_resume, NULL)
919 static const struct amba_id stm_ids[] = {
920 CS_AMBA_ID_DATA(0x000bb962, "STM32"),
921 CS_AMBA_ID_DATA(0x000bb963, "STM500"),
925 static struct amba_driver stm_driver = {
927 .name = "coresight-stm",
928 .owner = THIS_MODULE,
929 .pm = &stm_dev_pm_ops,
930 .suppress_bind_attrs = true,
936 builtin_amba_driver(stm_driver);