drivers/hwtracing/coresight/coresight-etm4x.c

   1 /* Copyright (c) 2014, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/moduleparam.h>
  15 #include <linux/init.h>
  16 #include <linux/types.h>
  17 #include <linux/device.h>
  18 #include <linux/io.h>
  19 #include <linux/err.h>
  20 #include <linux/fs.h>
  21 #include <linux/slab.h>
  22 #include <linux/delay.h>
  23 #include <linux/smp.h>
  24 #include <linux/sysfs.h>
  25 #include <linux/stat.h>
  26 #include <linux/clk.h>
  27 #include <linux/cpu.h>
  28 #include <linux/coresight.h>
  29 #include <linux/coresight-pmu.h>
  30 #include <linux/pm_wakeup.h>
  31 #include <linux/amba/bus.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/uaccess.h>
  34 #include <linux/perf_event.h>
  35 #include <linux/pm_runtime.h>
  36 #include <asm/sections.h>
  37 #include <asm/local.h>
  38
  39 #include "coresight-etm4x.h"
  40 #include "coresight-etm-perf.h"
  41
  42 static int boot_enable;
  43 module_param_named(boot_enable, boot_enable, int, S_IRUGO);
  44
  45 /* The number of ETMv4 currently registered */
  46 static int etm4_count;
  47 static struct etmv4_drvdata *etmdrvdata[NR_CPUS];
  48 static void etm4_set_default_config(struct etmv4_config *config);
  49 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
  50                                   struct perf_event *event);
  51
  52 static enum cpuhp_state hp_online;
  53
  54 static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
  55 {
  56         /* Writing any value to ETMOSLAR unlocks the trace registers */
  57         writel_relaxed(0x0, drvdata->base + TRCOSLAR);
  58         drvdata->os_unlock = true;
  59         isb();
  60 }
  61
  62 static bool etm4_arch_supported(u8 arch)
  63 {
  64         switch (arch) {
  65         case ETM_ARCH_V4:
  66                 break;
  67         default:
  68                 return false;
  69         }
  70         return true;
  71 }
  72
  73 static int etm4_cpu_id(struct coresight_device *csdev)
  74 {
  75         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  76
  77         return drvdata->cpu;
  78 }
  79
  80 static int etm4_trace_id(struct coresight_device *csdev)
  81 {
  82         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  83
  84         return drvdata->trcid;
  85 }
  86
  87 static void etm4_enable_hw(void *info)
  88 {
  89         int i;
  90         struct etmv4_drvdata *drvdata = info;
  91         struct etmv4_config *config = &drvdata->config;
  92
  93         CS_UNLOCK(drvdata->base);
  94
  95         etm4_os_unlock(drvdata);
  96
  97         /* Disable the trace unit before programming trace registers */
  98         writel_relaxed(0, drvdata->base + TRCPRGCTLR);
  99
 100         /* wait for TRCSTATR.IDLE to go up */
 101         if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
 102                 dev_err(drvdata->dev,
 103                         "timeout while waiting for Idle Trace Status\n");
 104
 105         writel_relaxed(config->pe_sel, drvdata->base + TRCPROCSELR);
 106         writel_relaxed(config->cfg, drvdata->base + TRCCONFIGR);
 107         /* nothing specific implemented */
 108         writel_relaxed(0x0, drvdata->base + TRCAUXCTLR);
 109         writel_relaxed(config->eventctrl0, drvdata->base + TRCEVENTCTL0R);
 110         writel_relaxed(config->eventctrl1, drvdata->base + TRCEVENTCTL1R);
 111         writel_relaxed(config->stall_ctrl, drvdata->base + TRCSTALLCTLR);
 112         writel_relaxed(config->ts_ctrl, drvdata->base + TRCTSCTLR);
 113         writel_relaxed(config->syncfreq, drvdata->base + TRCSYNCPR);
 114         writel_relaxed(config->ccctlr, drvdata->base + TRCCCCTLR);
 115         writel_relaxed(config->bb_ctrl, drvdata->base + TRCBBCTLR);
 116         writel_relaxed(drvdata->trcid, drvdata->base + TRCTRACEIDR);
 117         writel_relaxed(config->vinst_ctrl, drvdata->base + TRCVICTLR);
 118         writel_relaxed(config->viiectlr, drvdata->base + TRCVIIECTLR);
 119         writel_relaxed(config->vissctlr,
 120                        drvdata->base + TRCVISSCTLR);
 121         writel_relaxed(config->vipcssctlr,
 122                        drvdata->base + TRCVIPCSSCTLR);
 123         for (i = 0; i < drvdata->nrseqstate - 1; i++)
 124                 writel_relaxed(config->seq_ctrl[i],
 125                                drvdata->base + TRCSEQEVRn(i));
 126         writel_relaxed(config->seq_rst, drvdata->base + TRCSEQRSTEVR);
 127         writel_relaxed(config->seq_state, drvdata->base + TRCSEQSTR);
 128         writel_relaxed(config->ext_inp, drvdata->base + TRCEXTINSELR);
 129         for (i = 0; i < drvdata->nr_cntr; i++) {
 130                 writel_relaxed(config->cntrldvr[i],
 131                                drvdata->base + TRCCNTRLDVRn(i));
 132                 writel_relaxed(config->cntr_ctrl[i],
 133                                drvdata->base + TRCCNTCTLRn(i));
 134                 writel_relaxed(config->cntr_val[i],
 135                                drvdata->base + TRCCNTVRn(i));
 136         }
 137
 138         /* Resource selector pair 0 is always implemented and reserved */
 139         for (i = 0; i < drvdata->nr_resource * 2; i++)
 140                 writel_relaxed(config->res_ctrl[i],
 141                                drvdata->base + TRCRSCTLRn(i));
 142
 143         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
 144                 writel_relaxed(config->ss_ctrl[i],
 145                                drvdata->base + TRCSSCCRn(i));
 146                 writel_relaxed(config->ss_status[i],
 147                                drvdata->base + TRCSSCSRn(i));
 148                 writel_relaxed(config->ss_pe_cmp[i],
 149                                drvdata->base + TRCSSPCICRn(i));
 150         }
 151         for (i = 0; i < drvdata->nr_addr_cmp; i++) {
 152                 writeq_relaxed(config->addr_val[i],
 153                                drvdata->base + TRCACVRn(i));
 154                 writeq_relaxed(config->addr_acc[i],
 155                                drvdata->base + TRCACATRn(i));
 156         }
 157         for (i = 0; i < drvdata->numcidc; i++)
 158                 writeq_relaxed(config->ctxid_pid[i],
 159                                drvdata->base + TRCCIDCVRn(i));
 160         writel_relaxed(config->ctxid_mask0, drvdata->base + TRCCIDCCTLR0);
 161         writel_relaxed(config->ctxid_mask1, drvdata->base + TRCCIDCCTLR1);
 162
 163         for (i = 0; i < drvdata->numvmidc; i++)
 164                 writeq_relaxed(config->vmid_val[i],
 165                                drvdata->base + TRCVMIDCVRn(i));
 166         writel_relaxed(config->vmid_mask0, drvdata->base + TRCVMIDCCTLR0);
 167         writel_relaxed(config->vmid_mask1, drvdata->base + TRCVMIDCCTLR1);
 168
 169         /*
 170          * Request to keep the trace unit powered and also
 171          * emulation of powerdown
 172          */
 173         writel_relaxed(readl_relaxed(drvdata->base + TRCPDCR) | TRCPDCR_PU,
 174                        drvdata->base + TRCPDCR);
 175
 176         /* Enable the trace unit */
 177         writel_relaxed(1, drvdata->base + TRCPRGCTLR);
 178
 179         /* wait for TRCSTATR.IDLE to go back down to '0' */
 180         if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
 181                 dev_err(drvdata->dev,
 182                         "timeout while waiting for Idle Trace Status\n");
 183
 184         CS_LOCK(drvdata->base);
 185
 186         dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu);
 187 }
 188
 189 static int etm4_parse_event_config(struct etmv4_drvdata *drvdata,
 190                                    struct perf_event *event)
 191 {
 192         int ret = 0;
 193         struct etmv4_config *config = &drvdata->config;
 194         struct perf_event_attr *attr = &event->attr;
 195
 196         if (!attr) {
 197                 ret = -EINVAL;
 198                 goto out;
 199         }
 200
 201         /* Clear configuration from previous run */
 202         memset(config, 0, sizeof(struct etmv4_config));
 203
 204         if (attr->exclude_kernel)
 205                 config->mode = ETM_MODE_EXCL_KERN;
 206
 207         if (attr->exclude_user)
 208                 config->mode = ETM_MODE_EXCL_USER;
 209
 210         /* Always start from the default config */
 211         etm4_set_default_config(config);
 212
 213         /* Configure filters specified on the perf cmd line, if any. */
 214         ret = etm4_set_event_filters(drvdata, event);
 215         if (ret)
 216                 goto out;
 217
 218         /* Go from generic option to ETMv4 specifics */
 219         if (attr->config & BIT(ETM_OPT_CYCACC)) {
 220                 config->cfg |= BIT(4);
 221                 /* TRM: Must program this for cycacc to work */
 222                 config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT;
 223         }
 224         if (attr->config & BIT(ETM_OPT_TS))
 225                 /* bit[11], Global timestamp tracing bit */
 226                 config->cfg |= BIT(11);
 227
 228 out:
 229         return ret;
 230 }
 231
 232 static int etm4_enable_perf(struct coresight_device *csdev,
 233                             struct perf_event *event)
 234 {
 235         int ret = 0;
 236         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 237
 238         if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) {
 239                 ret = -EINVAL;
 240                 goto out;
 241         }
 242
 243         /* Configure the tracer based on the session's specifics */
 244         ret = etm4_parse_event_config(drvdata, event);
 245         if (ret)
 246                 goto out;
 247         /* And enable it */
 248         etm4_enable_hw(drvdata);
 249
 250 out:
 251         return ret;
 252 }
 253
 254 static int etm4_enable_sysfs(struct coresight_device *csdev)
 255 {
 256         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 257         int ret;
 258
 259         spin_lock(&drvdata->spinlock);
 260
 261         /*
 262          * Executing etm4_enable_hw on the cpu whose ETM is being enabled
 263          * ensures that register writes occur when cpu is powered.
 264          */
 265         ret = smp_call_function_single(drvdata->cpu,
 266                                        etm4_enable_hw, drvdata, 1);
 267         if (ret)
 268                 goto err;
 269
 270         drvdata->sticky_enable = true;
 271         spin_unlock(&drvdata->spinlock);
 272
 273         dev_info(drvdata->dev, "ETM tracing enabled\n");
 274         return 0;
 275
 276 err:
 277         spin_unlock(&drvdata->spinlock);
 278         return ret;
 279 }
 280
 281 static int etm4_enable(struct coresight_device *csdev,
 282                        struct perf_event *event, u32 mode)
 283 {
 284         int ret;
 285         u32 val;
 286         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 287
 288         val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
 289
 290         /* Someone is already using the tracer */
 291         if (val)
 292                 return -EBUSY;
 293
 294         switch (mode) {
 295         case CS_MODE_SYSFS:
 296                 ret = etm4_enable_sysfs(csdev);
 297                 break;
 298         case CS_MODE_PERF:
 299                 ret = etm4_enable_perf(csdev, event);
 300                 break;
 301         default:
 302                 ret = -EINVAL;
 303         }
 304
 305         /* The tracer didn't start */
 306         if (ret)
 307                 local_set(&drvdata->mode, CS_MODE_DISABLED);
 308
 309         return ret;
 310 }
 311
 312 static void etm4_disable_hw(void *info)
 313 {
 314         u32 control;
 315         struct etmv4_drvdata *drvdata = info;
 316
 317         CS_UNLOCK(drvdata->base);
 318
 319         /* power can be removed from the trace unit now */
 320         control = readl_relaxed(drvdata->base + TRCPDCR);
 321         control &= ~TRCPDCR_PU;
 322         writel_relaxed(control, drvdata->base + TRCPDCR);
 323
 324         control = readl_relaxed(drvdata->base + TRCPRGCTLR);
 325
 326         /* EN, bit[0] Trace unit enable bit */
 327         control &= ~0x1;
 328
 329         /* make sure everything completes before disabling */
 330         mb();
 331         isb();
 332         writel_relaxed(control, drvdata->base + TRCPRGCTLR);
 333
 334         CS_LOCK(drvdata->base);
 335
 336         dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu);
 337 }
 338
 339 static int etm4_disable_perf(struct coresight_device *csdev,
 340                              struct perf_event *event)
 341 {
 342         u32 control;
 343         struct etm_filters *filters = event->hw.addr_filters;
 344         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 345
 346         if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
 347                 return -EINVAL;
 348
 349         etm4_disable_hw(drvdata);
 350
 351         /*
 352          * Check if the start/stop logic was active when the unit was stopped.
 353          * That way we can re-enable the start/stop logic when the process is
 354          * scheduled again.  Configuration of the start/stop logic happens in
 355          * function etm4_set_event_filters().
 356          */
 357         control = readl_relaxed(drvdata->base + TRCVICTLR);
 358         /* TRCVICTLR::SSSTATUS, bit[9] */
 359         filters->ssstatus = (control & BIT(9));
 360
 361         return 0;
 362 }
 363
 364 static void etm4_disable_sysfs(struct coresight_device *csdev)
 365 {
 366         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 367
 368         /*
 369          * Taking hotplug lock here protects from clocks getting disabled
 370          * with tracing being left on (crash scenario) if user disable occurs
 371          * after cpu online mask indicates the cpu is offline but before the
 372          * DYING hotplug callback is serviced by the ETM driver.
 373          */
 374         cpus_read_lock();
 375         spin_lock(&drvdata->spinlock);
 376
 377         /*
 378          * Executing etm4_disable_hw on the cpu whose ETM is being disabled
 379          * ensures that register writes occur when cpu is powered.
 380          */
 381         smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1);
 382
 383         spin_unlock(&drvdata->spinlock);
 384         cpus_read_unlock();
 385
 386         dev_info(drvdata->dev, "ETM tracing disabled\n");
 387 }
 388
 389 static void etm4_disable(struct coresight_device *csdev,
 390                          struct perf_event *event)
 391 {
 392         u32 mode;
 393         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 394
 395         /*
 396          * For as long as the tracer isn't disabled another entity can't
 397          * change its status.  As such we can read the status here without
 398          * fearing it will change under us.
 399          */
 400         mode = local_read(&drvdata->mode);
 401
 402         switch (mode) {
 403         case CS_MODE_DISABLED:
 404                 break;
 405         case CS_MODE_SYSFS:
 406                 etm4_disable_sysfs(csdev);
 407                 break;
 408         case CS_MODE_PERF:
 409                 etm4_disable_perf(csdev, event);
 410                 break;
 411         }
 412
 413         if (mode)
 414                 local_set(&drvdata->mode, CS_MODE_DISABLED);
 415 }
 416
 417 static const struct coresight_ops_source etm4_source_ops = {
 418         .cpu_id         = etm4_cpu_id,
 419         .trace_id       = etm4_trace_id,
 420         .enable         = etm4_enable,
 421         .disable        = etm4_disable,
 422 };
 423
 424 static const struct coresight_ops etm4_cs_ops = {
 425         .source_ops     = &etm4_source_ops,
 426 };
 427
 428 static void etm4_init_arch_data(void *info)
 429 {
 430         u32 etmidr0;
 431         u32 etmidr1;
 432         u32 etmidr2;
 433         u32 etmidr3;
 434         u32 etmidr4;
 435         u32 etmidr5;
 436         struct etmv4_drvdata *drvdata = info;
 437
 438         /* Make sure all registers are accessible */
 439         etm4_os_unlock(drvdata);
 440
 441         CS_UNLOCK(drvdata->base);
 442
 443         /* find all capabilities of the tracing unit */
 444         etmidr0 = readl_relaxed(drvdata->base + TRCIDR0);
 445
 446         /* INSTP0, bits[2:1] P0 tracing support field */
 447         if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2))
 448                 drvdata->instrp0 = true;
 449         else
 450                 drvdata->instrp0 = false;
 451
 452         /* TRCBB, bit[5] Branch broadcast tracing support bit */
 453         if (BMVAL(etmidr0, 5, 5))
 454                 drvdata->trcbb = true;
 455         else
 456                 drvdata->trcbb = false;
 457
 458         /* TRCCOND, bit[6] Conditional instruction tracing support bit */
 459         if (BMVAL(etmidr0, 6, 6))
 460                 drvdata->trccond = true;
 461         else
 462                 drvdata->trccond = false;
 463
 464         /* TRCCCI, bit[7] Cycle counting instruction bit */
 465         if (BMVAL(etmidr0, 7, 7))
 466                 drvdata->trccci = true;
 467         else
 468                 drvdata->trccci = false;
 469
 470         /* RETSTACK, bit[9] Return stack bit */
 471         if (BMVAL(etmidr0, 9, 9))
 472                 drvdata->retstack = true;
 473         else
 474                 drvdata->retstack = false;
 475
 476         /* NUMEVENT, bits[11:10] Number of events field */
 477         drvdata->nr_event = BMVAL(etmidr0, 10, 11);
 478         /* QSUPP, bits[16:15] Q element support field */
 479         drvdata->q_support = BMVAL(etmidr0, 15, 16);
 480         /* TSSIZE, bits[28:24] Global timestamp size field */
 481         drvdata->ts_size = BMVAL(etmidr0, 24, 28);
 482
 483         /* base architecture of trace unit */
 484         etmidr1 = readl_relaxed(drvdata->base + TRCIDR1);
 485         /*
 486          * TRCARCHMIN, bits[7:4] architecture the minor version number
 487          * TRCARCHMAJ, bits[11:8] architecture major versin number
 488          */
 489         drvdata->arch = BMVAL(etmidr1, 4, 11);
 490
 491         /* maximum size of resources */
 492         etmidr2 = readl_relaxed(drvdata->base + TRCIDR2);
 493         /* CIDSIZE, bits[9:5] Indicates the Context ID size */
 494         drvdata->ctxid_size = BMVAL(etmidr2, 5, 9);
 495         /* VMIDSIZE, bits[14:10] Indicates the VMID size */
 496         drvdata->vmid_size = BMVAL(etmidr2, 10, 14);
 497         /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
 498         drvdata->ccsize = BMVAL(etmidr2, 25, 28);
 499
 500         etmidr3 = readl_relaxed(drvdata->base + TRCIDR3);
 501         /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
 502         drvdata->ccitmin = BMVAL(etmidr3, 0, 11);
 503         /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
 504         drvdata->s_ex_level = BMVAL(etmidr3, 16, 19);
 505         /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
 506         drvdata->ns_ex_level = BMVAL(etmidr3, 20, 23);
 507
 508         /*
 509          * TRCERR, bit[24] whether a trace unit can trace a
 510          * system error exception.
 511          */
 512         if (BMVAL(etmidr3, 24, 24))
 513                 drvdata->trc_error = true;
 514         else
 515                 drvdata->trc_error = false;
 516
 517         /* SYNCPR, bit[25] implementation has a fixed synchronization period? */
 518         if (BMVAL(etmidr3, 25, 25))
 519                 drvdata->syncpr = true;
 520         else
 521                 drvdata->syncpr = false;
 522
 523         /* STALLCTL, bit[26] is stall control implemented? */
 524         if (BMVAL(etmidr3, 26, 26))
 525                 drvdata->stallctl = true;
 526         else
 527                 drvdata->stallctl = false;
 528
 529         /* SYSSTALL, bit[27] implementation can support stall control? */
 530         if (BMVAL(etmidr3, 27, 27))
 531                 drvdata->sysstall = true;
 532         else
 533                 drvdata->sysstall = false;
 534
 535         /* NUMPROC, bits[30:28] the number of PEs available for tracing */
 536         drvdata->nr_pe = BMVAL(etmidr3, 28, 30);
 537
 538         /* NOOVERFLOW, bit[31] is trace overflow prevention supported */
 539         if (BMVAL(etmidr3, 31, 31))
 540                 drvdata->nooverflow = true;
 541         else
 542                 drvdata->nooverflow = false;
 543
 544         /* number of resources trace unit supports */
 545         etmidr4 = readl_relaxed(drvdata->base + TRCIDR4);
 546         /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
 547         drvdata->nr_addr_cmp = BMVAL(etmidr4, 0, 3);
 548         /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
 549         drvdata->nr_pe_cmp = BMVAL(etmidr4, 12, 15);
 550         /*
 551          * NUMRSPAIR, bits[19:16]
 552          * The number of resource pairs conveyed by the HW starts at 0, i.e a
 553          * value of 0x0 indicate 1 resource pair, 0x1 indicate two and so on.
 554          * As such add 1 to the value of NUMRSPAIR for a better representation.
 555          */
 556         drvdata->nr_resource = BMVAL(etmidr4, 16, 19) + 1;
 557         /*
 558          * NUMSSCC, bits[23:20] the number of single-shot
 559          * comparator control for tracing
 560          */
 561         drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23);
 562         /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
 563         drvdata->numcidc = BMVAL(etmidr4, 24, 27);
 564         /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
 565         drvdata->numvmidc = BMVAL(etmidr4, 28, 31);
 566
 567         etmidr5 = readl_relaxed(drvdata->base + TRCIDR5);
 568         /* NUMEXTIN, bits[8:0] number of external inputs implemented */
 569         drvdata->nr_ext_inp = BMVAL(etmidr5, 0, 8);
 570         /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
 571         drvdata->trcid_size = BMVAL(etmidr5, 16, 21);
 572         /* ATBTRIG, bit[22] implementation can support ATB triggers? */
 573         if (BMVAL(etmidr5, 22, 22))
 574                 drvdata->atbtrig = true;
 575         else
 576                 drvdata->atbtrig = false;
 577         /*
 578          * LPOVERRIDE, bit[23] implementation supports
 579          * low-power state override
 580          */
 581         if (BMVAL(etmidr5, 23, 23))
 582                 drvdata->lpoverride = true;
 583         else
 584                 drvdata->lpoverride = false;
 585         /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
 586         drvdata->nrseqstate = BMVAL(etmidr5, 25, 27);
 587         /* NUMCNTR, bits[30:28] number of counters available for tracing */
 588         drvdata->nr_cntr = BMVAL(etmidr5, 28, 30);
 589         CS_LOCK(drvdata->base);
 590 }
 591
 592 static void etm4_set_default_config(struct etmv4_config *config)
 593 {
 594         /* disable all events tracing */
 595         config->eventctrl0 = 0x0;
 596         config->eventctrl1 = 0x0;
 597
 598         /* disable stalling */
 599         config->stall_ctrl = 0x0;
 600
 601         /* enable trace synchronization every 4096 bytes, if available */
 602         config->syncfreq = 0xC;
 603
 604         /* disable timestamp event */
 605         config->ts_ctrl = 0x0;
 606
 607         /* TRCVICTLR::EVENT = 0x01, select the always on logic */
 608         config->vinst_ctrl |= BIT(0);
 609 }
 610
 611 static u64 etm4_get_access_type(struct etmv4_config *config)
 612 {
 613         u64 access_type = 0;
 614
 615         /*
 616          * EXLEVEL_NS, bits[15:12]
 617          * The Exception levels are:
 618          *   Bit[12] Exception level 0 - Application
 619          *   Bit[13] Exception level 1 - OS
 620          *   Bit[14] Exception level 2 - Hypervisor
 621          *   Bit[15] Never implemented
 622          *
 623          * Always stay away from hypervisor mode.
 624          */
 625         access_type = ETM_EXLEVEL_NS_HYP;
 626
 627         if (config->mode & ETM_MODE_EXCL_KERN)
 628                 access_type |= ETM_EXLEVEL_NS_OS;
 629
 630         if (config->mode & ETM_MODE_EXCL_USER)
 631                 access_type |= ETM_EXLEVEL_NS_APP;
 632
 633         /*
 634          * EXLEVEL_S, bits[11:8], don't trace anything happening
 635          * in secure state.
 636          */
 637         access_type |= (ETM_EXLEVEL_S_APP       |
 638                         ETM_EXLEVEL_S_OS        |
 639                         ETM_EXLEVEL_S_HYP);
 640
 641         return access_type;
 642 }
 643
 644 static void etm4_set_comparator_filter(struct etmv4_config *config,
 645                                        u64 start, u64 stop, int comparator)
 646 {
 647         u64 access_type = etm4_get_access_type(config);
 648
 649         /* First half of default address comparator */
 650         config->addr_val[comparator] = start;
 651         config->addr_acc[comparator] = access_type;
 652         config->addr_type[comparator] = ETM_ADDR_TYPE_RANGE;
 653
 654         /* Second half of default address comparator */
 655         config->addr_val[comparator + 1] = stop;
 656         config->addr_acc[comparator + 1] = access_type;
 657         config->addr_type[comparator + 1] = ETM_ADDR_TYPE_RANGE;
 658
 659         /*
 660          * Configure the ViewInst function to include this address range
 661          * comparator.
 662          *
 663          * @comparator is divided by two since it is the index in the
 664          * etmv4_config::addr_val array but register TRCVIIECTLR deals with
 665          * address range comparator _pairs_.
 666          *
 667          * Therefore:
 668          *      index 0 -> compatator pair 0
 669          *      index 2 -> comparator pair 1
 670          *      index 4 -> comparator pair 2
 671          *      ...
 672          *      index 14 -> comparator pair 7
 673          */
 674         config->viiectlr |= BIT(comparator / 2);
 675 }
 676
 677 static void etm4_set_start_stop_filter(struct etmv4_config *config,
 678                                        u64 address, int comparator,
 679                                        enum etm_addr_type type)
 680 {
 681         int shift;
 682         u64 access_type = etm4_get_access_type(config);
 683
 684         /* Configure the comparator */
 685         config->addr_val[comparator] = address;
 686         config->addr_acc[comparator] = access_type;
 687         config->addr_type[comparator] = type;
 688
 689         /*
 690          * Configure ViewInst Start-Stop control register.
 691          * Addresses configured to start tracing go from bit 0 to n-1,
 692          * while those configured to stop tracing from 16 to 16 + n-1.
 693          */
 694         shift = (type == ETM_ADDR_TYPE_START ? 0 : 16);
 695         config->vissctlr |= BIT(shift + comparator);
 696 }
 697
 698 static void etm4_set_default_filter(struct etmv4_config *config)
 699 {
 700         u64 start, stop;
 701
 702         /*
 703          * Configure address range comparator '0' to encompass all
 704          * possible addresses.
 705          */
 706         start = 0x0;
 707         stop = ~0x0;
 708
 709         etm4_set_comparator_filter(config, start, stop,
 710                                    ETM_DEFAULT_ADDR_COMP);
 711
 712         /*
 713          * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
 714          * in the started state
 715          */
 716         config->vinst_ctrl |= BIT(9);
 717
 718         /* No start-stop filtering for ViewInst */
 719         config->vissctlr = 0x0;
 720 }
 721
 722 static void etm4_set_default(struct etmv4_config *config)
 723 {
 724         if (WARN_ON_ONCE(!config))
 725                 return;
 726
 727         /*
 728          * Make default initialisation trace everything
 729          *
 730          * Select the "always true" resource selector on the
 731          * "Enablign Event" line and configure address range comparator
 732          * '0' to trace all the possible address range.  From there
 733          * configure the "include/exclude" engine to include address
 734          * range comparator '0'.
 735          */
 736         etm4_set_default_config(config);
 737         etm4_set_default_filter(config);
 738 }
 739
 740 static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type)
 741 {
 742         int nr_comparator, index = 0;
 743         struct etmv4_config *config = &drvdata->config;
 744
 745         /*
 746          * nr_addr_cmp holds the number of comparator _pair_, so time 2
 747          * for the total number of comparators.
 748          */
 749         nr_comparator = drvdata->nr_addr_cmp * 2;
 750
 751         /* Go through the tally of comparators looking for a free one. */
 752         while (index < nr_comparator) {
 753                 switch (type) {
 754                 case ETM_ADDR_TYPE_RANGE:
 755                         if (config->addr_type[index] == ETM_ADDR_TYPE_NONE &&
 756                             config->addr_type[index + 1] == ETM_ADDR_TYPE_NONE)
 757                                 return index;
 758
 759                         /* Address range comparators go in pairs */
 760                         index += 2;
 761                         break;
 762                 case ETM_ADDR_TYPE_START:
 763                 case ETM_ADDR_TYPE_STOP:
 764                         if (config->addr_type[index] == ETM_ADDR_TYPE_NONE)
 765                                 return index;
 766
 767                         /* Start/stop address can have odd indexes */
 768                         index += 1;
 769                         break;
 770                 default:
 771                         return -EINVAL;
 772                 }
 773         }
 774
 775         /* If we are here all the comparators have been used. */
 776         return -ENOSPC;
 777 }
 778
 779 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
 780                                   struct perf_event *event)
 781 {
 782         int i, comparator, ret = 0;
 783         u64 address;
 784         struct etmv4_config *config = &drvdata->config;
 785         struct etm_filters *filters = event->hw.addr_filters;
 786
 787         if (!filters)
 788                 goto default_filter;
 789
 790         /* Sync events with what Perf got */
 791         perf_event_addr_filters_sync(event);
 792
 793         /*
 794          * If there are no filters to deal with simply go ahead with
 795          * the default filter, i.e the entire address range.
 796          */
 797         if (!filters->nr_filters)
 798                 goto default_filter;
 799
 800         for (i = 0; i < filters->nr_filters; i++) {
 801                 struct etm_filter *filter = &filters->etm_filter[i];
 802                 enum etm_addr_type type = filter->type;
 803
 804                 /* See if a comparator is free. */
 805                 comparator = etm4_get_next_comparator(drvdata, type);
 806                 if (comparator < 0) {
 807                         ret = comparator;
 808                         goto out;
 809                 }
 810
 811                 switch (type) {
 812                 case ETM_ADDR_TYPE_RANGE:
 813                         etm4_set_comparator_filter(config,
 814                                                    filter->start_addr,
 815                                                    filter->stop_addr,
 816                                                    comparator);
 817                         /*
 818                          * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
 819                          * in the started state
 820                          */
 821                         config->vinst_ctrl |= BIT(9);
 822
 823                         /* No start-stop filtering for ViewInst */
 824                         config->vissctlr = 0x0;
 825                         break;
 826                 case ETM_ADDR_TYPE_START:
 827                 case ETM_ADDR_TYPE_STOP:
 828                         /* Get the right start or stop address */
 829                         address = (type == ETM_ADDR_TYPE_START ?
 830                                    filter->start_addr :
 831                                    filter->stop_addr);
 832
 833                         /* Configure comparator */
 834                         etm4_set_start_stop_filter(config, address,
 835                                                    comparator, type);
 836
 837                         /*
 838                          * If filters::ssstatus == 1, trace acquisition was
 839                          * started but the process was yanked away before the
 840                          * the stop address was hit.  As such the start/stop
 841                          * logic needs to be re-started so that tracing can
 842                          * resume where it left.
 843                          *
 844                          * The start/stop logic status when a process is
 845                          * scheduled out is checked in function
 846                          * etm4_disable_perf().
 847                          */
 848                         if (filters->ssstatus)
 849                                 config->vinst_ctrl |= BIT(9);
 850
 851                         /* No include/exclude filtering for ViewInst */
 852                         config->viiectlr = 0x0;
 853                         break;
 854                 default:
 855                         ret = -EINVAL;
 856                         goto out;
 857                 }
 858         }
 859
 860         goto out;
 861
 862
 863 default_filter:
 864         etm4_set_default_filter(config);
 865
 866 out:
 867         return ret;
 868 }
 869
 870 void etm4_config_trace_mode(struct etmv4_config *config)
 871 {
 872         u32 addr_acc, mode;
 873
 874         mode = config->mode;
 875         mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
 876
 877         /* excluding kernel AND user space doesn't make sense */
 878         WARN_ON_ONCE(mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER));
 879
 880         /* nothing to do if neither flags are set */
 881         if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
 882                 return;
 883
 884         addr_acc = config->addr_acc[ETM_DEFAULT_ADDR_COMP];
 885         /* clear default config */
 886         addr_acc &= ~(ETM_EXLEVEL_NS_APP | ETM_EXLEVEL_NS_OS);
 887
 888         /*
 889          * EXLEVEL_NS, bits[15:12]
 890          * The Exception levels are:
 891          *   Bit[12] Exception level 0 - Application
 892          *   Bit[13] Exception level 1 - OS
 893          *   Bit[14] Exception level 2 - Hypervisor
 894          *   Bit[15] Never implemented
 895          */
 896         if (mode & ETM_MODE_EXCL_KERN)
 897                 addr_acc |= ETM_EXLEVEL_NS_OS;
 898         else
 899                 addr_acc |= ETM_EXLEVEL_NS_APP;
 900
 901         config->addr_acc[ETM_DEFAULT_ADDR_COMP] = addr_acc;
 902         config->addr_acc[ETM_DEFAULT_ADDR_COMP + 1] = addr_acc;
 903 }
 904
 905 static int etm4_online_cpu(unsigned int cpu)
 906 {
 907         if (!etmdrvdata[cpu])
 908                 return 0;
 909
 910         if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable)
 911                 coresight_enable(etmdrvdata[cpu]->csdev);
 912         return 0;
 913 }
 914
 915 static int etm4_starting_cpu(unsigned int cpu)
 916 {
 917         if (!etmdrvdata[cpu])
 918                 return 0;
 919
 920         spin_lock(&etmdrvdata[cpu]->spinlock);
 921         if (!etmdrvdata[cpu]->os_unlock) {
 922                 etm4_os_unlock(etmdrvdata[cpu]);
 923                 etmdrvdata[cpu]->os_unlock = true;
 924         }
 925
 926         if (local_read(&etmdrvdata[cpu]->mode))
 927                 etm4_enable_hw(etmdrvdata[cpu]);
 928         spin_unlock(&etmdrvdata[cpu]->spinlock);
 929         return 0;
 930 }
 931
 932 static int etm4_dying_cpu(unsigned int cpu)
 933 {
 934         if (!etmdrvdata[cpu])
 935                 return 0;
 936
 937         spin_lock(&etmdrvdata[cpu]->spinlock);
 938         if (local_read(&etmdrvdata[cpu]->mode))
 939                 etm4_disable_hw(etmdrvdata[cpu]);
 940         spin_unlock(&etmdrvdata[cpu]->spinlock);
 941         return 0;
 942 }
 943
 944 static void etm4_init_trace_id(struct etmv4_drvdata *drvdata)
 945 {
 946         drvdata->trcid = coresight_get_trace_id(drvdata->cpu);
 947 }
 948
 949 static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
 950 {
 951         int ret;
 952         void __iomem *base;
 953         struct device *dev = &adev->dev;
 954         struct coresight_platform_data *pdata = NULL;
 955         struct etmv4_drvdata *drvdata;
 956         struct resource *res = &adev->res;
 957         struct coresight_desc desc = { 0 };
 958         struct device_node *np = adev->dev.of_node;
 959
 960         drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
 961         if (!drvdata)
 962                 return -ENOMEM;
 963
 964         if (np) {
 965                 pdata = of_get_coresight_platform_data(dev, np);
 966                 if (IS_ERR(pdata))
 967                         return PTR_ERR(pdata);
 968                 adev->dev.platform_data = pdata;
 969         }
 970
 971         drvdata->dev = &adev->dev;
 972         dev_set_drvdata(dev, drvdata);
 973
 974         /* Validity for the resource is already checked by the AMBA core */
 975         base = devm_ioremap_resource(dev, res);
 976         if (IS_ERR(base))
 977                 return PTR_ERR(base);
 978
 979         drvdata->base = base;
 980
 981         spin_lock_init(&drvdata->spinlock);
 982
 983         drvdata->cpu = pdata ? pdata->cpu : 0;
 984
 985         cpus_read_lock();
 986         etmdrvdata[drvdata->cpu] = drvdata;
 987
 988         if (smp_call_function_single(drvdata->cpu,
 989                                 etm4_init_arch_data,  drvdata, 1))
 990                 dev_err(dev, "ETM arch init failed\n");
 991
 992         if (!etm4_count++) {
 993                 cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ARM_CORESIGHT_STARTING,
 994                                                      "arm/coresight4:starting",
 995                                                      etm4_starting_cpu, etm4_dying_cpu);
 996                 ret = cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ONLINE_DYN,
 997                                                            "arm/coresight4:online",
 998                                                            etm4_online_cpu, NULL);
 999                 if (ret < 0)
1000                         goto err_arch_supported;
1001                 hp_online = ret;
1002         }
1003
1004         cpus_read_unlock();
1005
1006         if (etm4_arch_supported(drvdata->arch) == false) {
1007                 ret = -EINVAL;
1008                 goto err_arch_supported;
1009         }
1010
1011         etm4_init_trace_id(drvdata);
1012         etm4_set_default(&drvdata->config);
1013
1014         desc.type = CORESIGHT_DEV_TYPE_SOURCE;
1015         desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
1016         desc.ops = &etm4_cs_ops;
1017         desc.pdata = pdata;
1018         desc.dev = dev;
1019         desc.groups = coresight_etmv4_groups;
1020         drvdata->csdev = coresight_register(&desc);
1021         if (IS_ERR(drvdata->csdev)) {
1022                 ret = PTR_ERR(drvdata->csdev);
1023                 goto err_arch_supported;
1024         }
1025
1026         ret = etm_perf_symlink(drvdata->csdev, true);
1027         if (ret) {
1028                 coresight_unregister(drvdata->csdev);
1029                 goto err_arch_supported;
1030         }
1031
1032         pm_runtime_put(&adev->dev);
1033         dev_info(dev, "%s initialized\n", (char *)id->data);
1034
1035         if (boot_enable) {
1036                 coresight_enable(drvdata->csdev);
1037                 drvdata->boot_enable = true;
1038         }
1039
1040         return 0;
1041
1042 err_arch_supported:
1043         if (--etm4_count == 0) {
1044                 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
1045                 if (hp_online)
1046                         cpuhp_remove_state_nocalls(hp_online);
1047         }
1048         return ret;
1049 }
1050
1051 static struct amba_id etm4_ids[] = {
1052         {       /* ETM 4.0 - Cortex-A53  */
1053                 .id     = 0x000bb95d,
1054                 .mask   = 0x000fffff,
1055                 .data   = "ETM 4.0",
1056         },
1057         {       /* ETM 4.0 - Cortex-A57 */
1058                 .id     = 0x000bb95e,
1059                 .mask   = 0x000fffff,
1060                 .data   = "ETM 4.0",
1061         },
1062         {       /* ETM 4.0 - A72, Maia, HiSilicon */
1063                 .id = 0x000bb95a,
1064                 .mask = 0x000fffff,
1065                 .data = "ETM 4.0",
1066         },
1067         { 0, 0},
1068 };
1069
1070 static struct amba_driver etm4x_driver = {
1071         .drv = {
1072                 .name   = "coresight-etm4x",
1073                 .suppress_bind_attrs = true,
1074         },
1075         .probe          = etm4_probe,
1076         .id_table       = etm4_ids,
1077 };
1078 builtin_amba_driver(etm4x_driver);