drivers/hwtracing/coresight/coresight-etm4x.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/moduleparam.h>
   8 #include <linux/init.h>
   9 #include <linux/types.h>
  10 #include <linux/device.h>
  11 #include <linux/io.h>
  12 #include <linux/err.h>
  13 #include <linux/fs.h>
  14 #include <linux/slab.h>
  15 #include <linux/delay.h>
  16 #include <linux/smp.h>
  17 #include <linux/sysfs.h>
  18 #include <linux/stat.h>
  19 #include <linux/clk.h>
  20 #include <linux/cpu.h>
  21 #include <linux/cpu_pm.h>
  22 #include <linux/coresight.h>
  23 #include <linux/coresight-pmu.h>
  24 #include <linux/pm_wakeup.h>
  25 #include <linux/amba/bus.h>
  26 #include <linux/seq_file.h>
  27 #include <linux/uaccess.h>
  28 #include <linux/perf_event.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/property.h>
  31 #include <asm/sections.h>
  32 #include <asm/local.h>
  33 #include <asm/virt.h>
  34
  35 #include "coresight-etm4x.h"
  36 #include "coresight-etm-perf.h"
  37
  38 static int boot_enable;
  39 module_param(boot_enable, int, 0444);
  40 MODULE_PARM_DESC(boot_enable, "Enable tracing on boot");
  41
  42 #define PARAM_PM_SAVE_FIRMWARE    0 /* save self-hosted state as per firmware */
  43 #define PARAM_PM_SAVE_NEVER       1 /* never save any state */
  44 #define PARAM_PM_SAVE_SELF_HOSTED 2 /* save self-hosted state only */
  45
  46 static int pm_save_enable = PARAM_PM_SAVE_FIRMWARE;
  47 module_param(pm_save_enable, int, 0444);
  48 MODULE_PARM_DESC(pm_save_enable,
  49         "Save/restore state on power down: 1 = never, 2 = self-hosted");
  50
  51 /* The number of ETMv4 currently registered */
  52 static int etm4_count;
  53 static struct etmv4_drvdata *etmdrvdata[NR_CPUS];
  54 static void etm4_set_default_config(struct etmv4_config *config);
  55 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
  56                                   struct perf_event *event);
  57
  58 static enum cpuhp_state hp_online;
  59
  60 static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
  61 {
  62         /* Writing 0 to TRCOSLAR unlocks the trace registers */
  63         writel_relaxed(0x0, drvdata->base + TRCOSLAR);
  64         drvdata->os_unlock = true;
  65         isb();
  66 }
  67
  68 static void etm4_os_lock(struct etmv4_drvdata *drvdata)
  69 {
  70         /* Writing 0x1 to TRCOSLAR locks the trace registers */
  71         writel_relaxed(0x1, drvdata->base + TRCOSLAR);
  72         drvdata->os_unlock = false;
  73         isb();
  74 }
  75
  76 static bool etm4_arch_supported(u8 arch)
  77 {
  78         /* Mask out the minor version number */
  79         switch (arch & 0xf0) {
  80         case ETM_ARCH_V4:
  81                 break;
  82         default:
  83                 return false;
  84         }
  85         return true;
  86 }
  87
  88 static int etm4_cpu_id(struct coresight_device *csdev)
  89 {
  90         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  91
  92         return drvdata->cpu;
  93 }
  94
  95 static int etm4_trace_id(struct coresight_device *csdev)
  96 {
  97         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  98
  99         return drvdata->trcid;
 100 }
 101
 102 struct etm4_enable_arg {
 103         struct etmv4_drvdata *drvdata;
 104         int rc;
 105 };
 106
 107 static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
 108 {
 109         int i, rc;
 110         struct etmv4_config *config = &drvdata->config;
 111         struct device *etm_dev = &drvdata->csdev->dev;
 112
 113         CS_UNLOCK(drvdata->base);
 114
 115         etm4_os_unlock(drvdata);
 116
 117         rc = coresight_claim_device_unlocked(drvdata->base);
 118         if (rc)
 119                 goto done;
 120
 121         /* Disable the trace unit before programming trace registers */
 122         writel_relaxed(0, drvdata->base + TRCPRGCTLR);
 123
 124         /* wait for TRCSTATR.IDLE to go up */
 125         if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
 126                 dev_err(etm_dev,
 127                         "timeout while waiting for Idle Trace Status\n");
 128
 129         writel_relaxed(config->pe_sel, drvdata->base + TRCPROCSELR);
 130         writel_relaxed(config->cfg, drvdata->base + TRCCONFIGR);
 131         /* nothing specific implemented */
 132         writel_relaxed(0x0, drvdata->base + TRCAUXCTLR);
 133         writel_relaxed(config->eventctrl0, drvdata->base + TRCEVENTCTL0R);
 134         writel_relaxed(config->eventctrl1, drvdata->base + TRCEVENTCTL1R);
 135         writel_relaxed(config->stall_ctrl, drvdata->base + TRCSTALLCTLR);
 136         writel_relaxed(config->ts_ctrl, drvdata->base + TRCTSCTLR);
 137         writel_relaxed(config->syncfreq, drvdata->base + TRCSYNCPR);
 138         writel_relaxed(config->ccctlr, drvdata->base + TRCCCCTLR);
 139         writel_relaxed(config->bb_ctrl, drvdata->base + TRCBBCTLR);
 140         writel_relaxed(drvdata->trcid, drvdata->base + TRCTRACEIDR);
 141         writel_relaxed(config->vinst_ctrl, drvdata->base + TRCVICTLR);
 142         writel_relaxed(config->viiectlr, drvdata->base + TRCVIIECTLR);
 143         writel_relaxed(config->vissctlr,
 144                        drvdata->base + TRCVISSCTLR);
 145         writel_relaxed(config->vipcssctlr,
 146                        drvdata->base + TRCVIPCSSCTLR);
 147         for (i = 0; i < drvdata->nrseqstate - 1; i++)
 148                 writel_relaxed(config->seq_ctrl[i],
 149                                drvdata->base + TRCSEQEVRn(i));
 150         writel_relaxed(config->seq_rst, drvdata->base + TRCSEQRSTEVR);
 151         writel_relaxed(config->seq_state, drvdata->base + TRCSEQSTR);
 152         writel_relaxed(config->ext_inp, drvdata->base + TRCEXTINSELR);
 153         for (i = 0; i < drvdata->nr_cntr; i++) {
 154                 writel_relaxed(config->cntrldvr[i],
 155                                drvdata->base + TRCCNTRLDVRn(i));
 156                 writel_relaxed(config->cntr_ctrl[i],
 157                                drvdata->base + TRCCNTCTLRn(i));
 158                 writel_relaxed(config->cntr_val[i],
 159                                drvdata->base + TRCCNTVRn(i));
 160         }
 161
 162         /*
 163          * Resource selector pair 0 is always implemented and reserved.  As
 164          * such start at 2.
 165          */
 166         for (i = 2; i < drvdata->nr_resource * 2; i++)
 167                 writel_relaxed(config->res_ctrl[i],
 168                                drvdata->base + TRCRSCTLRn(i));
 169
 170         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
 171                 /* always clear status bit on restart if using single-shot */
 172                 if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
 173                         config->ss_status[i] &= ~BIT(31);
 174                 writel_relaxed(config->ss_ctrl[i],
 175                                drvdata->base + TRCSSCCRn(i));
 176                 writel_relaxed(config->ss_status[i],
 177                                drvdata->base + TRCSSCSRn(i));
 178                 writel_relaxed(config->ss_pe_cmp[i],
 179                                drvdata->base + TRCSSPCICRn(i));
 180         }
 181         for (i = 0; i < drvdata->nr_addr_cmp; i++) {
 182                 writeq_relaxed(config->addr_val[i],
 183                                drvdata->base + TRCACVRn(i));
 184                 writeq_relaxed(config->addr_acc[i],
 185                                drvdata->base + TRCACATRn(i));
 186         }
 187         for (i = 0; i < drvdata->numcidc; i++)
 188                 writeq_relaxed(config->ctxid_pid[i],
 189                                drvdata->base + TRCCIDCVRn(i));
 190         writel_relaxed(config->ctxid_mask0, drvdata->base + TRCCIDCCTLR0);
 191         writel_relaxed(config->ctxid_mask1, drvdata->base + TRCCIDCCTLR1);
 192
 193         for (i = 0; i < drvdata->numvmidc; i++)
 194                 writeq_relaxed(config->vmid_val[i],
 195                                drvdata->base + TRCVMIDCVRn(i));
 196         writel_relaxed(config->vmid_mask0, drvdata->base + TRCVMIDCCTLR0);
 197         writel_relaxed(config->vmid_mask1, drvdata->base + TRCVMIDCCTLR1);
 198
 199         /*
 200          * Request to keep the trace unit powered and also
 201          * emulation of powerdown
 202          */
 203         writel_relaxed(readl_relaxed(drvdata->base + TRCPDCR) | TRCPDCR_PU,
 204                        drvdata->base + TRCPDCR);
 205
 206         /* Enable the trace unit */
 207         writel_relaxed(1, drvdata->base + TRCPRGCTLR);
 208
 209         /* wait for TRCSTATR.IDLE to go back down to '0' */
 210         if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
 211                 dev_err(etm_dev,
 212                         "timeout while waiting for Idle Trace Status\n");
 213
 214         /*
 215          * As recommended by section 4.3.7 ("Synchronization when using the
 216          * memory-mapped interface") of ARM IHI 0064D
 217          */
 218         dsb(sy);
 219         isb();
 220
 221 done:
 222         CS_LOCK(drvdata->base);
 223
 224         dev_dbg(etm_dev, "cpu: %d enable smp call done: %d\n",
 225                 drvdata->cpu, rc);
 226         return rc;
 227 }
 228
 229 static void etm4_enable_hw_smp_call(void *info)
 230 {
 231         struct etm4_enable_arg *arg = info;
 232
 233         if (WARN_ON(!arg))
 234                 return;
 235         arg->rc = etm4_enable_hw(arg->drvdata);
 236 }
 237
 238 /*
 239  * The goal of function etm4_config_timestamp_event() is to configure a
 240  * counter that will tell the tracer to emit a timestamp packet when it
 241  * reaches zero.  This is done in order to get a more fine grained idea
 242  * of when instructions are executed so that they can be correlated
 243  * with execution on other CPUs.
 244  *
 245  * To do this the counter itself is configured to self reload and
 246  * TRCRSCTLR1 (always true) used to get the counter to decrement.  From
 247  * there a resource selector is configured with the counter and the
 248  * timestamp control register to use the resource selector to trigger the
 249  * event that will insert a timestamp packet in the stream.
 250  */
 251 static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata)
 252 {
 253         int ctridx, ret = -EINVAL;
 254         int counter, rselector;
 255         u32 val = 0;
 256         struct etmv4_config *config = &drvdata->config;
 257
 258         /* No point in trying if we don't have at least one counter */
 259         if (!drvdata->nr_cntr)
 260                 goto out;
 261
 262         /* Find a counter that hasn't been initialised */
 263         for (ctridx = 0; ctridx < drvdata->nr_cntr; ctridx++)
 264                 if (config->cntr_val[ctridx] == 0)
 265                         break;
 266
 267         /* All the counters have been configured already, bail out */
 268         if (ctridx == drvdata->nr_cntr) {
 269                 pr_debug("%s: no available counter found\n", __func__);
 270                 ret = -ENOSPC;
 271                 goto out;
 272         }
 273
 274         /*
 275          * Searching for an available resource selector to use, starting at
 276          * '2' since every implementation has at least 2 resource selector.
 277          * ETMIDR4 gives the number of resource selector _pairs_,
 278          * hence multiply by 2.
 279          */
 280         for (rselector = 2; rselector < drvdata->nr_resource * 2; rselector++)
 281                 if (!config->res_ctrl[rselector])
 282                         break;
 283
 284         if (rselector == drvdata->nr_resource * 2) {
 285                 pr_debug("%s: no available resource selector found\n",
 286                          __func__);
 287                 ret = -ENOSPC;
 288                 goto out;
 289         }
 290
 291         /* Remember what counter we used */
 292         counter = 1 << ctridx;
 293
 294         /*
 295          * Initialise original and reload counter value to the smallest
 296          * possible value in order to get as much precision as we can.
 297          */
 298         config->cntr_val[ctridx] = 1;
 299         config->cntrldvr[ctridx] = 1;
 300
 301         /* Set the trace counter control register */
 302         val =  0x1 << 16        |  /* Bit 16, reload counter automatically */
 303                0x0 << 7         |  /* Select single resource selector */
 304                0x1;                /* Resource selector 1, i.e always true */
 305
 306         config->cntr_ctrl[ctridx] = val;
 307
 308         val = 0x2 << 16         | /* Group 0b0010 - Counter and sequencers */
 309               counter << 0;       /* Counter to use */
 310
 311         config->res_ctrl[rselector] = val;
 312
 313         val = 0x0 << 7          | /* Select single resource selector */
 314               rselector;          /* Resource selector */
 315
 316         config->ts_ctrl = val;
 317
 318         ret = 0;
 319 out:
 320         return ret;
 321 }
 322
 323 static int etm4_parse_event_config(struct etmv4_drvdata *drvdata,
 324                                    struct perf_event *event)
 325 {
 326         int ret = 0;
 327         struct etmv4_config *config = &drvdata->config;
 328         struct perf_event_attr *attr = &event->attr;
 329
 330         if (!attr) {
 331                 ret = -EINVAL;
 332                 goto out;
 333         }
 334
 335         /* Clear configuration from previous run */
 336         memset(config, 0, sizeof(struct etmv4_config));
 337
 338         if (attr->exclude_kernel)
 339                 config->mode = ETM_MODE_EXCL_KERN;
 340
 341         if (attr->exclude_user)
 342                 config->mode = ETM_MODE_EXCL_USER;
 343
 344         /* Always start from the default config */
 345         etm4_set_default_config(config);
 346
 347         /* Configure filters specified on the perf cmd line, if any. */
 348         ret = etm4_set_event_filters(drvdata, event);
 349         if (ret)
 350                 goto out;
 351
 352         /* Go from generic option to ETMv4 specifics */
 353         if (attr->config & BIT(ETM_OPT_CYCACC)) {
 354                 config->cfg |= BIT(4);
 355                 /* TRM: Must program this for cycacc to work */
 356                 config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT;
 357         }
 358         if (attr->config & BIT(ETM_OPT_TS)) {
 359                 /*
 360                  * Configure timestamps to be emitted at regular intervals in
 361                  * order to correlate instructions executed on different CPUs
 362                  * (CPU-wide trace scenarios).
 363                  */
 364                 ret = etm4_config_timestamp_event(drvdata);
 365
 366                 /*
 367                  * No need to go further if timestamp intervals can't
 368                  * be configured.
 369                  */
 370                 if (ret)
 371                         goto out;
 372
 373                 /* bit[11], Global timestamp tracing bit */
 374                 config->cfg |= BIT(11);
 375         }
 376
 377         if (attr->config & BIT(ETM_OPT_CTXTID))
 378                 /* bit[6], Context ID tracing bit */
 379                 config->cfg |= BIT(ETM4_CFG_BIT_CTXTID);
 380
 381         /* return stack - enable if selected and supported */
 382         if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack)
 383                 /* bit[12], Return stack enable bit */
 384                 config->cfg |= BIT(12);
 385
 386 out:
 387         return ret;
 388 }
 389
 390 static int etm4_enable_perf(struct coresight_device *csdev,
 391                             struct perf_event *event)
 392 {
 393         int ret = 0;
 394         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 395
 396         if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) {
 397                 ret = -EINVAL;
 398                 goto out;
 399         }
 400
 401         /* Configure the tracer based on the session's specifics */
 402         ret = etm4_parse_event_config(drvdata, event);
 403         if (ret)
 404                 goto out;
 405         /* And enable it */
 406         ret = etm4_enable_hw(drvdata);
 407
 408 out:
 409         return ret;
 410 }
 411
 412 static int etm4_enable_sysfs(struct coresight_device *csdev)
 413 {
 414         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 415         struct etm4_enable_arg arg = { };
 416         int ret;
 417
 418         spin_lock(&drvdata->spinlock);
 419
 420         /*
 421          * Executing etm4_enable_hw on the cpu whose ETM is being enabled
 422          * ensures that register writes occur when cpu is powered.
 423          */
 424         arg.drvdata = drvdata;
 425         ret = smp_call_function_single(drvdata->cpu,
 426                                        etm4_enable_hw_smp_call, &arg, 1);
 427         if (!ret)
 428                 ret = arg.rc;
 429         if (!ret)
 430                 drvdata->sticky_enable = true;
 431         spin_unlock(&drvdata->spinlock);
 432
 433         if (!ret)
 434                 dev_dbg(&csdev->dev, "ETM tracing enabled\n");
 435         return ret;
 436 }
 437
 438 static int etm4_enable(struct coresight_device *csdev,
 439                        struct perf_event *event, u32 mode)
 440 {
 441         int ret;
 442         u32 val;
 443         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 444
 445         val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
 446
 447         /* Someone is already using the tracer */
 448         if (val)
 449                 return -EBUSY;
 450
 451         switch (mode) {
 452         case CS_MODE_SYSFS:
 453                 ret = etm4_enable_sysfs(csdev);
 454                 break;
 455         case CS_MODE_PERF:
 456                 ret = etm4_enable_perf(csdev, event);
 457                 break;
 458         default:
 459                 ret = -EINVAL;
 460         }
 461
 462         /* The tracer didn't start */
 463         if (ret)
 464                 local_set(&drvdata->mode, CS_MODE_DISABLED);
 465
 466         return ret;
 467 }
 468
 469 static void etm4_disable_hw(void *info)
 470 {
 471         u32 control;
 472         struct etmv4_drvdata *drvdata = info;
 473         struct etmv4_config *config = &drvdata->config;
 474         struct device *etm_dev = &drvdata->csdev->dev;
 475         int i;
 476
 477         CS_UNLOCK(drvdata->base);
 478
 479         /* power can be removed from the trace unit now */
 480         control = readl_relaxed(drvdata->base + TRCPDCR);
 481         control &= ~TRCPDCR_PU;
 482         writel_relaxed(control, drvdata->base + TRCPDCR);
 483
 484         control = readl_relaxed(drvdata->base + TRCPRGCTLR);
 485
 486         /* EN, bit[0] Trace unit enable bit */
 487         control &= ~0x1;
 488
 489         /*
 490          * Make sure everything completes before disabling, as recommended
 491          * by section 7.3.77 ("TRCVICTLR, ViewInst Main Control Register,
 492          * SSTATUS") of ARM IHI 0064D
 493          */
 494         dsb(sy);
 495         isb();
 496         writel_relaxed(control, drvdata->base + TRCPRGCTLR);
 497
 498         /* wait for TRCSTATR.PMSTABLE to go to '1' */
 499         if (coresight_timeout(drvdata->base, TRCSTATR,
 500                               TRCSTATR_PMSTABLE_BIT, 1))
 501                 dev_err(etm_dev,
 502                         "timeout while waiting for PM stable Trace Status\n");
 503
 504         /* read the status of the single shot comparators */
 505         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
 506                 config->ss_status[i] =
 507                         readl_relaxed(drvdata->base + TRCSSCSRn(i));
 508         }
 509
 510         coresight_disclaim_device_unlocked(drvdata->base);
 511
 512         CS_LOCK(drvdata->base);
 513
 514         dev_dbg(&drvdata->csdev->dev,
 515                 "cpu: %d disable smp call done\n", drvdata->cpu);
 516 }
 517
 518 static int etm4_disable_perf(struct coresight_device *csdev,
 519                              struct perf_event *event)
 520 {
 521         u32 control;
 522         struct etm_filters *filters = event->hw.addr_filters;
 523         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 524
 525         if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
 526                 return -EINVAL;
 527
 528         etm4_disable_hw(drvdata);
 529
 530         /*
 531          * Check if the start/stop logic was active when the unit was stopped.
 532          * That way we can re-enable the start/stop logic when the process is
 533          * scheduled again.  Configuration of the start/stop logic happens in
 534          * function etm4_set_event_filters().
 535          */
 536         control = readl_relaxed(drvdata->base + TRCVICTLR);
 537         /* TRCVICTLR::SSSTATUS, bit[9] */
 538         filters->ssstatus = (control & BIT(9));
 539
 540         return 0;
 541 }
 542
 543 static void etm4_disable_sysfs(struct coresight_device *csdev)
 544 {
 545         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 546
 547         /*
 548          * Taking hotplug lock here protects from clocks getting disabled
 549          * with tracing being left on (crash scenario) if user disable occurs
 550          * after cpu online mask indicates the cpu is offline but before the
 551          * DYING hotplug callback is serviced by the ETM driver.
 552          */
 553         cpus_read_lock();
 554         spin_lock(&drvdata->spinlock);
 555
 556         /*
 557          * Executing etm4_disable_hw on the cpu whose ETM is being disabled
 558          * ensures that register writes occur when cpu is powered.
 559          */
 560         smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1);
 561
 562         spin_unlock(&drvdata->spinlock);
 563         cpus_read_unlock();
 564
 565         dev_dbg(&csdev->dev, "ETM tracing disabled\n");
 566 }
 567
 568 static void etm4_disable(struct coresight_device *csdev,
 569                          struct perf_event *event)
 570 {
 571         u32 mode;
 572         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 573
 574         /*
 575          * For as long as the tracer isn't disabled another entity can't
 576          * change its status.  As such we can read the status here without
 577          * fearing it will change under us.
 578          */
 579         mode = local_read(&drvdata->mode);
 580
 581         switch (mode) {
 582         case CS_MODE_DISABLED:
 583                 break;
 584         case CS_MODE_SYSFS:
 585                 etm4_disable_sysfs(csdev);
 586                 break;
 587         case CS_MODE_PERF:
 588                 etm4_disable_perf(csdev, event);
 589                 break;
 590         }
 591
 592         if (mode)
 593                 local_set(&drvdata->mode, CS_MODE_DISABLED);
 594 }
 595
 596 static const struct coresight_ops_source etm4_source_ops = {
 597         .cpu_id         = etm4_cpu_id,
 598         .trace_id       = etm4_trace_id,
 599         .enable         = etm4_enable,
 600         .disable        = etm4_disable,
 601 };
 602
 603 static const struct coresight_ops etm4_cs_ops = {
 604         .source_ops     = &etm4_source_ops,
 605 };
 606
 607 static void etm4_init_arch_data(void *info)
 608 {
 609         u32 etmidr0;
 610         u32 etmidr1;
 611         u32 etmidr2;
 612         u32 etmidr3;
 613         u32 etmidr4;
 614         u32 etmidr5;
 615         struct etmv4_drvdata *drvdata = info;
 616         int i;
 617
 618         /* Make sure all registers are accessible */
 619         etm4_os_unlock(drvdata);
 620
 621         CS_UNLOCK(drvdata->base);
 622
 623         /* find all capabilities of the tracing unit */
 624         etmidr0 = readl_relaxed(drvdata->base + TRCIDR0);
 625
 626         /* INSTP0, bits[2:1] P0 tracing support field */
 627         if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2))
 628                 drvdata->instrp0 = true;
 629         else
 630                 drvdata->instrp0 = false;
 631
 632         /* TRCBB, bit[5] Branch broadcast tracing support bit */
 633         if (BMVAL(etmidr0, 5, 5))
 634                 drvdata->trcbb = true;
 635         else
 636                 drvdata->trcbb = false;
 637
 638         /* TRCCOND, bit[6] Conditional instruction tracing support bit */
 639         if (BMVAL(etmidr0, 6, 6))
 640                 drvdata->trccond = true;
 641         else
 642                 drvdata->trccond = false;
 643
 644         /* TRCCCI, bit[7] Cycle counting instruction bit */
 645         if (BMVAL(etmidr0, 7, 7))
 646                 drvdata->trccci = true;
 647         else
 648                 drvdata->trccci = false;
 649
 650         /* RETSTACK, bit[9] Return stack bit */
 651         if (BMVAL(etmidr0, 9, 9))
 652                 drvdata->retstack = true;
 653         else
 654                 drvdata->retstack = false;
 655
 656         /* NUMEVENT, bits[11:10] Number of events field */
 657         drvdata->nr_event = BMVAL(etmidr0, 10, 11);
 658         /* QSUPP, bits[16:15] Q element support field */
 659         drvdata->q_support = BMVAL(etmidr0, 15, 16);
 660         /* TSSIZE, bits[28:24] Global timestamp size field */
 661         drvdata->ts_size = BMVAL(etmidr0, 24, 28);
 662
 663         /* base architecture of trace unit */
 664         etmidr1 = readl_relaxed(drvdata->base + TRCIDR1);
 665         /*
 666          * TRCARCHMIN, bits[7:4] architecture the minor version number
 667          * TRCARCHMAJ, bits[11:8] architecture major versin number
 668          */
 669         drvdata->arch = BMVAL(etmidr1, 4, 11);
 670         drvdata->config.arch = drvdata->arch;
 671
 672         /* maximum size of resources */
 673         etmidr2 = readl_relaxed(drvdata->base + TRCIDR2);
 674         /* CIDSIZE, bits[9:5] Indicates the Context ID size */
 675         drvdata->ctxid_size = BMVAL(etmidr2, 5, 9);
 676         /* VMIDSIZE, bits[14:10] Indicates the VMID size */
 677         drvdata->vmid_size = BMVAL(etmidr2, 10, 14);
 678         /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
 679         drvdata->ccsize = BMVAL(etmidr2, 25, 28);
 680
 681         etmidr3 = readl_relaxed(drvdata->base + TRCIDR3);
 682         /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
 683         drvdata->ccitmin = BMVAL(etmidr3, 0, 11);
 684         /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
 685         drvdata->s_ex_level = BMVAL(etmidr3, 16, 19);
 686         /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
 687         drvdata->ns_ex_level = BMVAL(etmidr3, 20, 23);
 688
 689         /*
 690          * TRCERR, bit[24] whether a trace unit can trace a
 691          * system error exception.
 692          */
 693         if (BMVAL(etmidr3, 24, 24))
 694                 drvdata->trc_error = true;
 695         else
 696                 drvdata->trc_error = false;
 697
 698         /* SYNCPR, bit[25] implementation has a fixed synchronization period? */
 699         if (BMVAL(etmidr3, 25, 25))
 700                 drvdata->syncpr = true;
 701         else
 702                 drvdata->syncpr = false;
 703
 704         /* STALLCTL, bit[26] is stall control implemented? */
 705         if (BMVAL(etmidr3, 26, 26))
 706                 drvdata->stallctl = true;
 707         else
 708                 drvdata->stallctl = false;
 709
 710         /* SYSSTALL, bit[27] implementation can support stall control? */
 711         if (BMVAL(etmidr3, 27, 27))
 712                 drvdata->sysstall = true;
 713         else
 714                 drvdata->sysstall = false;
 715
 716         /* NUMPROC, bits[30:28] the number of PEs available for tracing */
 717         drvdata->nr_pe = BMVAL(etmidr3, 28, 30);
 718
 719         /* NOOVERFLOW, bit[31] is trace overflow prevention supported */
 720         if (BMVAL(etmidr3, 31, 31))
 721                 drvdata->nooverflow = true;
 722         else
 723                 drvdata->nooverflow = false;
 724
 725         /* number of resources trace unit supports */
 726         etmidr4 = readl_relaxed(drvdata->base + TRCIDR4);
 727         /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
 728         drvdata->nr_addr_cmp = BMVAL(etmidr4, 0, 3);
 729         /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
 730         drvdata->nr_pe_cmp = BMVAL(etmidr4, 12, 15);
 731         /*
 732          * NUMRSPAIR, bits[19:16]
 733          * The number of resource pairs conveyed by the HW starts at 0, i.e a
 734          * value of 0x0 indicate 1 resource pair, 0x1 indicate two and so on.
 735          * As such add 1 to the value of NUMRSPAIR for a better representation.
 736          */
 737         drvdata->nr_resource = BMVAL(etmidr4, 16, 19) + 1;
 738         /*
 739          * NUMSSCC, bits[23:20] the number of single-shot
 740          * comparator control for tracing. Read any status regs as these
 741          * also contain RO capability data.
 742          */
 743         drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23);
 744         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
 745                 drvdata->config.ss_status[i] =
 746                         readl_relaxed(drvdata->base + TRCSSCSRn(i));
 747         }
 748         /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
 749         drvdata->numcidc = BMVAL(etmidr4, 24, 27);
 750         /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
 751         drvdata->numvmidc = BMVAL(etmidr4, 28, 31);
 752
 753         etmidr5 = readl_relaxed(drvdata->base + TRCIDR5);
 754         /* NUMEXTIN, bits[8:0] number of external inputs implemented */
 755         drvdata->nr_ext_inp = BMVAL(etmidr5, 0, 8);
 756         /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
 757         drvdata->trcid_size = BMVAL(etmidr5, 16, 21);
 758         /* ATBTRIG, bit[22] implementation can support ATB triggers? */
 759         if (BMVAL(etmidr5, 22, 22))
 760                 drvdata->atbtrig = true;
 761         else
 762                 drvdata->atbtrig = false;
 763         /*
 764          * LPOVERRIDE, bit[23] implementation supports
 765          * low-power state override
 766          */
 767         if (BMVAL(etmidr5, 23, 23))
 768                 drvdata->lpoverride = true;
 769         else
 770                 drvdata->lpoverride = false;
 771         /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
 772         drvdata->nrseqstate = BMVAL(etmidr5, 25, 27);
 773         /* NUMCNTR, bits[30:28] number of counters available for tracing */
 774         drvdata->nr_cntr = BMVAL(etmidr5, 28, 30);
 775         CS_LOCK(drvdata->base);
 776 }
 777
 778 static void etm4_set_default_config(struct etmv4_config *config)
 779 {
 780         /* disable all events tracing */
 781         config->eventctrl0 = 0x0;
 782         config->eventctrl1 = 0x0;
 783
 784         /* disable stalling */
 785         config->stall_ctrl = 0x0;
 786
 787         /* enable trace synchronization every 4096 bytes, if available */
 788         config->syncfreq = 0xC;
 789
 790         /* disable timestamp event */
 791         config->ts_ctrl = 0x0;
 792
 793         /* TRCVICTLR::EVENT = 0x01, select the always on logic */
 794         config->vinst_ctrl = BIT(0);
 795 }
 796
 797 static u64 etm4_get_ns_access_type(struct etmv4_config *config)
 798 {
 799         u64 access_type = 0;
 800
 801         /*
 802          * EXLEVEL_NS, bits[15:12]
 803          * The Exception levels are:
 804          *   Bit[12] Exception level 0 - Application
 805          *   Bit[13] Exception level 1 - OS
 806          *   Bit[14] Exception level 2 - Hypervisor
 807          *   Bit[15] Never implemented
 808          */
 809         if (!is_kernel_in_hyp_mode()) {
 810                 /* Stay away from hypervisor mode for non-VHE */
 811                 access_type =  ETM_EXLEVEL_NS_HYP;
 812                 if (config->mode & ETM_MODE_EXCL_KERN)
 813                         access_type |= ETM_EXLEVEL_NS_OS;
 814         } else if (config->mode & ETM_MODE_EXCL_KERN) {
 815                 access_type = ETM_EXLEVEL_NS_HYP;
 816         }
 817
 818         if (config->mode & ETM_MODE_EXCL_USER)
 819                 access_type |= ETM_EXLEVEL_NS_APP;
 820
 821         return access_type;
 822 }
 823
 824 static u64 etm4_get_access_type(struct etmv4_config *config)
 825 {
 826         u64 access_type = etm4_get_ns_access_type(config);
 827         u64 s_hyp = (config->arch & 0x0f) >= 0x4 ? ETM_EXLEVEL_S_HYP : 0;
 828
 829         /*
 830          * EXLEVEL_S, bits[11:8], don't trace anything happening
 831          * in secure state.
 832          */
 833         access_type |= (ETM_EXLEVEL_S_APP       |
 834                         ETM_EXLEVEL_S_OS        |
 835                         s_hyp                   |
 836                         ETM_EXLEVEL_S_MON);
 837
 838         return access_type;
 839 }
 840
 841 static void etm4_set_comparator_filter(struct etmv4_config *config,
 842                                        u64 start, u64 stop, int comparator)
 843 {
 844         u64 access_type = etm4_get_access_type(config);
 845
 846         /* First half of default address comparator */
 847         config->addr_val[comparator] = start;
 848         config->addr_acc[comparator] = access_type;
 849         config->addr_type[comparator] = ETM_ADDR_TYPE_RANGE;
 850
 851         /* Second half of default address comparator */
 852         config->addr_val[comparator + 1] = stop;
 853         config->addr_acc[comparator + 1] = access_type;
 854         config->addr_type[comparator + 1] = ETM_ADDR_TYPE_RANGE;
 855
 856         /*
 857          * Configure the ViewInst function to include this address range
 858          * comparator.
 859          *
 860          * @comparator is divided by two since it is the index in the
 861          * etmv4_config::addr_val array but register TRCVIIECTLR deals with
 862          * address range comparator _pairs_.
 863          *
 864          * Therefore:
 865          *      index 0 -> compatator pair 0
 866          *      index 2 -> comparator pair 1
 867          *      index 4 -> comparator pair 2
 868          *      ...
 869          *      index 14 -> comparator pair 7
 870          */
 871         config->viiectlr |= BIT(comparator / 2);
 872 }
 873
 874 static void etm4_set_start_stop_filter(struct etmv4_config *config,
 875                                        u64 address, int comparator,
 876                                        enum etm_addr_type type)
 877 {
 878         int shift;
 879         u64 access_type = etm4_get_access_type(config);
 880
 881         /* Configure the comparator */
 882         config->addr_val[comparator] = address;
 883         config->addr_acc[comparator] = access_type;
 884         config->addr_type[comparator] = type;
 885
 886         /*
 887          * Configure ViewInst Start-Stop control register.
 888          * Addresses configured to start tracing go from bit 0 to n-1,
 889          * while those configured to stop tracing from 16 to 16 + n-1.
 890          */
 891         shift = (type == ETM_ADDR_TYPE_START ? 0 : 16);
 892         config->vissctlr |= BIT(shift + comparator);
 893 }
 894
 895 static void etm4_set_default_filter(struct etmv4_config *config)
 896 {
 897         /* Trace everything 'default' filter achieved by no filtering */
 898         config->viiectlr = 0x0;
 899
 900         /*
 901          * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
 902          * in the started state
 903          */
 904         config->vinst_ctrl |= BIT(9);
 905         config->mode |= ETM_MODE_VIEWINST_STARTSTOP;
 906
 907         /* No start-stop filtering for ViewInst */
 908         config->vissctlr = 0x0;
 909 }
 910
 911 static void etm4_set_default(struct etmv4_config *config)
 912 {
 913         if (WARN_ON_ONCE(!config))
 914                 return;
 915
 916         /*
 917          * Make default initialisation trace everything
 918          *
 919          * This is done by a minimum default config sufficient to enable
 920          * full instruction trace - with a default filter for trace all
 921          * achieved by having no filtering.
 922          */
 923         etm4_set_default_config(config);
 924         etm4_set_default_filter(config);
 925 }
 926
 927 static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type)
 928 {
 929         int nr_comparator, index = 0;
 930         struct etmv4_config *config = &drvdata->config;
 931
 932         /*
 933          * nr_addr_cmp holds the number of comparator _pair_, so time 2
 934          * for the total number of comparators.
 935          */
 936         nr_comparator = drvdata->nr_addr_cmp * 2;
 937
 938         /* Go through the tally of comparators looking for a free one. */
 939         while (index < nr_comparator) {
 940                 switch (type) {
 941                 case ETM_ADDR_TYPE_RANGE:
 942                         if (config->addr_type[index] == ETM_ADDR_TYPE_NONE &&
 943                             config->addr_type[index + 1] == ETM_ADDR_TYPE_NONE)
 944                                 return index;
 945
 946                         /* Address range comparators go in pairs */
 947                         index += 2;
 948                         break;
 949                 case ETM_ADDR_TYPE_START:
 950                 case ETM_ADDR_TYPE_STOP:
 951                         if (config->addr_type[index] == ETM_ADDR_TYPE_NONE)
 952                                 return index;
 953
 954                         /* Start/stop address can have odd indexes */
 955                         index += 1;
 956                         break;
 957                 default:
 958                         return -EINVAL;
 959                 }
 960         }
 961
 962         /* If we are here all the comparators have been used. */
 963         return -ENOSPC;
 964 }
 965
 966 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
 967                                   struct perf_event *event)
 968 {
 969         int i, comparator, ret = 0;
 970         u64 address;
 971         struct etmv4_config *config = &drvdata->config;
 972         struct etm_filters *filters = event->hw.addr_filters;
 973
 974         if (!filters)
 975                 goto default_filter;
 976
 977         /* Sync events with what Perf got */
 978         perf_event_addr_filters_sync(event);
 979
 980         /*
 981          * If there are no filters to deal with simply go ahead with
 982          * the default filter, i.e the entire address range.
 983          */
 984         if (!filters->nr_filters)
 985                 goto default_filter;
 986
 987         for (i = 0; i < filters->nr_filters; i++) {
 988                 struct etm_filter *filter = &filters->etm_filter[i];
 989                 enum etm_addr_type type = filter->type;
 990
 991                 /* See if a comparator is free. */
 992                 comparator = etm4_get_next_comparator(drvdata, type);
 993                 if (comparator < 0) {
 994                         ret = comparator;
 995                         goto out;
 996                 }
 997
 998                 switch (type) {
 999                 case ETM_ADDR_TYPE_RANGE:
1000                         etm4_set_comparator_filter(config,
1001                                                    filter->start_addr,
1002                                                    filter->stop_addr,
1003                                                    comparator);
1004                         /*
1005                          * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1006                          * in the started state
1007                          */
1008                         config->vinst_ctrl |= BIT(9);
1009
1010                         /* No start-stop filtering for ViewInst */
1011                         config->vissctlr = 0x0;
1012                         break;
1013                 case ETM_ADDR_TYPE_START:
1014                 case ETM_ADDR_TYPE_STOP:
1015                         /* Get the right start or stop address */
1016                         address = (type == ETM_ADDR_TYPE_START ?
1017                                    filter->start_addr :
1018                                    filter->stop_addr);
1019
1020                         /* Configure comparator */
1021                         etm4_set_start_stop_filter(config, address,
1022                                                    comparator, type);
1023
1024                         /*
1025                          * If filters::ssstatus == 1, trace acquisition was
1026                          * started but the process was yanked away before the
1027                          * the stop address was hit.  As such the start/stop
1028                          * logic needs to be re-started so that tracing can
1029                          * resume where it left.
1030                          *
1031                          * The start/stop logic status when a process is
1032                          * scheduled out is checked in function
1033                          * etm4_disable_perf().
1034                          */
1035                         if (filters->ssstatus)
1036                                 config->vinst_ctrl |= BIT(9);
1037
1038                         /* No include/exclude filtering for ViewInst */
1039                         config->viiectlr = 0x0;
1040                         break;
1041                 default:
1042                         ret = -EINVAL;
1043                         goto out;
1044                 }
1045         }
1046
1047         goto out;
1048
1049
1050 default_filter:
1051         etm4_set_default_filter(config);
1052
1053 out:
1054         return ret;
1055 }
1056
1057 void etm4_config_trace_mode(struct etmv4_config *config)
1058 {
1059         u32 addr_acc, mode;
1060
1061         mode = config->mode;
1062         mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
1063
1064         /* excluding kernel AND user space doesn't make sense */
1065         WARN_ON_ONCE(mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER));
1066
1067         /* nothing to do if neither flags are set */
1068         if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
1069                 return;
1070
1071         addr_acc = config->addr_acc[ETM_DEFAULT_ADDR_COMP];
1072         /* clear default config */
1073         addr_acc &= ~(ETM_EXLEVEL_NS_APP | ETM_EXLEVEL_NS_OS |
1074                       ETM_EXLEVEL_NS_HYP);
1075
1076         addr_acc |= etm4_get_ns_access_type(config);
1077
1078         config->addr_acc[ETM_DEFAULT_ADDR_COMP] = addr_acc;
1079         config->addr_acc[ETM_DEFAULT_ADDR_COMP + 1] = addr_acc;
1080 }
1081
1082 static int etm4_online_cpu(unsigned int cpu)
1083 {
1084         if (!etmdrvdata[cpu])
1085                 return 0;
1086
1087         if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable)
1088                 coresight_enable(etmdrvdata[cpu]->csdev);
1089         return 0;
1090 }
1091
1092 static int etm4_starting_cpu(unsigned int cpu)
1093 {
1094         if (!etmdrvdata[cpu])
1095                 return 0;
1096
1097         spin_lock(&etmdrvdata[cpu]->spinlock);
1098         if (!etmdrvdata[cpu]->os_unlock)
1099                 etm4_os_unlock(etmdrvdata[cpu]);
1100
1101         if (local_read(&etmdrvdata[cpu]->mode))
1102                 etm4_enable_hw(etmdrvdata[cpu]);
1103         spin_unlock(&etmdrvdata[cpu]->spinlock);
1104         return 0;
1105 }
1106
1107 static int etm4_dying_cpu(unsigned int cpu)
1108 {
1109         if (!etmdrvdata[cpu])
1110                 return 0;
1111
1112         spin_lock(&etmdrvdata[cpu]->spinlock);
1113         if (local_read(&etmdrvdata[cpu]->mode))
1114                 etm4_disable_hw(etmdrvdata[cpu]);
1115         spin_unlock(&etmdrvdata[cpu]->spinlock);
1116         return 0;
1117 }
1118
1119 static void etm4_init_trace_id(struct etmv4_drvdata *drvdata)
1120 {
1121         drvdata->trcid = coresight_get_trace_id(drvdata->cpu);
1122 }
1123
1124 static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
1125 {
1126         int i, ret = 0;
1127         struct etmv4_save_state *state;
1128         struct device *etm_dev = &drvdata->csdev->dev;
1129
1130         /*
1131          * As recommended by 3.4.1 ("The procedure when powering down the PE")
1132          * of ARM IHI 0064D
1133          */
1134         dsb(sy);
1135         isb();
1136
1137         CS_UNLOCK(drvdata->base);
1138
1139         /* Lock the OS lock to disable trace and external debugger access */
1140         etm4_os_lock(drvdata);
1141
1142         /* wait for TRCSTATR.PMSTABLE to go up */
1143         if (coresight_timeout(drvdata->base, TRCSTATR,
1144                               TRCSTATR_PMSTABLE_BIT, 1)) {
1145                 dev_err(etm_dev,
1146                         "timeout while waiting for PM Stable Status\n");
1147                 etm4_os_unlock(drvdata);
1148                 ret = -EBUSY;
1149                 goto out;
1150         }
1151
1152         state = drvdata->save_state;
1153
1154         state->trcprgctlr = readl(drvdata->base + TRCPRGCTLR);
1155         state->trcprocselr = readl(drvdata->base + TRCPROCSELR);
1156         state->trcconfigr = readl(drvdata->base + TRCCONFIGR);
1157         state->trcauxctlr = readl(drvdata->base + TRCAUXCTLR);
1158         state->trceventctl0r = readl(drvdata->base + TRCEVENTCTL0R);
1159         state->trceventctl1r = readl(drvdata->base + TRCEVENTCTL1R);
1160         state->trcstallctlr = readl(drvdata->base + TRCSTALLCTLR);
1161         state->trctsctlr = readl(drvdata->base + TRCTSCTLR);
1162         state->trcsyncpr = readl(drvdata->base + TRCSYNCPR);
1163         state->trcccctlr = readl(drvdata->base + TRCCCCTLR);
1164         state->trcbbctlr = readl(drvdata->base + TRCBBCTLR);
1165         state->trctraceidr = readl(drvdata->base + TRCTRACEIDR);
1166         state->trcqctlr = readl(drvdata->base + TRCQCTLR);
1167
1168         state->trcvictlr = readl(drvdata->base + TRCVICTLR);
1169         state->trcviiectlr = readl(drvdata->base + TRCVIIECTLR);
1170         state->trcvissctlr = readl(drvdata->base + TRCVISSCTLR);
1171         state->trcvipcssctlr = readl(drvdata->base + TRCVIPCSSCTLR);
1172         state->trcvdctlr = readl(drvdata->base + TRCVDCTLR);
1173         state->trcvdsacctlr = readl(drvdata->base + TRCVDSACCTLR);
1174         state->trcvdarcctlr = readl(drvdata->base + TRCVDARCCTLR);
1175
1176         for (i = 0; i < drvdata->nrseqstate; i++)
1177                 state->trcseqevr[i] = readl(drvdata->base + TRCSEQEVRn(i));
1178
1179         state->trcseqrstevr = readl(drvdata->base + TRCSEQRSTEVR);
1180         state->trcseqstr = readl(drvdata->base + TRCSEQSTR);
1181         state->trcextinselr = readl(drvdata->base + TRCEXTINSELR);
1182
1183         for (i = 0; i < drvdata->nr_cntr; i++) {
1184                 state->trccntrldvr[i] = readl(drvdata->base + TRCCNTRLDVRn(i));
1185                 state->trccntctlr[i] = readl(drvdata->base + TRCCNTCTLRn(i));
1186                 state->trccntvr[i] = readl(drvdata->base + TRCCNTVRn(i));
1187         }
1188
1189         for (i = 0; i < drvdata->nr_resource * 2; i++)
1190                 state->trcrsctlr[i] = readl(drvdata->base + TRCRSCTLRn(i));
1191
1192         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1193                 state->trcssccr[i] = readl(drvdata->base + TRCSSCCRn(i));
1194                 state->trcsscsr[i] = readl(drvdata->base + TRCSSCSRn(i));
1195                 state->trcsspcicr[i] = readl(drvdata->base + TRCSSPCICRn(i));
1196         }
1197
1198         for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1199                 state->trcacvr[i] = readl(drvdata->base + TRCACVRn(i));
1200                 state->trcacatr[i] = readl(drvdata->base + TRCACATRn(i));
1201         }
1202
1203         /*
1204          * Data trace stream is architecturally prohibited for A profile cores
1205          * so we don't save (or later restore) trcdvcvr and trcdvcmr - As per
1206          * section 1.3.4 ("Possible functional configurations of an ETMv4 trace
1207          * unit") of ARM IHI 0064D.
1208          */
1209
1210         for (i = 0; i < drvdata->numcidc; i++)
1211                 state->trccidcvr[i] = readl(drvdata->base + TRCCIDCVRn(i));
1212
1213         for (i = 0; i < drvdata->numvmidc; i++)
1214                 state->trcvmidcvr[i] = readl(drvdata->base + TRCVMIDCVRn(i));
1215
1216         state->trccidcctlr0 = readl(drvdata->base + TRCCIDCCTLR0);
1217         state->trccidcctlr1 = readl(drvdata->base + TRCCIDCCTLR1);
1218
1219         state->trcvmidcctlr0 = readl(drvdata->base + TRCVMIDCCTLR0);
1220         state->trcvmidcctlr0 = readl(drvdata->base + TRCVMIDCCTLR1);
1221
1222         state->trcclaimset = readl(drvdata->base + TRCCLAIMCLR);
1223
1224         state->trcpdcr = readl(drvdata->base + TRCPDCR);
1225
1226         /* wait for TRCSTATR.IDLE to go up */
1227         if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) {
1228                 dev_err(etm_dev,
1229                         "timeout while waiting for Idle Trace Status\n");
1230                 etm4_os_unlock(drvdata);
1231                 ret = -EBUSY;
1232                 goto out;
1233         }
1234
1235         drvdata->state_needs_restore = true;
1236
1237         /*
1238          * Power can be removed from the trace unit now. We do this to
1239          * potentially save power on systems that respect the TRCPDCR_PU
1240          * despite requesting software to save/restore state.
1241          */
1242         writel_relaxed((state->trcpdcr & ~TRCPDCR_PU),
1243                         drvdata->base + TRCPDCR);
1244
1245 out:
1246         CS_LOCK(drvdata->base);
1247         return ret;
1248 }
1249
1250 static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
1251 {
1252         int i;
1253         struct etmv4_save_state *state = drvdata->save_state;
1254
1255         CS_UNLOCK(drvdata->base);
1256
1257         writel_relaxed(state->trcclaimset, drvdata->base + TRCCLAIMSET);
1258
1259         writel_relaxed(state->trcprgctlr, drvdata->base + TRCPRGCTLR);
1260         writel_relaxed(state->trcprocselr, drvdata->base + TRCPROCSELR);
1261         writel_relaxed(state->trcconfigr, drvdata->base + TRCCONFIGR);
1262         writel_relaxed(state->trcauxctlr, drvdata->base + TRCAUXCTLR);
1263         writel_relaxed(state->trceventctl0r, drvdata->base + TRCEVENTCTL0R);
1264         writel_relaxed(state->trceventctl1r, drvdata->base + TRCEVENTCTL1R);
1265         writel_relaxed(state->trcstallctlr, drvdata->base + TRCSTALLCTLR);
1266         writel_relaxed(state->trctsctlr, drvdata->base + TRCTSCTLR);
1267         writel_relaxed(state->trcsyncpr, drvdata->base + TRCSYNCPR);
1268         writel_relaxed(state->trcccctlr, drvdata->base + TRCCCCTLR);
1269         writel_relaxed(state->trcbbctlr, drvdata->base + TRCBBCTLR);
1270         writel_relaxed(state->trctraceidr, drvdata->base + TRCTRACEIDR);
1271         writel_relaxed(state->trcqctlr, drvdata->base + TRCQCTLR);
1272
1273         writel_relaxed(state->trcvictlr, drvdata->base + TRCVICTLR);
1274         writel_relaxed(state->trcviiectlr, drvdata->base + TRCVIIECTLR);
1275         writel_relaxed(state->trcvissctlr, drvdata->base + TRCVISSCTLR);
1276         writel_relaxed(state->trcvipcssctlr, drvdata->base + TRCVIPCSSCTLR);
1277         writel_relaxed(state->trcvdctlr, drvdata->base + TRCVDCTLR);
1278         writel_relaxed(state->trcvdsacctlr, drvdata->base + TRCVDSACCTLR);
1279         writel_relaxed(state->trcvdarcctlr, drvdata->base + TRCVDARCCTLR);
1280
1281         for (i = 0; i < drvdata->nrseqstate; i++)
1282                 writel_relaxed(state->trcseqevr[i],
1283                                drvdata->base + TRCSEQEVRn(i));
1284
1285         writel_relaxed(state->trcseqrstevr, drvdata->base + TRCSEQRSTEVR);
1286         writel_relaxed(state->trcseqstr, drvdata->base + TRCSEQSTR);
1287         writel_relaxed(state->trcextinselr, drvdata->base + TRCEXTINSELR);
1288
1289         for (i = 0; i < drvdata->nr_cntr; i++) {
1290                 writel_relaxed(state->trccntrldvr[i],
1291                                drvdata->base + TRCCNTRLDVRn(i));
1292                 writel_relaxed(state->trccntctlr[i],
1293                                drvdata->base + TRCCNTCTLRn(i));
1294                 writel_relaxed(state->trccntvr[i],
1295                                drvdata->base + TRCCNTVRn(i));
1296         }
1297
1298         for (i = 0; i < drvdata->nr_resource * 2; i++)
1299                 writel_relaxed(state->trcrsctlr[i],
1300                                drvdata->base + TRCRSCTLRn(i));
1301
1302         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1303                 writel_relaxed(state->trcssccr[i],
1304                                drvdata->base + TRCSSCCRn(i));
1305                 writel_relaxed(state->trcsscsr[i],
1306                                drvdata->base + TRCSSCSRn(i));
1307                 writel_relaxed(state->trcsspcicr[i],
1308                                drvdata->base + TRCSSPCICRn(i));
1309         }
1310
1311         for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1312                 writel_relaxed(state->trcacvr[i],
1313                                drvdata->base + TRCACVRn(i));
1314                 writel_relaxed(state->trcacatr[i],
1315                                drvdata->base + TRCACATRn(i));
1316         }
1317
1318         for (i = 0; i < drvdata->numcidc; i++)
1319                 writel_relaxed(state->trccidcvr[i],
1320                                drvdata->base + TRCCIDCVRn(i));
1321
1322         for (i = 0; i < drvdata->numvmidc; i++)
1323                 writel_relaxed(state->trcvmidcvr[i],
1324                                drvdata->base + TRCVMIDCVRn(i));
1325
1326         writel_relaxed(state->trccidcctlr0, drvdata->base + TRCCIDCCTLR0);
1327         writel_relaxed(state->trccidcctlr1, drvdata->base + TRCCIDCCTLR1);
1328
1329         writel_relaxed(state->trcvmidcctlr0, drvdata->base + TRCVMIDCCTLR0);
1330         writel_relaxed(state->trcvmidcctlr0, drvdata->base + TRCVMIDCCTLR1);
1331
1332         writel_relaxed(state->trcclaimset, drvdata->base + TRCCLAIMSET);
1333
1334         writel_relaxed(state->trcpdcr, drvdata->base + TRCPDCR);
1335
1336         drvdata->state_needs_restore = false;
1337
1338         /*
1339          * As recommended by section 4.3.7 ("Synchronization when using the
1340          * memory-mapped interface") of ARM IHI 0064D
1341          */
1342         dsb(sy);
1343         isb();
1344
1345         /* Unlock the OS lock to re-enable trace and external debug access */
1346         etm4_os_unlock(drvdata);
1347         CS_LOCK(drvdata->base);
1348 }
1349
1350 static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd,
1351                               void *v)
1352 {
1353         struct etmv4_drvdata *drvdata;
1354         unsigned int cpu = smp_processor_id();
1355
1356         if (!etmdrvdata[cpu])
1357                 return NOTIFY_OK;
1358
1359         drvdata = etmdrvdata[cpu];
1360
1361         if (!drvdata->save_state)
1362                 return NOTIFY_OK;
1363
1364         if (WARN_ON_ONCE(drvdata->cpu != cpu))
1365                 return NOTIFY_BAD;
1366
1367         switch (cmd) {
1368         case CPU_PM_ENTER:
1369                 /* save the state if self-hosted coresight is in use */
1370                 if (local_read(&drvdata->mode))
1371                         if (etm4_cpu_save(drvdata))
1372                                 return NOTIFY_BAD;
1373                 break;
1374         case CPU_PM_EXIT:
1375                 /* fallthrough */
1376         case CPU_PM_ENTER_FAILED:
1377                 if (drvdata->state_needs_restore)
1378                         etm4_cpu_restore(drvdata);
1379                 break;
1380         default:
1381                 return NOTIFY_DONE;
1382         }
1383
1384         return NOTIFY_OK;
1385 }
1386
1387 static struct notifier_block etm4_cpu_pm_nb = {
1388         .notifier_call = etm4_cpu_pm_notify,
1389 };
1390
1391 static int etm4_cpu_pm_register(void)
1392 {
1393         if (IS_ENABLED(CONFIG_CPU_PM))
1394                 return cpu_pm_register_notifier(&etm4_cpu_pm_nb);
1395
1396         return 0;
1397 }
1398
1399 static void etm4_cpu_pm_unregister(void)
1400 {
1401         if (IS_ENABLED(CONFIG_CPU_PM))
1402                 cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
1403 }
1404
1405 static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
1406 {
1407         int ret;
1408         void __iomem *base;
1409         struct device *dev = &adev->dev;
1410         struct coresight_platform_data *pdata = NULL;
1411         struct etmv4_drvdata *drvdata;
1412         struct resource *res = &adev->res;
1413         struct coresight_desc desc = { 0 };
1414
1415         drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
1416         if (!drvdata)
1417                 return -ENOMEM;
1418
1419         dev_set_drvdata(dev, drvdata);
1420
1421         if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE)
1422                 pm_save_enable = coresight_loses_context_with_cpu(dev) ?
1423                                PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER;
1424
1425         if (pm_save_enable != PARAM_PM_SAVE_NEVER) {
1426                 drvdata->save_state = devm_kmalloc(dev,
1427                                 sizeof(struct etmv4_save_state), GFP_KERNEL);
1428                 if (!drvdata->save_state)
1429                         return -ENOMEM;
1430         }
1431
1432         /* Validity for the resource is already checked by the AMBA core */
1433         base = devm_ioremap_resource(dev, res);
1434         if (IS_ERR(base))
1435                 return PTR_ERR(base);
1436
1437         drvdata->base = base;
1438
1439         spin_lock_init(&drvdata->spinlock);
1440
1441         drvdata->cpu = coresight_get_cpu(dev);
1442         if (drvdata->cpu < 0)
1443                 return drvdata->cpu;
1444
1445         desc.name = devm_kasprintf(dev, GFP_KERNEL, "etm%d", drvdata->cpu);
1446         if (!desc.name)
1447                 return -ENOMEM;
1448
1449         cpus_read_lock();
1450         etmdrvdata[drvdata->cpu] = drvdata;
1451
1452         if (smp_call_function_single(drvdata->cpu,
1453                                 etm4_init_arch_data,  drvdata, 1))
1454                 dev_err(dev, "ETM arch init failed\n");
1455
1456         if (!etm4_count++) {
1457                 cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ARM_CORESIGHT_STARTING,
1458                                                      "arm/coresight4:starting",
1459                                                      etm4_starting_cpu, etm4_dying_cpu);
1460                 ret = cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ONLINE_DYN,
1461                                                            "arm/coresight4:online",
1462                                                            etm4_online_cpu, NULL);
1463                 if (ret < 0)
1464                         goto err_arch_supported;
1465                 hp_online = ret;
1466
1467                 ret = etm4_cpu_pm_register();
1468                 if (ret)
1469                         goto err_arch_supported;
1470         }
1471
1472         cpus_read_unlock();
1473
1474         if (etm4_arch_supported(drvdata->arch) == false) {
1475                 ret = -EINVAL;
1476                 goto err_arch_supported;
1477         }
1478
1479         etm4_init_trace_id(drvdata);
1480         etm4_set_default(&drvdata->config);
1481
1482         pdata = coresight_get_platform_data(dev);
1483         if (IS_ERR(pdata)) {
1484                 ret = PTR_ERR(pdata);
1485                 goto err_arch_supported;
1486         }
1487         adev->dev.platform_data = pdata;
1488
1489         desc.type = CORESIGHT_DEV_TYPE_SOURCE;
1490         desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
1491         desc.ops = &etm4_cs_ops;
1492         desc.pdata = pdata;
1493         desc.dev = dev;
1494         desc.groups = coresight_etmv4_groups;
1495         drvdata->csdev = coresight_register(&desc);
1496         if (IS_ERR(drvdata->csdev)) {
1497                 ret = PTR_ERR(drvdata->csdev);
1498                 goto err_arch_supported;
1499         }
1500
1501         ret = etm_perf_symlink(drvdata->csdev, true);
1502         if (ret) {
1503                 coresight_unregister(drvdata->csdev);
1504                 goto err_arch_supported;
1505         }
1506
1507         pm_runtime_put(&adev->dev);
1508         dev_info(&drvdata->csdev->dev, "CPU%d: ETM v%d.%d initialized\n",
1509                  drvdata->cpu, drvdata->arch >> 4, drvdata->arch & 0xf);
1510
1511         if (boot_enable) {
1512                 coresight_enable(drvdata->csdev);
1513                 drvdata->boot_enable = true;
1514         }
1515
1516         return 0;
1517
1518 err_arch_supported:
1519         etmdrvdata[drvdata->cpu] = NULL;
1520         if (--etm4_count == 0) {
1521                 etm4_cpu_pm_unregister();
1522
1523                 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
1524                 if (hp_online)
1525                         cpuhp_remove_state_nocalls(hp_online);
1526         }
1527         return ret;
1528 }
1529
1530 static struct amba_cs_uci_id uci_id_etm4[] = {
1531         {
1532                 /*  ETMv4 UCI data */
1533                 .devarch        = 0x47704a13,
1534                 .devarch_mask   = 0xfff0ffff,
1535                 .devtype        = 0x00000013,
1536         }
1537 };
1538
1539 static const struct amba_id etm4_ids[] = {
1540         CS_AMBA_ID(0x000bb95d),                 /* Cortex-A53 */
1541         CS_AMBA_ID(0x000bb95e),                 /* Cortex-A57 */
1542         CS_AMBA_ID(0x000bb95a),                 /* Cortex-A72 */
1543         CS_AMBA_ID(0x000bb959),                 /* Cortex-A73 */
1544         CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */
1545         CS_AMBA_UCI_ID(0x000bbd0c, uci_id_etm4),/* Neoverse N1 */
1546         CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */
1547         CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */
1548         CS_AMBA_UCI_ID(0x000bb802, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A55 */
1549         CS_AMBA_UCI_ID(0x000bb803, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A75 */
1550         CS_AMBA_UCI_ID(0x000bb805, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A55 */
1551         CS_AMBA_UCI_ID(0x000bb804, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A76 */
1552         CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */
1553         {},
1554 };
1555
1556 static struct amba_driver etm4x_driver = {
1557         .drv = {
1558                 .name   = "coresight-etm4x",
1559                 .suppress_bind_attrs = true,
1560         },
1561         .probe          = etm4_probe,
1562         .id_table       = etm4_ids,
1563 };
1564 builtin_amba_driver(etm4x_driver);