1 /* Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
13 #include <linux/kernel.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/types.h>
17 #include <linux/device.h>
19 #include <linux/err.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/smp.h>
24 #include <linux/sysfs.h>
25 #include <linux/stat.h>
26 #include <linux/clk.h>
27 #include <linux/cpu.h>
28 #include <linux/coresight.h>
29 #include <linux/pm_wakeup.h>
30 #include <linux/amba/bus.h>
31 #include <linux/seq_file.h>
32 #include <linux/uaccess.h>
33 #include <linux/pm_runtime.h>
34 #include <asm/sections.h>
36 #include "coresight-etm4x.h"
38 static int boot_enable;
39 module_param_named(boot_enable, boot_enable, int, S_IRUGO);
41 /* The number of ETMv4 currently registered */
42 static int etm4_count;
43 static struct etmv4_drvdata *etmdrvdata[NR_CPUS];
45 static void etm4_os_unlock(void *info)
47 struct etmv4_drvdata *drvdata = (struct etmv4_drvdata *)info;
49 /* Writing any value to ETMOSLAR unlocks the trace registers */
50 writel_relaxed(0x0, drvdata->base + TRCOSLAR);
54 static bool etm4_arch_supported(u8 arch)
65 static int etm4_trace_id(struct coresight_device *csdev)
67 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
72 return drvdata->trcid;
74 pm_runtime_get_sync(drvdata->dev);
75 spin_lock_irqsave(&drvdata->spinlock, flags);
77 CS_UNLOCK(drvdata->base);
78 trace_id = readl_relaxed(drvdata->base + TRCTRACEIDR);
79 trace_id &= ETM_TRACEID_MASK;
80 CS_LOCK(drvdata->base);
82 spin_unlock_irqrestore(&drvdata->spinlock, flags);
83 pm_runtime_put(drvdata->dev);
88 static void etm4_enable_hw(void *info)
91 struct etmv4_drvdata *drvdata = info;
93 CS_UNLOCK(drvdata->base);
95 etm4_os_unlock(drvdata);
97 /* Disable the trace unit before programming trace registers */
98 writel_relaxed(0, drvdata->base + TRCPRGCTLR);
100 /* wait for TRCSTATR.IDLE to go up */
101 if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
102 dev_err(drvdata->dev,
103 "timeout observed when probing at offset %#x\n",
106 writel_relaxed(drvdata->pe_sel, drvdata->base + TRCPROCSELR);
107 writel_relaxed(drvdata->cfg, drvdata->base + TRCCONFIGR);
108 /* nothing specific implemented */
109 writel_relaxed(0x0, drvdata->base + TRCAUXCTLR);
110 writel_relaxed(drvdata->eventctrl0, drvdata->base + TRCEVENTCTL0R);
111 writel_relaxed(drvdata->eventctrl1, drvdata->base + TRCEVENTCTL1R);
112 writel_relaxed(drvdata->stall_ctrl, drvdata->base + TRCSTALLCTLR);
113 writel_relaxed(drvdata->ts_ctrl, drvdata->base + TRCTSCTLR);
114 writel_relaxed(drvdata->syncfreq, drvdata->base + TRCSYNCPR);
115 writel_relaxed(drvdata->ccctlr, drvdata->base + TRCCCCTLR);
116 writel_relaxed(drvdata->bb_ctrl, drvdata->base + TRCBBCTLR);
117 writel_relaxed(drvdata->trcid, drvdata->base + TRCTRACEIDR);
118 writel_relaxed(drvdata->vinst_ctrl, drvdata->base + TRCVICTLR);
119 writel_relaxed(drvdata->viiectlr, drvdata->base + TRCVIIECTLR);
120 writel_relaxed(drvdata->vissctlr,
121 drvdata->base + TRCVISSCTLR);
122 writel_relaxed(drvdata->vipcssctlr,
123 drvdata->base + TRCVIPCSSCTLR);
124 for (i = 0; i < drvdata->nrseqstate - 1; i++)
125 writel_relaxed(drvdata->seq_ctrl[i],
126 drvdata->base + TRCSEQEVRn(i));
127 writel_relaxed(drvdata->seq_rst, drvdata->base + TRCSEQRSTEVR);
128 writel_relaxed(drvdata->seq_state, drvdata->base + TRCSEQSTR);
129 writel_relaxed(drvdata->ext_inp, drvdata->base + TRCEXTINSELR);
130 for (i = 0; i < drvdata->nr_cntr; i++) {
131 writel_relaxed(drvdata->cntrldvr[i],
132 drvdata->base + TRCCNTRLDVRn(i));
133 writel_relaxed(drvdata->cntr_ctrl[i],
134 drvdata->base + TRCCNTCTLRn(i));
135 writel_relaxed(drvdata->cntr_val[i],
136 drvdata->base + TRCCNTVRn(i));
138 for (i = 0; i < drvdata->nr_resource; i++)
139 writel_relaxed(drvdata->res_ctrl[i],
140 drvdata->base + TRCRSCTLRn(i));
142 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
143 writel_relaxed(drvdata->ss_ctrl[i],
144 drvdata->base + TRCSSCCRn(i));
145 writel_relaxed(drvdata->ss_status[i],
146 drvdata->base + TRCSSCSRn(i));
147 writel_relaxed(drvdata->ss_pe_cmp[i],
148 drvdata->base + TRCSSPCICRn(i));
150 for (i = 0; i < drvdata->nr_addr_cmp; i++) {
151 writeq_relaxed(drvdata->addr_val[i],
152 drvdata->base + TRCACVRn(i));
153 writeq_relaxed(drvdata->addr_acc[i],
154 drvdata->base + TRCACATRn(i));
156 for (i = 0; i < drvdata->numcidc; i++)
157 writeq_relaxed(drvdata->ctxid_val[i],
158 drvdata->base + TRCCIDCVRn(i));
159 writel_relaxed(drvdata->ctxid_mask0, drvdata->base + TRCCIDCCTLR0);
160 writel_relaxed(drvdata->ctxid_mask1, drvdata->base + TRCCIDCCTLR1);
162 for (i = 0; i < drvdata->numvmidc; i++)
163 writeq_relaxed(drvdata->vmid_val[i],
164 drvdata->base + TRCVMIDCVRn(i));
165 writel_relaxed(drvdata->vmid_mask0, drvdata->base + TRCVMIDCCTLR0);
166 writel_relaxed(drvdata->vmid_mask1, drvdata->base + TRCVMIDCCTLR1);
168 /* Enable the trace unit */
169 writel_relaxed(1, drvdata->base + TRCPRGCTLR);
171 /* wait for TRCSTATR.IDLE to go back down to '0' */
172 if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
173 dev_err(drvdata->dev,
174 "timeout observed when probing at offset %#x\n",
177 CS_LOCK(drvdata->base);
179 dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu);
182 static int etm4_enable(struct coresight_device *csdev)
184 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
187 pm_runtime_get_sync(drvdata->dev);
188 spin_lock(&drvdata->spinlock);
191 * Executing etm4_enable_hw on the cpu whose ETM is being enabled
192 * ensures that register writes occur when cpu is powered.
194 ret = smp_call_function_single(drvdata->cpu,
195 etm4_enable_hw, drvdata, 1);
198 drvdata->enable = true;
199 drvdata->sticky_enable = true;
201 spin_unlock(&drvdata->spinlock);
203 dev_info(drvdata->dev, "ETM tracing enabled\n");
206 spin_unlock(&drvdata->spinlock);
207 pm_runtime_put(drvdata->dev);
211 static void etm4_disable_hw(void *info)
214 struct etmv4_drvdata *drvdata = info;
216 CS_UNLOCK(drvdata->base);
218 control = readl_relaxed(drvdata->base + TRCPRGCTLR);
220 /* EN, bit[0] Trace unit enable bit */
223 /* make sure everything completes before disabling */
226 writel_relaxed(control, drvdata->base + TRCPRGCTLR);
228 CS_LOCK(drvdata->base);
230 dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu);
233 static void etm4_disable(struct coresight_device *csdev)
235 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
238 * Taking hotplug lock here protects from clocks getting disabled
239 * with tracing being left on (crash scenario) if user disable occurs
240 * after cpu online mask indicates the cpu is offline but before the
241 * DYING hotplug callback is serviced by the ETM driver.
244 spin_lock(&drvdata->spinlock);
247 * Executing etm4_disable_hw on the cpu whose ETM is being disabled
248 * ensures that register writes occur when cpu is powered.
250 smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1);
251 drvdata->enable = false;
253 spin_unlock(&drvdata->spinlock);
256 pm_runtime_put(drvdata->dev);
258 dev_info(drvdata->dev, "ETM tracing disabled\n");
261 static const struct coresight_ops_source etm4_source_ops = {
262 .trace_id = etm4_trace_id,
263 .enable = etm4_enable,
264 .disable = etm4_disable,
267 static const struct coresight_ops etm4_cs_ops = {
268 .source_ops = &etm4_source_ops,
271 static int etm4_set_mode_exclude(struct etmv4_drvdata *drvdata, bool exclude)
273 u8 idx = drvdata->addr_idx;
276 * TRCACATRn.TYPE bit[1:0]: type of comparison
277 * the trace unit performs
279 if (BMVAL(drvdata->addr_acc[idx], 0, 1) == ETM_INSTR_ADDR) {
284 * We are performing instruction address comparison. Set the
285 * relevant bit of ViewInst Include/Exclude Control register
286 * for corresponding address comparator pair.
288 if (drvdata->addr_type[idx] != ETM_ADDR_TYPE_RANGE ||
289 drvdata->addr_type[idx + 1] != ETM_ADDR_TYPE_RANGE)
292 if (exclude == true) {
294 * Set exclude bit and unset the include bit
295 * corresponding to comparator pair
297 drvdata->viiectlr |= BIT(idx / 2 + 16);
298 drvdata->viiectlr &= ~BIT(idx / 2);
301 * Set include bit and unset exclude bit
302 * corresponding to comparator pair
304 drvdata->viiectlr |= BIT(idx / 2);
305 drvdata->viiectlr &= ~BIT(idx / 2 + 16);
311 static ssize_t nr_pe_cmp_show(struct device *dev,
312 struct device_attribute *attr,
316 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
318 val = drvdata->nr_pe_cmp;
319 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
321 static DEVICE_ATTR_RO(nr_pe_cmp);
323 static ssize_t nr_addr_cmp_show(struct device *dev,
324 struct device_attribute *attr,
328 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
330 val = drvdata->nr_addr_cmp;
331 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
333 static DEVICE_ATTR_RO(nr_addr_cmp);
335 static ssize_t nr_cntr_show(struct device *dev,
336 struct device_attribute *attr,
340 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
342 val = drvdata->nr_cntr;
343 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
345 static DEVICE_ATTR_RO(nr_cntr);
347 static ssize_t nr_ext_inp_show(struct device *dev,
348 struct device_attribute *attr,
352 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
354 val = drvdata->nr_ext_inp;
355 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
357 static DEVICE_ATTR_RO(nr_ext_inp);
359 static ssize_t numcidc_show(struct device *dev,
360 struct device_attribute *attr,
364 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
366 val = drvdata->numcidc;
367 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
369 static DEVICE_ATTR_RO(numcidc);
371 static ssize_t numvmidc_show(struct device *dev,
372 struct device_attribute *attr,
376 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
378 val = drvdata->numvmidc;
379 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
381 static DEVICE_ATTR_RO(numvmidc);
383 static ssize_t nrseqstate_show(struct device *dev,
384 struct device_attribute *attr,
388 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
390 val = drvdata->nrseqstate;
391 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
393 static DEVICE_ATTR_RO(nrseqstate);
395 static ssize_t nr_resource_show(struct device *dev,
396 struct device_attribute *attr,
400 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
402 val = drvdata->nr_resource;
403 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
405 static DEVICE_ATTR_RO(nr_resource);
407 static ssize_t nr_ss_cmp_show(struct device *dev,
408 struct device_attribute *attr,
412 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
414 val = drvdata->nr_ss_cmp;
415 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
417 static DEVICE_ATTR_RO(nr_ss_cmp);
419 static ssize_t reset_store(struct device *dev,
420 struct device_attribute *attr,
421 const char *buf, size_t size)
425 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
427 if (kstrtoul(buf, 16, &val))
430 spin_lock(&drvdata->spinlock);
434 /* Disable data tracing: do not trace load and store data transfers */
435 drvdata->mode &= ~(ETM_MODE_LOAD | ETM_MODE_STORE);
436 drvdata->cfg &= ~(BIT(1) | BIT(2));
438 /* Disable data value and data address tracing */
439 drvdata->mode &= ~(ETM_MODE_DATA_TRACE_ADDR |
440 ETM_MODE_DATA_TRACE_VAL);
441 drvdata->cfg &= ~(BIT(16) | BIT(17));
443 /* Disable all events tracing */
444 drvdata->eventctrl0 = 0x0;
445 drvdata->eventctrl1 = 0x0;
447 /* Disable timestamp event */
448 drvdata->ts_ctrl = 0x0;
450 /* Disable stalling */
451 drvdata->stall_ctrl = 0x0;
453 /* Reset trace synchronization period to 2^8 = 256 bytes*/
454 if (drvdata->syncpr == false)
455 drvdata->syncfreq = 0x8;
458 * Enable ViewInst to trace everything with start-stop logic in
459 * started state. ARM recommends start-stop logic is set before
462 drvdata->vinst_ctrl |= BIT(0);
463 if (drvdata->nr_addr_cmp == true) {
464 drvdata->mode |= ETM_MODE_VIEWINST_STARTSTOP;
465 /* SSSTATUS, bit[9] */
466 drvdata->vinst_ctrl |= BIT(9);
469 /* No address range filtering for ViewInst */
470 drvdata->viiectlr = 0x0;
472 /* No start-stop filtering for ViewInst */
473 drvdata->vissctlr = 0x0;
475 /* Disable seq events */
476 for (i = 0; i < drvdata->nrseqstate-1; i++)
477 drvdata->seq_ctrl[i] = 0x0;
478 drvdata->seq_rst = 0x0;
479 drvdata->seq_state = 0x0;
481 /* Disable external input events */
482 drvdata->ext_inp = 0x0;
484 drvdata->cntr_idx = 0x0;
485 for (i = 0; i < drvdata->nr_cntr; i++) {
486 drvdata->cntrldvr[i] = 0x0;
487 drvdata->cntr_ctrl[i] = 0x0;
488 drvdata->cntr_val[i] = 0x0;
491 drvdata->res_idx = 0x0;
492 for (i = 0; i < drvdata->nr_resource; i++)
493 drvdata->res_ctrl[i] = 0x0;
495 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
496 drvdata->ss_ctrl[i] = 0x0;
497 drvdata->ss_pe_cmp[i] = 0x0;
500 drvdata->addr_idx = 0x0;
501 for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
502 drvdata->addr_val[i] = 0x0;
503 drvdata->addr_acc[i] = 0x0;
504 drvdata->addr_type[i] = ETM_ADDR_TYPE_NONE;
507 drvdata->ctxid_idx = 0x0;
508 for (i = 0; i < drvdata->numcidc; i++)
509 drvdata->ctxid_val[i] = 0x0;
510 drvdata->ctxid_mask0 = 0x0;
511 drvdata->ctxid_mask1 = 0x0;
513 drvdata->vmid_idx = 0x0;
514 for (i = 0; i < drvdata->numvmidc; i++)
515 drvdata->vmid_val[i] = 0x0;
516 drvdata->vmid_mask0 = 0x0;
517 drvdata->vmid_mask1 = 0x0;
519 drvdata->trcid = drvdata->cpu + 1;
520 spin_unlock(&drvdata->spinlock);
523 static DEVICE_ATTR_WO(reset);
525 static ssize_t mode_show(struct device *dev,
526 struct device_attribute *attr,
530 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
533 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
536 static ssize_t mode_store(struct device *dev,
537 struct device_attribute *attr,
538 const char *buf, size_t size)
540 unsigned long val, mode;
541 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
543 if (kstrtoul(buf, 16, &val))
546 spin_lock(&drvdata->spinlock);
547 drvdata->mode = val & ETMv4_MODE_ALL;
549 if (drvdata->mode & ETM_MODE_EXCLUDE)
550 etm4_set_mode_exclude(drvdata, true);
552 etm4_set_mode_exclude(drvdata, false);
554 if (drvdata->instrp0 == true) {
555 /* start by clearing instruction P0 field */
556 drvdata->cfg &= ~(BIT(1) | BIT(2));
557 if (drvdata->mode & ETM_MODE_LOAD)
558 /* 0b01 Trace load instructions as P0 instructions */
559 drvdata->cfg |= BIT(1);
560 if (drvdata->mode & ETM_MODE_STORE)
561 /* 0b10 Trace store instructions as P0 instructions */
562 drvdata->cfg |= BIT(2);
563 if (drvdata->mode & ETM_MODE_LOAD_STORE)
565 * 0b11 Trace load and store instructions
568 drvdata->cfg |= BIT(1) | BIT(2);
571 /* bit[3], Branch broadcast mode */
572 if ((drvdata->mode & ETM_MODE_BB) && (drvdata->trcbb == true))
573 drvdata->cfg |= BIT(3);
575 drvdata->cfg &= ~BIT(3);
577 /* bit[4], Cycle counting instruction trace bit */
578 if ((drvdata->mode & ETMv4_MODE_CYCACC) &&
579 (drvdata->trccci == true))
580 drvdata->cfg |= BIT(4);
582 drvdata->cfg &= ~BIT(4);
584 /* bit[6], Context ID tracing bit */
585 if ((drvdata->mode & ETMv4_MODE_CTXID) && (drvdata->ctxid_size))
586 drvdata->cfg |= BIT(6);
588 drvdata->cfg &= ~BIT(6);
590 if ((drvdata->mode & ETM_MODE_VMID) && (drvdata->vmid_size))
591 drvdata->cfg |= BIT(7);
593 drvdata->cfg &= ~BIT(7);
595 /* bits[10:8], Conditional instruction tracing bit */
596 mode = ETM_MODE_COND(drvdata->mode);
597 if (drvdata->trccond == true) {
598 drvdata->cfg &= ~(BIT(8) | BIT(9) | BIT(10));
599 drvdata->cfg |= mode << 8;
602 /* bit[11], Global timestamp tracing bit */
603 if ((drvdata->mode & ETMv4_MODE_TIMESTAMP) && (drvdata->ts_size))
604 drvdata->cfg |= BIT(11);
606 drvdata->cfg &= ~BIT(11);
608 /* bit[12], Return stack enable bit */
609 if ((drvdata->mode & ETM_MODE_RETURNSTACK) &&
610 (drvdata->retstack == true))
611 drvdata->cfg |= BIT(12);
613 drvdata->cfg &= ~BIT(12);
615 /* bits[14:13], Q element enable field */
616 mode = ETM_MODE_QELEM(drvdata->mode);
617 /* start by clearing QE bits */
618 drvdata->cfg &= ~(BIT(13) | BIT(14));
619 /* if supported, Q elements with instruction counts are enabled */
620 if ((mode & BIT(0)) && (drvdata->q_support & BIT(0)))
621 drvdata->cfg |= BIT(13);
623 * if supported, Q elements with and without instruction
626 if ((mode & BIT(1)) && (drvdata->q_support & BIT(1)))
627 drvdata->cfg |= BIT(14);
629 /* bit[11], AMBA Trace Bus (ATB) trigger enable bit */
630 if ((drvdata->mode & ETM_MODE_ATB_TRIGGER) &&
631 (drvdata->atbtrig == true))
632 drvdata->eventctrl1 |= BIT(11);
634 drvdata->eventctrl1 &= ~BIT(11);
636 /* bit[12], Low-power state behavior override bit */
637 if ((drvdata->mode & ETM_MODE_LPOVERRIDE) &&
638 (drvdata->lpoverride == true))
639 drvdata->eventctrl1 |= BIT(12);
641 drvdata->eventctrl1 &= ~BIT(12);
643 /* bit[8], Instruction stall bit */
644 if (drvdata->mode & ETM_MODE_ISTALL_EN)
645 drvdata->stall_ctrl |= BIT(8);
647 drvdata->stall_ctrl &= ~BIT(8);
649 /* bit[10], Prioritize instruction trace bit */
650 if (drvdata->mode & ETM_MODE_INSTPRIO)
651 drvdata->stall_ctrl |= BIT(10);
653 drvdata->stall_ctrl &= ~BIT(10);
655 /* bit[13], Trace overflow prevention bit */
656 if ((drvdata->mode & ETM_MODE_NOOVERFLOW) &&
657 (drvdata->nooverflow == true))
658 drvdata->stall_ctrl |= BIT(13);
660 drvdata->stall_ctrl &= ~BIT(13);
662 /* bit[9] Start/stop logic control bit */
663 if (drvdata->mode & ETM_MODE_VIEWINST_STARTSTOP)
664 drvdata->vinst_ctrl |= BIT(9);
666 drvdata->vinst_ctrl &= ~BIT(9);
668 /* bit[10], Whether a trace unit must trace a Reset exception */
669 if (drvdata->mode & ETM_MODE_TRACE_RESET)
670 drvdata->vinst_ctrl |= BIT(10);
672 drvdata->vinst_ctrl &= ~BIT(10);
674 /* bit[11], Whether a trace unit must trace a system error exception */
675 if ((drvdata->mode & ETM_MODE_TRACE_ERR) &&
676 (drvdata->trc_error == true))
677 drvdata->vinst_ctrl |= BIT(11);
679 drvdata->vinst_ctrl &= ~BIT(11);
681 spin_unlock(&drvdata->spinlock);
684 static DEVICE_ATTR_RW(mode);
686 static ssize_t pe_show(struct device *dev,
687 struct device_attribute *attr,
691 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
693 val = drvdata->pe_sel;
694 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
697 static ssize_t pe_store(struct device *dev,
698 struct device_attribute *attr,
699 const char *buf, size_t size)
702 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
704 if (kstrtoul(buf, 16, &val))
707 spin_lock(&drvdata->spinlock);
708 if (val > drvdata->nr_pe) {
709 spin_unlock(&drvdata->spinlock);
713 drvdata->pe_sel = val;
714 spin_unlock(&drvdata->spinlock);
717 static DEVICE_ATTR_RW(pe);
719 static ssize_t event_show(struct device *dev,
720 struct device_attribute *attr,
724 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
726 val = drvdata->eventctrl0;
727 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
730 static ssize_t event_store(struct device *dev,
731 struct device_attribute *attr,
732 const char *buf, size_t size)
735 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
737 if (kstrtoul(buf, 16, &val))
740 spin_lock(&drvdata->spinlock);
741 switch (drvdata->nr_event) {
743 /* EVENT0, bits[7:0] */
744 drvdata->eventctrl0 = val & 0xFF;
747 /* EVENT1, bits[15:8] */
748 drvdata->eventctrl0 = val & 0xFFFF;
751 /* EVENT2, bits[23:16] */
752 drvdata->eventctrl0 = val & 0xFFFFFF;
755 /* EVENT3, bits[31:24] */
756 drvdata->eventctrl0 = val;
761 spin_unlock(&drvdata->spinlock);
764 static DEVICE_ATTR_RW(event);
766 static ssize_t event_instren_show(struct device *dev,
767 struct device_attribute *attr,
771 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
773 val = BMVAL(drvdata->eventctrl1, 0, 3);
774 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
777 static ssize_t event_instren_store(struct device *dev,
778 struct device_attribute *attr,
779 const char *buf, size_t size)
782 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
784 if (kstrtoul(buf, 16, &val))
787 spin_lock(&drvdata->spinlock);
788 /* start by clearing all instruction event enable bits */
789 drvdata->eventctrl1 &= ~(BIT(0) | BIT(1) | BIT(2) | BIT(3));
790 switch (drvdata->nr_event) {
792 /* generate Event element for event 1 */
793 drvdata->eventctrl1 |= val & BIT(1);
796 /* generate Event element for event 1 and 2 */
797 drvdata->eventctrl1 |= val & (BIT(0) | BIT(1));
800 /* generate Event element for event 1, 2 and 3 */
801 drvdata->eventctrl1 |= val & (BIT(0) | BIT(1) | BIT(2));
804 /* generate Event element for all 4 events */
805 drvdata->eventctrl1 |= val & 0xF;
810 spin_unlock(&drvdata->spinlock);
813 static DEVICE_ATTR_RW(event_instren);
815 static ssize_t event_ts_show(struct device *dev,
816 struct device_attribute *attr,
820 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
822 val = drvdata->ts_ctrl;
823 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
826 static ssize_t event_ts_store(struct device *dev,
827 struct device_attribute *attr,
828 const char *buf, size_t size)
831 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
833 if (kstrtoul(buf, 16, &val))
835 if (!drvdata->ts_size)
838 drvdata->ts_ctrl = val & ETMv4_EVENT_MASK;
841 static DEVICE_ATTR_RW(event_ts);
843 static ssize_t syncfreq_show(struct device *dev,
844 struct device_attribute *attr,
848 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
850 val = drvdata->syncfreq;
851 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
854 static ssize_t syncfreq_store(struct device *dev,
855 struct device_attribute *attr,
856 const char *buf, size_t size)
859 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
861 if (kstrtoul(buf, 16, &val))
863 if (drvdata->syncpr == true)
866 drvdata->syncfreq = val & ETMv4_SYNC_MASK;
869 static DEVICE_ATTR_RW(syncfreq);
871 static ssize_t cyc_threshold_show(struct device *dev,
872 struct device_attribute *attr,
876 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
878 val = drvdata->ccctlr;
879 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
882 static ssize_t cyc_threshold_store(struct device *dev,
883 struct device_attribute *attr,
884 const char *buf, size_t size)
887 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
889 if (kstrtoul(buf, 16, &val))
891 if (val < drvdata->ccitmin)
894 drvdata->ccctlr = val & ETM_CYC_THRESHOLD_MASK;
897 static DEVICE_ATTR_RW(cyc_threshold);
899 static ssize_t bb_ctrl_show(struct device *dev,
900 struct device_attribute *attr,
904 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
906 val = drvdata->bb_ctrl;
907 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
910 static ssize_t bb_ctrl_store(struct device *dev,
911 struct device_attribute *attr,
912 const char *buf, size_t size)
915 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
917 if (kstrtoul(buf, 16, &val))
919 if (drvdata->trcbb == false)
921 if (!drvdata->nr_addr_cmp)
924 * Bit[7:0] selects which address range comparator is used for
925 * branch broadcast control.
927 if (BMVAL(val, 0, 7) > drvdata->nr_addr_cmp)
930 drvdata->bb_ctrl = val;
933 static DEVICE_ATTR_RW(bb_ctrl);
935 static ssize_t event_vinst_show(struct device *dev,
936 struct device_attribute *attr,
940 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
942 val = drvdata->vinst_ctrl & ETMv4_EVENT_MASK;
943 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
946 static ssize_t event_vinst_store(struct device *dev,
947 struct device_attribute *attr,
948 const char *buf, size_t size)
951 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
953 if (kstrtoul(buf, 16, &val))
956 spin_lock(&drvdata->spinlock);
957 val &= ETMv4_EVENT_MASK;
958 drvdata->vinst_ctrl &= ~ETMv4_EVENT_MASK;
959 drvdata->vinst_ctrl |= val;
960 spin_unlock(&drvdata->spinlock);
963 static DEVICE_ATTR_RW(event_vinst);
965 static ssize_t s_exlevel_vinst_show(struct device *dev,
966 struct device_attribute *attr,
970 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
972 val = BMVAL(drvdata->vinst_ctrl, 16, 19);
973 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
976 static ssize_t s_exlevel_vinst_store(struct device *dev,
977 struct device_attribute *attr,
978 const char *buf, size_t size)
981 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
983 if (kstrtoul(buf, 16, &val))
986 spin_lock(&drvdata->spinlock);
987 /* clear all EXLEVEL_S bits (bit[18] is never implemented) */
988 drvdata->vinst_ctrl &= ~(BIT(16) | BIT(17) | BIT(19));
989 /* enable instruction tracing for corresponding exception level */
990 val &= drvdata->s_ex_level;
991 drvdata->vinst_ctrl |= (val << 16);
992 spin_unlock(&drvdata->spinlock);
995 static DEVICE_ATTR_RW(s_exlevel_vinst);
997 static ssize_t ns_exlevel_vinst_show(struct device *dev,
998 struct device_attribute *attr,
1002 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
1004 /* EXLEVEL_NS, bits[23:20] */
1005 val = BMVAL(drvdata->vinst_ctrl, 20, 23);
1006 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
1009 static ssize_t ns_exlevel_vinst_store(struct device *dev,
1010 struct device_attribute *attr,
1011 const char *buf, size_t size)
1014 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
1016 if (kstrtoul(buf, 16, &val))
1019 spin_lock(&drvdata->spinlock);
1020 /* clear EXLEVEL_NS bits (bit[23] is never implemented */
1021 drvdata->vinst_ctrl &= ~(BIT(20) | BIT(21) | BIT(22));
1022 /* enable instruction tracing for corresponding exception level */
1023 val &= drvdata->ns_ex_level;
1024 drvdata->vinst_ctrl |= (val << 20);
1025 spin_unlock(&drvdata->spinlock);
1028 static DEVICE_ATTR_RW(ns_exlevel_vinst);
1030 static ssize_t addr_idx_show(struct device *dev,
1031 struct device_attribute *attr,
1035 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
1037 val = drvdata->addr_idx;
1038 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
1041 static ssize_t addr_idx_store(struct device *dev,
1042 struct device_attribute *attr,
1043 const char *buf, size_t size)
1046 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
1048 if (kstrtoul(buf, 16, &val))
1050 if (val >= drvdata->nr_addr_cmp * 2)
1054 * Use spinlock to ensure index doesn't change while it gets
1055 * dereferenced multiple times within a spinlock block elsewhere.
1057 spin_lock(&drvdata->spinlock);
1058 drvdata->addr_idx = val;
1059 spin_unlock(&drvdata->spinlock);
1062 static DEVICE_ATTR_RW(addr_idx);
1064 static ssize_t addr_instdatatype_show(struct device *dev,
1065 struct device_attribute *attr,
1070 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
1072 spin_lock(&drvdata->spinlock);
1073 idx = drvdata->addr_idx;
1074 val = BMVAL(drvdata->addr_acc[idx], 0, 1);
1075 len = scnprintf(buf, PAGE_SIZE, "%s\n",
1076 val == ETM_INSTR_ADDR ? "instr" :
1077 (val == ETM_DATA_LOAD_ADDR ? "data_load" :
1078 (val == ETM_DATA_STORE_ADDR ? "data_store" :
1079 "data_load_store")));
1080 spin_unlock(&drvdata->spinlock);
1084 static ssize_t addr_instdatatype_store(struct device *dev,
1085 struct device_attribute *attr,
1086 const char *buf, size_t size)
1090 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
1092 if (strlen(buf) >= 20)
1094 if (sscanf(buf, "%s", str) != 1)
1097 spin_lock(&drvdata->spinlock);
1098 idx = drvdata->addr_idx;
1099 if (!strcmp(str, "instr"))
1100 /* TYPE, bits[1:0] */
1101 drvdata->addr_acc[idx] &= ~(BIT(0) | BIT(1));
1103 spin_unlock(&drvdata->spinlock);
1106 static DEVICE_ATTR_RW(addr_instdatatype);
1108 static ssize_t addr_single_show(struct device *dev,
1109 struct device_attribute *attr,
1114 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
1116 idx = drvdata->addr_idx;
1117 spin_lock(&drvdata->spinlock);
1118 if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
1119 drvdata->addr_type[idx] == ETM_ADDR_TYPE_SINGLE)) {
1120 spin_unlock(&drvdata->spinlock);
1123 val = (unsigned long)drvdata->addr_val[idx];
1124 spin_unlock(&drvdata->spinlock);
1125 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
1128 static ssize_t addr_single_store(struct device *dev,
1129 struct device_attribute *attr,
1130 const char *buf, size_t size)
1134 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
1136 if (kstrtoul(buf, 16, &val))
1139 spin_lock(&drvdata->spinlock);
1140 idx = drvdata->addr_idx;
1141 if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
1142 drvdata->addr_type[idx] == ETM_ADDR_TYPE_SINGLE)) {
1143 spin_unlock(&drvdata->spinlock);
1147 drvdata->addr_val[idx] = (u64)val;
1148 drvdata->addr_type[idx] = ETM_ADDR_TYPE_SINGLE;
1149 spin_unlock(&drvdata->spinlock);
1152 static DEVICE_ATTR_RW(addr_single);
1154 static ssize_t addr_range_show(struct device *dev,
1155 struct device_attribute *attr,
1159 unsigned long val1, val2;
1160 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
1162 spin_lock(&drvdata->spinlock);
1163 idx = drvdata->addr_idx;
1165 spin_unlock(&drvdata->spinlock);
1168 if (!((drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE &&
1169 drvdata->addr_type[idx + 1] == ETM_ADDR_TYPE_NONE) ||
1170 (drvdata->addr_type[idx] == ETM_ADDR_TYPE_RANGE &&
1171 drvdata->addr_type[idx + 1] == ETM_ADDR_TYPE_RANGE))) {
1172 spin_unlock(&drvdata->spinlock);
1176 val1 = (unsigned long)drvdata->addr_val[idx];
1177 val2 = (unsigned long)drvdata->addr_val[idx + 1];
1178 spin_unlock(&drvdata->spinlock);
1179 return scnprintf(buf, PAGE_SIZE, "%#lx %#lx\n", val1, val2);
1182 static ssize_t addr_range_store(struct device *dev,
1183 struct device_attribute *attr,
1184 const char *buf, size_t size)
1187 unsigned long val1, val2;
1188 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
1190 if (sscanf(buf, "%lx %lx", &val1, &val2) != 2)
1192 /* lower address comparator cannot have a higher address value */
1196 spin_lock(&drvdata->spinlock);
1197 idx = drvdata->addr_idx;
1199 spin_unlock(&drvdata->spinlock);
1203 if (!((drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE &&
1204 drvdata->addr_type[idx + 1] == ETM_ADDR_TYPE_NONE) ||
1205 (drvdata->addr_type[idx] == ETM_ADDR_TYPE_RANGE &&
1206 drvdata->addr_type[idx + 1] == ETM_ADDR_TYPE_RANGE))) {
1207 spin_unlock(&drvdata->spinlock);
1211 drvdata->addr_val[idx] = (u64)val1;
1212 drvdata->addr_type[idx] = ETM_ADDR_TYPE_RANGE;
1213 drvdata->addr_val[idx + 1] = (u64)val2;
1214 drvdata->addr_type[idx + 1] = ETM_ADDR_TYPE_RANGE;
1216 * Program include or exclude control bits for vinst or vdata
1217 * whenever we change addr comparators to ETM_ADDR_TYPE_RANGE
1219 if (drvdata->mode & ETM_MODE_EXCLUDE)
1220 etm4_set_mode_exclude(drvdata, true);
1222 etm4_set_mode_exclude(drvdata, false);
1224 spin_unlock(&drvdata->spinlock);
1227 static DEVICE_ATTR_RW(addr_range);
1229 static ssize_t addr_start_show(struct device *dev,
1230 struct device_attribute *attr,
1235 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
1237 spin_lock(&drvdata->spinlock);
1238 idx = drvdata->addr_idx;
1240 if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
1241 drvdata->addr_type[idx] == ETM_ADDR_TYPE_START)) {
1242 spin_unlock(&drvdata->spinlock);
1246 val = (unsigned long)drvdata->addr_val[idx];
1247 spin_unlock(&drvdata->spinlock);
1248 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
1251 static ssize_t addr_start_store(struct device *dev,
1252 struct device_attribute *attr,
1253 const char *buf, size_t size)
1257 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
1259 if (kstrtoul(buf, 16, &val))
1262 spin_lock(&drvdata->spinlock);
1263 idx = drvdata->addr_idx;
1264 if (!drvdata->nr_addr_cmp) {
1265 spin_unlock(&drvdata->spinlock);
1268 if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
1269 drvdata->addr_type[idx] == ETM_ADDR_TYPE_START)) {
1270 spin_unlock(&drvdata->spinlock);
1274 drvdata->addr_val[idx] = (u64)val;
1275 drvdata->addr_type[idx] = ETM_ADDR_TYPE_START;
1276 drvdata->vissctlr |= BIT(idx);
1277 /* SSSTATUS, bit[9] - turn on start/stop logic */
1278 drvdata->vinst_ctrl |= BIT(9);
1279 spin_unlock(&drvdata->spinlock);
1282 static DEVICE_ATTR_RW(addr_start);
1284 static ssize_t addr_stop_show(struct device *dev,
1285 struct device_attribute *attr,
1290 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
1292 spin_lock(&drvdata->spinlock);
1293 idx = drvdata->addr_idx;
1295 if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
1296 drvdata->addr_type[idx] == ETM_ADDR_TYPE_STOP)) {
1297 spin_unlock(&drvdata->spinlock);
1301 val = (unsigned long)drvdata->addr_val[idx];
1302 spin_unlock(&drvdata->spinlock);
1303 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
1306 static ssize_t addr_stop_store(struct device *dev,
1307 struct device_attribute *attr,
1308 const char *buf, size_t size)
1312 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
1314 if (kstrtoul(buf, 16, &val))
1317 spin_lock(&drvdata->spinlock);
1318 idx = drvdata->addr_idx;
1319 if (!drvdata->nr_addr_cmp) {
1320 spin_unlock(&drvdata->spinlock);
1323 if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
1324 drvdata->addr_type[idx] == ETM_ADDR_TYPE_STOP)) {
1325 spin_unlock(&drvdata->spinlock);
1329 drvdata->addr_val[idx] = (u64)val;
1330 drvdata->addr_type[idx] = ETM_ADDR_TYPE_STOP;
1331 drvdata->vissctlr |= BIT(idx + 16);
1332 /* SSSTATUS, bit[9] - turn on start/stop logic */
1333 drvdata->vinst_ctrl |= BIT(9);
1334 spin_unlock(&drvdata->spinlock);
1337 static DEVICE_ATTR_RW(addr_stop);
1339 static ssize_t addr_ctxtype_show(struct device *dev,
1340 struct device_attribute *attr,
1345 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
1347 spin_lock(&drvdata->spinlock);
1348 idx = drvdata->addr_idx;
1349 /* CONTEXTTYPE, bits[3:2] */
1350 val = BMVAL(drvdata->addr_acc[idx], 2, 3);
1351 len = scnprintf(buf, PAGE_SIZE, "%s\n", val == ETM_CTX_NONE ? "none" :
1352 (val == ETM_CTX_CTXID ? "ctxid" :
1353 (val == ETM_CTX_VMID ? "vmid" : "all")));
1354 spin_unlock(&drvdata->spinlock);
1358 static ssize_t addr_ctxtype_store(struct device *dev,
1359 struct device_attribute *attr,
1360 const char *buf, size_t size)
1364 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
1366 if (strlen(buf) >= 10)
1368 if (sscanf(buf, "%s", str) != 1)
1371 spin_lock(&drvdata->spinlock);
1372 idx = drvdata->addr_idx;
1373 if (!strcmp(str, "none"))
1374 /* start by clearing context type bits */
1375 drvdata->addr_acc[idx] &= ~(BIT(2) | BIT(3));
1376 else if (!strcmp(str, "ctxid")) {
1377 /* 0b01 The trace unit performs a Context ID */
1378 if (drvdata->numcidc) {
1379 drvdata->addr_acc[idx] |= BIT(2);
1380 drvdata->addr_acc[idx] &= ~BIT(3);
1382 } else if (!strcmp(str, "vmid")) {
1383 /* 0b10 The trace unit performs a VMID */
1384 if (drvdata->numvmidc) {
1385 drvdata->addr_acc[idx] &= ~BIT(2);
1386 drvdata->addr_acc[idx] |= BIT(3);
1388 } else if (!strcmp(str, "all")) {
1390 * 0b11 The trace unit performs a Context ID
1391 * comparison and a VMID
1393 if (drvdata->numcidc)
1394 drvdata->addr_acc[idx] |= BIT(2);
1395 if (drvdata->numvmidc)
1396 drvdata->addr_acc[idx] |= BIT(3);
1398 spin_unlock(&drvdata->spinlock);
1401 static DEVICE_ATTR_RW(addr_ctxtype);
1403 static ssize_t addr_context_show(struct device *dev,
1404 struct device_attribute *attr,
1409 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
1411 spin_lock(&drvdata->spinlock);
1412 idx = drvdata->addr_idx;
1413 /* context ID comparator bits[6:4] */
1414 val = BMVAL(drvdata->addr_acc[idx], 4, 6);
1415 spin_unlock(&drvdata->spinlock);
1416 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
1419 static ssize_t addr_context_store(struct device *dev,
1420 struct device_attribute *attr,
1421 const char *buf, size_t size)
1425 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
1427 if (kstrtoul(buf, 16, &val))
1429 if ((drvdata->numcidc <= 1) && (drvdata->numvmidc <= 1))
1431 if (val >= (drvdata->numcidc >= drvdata->numvmidc ?
1432 drvdata->numcidc : drvdata->numvmidc))
1435 spin_lock(&drvdata->spinlock);
1436 idx = drvdata->addr_idx;
1437 /* clear context ID comparator bits[6:4] */
1438 drvdata->addr_acc[idx] &= ~(BIT(4) | BIT(5) | BIT(6));
1439 drvdata->addr_acc[idx] |= (val << 4);
1440 spin_unlock(&drvdata->spinlock);
1443 static DEVICE_ATTR_RW(addr_context);
1445 static ssize_t seq_idx_show(struct device *dev,
1446 struct device_attribute *attr,
1450 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
1452 val = drvdata->seq_idx;
1453 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
1456 static ssize_t seq_idx_store(struct device *dev,
1457 struct device_attribute *attr,
1458 const char *buf, size_t size)
1461 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
1463 if (kstrtoul(buf, 16, &val))
1465 if (val >= drvdata->nrseqstate - 1)
1469 * Use spinlock to ensure index doesn't change while it gets
1470 * dereferenced multiple times within a spinlock block elsewhere.
1472 spin_lock(&drvdata->spinlock);
1473 drvdata->seq_idx = val;
1474 spin_unlock(&drvdata->spinlock);
1477 static DEVICE_ATTR_RW(seq_idx);
1479 static ssize_t seq_state_show(struct device *dev,
1480 struct device_attribute *attr,
1484 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
1486 val = drvdata->seq_state;
1487 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
1490 static ssize_t seq_state_store(struct device *dev,
1491 struct device_attribute *attr,
1492 const char *buf, size_t size)
1495 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
1497 if (kstrtoul(buf, 16, &val))
1499 if (val >= drvdata->nrseqstate)
1502 drvdata->seq_state = val;
1505 static DEVICE_ATTR_RW(seq_state);
1507 static ssize_t seq_event_show(struct device *dev,
1508 struct device_attribute *attr,
1513 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
1515 spin_lock(&drvdata->spinlock);
1516 idx = drvdata->seq_idx;
1517 val = drvdata->seq_ctrl[idx];
1518 spin_unlock(&drvdata->spinlock);
1519 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
1522 static ssize_t seq_event_store(struct device *dev,
1523 struct device_attribute *attr,
1524 const char *buf, size_t size)
1528 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
1530 if (kstrtoul(buf, 16, &val))
1533 spin_lock(&drvdata->spinlock);
1534 idx = drvdata->seq_idx;
1535 /* RST, bits[7:0] */
1536 drvdata->seq_ctrl[idx] = val & 0xFF;
1537 spin_unlock(&drvdata->spinlock);
1540 static DEVICE_ATTR_RW(seq_event);
1542 static ssize_t seq_reset_event_show(struct device *dev,
1543 struct device_attribute *attr,
1547 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
1549 val = drvdata->seq_rst;
1550 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
1553 static ssize_t seq_reset_event_store(struct device *dev,
1554 struct device_attribute *attr,
1555 const char *buf, size_t size)
1558 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
1560 if (kstrtoul(buf, 16, &val))
1562 if (!(drvdata->nrseqstate))
1565 drvdata->seq_rst = val & ETMv4_EVENT_MASK;
1568 static DEVICE_ATTR_RW(seq_reset_event);
1570 static ssize_t cntr_idx_show(struct device *dev,
1571 struct device_attribute *attr,
1575 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
1577 val = drvdata->cntr_idx;
1578 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
1581 static ssize_t cntr_idx_store(struct device *dev,
1582 struct device_attribute *attr,
1583 const char *buf, size_t size)
1586 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
1588 if (kstrtoul(buf, 16, &val))
1590 if (val >= drvdata->nr_cntr)
1594 * Use spinlock to ensure index doesn't change while it gets
1595 * dereferenced multiple times within a spinlock block elsewhere.
1597 spin_lock(&drvdata->spinlock);
1598 drvdata->cntr_idx = val;
1599 spin_unlock(&drvdata->spinlock);
1602 static DEVICE_ATTR_RW(cntr_idx);
1604 static ssize_t cntrldvr_show(struct device *dev,
1605 struct device_attribute *attr,
1610 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
1612 spin_lock(&drvdata->spinlock);
1613 idx = drvdata->cntr_idx;
1614 val = drvdata->cntrldvr[idx];
1615 spin_unlock(&drvdata->spinlock);
1616 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
1619 static ssize_t cntrldvr_store(struct device *dev,
1620 struct device_attribute *attr,
1621 const char *buf, size_t size)
1625 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
1627 if (kstrtoul(buf, 16, &val))
1629 if (val > ETM_CNTR_MAX_VAL)
1632 spin_lock(&drvdata->spinlock);
1633 idx = drvdata->cntr_idx;
1634 drvdata->cntrldvr[idx] = val;
1635 spin_unlock(&drvdata->spinlock);
1638 static DEVICE_ATTR_RW(cntrldvr);
1640 static ssize_t cntr_val_show(struct device *dev,
1641 struct device_attribute *attr,
1646 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
1648 spin_lock(&drvdata->spinlock);
1649 idx = drvdata->cntr_idx;
1650 val = drvdata->cntr_val[idx];
1651 spin_unlock(&drvdata->spinlock);
1652 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
1655 static ssize_t cntr_val_store(struct device *dev,
1656 struct device_attribute *attr,
1657 const char *buf, size_t size)
1661 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
1663 if (kstrtoul(buf, 16, &val))
1665 if (val > ETM_CNTR_MAX_VAL)
1668 spin_lock(&drvdata->spinlock);
1669 idx = drvdata->cntr_idx;
1670 drvdata->cntr_val[idx] = val;
1671 spin_unlock(&drvdata->spinlock);
1674 static DEVICE_ATTR_RW(cntr_val);
1676 static ssize_t cntr_ctrl_show(struct device *dev,
1677 struct device_attribute *attr,
1682 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
1684 spin_lock(&drvdata->spinlock);
1685 idx = drvdata->cntr_idx;
1686 val = drvdata->cntr_ctrl[idx];
1687 spin_unlock(&drvdata->spinlock);
1688 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
1691 static ssize_t cntr_ctrl_store(struct device *dev,
1692 struct device_attribute *attr,
1693 const char *buf, size_t size)
1697 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
1699 if (kstrtoul(buf, 16, &val))
1702 spin_lock(&drvdata->spinlock);
1703 idx = drvdata->cntr_idx;
1704 drvdata->cntr_ctrl[idx] = val;
1705 spin_unlock(&drvdata->spinlock);
1708 static DEVICE_ATTR_RW(cntr_ctrl);
1710 static ssize_t cpu_show(struct device *dev,
1711 struct device_attribute *attr, char *buf)
1714 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
1717 return scnprintf(buf, PAGE_SIZE, "%d\n", val);
1720 static DEVICE_ATTR_RO(cpu);
1722 static struct attribute *coresight_etmv4_attrs[] = {
1723 &dev_attr_nr_pe_cmp.attr,
1724 &dev_attr_nr_addr_cmp.attr,
1725 &dev_attr_nr_cntr.attr,
1726 &dev_attr_nr_ext_inp.attr,
1727 &dev_attr_numcidc.attr,
1728 &dev_attr_numvmidc.attr,
1729 &dev_attr_nrseqstate.attr,
1730 &dev_attr_nr_resource.attr,
1731 &dev_attr_nr_ss_cmp.attr,
1732 &dev_attr_reset.attr,
1733 &dev_attr_mode.attr,
1735 &dev_attr_event.attr,
1736 &dev_attr_event_instren.attr,
1737 &dev_attr_event_ts.attr,
1738 &dev_attr_syncfreq.attr,
1739 &dev_attr_cyc_threshold.attr,
1740 &dev_attr_bb_ctrl.attr,
1741 &dev_attr_event_vinst.attr,
1742 &dev_attr_s_exlevel_vinst.attr,
1743 &dev_attr_ns_exlevel_vinst.attr,
1744 &dev_attr_addr_idx.attr,
1745 &dev_attr_addr_instdatatype.attr,
1746 &dev_attr_addr_single.attr,
1747 &dev_attr_addr_range.attr,
1748 &dev_attr_addr_start.attr,
1749 &dev_attr_addr_stop.attr,
1750 &dev_attr_addr_ctxtype.attr,
1751 &dev_attr_addr_context.attr,
1752 &dev_attr_seq_idx.attr,
1753 &dev_attr_seq_state.attr,
1754 &dev_attr_seq_event.attr,
1755 &dev_attr_seq_reset_event.attr,
1756 &dev_attr_cntr_idx.attr,
1757 &dev_attr_cntrldvr.attr,
1758 &dev_attr_cntr_val.attr,
1759 &dev_attr_cntr_ctrl.attr,
1763 ATTRIBUTE_GROUPS(coresight_etmv4);
1765 static void etm4_init_arch_data(void *info)
1773 struct etmv4_drvdata *drvdata = info;
1775 CS_UNLOCK(drvdata->base);
1777 /* find all capabilities of the tracing unit */
1778 etmidr0 = readl_relaxed(drvdata->base + TRCIDR0);
1780 /* INSTP0, bits[2:1] P0 tracing support field */
1781 if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2))
1782 drvdata->instrp0 = true;
1784 drvdata->instrp0 = false;
1786 /* TRCBB, bit[5] Branch broadcast tracing support bit */
1787 if (BMVAL(etmidr0, 5, 5))
1788 drvdata->trcbb = true;
1790 drvdata->trcbb = false;
1792 /* TRCCOND, bit[6] Conditional instruction tracing support bit */
1793 if (BMVAL(etmidr0, 6, 6))
1794 drvdata->trccond = true;
1796 drvdata->trccond = false;
1798 /* TRCCCI, bit[7] Cycle counting instruction bit */
1799 if (BMVAL(etmidr0, 7, 7))
1800 drvdata->trccci = true;
1802 drvdata->trccci = false;
1804 /* RETSTACK, bit[9] Return stack bit */
1805 if (BMVAL(etmidr0, 9, 9))
1806 drvdata->retstack = true;
1808 drvdata->retstack = false;
1810 /* NUMEVENT, bits[11:10] Number of events field */
1811 drvdata->nr_event = BMVAL(etmidr0, 10, 11);
1812 /* QSUPP, bits[16:15] Q element support field */
1813 drvdata->q_support = BMVAL(etmidr0, 15, 16);
1814 /* TSSIZE, bits[28:24] Global timestamp size field */
1815 drvdata->ts_size = BMVAL(etmidr0, 24, 28);
1817 /* base architecture of trace unit */
1818 etmidr1 = readl_relaxed(drvdata->base + TRCIDR1);
1820 * TRCARCHMIN, bits[7:4] architecture the minor version number
1821 * TRCARCHMAJ, bits[11:8] architecture major versin number
1823 drvdata->arch = BMVAL(etmidr1, 4, 11);
1825 /* maximum size of resources */
1826 etmidr2 = readl_relaxed(drvdata->base + TRCIDR2);
1827 /* CIDSIZE, bits[9:5] Indicates the Context ID size */
1828 drvdata->ctxid_size = BMVAL(etmidr2, 5, 9);
1829 /* VMIDSIZE, bits[14:10] Indicates the VMID size */
1830 drvdata->vmid_size = BMVAL(etmidr2, 10, 14);
1831 /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
1832 drvdata->ccsize = BMVAL(etmidr2, 25, 28);
1834 etmidr3 = readl_relaxed(drvdata->base + TRCIDR3);
1835 /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
1836 drvdata->ccitmin = BMVAL(etmidr3, 0, 11);
1837 /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
1838 drvdata->s_ex_level = BMVAL(etmidr3, 16, 19);
1839 /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
1840 drvdata->ns_ex_level = BMVAL(etmidr3, 20, 23);
1843 * TRCERR, bit[24] whether a trace unit can trace a
1844 * system error exception.
1846 if (BMVAL(etmidr3, 24, 24))
1847 drvdata->trc_error = true;
1849 drvdata->trc_error = false;
1851 /* SYNCPR, bit[25] implementation has a fixed synchronization period? */
1852 if (BMVAL(etmidr3, 25, 25))
1853 drvdata->syncpr = true;
1855 drvdata->syncpr = false;
1857 /* STALLCTL, bit[26] is stall control implemented? */
1858 if (BMVAL(etmidr3, 26, 26))
1859 drvdata->stallctl = true;
1861 drvdata->stallctl = false;
1863 /* SYSSTALL, bit[27] implementation can support stall control? */
1864 if (BMVAL(etmidr3, 27, 27))
1865 drvdata->sysstall = true;
1867 drvdata->sysstall = false;
1869 /* NUMPROC, bits[30:28] the number of PEs available for tracing */
1870 drvdata->nr_pe = BMVAL(etmidr3, 28, 30);
1872 /* NOOVERFLOW, bit[31] is trace overflow prevention supported */
1873 if (BMVAL(etmidr3, 31, 31))
1874 drvdata->nooverflow = true;
1876 drvdata->nooverflow = false;
1878 /* number of resources trace unit supports */
1879 etmidr4 = readl_relaxed(drvdata->base + TRCIDR4);
1880 /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
1881 drvdata->nr_addr_cmp = BMVAL(etmidr4, 0, 3);
1882 /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
1883 drvdata->nr_pe_cmp = BMVAL(etmidr4, 12, 15);
1884 /* NUMRSPAIR, bits[19:16] the number of resource pairs for tracing */
1885 drvdata->nr_resource = BMVAL(etmidr4, 16, 19);
1887 * NUMSSCC, bits[23:20] the number of single-shot
1888 * comparator control for tracing
1890 drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23);
1891 /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
1892 drvdata->numcidc = BMVAL(etmidr4, 24, 27);
1893 /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
1894 drvdata->numvmidc = BMVAL(etmidr4, 28, 31);
1896 etmidr5 = readl_relaxed(drvdata->base + TRCIDR5);
1897 /* NUMEXTIN, bits[8:0] number of external inputs implemented */
1898 drvdata->nr_ext_inp = BMVAL(etmidr5, 0, 8);
1899 /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
1900 drvdata->trcid_size = BMVAL(etmidr5, 16, 21);
1901 /* ATBTRIG, bit[22] implementation can support ATB triggers? */
1902 if (BMVAL(etmidr5, 22, 22))
1903 drvdata->atbtrig = true;
1905 drvdata->atbtrig = false;
1907 * LPOVERRIDE, bit[23] implementation supports
1908 * low-power state override
1910 if (BMVAL(etmidr5, 23, 23))
1911 drvdata->lpoverride = true;
1913 drvdata->lpoverride = false;
1914 /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
1915 drvdata->nrseqstate = BMVAL(etmidr5, 25, 27);
1916 /* NUMCNTR, bits[30:28] number of counters available for tracing */
1917 drvdata->nr_cntr = BMVAL(etmidr5, 28, 30);
1918 CS_LOCK(drvdata->base);
1921 static void etm4_init_default_data(struct etmv4_drvdata *drvdata)
1925 drvdata->pe_sel = 0x0;
1926 drvdata->cfg = (ETMv4_MODE_CTXID | ETM_MODE_VMID |
1927 ETMv4_MODE_TIMESTAMP | ETM_MODE_RETURNSTACK);
1929 /* disable all events tracing */
1930 drvdata->eventctrl0 = 0x0;
1931 drvdata->eventctrl1 = 0x0;
1933 /* disable stalling */
1934 drvdata->stall_ctrl = 0x0;
1936 /* disable timestamp event */
1937 drvdata->ts_ctrl = 0x0;
1939 /* enable trace synchronization every 4096 bytes for trace */
1940 if (drvdata->syncpr == false)
1941 drvdata->syncfreq = 0xC;
1944 * enable viewInst to trace everything with start-stop logic in
1947 drvdata->vinst_ctrl |= BIT(0);
1948 /* set initial state of start-stop logic */
1949 if (drvdata->nr_addr_cmp)
1950 drvdata->vinst_ctrl |= BIT(9);
1952 /* no address range filtering for ViewInst */
1953 drvdata->viiectlr = 0x0;
1954 /* no start-stop filtering for ViewInst */
1955 drvdata->vissctlr = 0x0;
1957 /* disable seq events */
1958 for (i = 0; i < drvdata->nrseqstate-1; i++)
1959 drvdata->seq_ctrl[i] = 0x0;
1960 drvdata->seq_rst = 0x0;
1961 drvdata->seq_state = 0x0;
1963 /* disable external input events */
1964 drvdata->ext_inp = 0x0;
1966 for (i = 0; i < drvdata->nr_cntr; i++) {
1967 drvdata->cntrldvr[i] = 0x0;
1968 drvdata->cntr_ctrl[i] = 0x0;
1969 drvdata->cntr_val[i] = 0x0;
1972 for (i = 2; i < drvdata->nr_resource * 2; i++)
1973 drvdata->res_ctrl[i] = 0x0;
1975 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1976 drvdata->ss_ctrl[i] = 0x0;
1977 drvdata->ss_pe_cmp[i] = 0x0;
1980 if (drvdata->nr_addr_cmp >= 1) {
1981 drvdata->addr_val[0] = (unsigned long)_stext;
1982 drvdata->addr_val[1] = (unsigned long)_etext;
1983 drvdata->addr_type[0] = ETM_ADDR_TYPE_RANGE;
1984 drvdata->addr_type[1] = ETM_ADDR_TYPE_RANGE;
1987 for (i = 0; i < drvdata->numcidc; i++)
1988 drvdata->ctxid_val[i] = 0x0;
1989 drvdata->ctxid_mask0 = 0x0;
1990 drvdata->ctxid_mask1 = 0x0;
1992 for (i = 0; i < drvdata->numvmidc; i++)
1993 drvdata->vmid_val[i] = 0x0;
1994 drvdata->vmid_mask0 = 0x0;
1995 drvdata->vmid_mask1 = 0x0;
1998 * A trace ID value of 0 is invalid, so let's start at some
1999 * random value that fits in 7 bits. ETMv3.x has 0x10 so let's
2002 drvdata->trcid = 0x20 + drvdata->cpu;
2005 static int etm4_cpu_callback(struct notifier_block *nfb, unsigned long action,
2008 unsigned int cpu = (unsigned long)hcpu;
2010 if (!etmdrvdata[cpu])
2013 switch (action & (~CPU_TASKS_FROZEN)) {
2015 spin_lock(&etmdrvdata[cpu]->spinlock);
2016 if (!etmdrvdata[cpu]->os_unlock) {
2017 etm4_os_unlock(etmdrvdata[cpu]);
2018 etmdrvdata[cpu]->os_unlock = true;
2021 if (etmdrvdata[cpu]->enable)
2022 etm4_enable_hw(etmdrvdata[cpu]);
2023 spin_unlock(&etmdrvdata[cpu]->spinlock);
2027 if (etmdrvdata[cpu]->boot_enable &&
2028 !etmdrvdata[cpu]->sticky_enable)
2029 coresight_enable(etmdrvdata[cpu]->csdev);
2033 spin_lock(&etmdrvdata[cpu]->spinlock);
2034 if (etmdrvdata[cpu]->enable)
2035 etm4_disable_hw(etmdrvdata[cpu]);
2036 spin_unlock(&etmdrvdata[cpu]->spinlock);
2043 static struct notifier_block etm4_cpu_notifier = {
2044 .notifier_call = etm4_cpu_callback,
2047 static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
2051 struct device *dev = &adev->dev;
2052 struct coresight_platform_data *pdata = NULL;
2053 struct etmv4_drvdata *drvdata;
2054 struct resource *res = &adev->res;
2055 struct coresight_desc *desc;
2056 struct device_node *np = adev->dev.of_node;
2058 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
2062 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
2067 pdata = of_get_coresight_platform_data(dev, np);
2069 return PTR_ERR(pdata);
2070 adev->dev.platform_data = pdata;
2073 drvdata->dev = &adev->dev;
2074 dev_set_drvdata(dev, drvdata);
2076 /* Validity for the resource is already checked by the AMBA core */
2077 base = devm_ioremap_resource(dev, res);
2079 return PTR_ERR(base);
2081 drvdata->base = base;
2083 spin_lock_init(&drvdata->spinlock);
2085 drvdata->cpu = pdata ? pdata->cpu : 0;
2088 etmdrvdata[drvdata->cpu] = drvdata;
2090 if (!smp_call_function_single(drvdata->cpu, etm4_os_unlock, drvdata, 1))
2091 drvdata->os_unlock = true;
2093 if (smp_call_function_single(drvdata->cpu,
2094 etm4_init_arch_data, drvdata, 1))
2095 dev_err(dev, "ETM arch init failed\n");
2098 register_hotcpu_notifier(&etm4_cpu_notifier);
2102 if (etm4_arch_supported(drvdata->arch) == false) {
2104 goto err_arch_supported;
2106 etm4_init_default_data(drvdata);
2108 pm_runtime_put(&adev->dev);
2110 desc->type = CORESIGHT_DEV_TYPE_SOURCE;
2111 desc->subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
2112 desc->ops = &etm4_cs_ops;
2113 desc->pdata = pdata;
2115 desc->groups = coresight_etmv4_groups;
2116 drvdata->csdev = coresight_register(desc);
2117 if (IS_ERR(drvdata->csdev)) {
2118 ret = PTR_ERR(drvdata->csdev);
2119 goto err_coresight_register;
2122 dev_info(dev, "%s initialized\n", (char *)id->data);
2125 coresight_enable(drvdata->csdev);
2126 drvdata->boot_enable = true;
2132 pm_runtime_put(&adev->dev);
2133 err_coresight_register:
2134 if (--etm4_count == 0)
2135 unregister_hotcpu_notifier(&etm4_cpu_notifier);
2139 static int etm4_remove(struct amba_device *adev)
2141 struct etmv4_drvdata *drvdata = amba_get_drvdata(adev);
2143 coresight_unregister(drvdata->csdev);
2144 if (--etm4_count == 0)
2145 unregister_hotcpu_notifier(&etm4_cpu_notifier);
2150 static struct amba_id etm4_ids[] = {
2151 { /* ETM 4.0 - Qualcomm */
2156 { /* ETM 4.0 - Juno board */
2164 static struct amba_driver etm4x_driver = {
2166 .name = "coresight-etm4x",
2168 .probe = etm4_probe,
2169 .remove = etm4_remove,
2170 .id_table = etm4_ids,
2173 module_amba_driver(etm4x_driver);