drivers/hwtracing/coresight/coresight-etm4x-core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/bitops.h>
   7 #include <linux/kernel.h>
   8 #include <linux/moduleparam.h>
   9 #include <linux/init.h>
  10 #include <linux/types.h>
  11 #include <linux/device.h>
  12 #include <linux/io.h>
  13 #include <linux/err.h>
  14 #include <linux/fs.h>
  15 #include <linux/slab.h>
  16 #include <linux/delay.h>
  17 #include <linux/smp.h>
  18 #include <linux/sysfs.h>
  19 #include <linux/stat.h>
  20 #include <linux/clk.h>
  21 #include <linux/cpu.h>
  22 #include <linux/cpu_pm.h>
  23 #include <linux/coresight.h>
  24 #include <linux/coresight-pmu.h>
  25 #include <linux/pm_wakeup.h>
  26 #include <linux/amba/bus.h>
  27 #include <linux/seq_file.h>
  28 #include <linux/uaccess.h>
  29 #include <linux/perf_event.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/property.h>
  32
  33 #include <asm/sections.h>
  34 #include <asm/sysreg.h>
  35 #include <asm/local.h>
  36 #include <asm/virt.h>
  37
  38 #include "coresight-etm4x.h"
  39 #include "coresight-etm-perf.h"
  40
  41 static int boot_enable;
  42 module_param(boot_enable, int, 0444);
  43 MODULE_PARM_DESC(boot_enable, "Enable tracing on boot");
  44
  45 #define PARAM_PM_SAVE_FIRMWARE    0 /* save self-hosted state as per firmware */
  46 #define PARAM_PM_SAVE_NEVER       1 /* never save any state */
  47 #define PARAM_PM_SAVE_SELF_HOSTED 2 /* save self-hosted state only */
  48
  49 static int pm_save_enable = PARAM_PM_SAVE_FIRMWARE;
  50 module_param(pm_save_enable, int, 0444);
  51 MODULE_PARM_DESC(pm_save_enable,
  52         "Save/restore state on power down: 1 = never, 2 = self-hosted");
  53
  54 static struct etmv4_drvdata *etmdrvdata[NR_CPUS];
  55 static void etm4_set_default_config(struct etmv4_config *config);
  56 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
  57                                   struct perf_event *event);
  58 static u64 etm4_get_access_type(struct etmv4_config *config);
  59
  60 static enum cpuhp_state hp_online;
  61
  62 struct etm4_init_arg {
  63         struct etmv4_drvdata    *drvdata;
  64         struct csdev_access     *csa;
  65 };
  66
  67 /*
  68  * Check if TRCSSPCICRn(i) is implemented for a given instance.
  69  *
  70  * TRCSSPCICRn is implemented only if :
  71  *      TRCSSPCICR<n> is present only if all of the following are true:
  72  *              TRCIDR4.NUMSSCC > n.
  73  *              TRCIDR4.NUMPC > 0b0000 .
  74  *              TRCSSCSR<n>.PC == 0b1
  75  */
  76 static inline bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n)
  77 {
  78         return (n < drvdata->nr_ss_cmp) &&
  79                drvdata->nr_pe &&
  80                (drvdata->config.ss_status[n] & TRCSSCSRn_PC);
  81 }
  82
  83 u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
  84 {
  85         u64 res = 0;
  86
  87         switch (offset) {
  88         ETM4x_READ_SYSREG_CASES(res)
  89         default :
  90                 pr_warn_ratelimited("etm4x: trying to read unsupported register @%x\n",
  91                          offset);
  92         }
  93
  94         if (!_relaxed)
  95                 __iormb(res);   /* Imitate the !relaxed I/O helpers */
  96
  97         return res;
  98 }
  99
 100 void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
 101 {
 102         if (!_relaxed)
 103                 __iowmb();      /* Imitate the !relaxed I/O helpers */
 104         if (!_64bit)
 105                 val &= GENMASK(31, 0);
 106
 107         switch (offset) {
 108         ETM4x_WRITE_SYSREG_CASES(val)
 109         default :
 110                 pr_warn_ratelimited("etm4x: trying to write to unsupported register @%x\n",
 111                         offset);
 112         }
 113 }
 114
 115 static void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata, struct csdev_access *csa)
 116 {
 117         /* Writing 0 to TRCOSLAR unlocks the trace registers */
 118         etm4x_relaxed_write32(csa, 0x0, TRCOSLAR);
 119         drvdata->os_unlock = true;
 120         isb();
 121 }
 122
 123 static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
 124 {
 125         if (!WARN_ON(!drvdata->csdev))
 126                 etm4_os_unlock_csa(drvdata, &drvdata->csdev->access);
 127
 128 }
 129
 130 static void etm4_os_lock(struct etmv4_drvdata *drvdata)
 131 {
 132         if (WARN_ON(!drvdata->csdev))
 133                 return;
 134
 135         /* Writing 0x1 to TRCOSLAR locks the trace registers */
 136         etm4x_relaxed_write32(&drvdata->csdev->access, 0x1, TRCOSLAR);
 137         drvdata->os_unlock = false;
 138         isb();
 139 }
 140
 141 static void etm4_cs_lock(struct etmv4_drvdata *drvdata,
 142                          struct csdev_access *csa)
 143 {
 144         /* Software Lock is only accessible via memory mapped interface */
 145         if (csa->io_mem)
 146                 CS_LOCK(csa->base);
 147 }
 148
 149 static void etm4_cs_unlock(struct etmv4_drvdata *drvdata,
 150                            struct csdev_access *csa)
 151 {
 152         if (csa->io_mem)
 153                 CS_UNLOCK(csa->base);
 154 }
 155
 156 static int etm4_cpu_id(struct coresight_device *csdev)
 157 {
 158         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 159
 160         return drvdata->cpu;
 161 }
 162
 163 static int etm4_trace_id(struct coresight_device *csdev)
 164 {
 165         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 166
 167         return drvdata->trcid;
 168 }
 169
 170 struct etm4_enable_arg {
 171         struct etmv4_drvdata *drvdata;
 172         int rc;
 173 };
 174
 175 #ifdef CONFIG_ETM4X_IMPDEF_FEATURE
 176
 177 #define HISI_HIP08_AMBA_ID              0x000b6d01
 178 #define ETM4_AMBA_MASK                  0xfffff
 179 #define HISI_HIP08_CORE_COMMIT_MASK     0x3000
 180 #define HISI_HIP08_CORE_COMMIT_SHIFT    12
 181 #define HISI_HIP08_CORE_COMMIT_FULL     0b00
 182 #define HISI_HIP08_CORE_COMMIT_LVL_1    0b01
 183 #define HISI_HIP08_CORE_COMMIT_REG      sys_reg(3, 1, 15, 2, 5)
 184
 185 struct etm4_arch_features {
 186         void (*arch_callback)(bool enable);
 187 };
 188
 189 static bool etm4_hisi_match_pid(unsigned int id)
 190 {
 191         return (id & ETM4_AMBA_MASK) == HISI_HIP08_AMBA_ID;
 192 }
 193
 194 static void etm4_hisi_config_core_commit(bool enable)
 195 {
 196         u8 commit = enable ? HISI_HIP08_CORE_COMMIT_LVL_1 :
 197                     HISI_HIP08_CORE_COMMIT_FULL;
 198         u64 val;
 199
 200         /*
 201          * bit 12 and 13 of HISI_HIP08_CORE_COMMIT_REG are used together
 202          * to set core-commit, 2'b00 means cpu is at full speed, 2'b01,
 203          * 2'b10, 2'b11 mean reduce pipeline speed, and 2'b01 means level-1
 204          * speed(minimun value). So bit 12 and 13 should be cleared together.
 205          */
 206         val = read_sysreg_s(HISI_HIP08_CORE_COMMIT_REG);
 207         val &= ~HISI_HIP08_CORE_COMMIT_MASK;
 208         val |= commit << HISI_HIP08_CORE_COMMIT_SHIFT;
 209         write_sysreg_s(val, HISI_HIP08_CORE_COMMIT_REG);
 210 }
 211
 212 static struct etm4_arch_features etm4_features[] = {
 213         [ETM4_IMPDEF_HISI_CORE_COMMIT] = {
 214                 .arch_callback = etm4_hisi_config_core_commit,
 215         },
 216         {},
 217 };
 218
 219 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
 220 {
 221         struct etm4_arch_features *ftr;
 222         int bit;
 223
 224         for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
 225                 ftr = &etm4_features[bit];
 226
 227                 if (ftr->arch_callback)
 228                         ftr->arch_callback(true);
 229         }
 230 }
 231
 232 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
 233 {
 234         struct etm4_arch_features *ftr;
 235         int bit;
 236
 237         for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
 238                 ftr = &etm4_features[bit];
 239
 240                 if (ftr->arch_callback)
 241                         ftr->arch_callback(false);
 242         }
 243 }
 244
 245 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,
 246                                       unsigned int id)
 247 {
 248         if (etm4_hisi_match_pid(id))
 249                 set_bit(ETM4_IMPDEF_HISI_CORE_COMMIT, drvdata->arch_features);
 250 }
 251 #else
 252 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
 253 {
 254 }
 255
 256 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
 257 {
 258 }
 259
 260 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,
 261                                      unsigned int id)
 262 {
 263 }
 264 #endif /* CONFIG_ETM4X_IMPDEF_FEATURE */
 265
 266 static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
 267 {
 268         int i, rc;
 269         struct etmv4_config *config = &drvdata->config;
 270         struct coresight_device *csdev = drvdata->csdev;
 271         struct device *etm_dev = &csdev->dev;
 272         struct csdev_access *csa = &csdev->access;
 273
 274
 275         etm4_cs_unlock(drvdata, csa);
 276         etm4_enable_arch_specific(drvdata);
 277
 278         etm4_os_unlock(drvdata);
 279
 280         rc = coresight_claim_device_unlocked(csdev);
 281         if (rc)
 282                 goto done;
 283
 284         /* Disable the trace unit before programming trace registers */
 285         etm4x_relaxed_write32(csa, 0, TRCPRGCTLR);
 286
 287         /*
 288          * If we use system instructions, we need to synchronize the
 289          * write to the TRCPRGCTLR, before accessing the TRCSTATR.
 290          * See ARM IHI0064F, section
 291          * "4.3.7 Synchronization of register updates"
 292          */
 293         if (!csa->io_mem)
 294                 isb();
 295
 296         /* wait for TRCSTATR.IDLE to go up */
 297         if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
 298                 dev_err(etm_dev,
 299                         "timeout while waiting for Idle Trace Status\n");
 300         if (drvdata->nr_pe)
 301                 etm4x_relaxed_write32(csa, config->pe_sel, TRCPROCSELR);
 302         etm4x_relaxed_write32(csa, config->cfg, TRCCONFIGR);
 303         /* nothing specific implemented */
 304         etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR);
 305         etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R);
 306         etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R);
 307         etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
 308         etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR);
 309         etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR);
 310         etm4x_relaxed_write32(csa, config->ccctlr, TRCCCCTLR);
 311         etm4x_relaxed_write32(csa, config->bb_ctrl, TRCBBCTLR);
 312         etm4x_relaxed_write32(csa, drvdata->trcid, TRCTRACEIDR);
 313         etm4x_relaxed_write32(csa, config->vinst_ctrl, TRCVICTLR);
 314         etm4x_relaxed_write32(csa, config->viiectlr, TRCVIIECTLR);
 315         etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR);
 316         if (drvdata->nr_pe_cmp)
 317                 etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR);
 318         for (i = 0; i < drvdata->nrseqstate - 1; i++)
 319                 etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
 320         etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);
 321         etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR);
 322         etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR);
 323         for (i = 0; i < drvdata->nr_cntr; i++) {
 324                 etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i));
 325                 etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i));
 326                 etm4x_relaxed_write32(csa, config->cntr_val[i], TRCCNTVRn(i));
 327         }
 328
 329         /*
 330          * Resource selector pair 0 is always implemented and reserved.  As
 331          * such start at 2.
 332          */
 333         for (i = 2; i < drvdata->nr_resource * 2; i++)
 334                 etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i));
 335
 336         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
 337                 /* always clear status bit on restart if using single-shot */
 338                 if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
 339                         config->ss_status[i] &= ~BIT(31);
 340                 etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i));
 341                 etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i));
 342                 if (etm4x_sspcicrn_present(drvdata, i))
 343                         etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i));
 344         }
 345         for (i = 0; i < drvdata->nr_addr_cmp; i++) {
 346                 etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i));
 347                 etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i));
 348         }
 349         for (i = 0; i < drvdata->numcidc; i++)
 350                 etm4x_relaxed_write64(csa, config->ctxid_pid[i], TRCCIDCVRn(i));
 351         etm4x_relaxed_write32(csa, config->ctxid_mask0, TRCCIDCCTLR0);
 352         if (drvdata->numcidc > 4)
 353                 etm4x_relaxed_write32(csa, config->ctxid_mask1, TRCCIDCCTLR1);
 354
 355         for (i = 0; i < drvdata->numvmidc; i++)
 356                 etm4x_relaxed_write64(csa, config->vmid_val[i], TRCVMIDCVRn(i));
 357         etm4x_relaxed_write32(csa, config->vmid_mask0, TRCVMIDCCTLR0);
 358         if (drvdata->numvmidc > 4)
 359                 etm4x_relaxed_write32(csa, config->vmid_mask1, TRCVMIDCCTLR1);
 360
 361         if (!drvdata->skip_power_up) {
 362                 u32 trcpdcr = etm4x_relaxed_read32(csa, TRCPDCR);
 363
 364                 /*
 365                  * Request to keep the trace unit powered and also
 366                  * emulation of powerdown
 367                  */
 368                 etm4x_relaxed_write32(csa, trcpdcr | TRCPDCR_PU, TRCPDCR);
 369         }
 370
 371         /* Enable the trace unit */
 372         etm4x_relaxed_write32(csa, 1, TRCPRGCTLR);
 373
 374         /* Synchronize the register updates for sysreg access */
 375         if (!csa->io_mem)
 376                 isb();
 377
 378         /* wait for TRCSTATR.IDLE to go back down to '0' */
 379         if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
 380                 dev_err(etm_dev,
 381                         "timeout while waiting for Idle Trace Status\n");
 382
 383         /*
 384          * As recommended by section 4.3.7 ("Synchronization when using the
 385          * memory-mapped interface") of ARM IHI 0064D
 386          */
 387         dsb(sy);
 388         isb();
 389
 390 done:
 391         etm4_cs_lock(drvdata, csa);
 392
 393         dev_dbg(etm_dev, "cpu: %d enable smp call done: %d\n",
 394                 drvdata->cpu, rc);
 395         return rc;
 396 }
 397
 398 static void etm4_enable_hw_smp_call(void *info)
 399 {
 400         struct etm4_enable_arg *arg = info;
 401
 402         if (WARN_ON(!arg))
 403                 return;
 404         arg->rc = etm4_enable_hw(arg->drvdata);
 405 }
 406
 407 /*
 408  * The goal of function etm4_config_timestamp_event() is to configure a
 409  * counter that will tell the tracer to emit a timestamp packet when it
 410  * reaches zero.  This is done in order to get a more fine grained idea
 411  * of when instructions are executed so that they can be correlated
 412  * with execution on other CPUs.
 413  *
 414  * To do this the counter itself is configured to self reload and
 415  * TRCRSCTLR1 (always true) used to get the counter to decrement.  From
 416  * there a resource selector is configured with the counter and the
 417  * timestamp control register to use the resource selector to trigger the
 418  * event that will insert a timestamp packet in the stream.
 419  */
 420 static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata)
 421 {
 422         int ctridx, ret = -EINVAL;
 423         int counter, rselector;
 424         u32 val = 0;
 425         struct etmv4_config *config = &drvdata->config;
 426
 427         /* No point in trying if we don't have at least one counter */
 428         if (!drvdata->nr_cntr)
 429                 goto out;
 430
 431         /* Find a counter that hasn't been initialised */
 432         for (ctridx = 0; ctridx < drvdata->nr_cntr; ctridx++)
 433                 if (config->cntr_val[ctridx] == 0)
 434                         break;
 435
 436         /* All the counters have been configured already, bail out */
 437         if (ctridx == drvdata->nr_cntr) {
 438                 pr_debug("%s: no available counter found\n", __func__);
 439                 ret = -ENOSPC;
 440                 goto out;
 441         }
 442
 443         /*
 444          * Searching for an available resource selector to use, starting at
 445          * '2' since every implementation has at least 2 resource selector.
 446          * ETMIDR4 gives the number of resource selector _pairs_,
 447          * hence multiply by 2.
 448          */
 449         for (rselector = 2; rselector < drvdata->nr_resource * 2; rselector++)
 450                 if (!config->res_ctrl[rselector])
 451                         break;
 452
 453         if (rselector == drvdata->nr_resource * 2) {
 454                 pr_debug("%s: no available resource selector found\n",
 455                          __func__);
 456                 ret = -ENOSPC;
 457                 goto out;
 458         }
 459
 460         /* Remember what counter we used */
 461         counter = 1 << ctridx;
 462
 463         /*
 464          * Initialise original and reload counter value to the smallest
 465          * possible value in order to get as much precision as we can.
 466          */
 467         config->cntr_val[ctridx] = 1;
 468         config->cntrldvr[ctridx] = 1;
 469
 470         /* Set the trace counter control register */
 471         val =  0x1 << 16        |  /* Bit 16, reload counter automatically */
 472                0x0 << 7         |  /* Select single resource selector */
 473                0x1;                /* Resource selector 1, i.e always true */
 474
 475         config->cntr_ctrl[ctridx] = val;
 476
 477         val = 0x2 << 16         | /* Group 0b0010 - Counter and sequencers */
 478               counter << 0;       /* Counter to use */
 479
 480         config->res_ctrl[rselector] = val;
 481
 482         val = 0x0 << 7          | /* Select single resource selector */
 483               rselector;          /* Resource selector */
 484
 485         config->ts_ctrl = val;
 486
 487         ret = 0;
 488 out:
 489         return ret;
 490 }
 491
 492 static int etm4_parse_event_config(struct etmv4_drvdata *drvdata,
 493                                    struct perf_event *event)
 494 {
 495         int ret = 0;
 496         struct etmv4_config *config = &drvdata->config;
 497         struct perf_event_attr *attr = &event->attr;
 498
 499         if (!attr) {
 500                 ret = -EINVAL;
 501                 goto out;
 502         }
 503
 504         /* Clear configuration from previous run */
 505         memset(config, 0, sizeof(struct etmv4_config));
 506
 507         if (attr->exclude_kernel)
 508                 config->mode = ETM_MODE_EXCL_KERN;
 509
 510         if (attr->exclude_user)
 511                 config->mode = ETM_MODE_EXCL_USER;
 512
 513         /* Always start from the default config */
 514         etm4_set_default_config(config);
 515
 516         /* Configure filters specified on the perf cmd line, if any. */
 517         ret = etm4_set_event_filters(drvdata, event);
 518         if (ret)
 519                 goto out;
 520
 521         /* Go from generic option to ETMv4 specifics */
 522         if (attr->config & BIT(ETM_OPT_CYCACC)) {
 523                 config->cfg |= BIT(4);
 524                 /* TRM: Must program this for cycacc to work */
 525                 config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT;
 526         }
 527         if (attr->config & BIT(ETM_OPT_TS)) {
 528                 /*
 529                  * Configure timestamps to be emitted at regular intervals in
 530                  * order to correlate instructions executed on different CPUs
 531                  * (CPU-wide trace scenarios).
 532                  */
 533                 ret = etm4_config_timestamp_event(drvdata);
 534
 535                 /*
 536                  * No need to go further if timestamp intervals can't
 537                  * be configured.
 538                  */
 539                 if (ret)
 540                         goto out;
 541
 542                 /* bit[11], Global timestamp tracing bit */
 543                 config->cfg |= BIT(11);
 544         }
 545
 546         if (attr->config & BIT(ETM_OPT_CTXTID))
 547                 /* bit[6], Context ID tracing bit */
 548                 config->cfg |= BIT(ETM4_CFG_BIT_CTXTID);
 549
 550         /* return stack - enable if selected and supported */
 551         if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack)
 552                 /* bit[12], Return stack enable bit */
 553                 config->cfg |= BIT(12);
 554
 555 out:
 556         return ret;
 557 }
 558
 559 static int etm4_enable_perf(struct coresight_device *csdev,
 560                             struct perf_event *event)
 561 {
 562         int ret = 0;
 563         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 564
 565         if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) {
 566                 ret = -EINVAL;
 567                 goto out;
 568         }
 569
 570         /* Configure the tracer based on the session's specifics */
 571         ret = etm4_parse_event_config(drvdata, event);
 572         if (ret)
 573                 goto out;
 574         /* And enable it */
 575         ret = etm4_enable_hw(drvdata);
 576
 577 out:
 578         return ret;
 579 }
 580
 581 static int etm4_enable_sysfs(struct coresight_device *csdev)
 582 {
 583         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 584         struct etm4_enable_arg arg = { };
 585         int ret;
 586
 587         spin_lock(&drvdata->spinlock);
 588
 589         /*
 590          * Executing etm4_enable_hw on the cpu whose ETM is being enabled
 591          * ensures that register writes occur when cpu is powered.
 592          */
 593         arg.drvdata = drvdata;
 594         ret = smp_call_function_single(drvdata->cpu,
 595                                        etm4_enable_hw_smp_call, &arg, 1);
 596         if (!ret)
 597                 ret = arg.rc;
 598         if (!ret)
 599                 drvdata->sticky_enable = true;
 600         spin_unlock(&drvdata->spinlock);
 601
 602         if (!ret)
 603                 dev_dbg(&csdev->dev, "ETM tracing enabled\n");
 604         return ret;
 605 }
 606
 607 static int etm4_enable(struct coresight_device *csdev,
 608                        struct perf_event *event, u32 mode)
 609 {
 610         int ret;
 611         u32 val;
 612         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 613
 614         val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
 615
 616         /* Someone is already using the tracer */
 617         if (val)
 618                 return -EBUSY;
 619
 620         switch (mode) {
 621         case CS_MODE_SYSFS:
 622                 ret = etm4_enable_sysfs(csdev);
 623                 break;
 624         case CS_MODE_PERF:
 625                 ret = etm4_enable_perf(csdev, event);
 626                 break;
 627         default:
 628                 ret = -EINVAL;
 629         }
 630
 631         /* The tracer didn't start */
 632         if (ret)
 633                 local_set(&drvdata->mode, CS_MODE_DISABLED);
 634
 635         return ret;
 636 }
 637
 638 static void etm4_disable_hw(void *info)
 639 {
 640         u32 control;
 641         struct etmv4_drvdata *drvdata = info;
 642         struct etmv4_config *config = &drvdata->config;
 643         struct coresight_device *csdev = drvdata->csdev;
 644         struct device *etm_dev = &csdev->dev;
 645         struct csdev_access *csa = &csdev->access;
 646         int i;
 647
 648         etm4_cs_unlock(drvdata, csa);
 649         etm4_disable_arch_specific(drvdata);
 650
 651         if (!drvdata->skip_power_up) {
 652                 /* power can be removed from the trace unit now */
 653                 control = etm4x_relaxed_read32(csa, TRCPDCR);
 654                 control &= ~TRCPDCR_PU;
 655                 etm4x_relaxed_write32(csa, control, TRCPDCR);
 656         }
 657
 658         control = etm4x_relaxed_read32(csa, TRCPRGCTLR);
 659
 660         /* EN, bit[0] Trace unit enable bit */
 661         control &= ~0x1;
 662
 663         /*
 664          * Make sure everything completes before disabling, as recommended
 665          * by section 7.3.77 ("TRCVICTLR, ViewInst Main Control Register,
 666          * SSTATUS") of ARM IHI 0064D
 667          */
 668         dsb(sy);
 669         isb();
 670         etm4x_relaxed_write32(csa, control, TRCPRGCTLR);
 671
 672         /* wait for TRCSTATR.PMSTABLE to go to '1' */
 673         if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1))
 674                 dev_err(etm_dev,
 675                         "timeout while waiting for PM stable Trace Status\n");
 676
 677         /* read the status of the single shot comparators */
 678         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
 679                 config->ss_status[i] =
 680                         etm4x_relaxed_read32(csa, TRCSSCSRn(i));
 681         }
 682
 683         /* read back the current counter values */
 684         for (i = 0; i < drvdata->nr_cntr; i++) {
 685                 config->cntr_val[i] =
 686                         etm4x_relaxed_read32(csa, TRCCNTVRn(i));
 687         }
 688
 689         coresight_disclaim_device_unlocked(csdev);
 690         etm4_cs_lock(drvdata, csa);
 691
 692         dev_dbg(&drvdata->csdev->dev,
 693                 "cpu: %d disable smp call done\n", drvdata->cpu);
 694 }
 695
 696 static int etm4_disable_perf(struct coresight_device *csdev,
 697                              struct perf_event *event)
 698 {
 699         u32 control;
 700         struct etm_filters *filters = event->hw.addr_filters;
 701         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 702
 703         if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
 704                 return -EINVAL;
 705
 706         etm4_disable_hw(drvdata);
 707
 708         /*
 709          * Check if the start/stop logic was active when the unit was stopped.
 710          * That way we can re-enable the start/stop logic when the process is
 711          * scheduled again.  Configuration of the start/stop logic happens in
 712          * function etm4_set_event_filters().
 713          */
 714         control = etm4x_relaxed_read32(&csdev->access, TRCVICTLR);
 715         /* TRCVICTLR::SSSTATUS, bit[9] */
 716         filters->ssstatus = (control & BIT(9));
 717
 718         return 0;
 719 }
 720
 721 static void etm4_disable_sysfs(struct coresight_device *csdev)
 722 {
 723         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 724
 725         /*
 726          * Taking hotplug lock here protects from clocks getting disabled
 727          * with tracing being left on (crash scenario) if user disable occurs
 728          * after cpu online mask indicates the cpu is offline but before the
 729          * DYING hotplug callback is serviced by the ETM driver.
 730          */
 731         cpus_read_lock();
 732         spin_lock(&drvdata->spinlock);
 733
 734         /*
 735          * Executing etm4_disable_hw on the cpu whose ETM is being disabled
 736          * ensures that register writes occur when cpu is powered.
 737          */
 738         smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1);
 739
 740         spin_unlock(&drvdata->spinlock);
 741         cpus_read_unlock();
 742
 743         dev_dbg(&csdev->dev, "ETM tracing disabled\n");
 744 }
 745
 746 static void etm4_disable(struct coresight_device *csdev,
 747                          struct perf_event *event)
 748 {
 749         u32 mode;
 750         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 751
 752         /*
 753          * For as long as the tracer isn't disabled another entity can't
 754          * change its status.  As such we can read the status here without
 755          * fearing it will change under us.
 756          */
 757         mode = local_read(&drvdata->mode);
 758
 759         switch (mode) {
 760         case CS_MODE_DISABLED:
 761                 break;
 762         case CS_MODE_SYSFS:
 763                 etm4_disable_sysfs(csdev);
 764                 break;
 765         case CS_MODE_PERF:
 766                 etm4_disable_perf(csdev, event);
 767                 break;
 768         }
 769
 770         if (mode)
 771                 local_set(&drvdata->mode, CS_MODE_DISABLED);
 772 }
 773
 774 static const struct coresight_ops_source etm4_source_ops = {
 775         .cpu_id         = etm4_cpu_id,
 776         .trace_id       = etm4_trace_id,
 777         .enable         = etm4_enable,
 778         .disable        = etm4_disable,
 779 };
 780
 781 static const struct coresight_ops etm4_cs_ops = {
 782         .source_ops     = &etm4_source_ops,
 783 };
 784
 785 static inline bool cpu_supports_sysreg_trace(void)
 786 {
 787         u64 dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1);
 788
 789         return ((dfr0 >> ID_AA64DFR0_TRACEVER_SHIFT) & 0xfUL) > 0;
 790 }
 791
 792 static bool etm4_init_sysreg_access(struct etmv4_drvdata *drvdata,
 793                                     struct csdev_access *csa)
 794 {
 795         u32 devarch;
 796
 797         if (!cpu_supports_sysreg_trace())
 798                 return false;
 799
 800         /*
 801          * ETMs implementing sysreg access must implement TRCDEVARCH.
 802          */
 803         devarch = read_etm4x_sysreg_const_offset(TRCDEVARCH);
 804         if ((devarch & ETM_DEVARCH_ID_MASK) != ETM_DEVARCH_ETMv4x_ARCH)
 805                 return false;
 806         *csa = (struct csdev_access) {
 807                 .io_mem = false,
 808                 .read   = etm4x_sysreg_read,
 809                 .write  = etm4x_sysreg_write,
 810         };
 811
 812         drvdata->arch = etm_devarch_to_arch(devarch);
 813         return true;
 814 }
 815
 816 static bool etm4_init_iomem_access(struct etmv4_drvdata *drvdata,
 817                                    struct csdev_access *csa)
 818 {
 819         u32 devarch = readl_relaxed(drvdata->base + TRCDEVARCH);
 820         u32 idr1 = readl_relaxed(drvdata->base + TRCIDR1);
 821
 822         /*
 823          * All ETMs must implement TRCDEVARCH to indicate that
 824          * the component is an ETMv4. To support any broken
 825          * implementations we fall back to TRCIDR1 check, which
 826          * is not really reliable.
 827          */
 828         if ((devarch & ETM_DEVARCH_ID_MASK) == ETM_DEVARCH_ETMv4x_ARCH) {
 829                 drvdata->arch = etm_devarch_to_arch(devarch);
 830         } else {
 831                 pr_warn("CPU%d: ETM4x incompatible TRCDEVARCH: %x, falling back to TRCIDR1\n",
 832                         smp_processor_id(), devarch);
 833
 834                 if (ETM_TRCIDR1_ARCH_MAJOR(idr1) != ETM_TRCIDR1_ARCH_ETMv4)
 835                         return false;
 836                 drvdata->arch = etm_trcidr_to_arch(idr1);
 837         }
 838
 839         *csa = CSDEV_ACCESS_IOMEM(drvdata->base);
 840         return true;
 841 }
 842
 843 static bool etm4_init_csdev_access(struct etmv4_drvdata *drvdata,
 844                                    struct csdev_access *csa)
 845 {
 846         /*
 847          * Always choose the memory mapped io, if there is
 848          * a memory map to prevent sysreg access on broken
 849          * systems.
 850          */
 851         if (drvdata->base)
 852                 return etm4_init_iomem_access(drvdata, csa);
 853
 854         if (etm4_init_sysreg_access(drvdata, csa))
 855                 return true;
 856
 857         return false;
 858 }
 859
 860 static void etm4_init_arch_data(void *info)
 861 {
 862         u32 etmidr0;
 863         u32 etmidr2;
 864         u32 etmidr3;
 865         u32 etmidr4;
 866         u32 etmidr5;
 867         struct etm4_init_arg *init_arg = info;
 868         struct etmv4_drvdata *drvdata;
 869         struct csdev_access *csa;
 870         int i;
 871
 872         drvdata = init_arg->drvdata;
 873         csa = init_arg->csa;
 874
 875         /*
 876          * If we are unable to detect the access mechanism,
 877          * or unable to detect the trace unit type, fail
 878          * early.
 879          */
 880         if (!etm4_init_csdev_access(drvdata, csa))
 881                 return;
 882
 883         /* Make sure all registers are accessible */
 884         etm4_os_unlock_csa(drvdata, csa);
 885         etm4_cs_unlock(drvdata, csa);
 886
 887         /* find all capabilities of the tracing unit */
 888         etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);
 889
 890         /* INSTP0, bits[2:1] P0 tracing support field */
 891         if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2))
 892                 drvdata->instrp0 = true;
 893         else
 894                 drvdata->instrp0 = false;
 895
 896         /* TRCBB, bit[5] Branch broadcast tracing support bit */
 897         if (BMVAL(etmidr0, 5, 5))
 898                 drvdata->trcbb = true;
 899         else
 900                 drvdata->trcbb = false;
 901
 902         /* TRCCOND, bit[6] Conditional instruction tracing support bit */
 903         if (BMVAL(etmidr0, 6, 6))
 904                 drvdata->trccond = true;
 905         else
 906                 drvdata->trccond = false;
 907
 908         /* TRCCCI, bit[7] Cycle counting instruction bit */
 909         if (BMVAL(etmidr0, 7, 7))
 910                 drvdata->trccci = true;
 911         else
 912                 drvdata->trccci = false;
 913
 914         /* RETSTACK, bit[9] Return stack bit */
 915         if (BMVAL(etmidr0, 9, 9))
 916                 drvdata->retstack = true;
 917         else
 918                 drvdata->retstack = false;
 919
 920         /* NUMEVENT, bits[11:10] Number of events field */
 921         drvdata->nr_event = BMVAL(etmidr0, 10, 11);
 922         /* QSUPP, bits[16:15] Q element support field */
 923         drvdata->q_support = BMVAL(etmidr0, 15, 16);
 924         /* TSSIZE, bits[28:24] Global timestamp size field */
 925         drvdata->ts_size = BMVAL(etmidr0, 24, 28);
 926
 927         /* maximum size of resources */
 928         etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2);
 929         /* CIDSIZE, bits[9:5] Indicates the Context ID size */
 930         drvdata->ctxid_size = BMVAL(etmidr2, 5, 9);
 931         /* VMIDSIZE, bits[14:10] Indicates the VMID size */
 932         drvdata->vmid_size = BMVAL(etmidr2, 10, 14);
 933         /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
 934         drvdata->ccsize = BMVAL(etmidr2, 25, 28);
 935
 936         etmidr3 = etm4x_relaxed_read32(csa, TRCIDR3);
 937         /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
 938         drvdata->ccitmin = BMVAL(etmidr3, 0, 11);
 939         /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
 940         drvdata->s_ex_level = BMVAL(etmidr3, 16, 19);
 941         drvdata->config.s_ex_level = drvdata->s_ex_level;
 942         /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
 943         drvdata->ns_ex_level = BMVAL(etmidr3, 20, 23);
 944
 945         /*
 946          * TRCERR, bit[24] whether a trace unit can trace a
 947          * system error exception.
 948          */
 949         if (BMVAL(etmidr3, 24, 24))
 950                 drvdata->trc_error = true;
 951         else
 952                 drvdata->trc_error = false;
 953
 954         /* SYNCPR, bit[25] implementation has a fixed synchronization period? */
 955         if (BMVAL(etmidr3, 25, 25))
 956                 drvdata->syncpr = true;
 957         else
 958                 drvdata->syncpr = false;
 959
 960         /* STALLCTL, bit[26] is stall control implemented? */
 961         if (BMVAL(etmidr3, 26, 26))
 962                 drvdata->stallctl = true;
 963         else
 964                 drvdata->stallctl = false;
 965
 966         /* SYSSTALL, bit[27] implementation can support stall control? */
 967         if (BMVAL(etmidr3, 27, 27))
 968                 drvdata->sysstall = true;
 969         else
 970                 drvdata->sysstall = false;
 971
 972         /*
 973          * NUMPROC - the number of PEs available for tracing, 5bits
 974          *         = TRCIDR3.bits[13:12]bits[30:28]
 975          *  bits[4:3] = TRCIDR3.bits[13:12] (since etm-v4.2, otherwise RES0)
 976          *  bits[3:0] = TRCIDR3.bits[30:28]
 977          */
 978         drvdata->nr_pe = (BMVAL(etmidr3, 12, 13) << 3) | BMVAL(etmidr3, 28, 30);
 979
 980         /* NOOVERFLOW, bit[31] is trace overflow prevention supported */
 981         if (BMVAL(etmidr3, 31, 31))
 982                 drvdata->nooverflow = true;
 983         else
 984                 drvdata->nooverflow = false;
 985
 986         /* number of resources trace unit supports */
 987         etmidr4 = etm4x_relaxed_read32(csa, TRCIDR4);
 988         /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
 989         drvdata->nr_addr_cmp = BMVAL(etmidr4, 0, 3);
 990         /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
 991         drvdata->nr_pe_cmp = BMVAL(etmidr4, 12, 15);
 992         /*
 993          * NUMRSPAIR, bits[19:16]
 994          * The number of resource pairs conveyed by the HW starts at 0, i.e a
 995          * value of 0x0 indicate 1 resource pair, 0x1 indicate two and so on.
 996          * As such add 1 to the value of NUMRSPAIR for a better representation.
 997          *
 998          * For ETM v4.3 and later, 0x0 means 0, and no pairs are available -
 999          * the default TRUE and FALSE resource selectors are omitted.
1000          * Otherwise for values 0x1 and above the number is N + 1 as per v4.2.
1001          */
1002         drvdata->nr_resource = BMVAL(etmidr4, 16, 19);
1003         if ((drvdata->arch < ETM_ARCH_V4_3) || (drvdata->nr_resource > 0))
1004                 drvdata->nr_resource += 1;
1005         /*
1006          * NUMSSCC, bits[23:20] the number of single-shot
1007          * comparator control for tracing. Read any status regs as these
1008          * also contain RO capability data.
1009          */
1010         drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23);
1011         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1012                 drvdata->config.ss_status[i] =
1013                         etm4x_relaxed_read32(csa, TRCSSCSRn(i));
1014         }
1015         /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
1016         drvdata->numcidc = BMVAL(etmidr4, 24, 27);
1017         /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
1018         drvdata->numvmidc = BMVAL(etmidr4, 28, 31);
1019
1020         etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5);
1021         /* NUMEXTIN, bits[8:0] number of external inputs implemented */
1022         drvdata->nr_ext_inp = BMVAL(etmidr5, 0, 8);
1023         /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
1024         drvdata->trcid_size = BMVAL(etmidr5, 16, 21);
1025         /* ATBTRIG, bit[22] implementation can support ATB triggers? */
1026         if (BMVAL(etmidr5, 22, 22))
1027                 drvdata->atbtrig = true;
1028         else
1029                 drvdata->atbtrig = false;
1030         /*
1031          * LPOVERRIDE, bit[23] implementation supports
1032          * low-power state override
1033          */
1034         if (BMVAL(etmidr5, 23, 23) && (!drvdata->skip_power_up))
1035                 drvdata->lpoverride = true;
1036         else
1037                 drvdata->lpoverride = false;
1038         /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
1039         drvdata->nrseqstate = BMVAL(etmidr5, 25, 27);
1040         /* NUMCNTR, bits[30:28] number of counters available for tracing */
1041         drvdata->nr_cntr = BMVAL(etmidr5, 28, 30);
1042         etm4_cs_lock(drvdata, csa);
1043 }
1044
1045 static inline u32 etm4_get_victlr_access_type(struct etmv4_config *config)
1046 {
1047         return etm4_get_access_type(config) << TRCVICTLR_EXLEVEL_SHIFT;
1048 }
1049
1050 /* Set ELx trace filter access in the TRCVICTLR register */
1051 static void etm4_set_victlr_access(struct etmv4_config *config)
1052 {
1053         config->vinst_ctrl &= ~TRCVICTLR_EXLEVEL_MASK;
1054         config->vinst_ctrl |= etm4_get_victlr_access_type(config);
1055 }
1056
1057 static void etm4_set_default_config(struct etmv4_config *config)
1058 {
1059         /* disable all events tracing */
1060         config->eventctrl0 = 0x0;
1061         config->eventctrl1 = 0x0;
1062
1063         /* disable stalling */
1064         config->stall_ctrl = 0x0;
1065
1066         /* enable trace synchronization every 4096 bytes, if available */
1067         config->syncfreq = 0xC;
1068
1069         /* disable timestamp event */
1070         config->ts_ctrl = 0x0;
1071
1072         /* TRCVICTLR::EVENT = 0x01, select the always on logic */
1073         config->vinst_ctrl = BIT(0);
1074
1075         /* TRCVICTLR::EXLEVEL_NS:EXLEVELS: Set kernel / user filtering */
1076         etm4_set_victlr_access(config);
1077 }
1078
1079 static u64 etm4_get_ns_access_type(struct etmv4_config *config)
1080 {
1081         u64 access_type = 0;
1082
1083         /*
1084          * EXLEVEL_NS, for NonSecure Exception levels.
1085          * The mask here is a generic value and must be
1086          * shifted to the corresponding field for the registers
1087          */
1088         if (!is_kernel_in_hyp_mode()) {
1089                 /* Stay away from hypervisor mode for non-VHE */
1090                 access_type =  ETM_EXLEVEL_NS_HYP;
1091                 if (config->mode & ETM_MODE_EXCL_KERN)
1092                         access_type |= ETM_EXLEVEL_NS_OS;
1093         } else if (config->mode & ETM_MODE_EXCL_KERN) {
1094                 access_type = ETM_EXLEVEL_NS_HYP;
1095         }
1096
1097         if (config->mode & ETM_MODE_EXCL_USER)
1098                 access_type |= ETM_EXLEVEL_NS_APP;
1099
1100         return access_type;
1101 }
1102
1103 /*
1104  * Construct the exception level masks for a given config.
1105  * This must be shifted to the corresponding register field
1106  * for usage.
1107  */
1108 static u64 etm4_get_access_type(struct etmv4_config *config)
1109 {
1110         /* All Secure exception levels are excluded from the trace */
1111         return etm4_get_ns_access_type(config) | (u64)config->s_ex_level;
1112 }
1113
1114 static u64 etm4_get_comparator_access_type(struct etmv4_config *config)
1115 {
1116         return etm4_get_access_type(config) << TRCACATR_EXLEVEL_SHIFT;
1117 }
1118
1119 static void etm4_set_comparator_filter(struct etmv4_config *config,
1120                                        u64 start, u64 stop, int comparator)
1121 {
1122         u64 access_type = etm4_get_comparator_access_type(config);
1123
1124         /* First half of default address comparator */
1125         config->addr_val[comparator] = start;
1126         config->addr_acc[comparator] = access_type;
1127         config->addr_type[comparator] = ETM_ADDR_TYPE_RANGE;
1128
1129         /* Second half of default address comparator */
1130         config->addr_val[comparator + 1] = stop;
1131         config->addr_acc[comparator + 1] = access_type;
1132         config->addr_type[comparator + 1] = ETM_ADDR_TYPE_RANGE;
1133
1134         /*
1135          * Configure the ViewInst function to include this address range
1136          * comparator.
1137          *
1138          * @comparator is divided by two since it is the index in the
1139          * etmv4_config::addr_val array but register TRCVIIECTLR deals with
1140          * address range comparator _pairs_.
1141          *
1142          * Therefore:
1143          *      index 0 -> compatator pair 0
1144          *      index 2 -> comparator pair 1
1145          *      index 4 -> comparator pair 2
1146          *      ...
1147          *      index 14 -> comparator pair 7
1148          */
1149         config->viiectlr |= BIT(comparator / 2);
1150 }
1151
1152 static void etm4_set_start_stop_filter(struct etmv4_config *config,
1153                                        u64 address, int comparator,
1154                                        enum etm_addr_type type)
1155 {
1156         int shift;
1157         u64 access_type = etm4_get_comparator_access_type(config);
1158
1159         /* Configure the comparator */
1160         config->addr_val[comparator] = address;
1161         config->addr_acc[comparator] = access_type;
1162         config->addr_type[comparator] = type;
1163
1164         /*
1165          * Configure ViewInst Start-Stop control register.
1166          * Addresses configured to start tracing go from bit 0 to n-1,
1167          * while those configured to stop tracing from 16 to 16 + n-1.
1168          */
1169         shift = (type == ETM_ADDR_TYPE_START ? 0 : 16);
1170         config->vissctlr |= BIT(shift + comparator);
1171 }
1172
1173 static void etm4_set_default_filter(struct etmv4_config *config)
1174 {
1175         /* Trace everything 'default' filter achieved by no filtering */
1176         config->viiectlr = 0x0;
1177
1178         /*
1179          * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1180          * in the started state
1181          */
1182         config->vinst_ctrl |= BIT(9);
1183         config->mode |= ETM_MODE_VIEWINST_STARTSTOP;
1184
1185         /* No start-stop filtering for ViewInst */
1186         config->vissctlr = 0x0;
1187 }
1188
1189 static void etm4_set_default(struct etmv4_config *config)
1190 {
1191         if (WARN_ON_ONCE(!config))
1192                 return;
1193
1194         /*
1195          * Make default initialisation trace everything
1196          *
1197          * This is done by a minimum default config sufficient to enable
1198          * full instruction trace - with a default filter for trace all
1199          * achieved by having no filtering.
1200          */
1201         etm4_set_default_config(config);
1202         etm4_set_default_filter(config);
1203 }
1204
1205 static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type)
1206 {
1207         int nr_comparator, index = 0;
1208         struct etmv4_config *config = &drvdata->config;
1209
1210         /*
1211          * nr_addr_cmp holds the number of comparator _pair_, so time 2
1212          * for the total number of comparators.
1213          */
1214         nr_comparator = drvdata->nr_addr_cmp * 2;
1215
1216         /* Go through the tally of comparators looking for a free one. */
1217         while (index < nr_comparator) {
1218                 switch (type) {
1219                 case ETM_ADDR_TYPE_RANGE:
1220                         if (config->addr_type[index] == ETM_ADDR_TYPE_NONE &&
1221                             config->addr_type[index + 1] == ETM_ADDR_TYPE_NONE)
1222                                 return index;
1223
1224                         /* Address range comparators go in pairs */
1225                         index += 2;
1226                         break;
1227                 case ETM_ADDR_TYPE_START:
1228                 case ETM_ADDR_TYPE_STOP:
1229                         if (config->addr_type[index] == ETM_ADDR_TYPE_NONE)
1230                                 return index;
1231
1232                         /* Start/stop address can have odd indexes */
1233                         index += 1;
1234                         break;
1235                 default:
1236                         return -EINVAL;
1237                 }
1238         }
1239
1240         /* If we are here all the comparators have been used. */
1241         return -ENOSPC;
1242 }
1243
1244 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
1245                                   struct perf_event *event)
1246 {
1247         int i, comparator, ret = 0;
1248         u64 address;
1249         struct etmv4_config *config = &drvdata->config;
1250         struct etm_filters *filters = event->hw.addr_filters;
1251
1252         if (!filters)
1253                 goto default_filter;
1254
1255         /* Sync events with what Perf got */
1256         perf_event_addr_filters_sync(event);
1257
1258         /*
1259          * If there are no filters to deal with simply go ahead with
1260          * the default filter, i.e the entire address range.
1261          */
1262         if (!filters->nr_filters)
1263                 goto default_filter;
1264
1265         for (i = 0; i < filters->nr_filters; i++) {
1266                 struct etm_filter *filter = &filters->etm_filter[i];
1267                 enum etm_addr_type type = filter->type;
1268
1269                 /* See if a comparator is free. */
1270                 comparator = etm4_get_next_comparator(drvdata, type);
1271                 if (comparator < 0) {
1272                         ret = comparator;
1273                         goto out;
1274                 }
1275
1276                 switch (type) {
1277                 case ETM_ADDR_TYPE_RANGE:
1278                         etm4_set_comparator_filter(config,
1279                                                    filter->start_addr,
1280                                                    filter->stop_addr,
1281                                                    comparator);
1282                         /*
1283                          * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1284                          * in the started state
1285                          */
1286                         config->vinst_ctrl |= BIT(9);
1287
1288                         /* No start-stop filtering for ViewInst */
1289                         config->vissctlr = 0x0;
1290                         break;
1291                 case ETM_ADDR_TYPE_START:
1292                 case ETM_ADDR_TYPE_STOP:
1293                         /* Get the right start or stop address */
1294                         address = (type == ETM_ADDR_TYPE_START ?
1295                                    filter->start_addr :
1296                                    filter->stop_addr);
1297
1298                         /* Configure comparator */
1299                         etm4_set_start_stop_filter(config, address,
1300                                                    comparator, type);
1301
1302                         /*
1303                          * If filters::ssstatus == 1, trace acquisition was
1304                          * started but the process was yanked away before the
1305                          * the stop address was hit.  As such the start/stop
1306                          * logic needs to be re-started so that tracing can
1307                          * resume where it left.
1308                          *
1309                          * The start/stop logic status when a process is
1310                          * scheduled out is checked in function
1311                          * etm4_disable_perf().
1312                          */
1313                         if (filters->ssstatus)
1314                                 config->vinst_ctrl |= BIT(9);
1315
1316                         /* No include/exclude filtering for ViewInst */
1317                         config->viiectlr = 0x0;
1318                         break;
1319                 default:
1320                         ret = -EINVAL;
1321                         goto out;
1322                 }
1323         }
1324
1325         goto out;
1326
1327
1328 default_filter:
1329         etm4_set_default_filter(config);
1330
1331 out:
1332         return ret;
1333 }
1334
1335 void etm4_config_trace_mode(struct etmv4_config *config)
1336 {
1337         u32 mode;
1338
1339         mode = config->mode;
1340         mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
1341
1342         /* excluding kernel AND user space doesn't make sense */
1343         WARN_ON_ONCE(mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER));
1344
1345         /* nothing to do if neither flags are set */
1346         if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
1347                 return;
1348
1349         etm4_set_victlr_access(config);
1350 }
1351
1352 static int etm4_online_cpu(unsigned int cpu)
1353 {
1354         if (!etmdrvdata[cpu])
1355                 return 0;
1356
1357         if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable)
1358                 coresight_enable(etmdrvdata[cpu]->csdev);
1359         return 0;
1360 }
1361
1362 static int etm4_starting_cpu(unsigned int cpu)
1363 {
1364         if (!etmdrvdata[cpu])
1365                 return 0;
1366
1367         spin_lock(&etmdrvdata[cpu]->spinlock);
1368         if (!etmdrvdata[cpu]->os_unlock)
1369                 etm4_os_unlock(etmdrvdata[cpu]);
1370
1371         if (local_read(&etmdrvdata[cpu]->mode))
1372                 etm4_enable_hw(etmdrvdata[cpu]);
1373         spin_unlock(&etmdrvdata[cpu]->spinlock);
1374         return 0;
1375 }
1376
1377 static int etm4_dying_cpu(unsigned int cpu)
1378 {
1379         if (!etmdrvdata[cpu])
1380                 return 0;
1381
1382         spin_lock(&etmdrvdata[cpu]->spinlock);
1383         if (local_read(&etmdrvdata[cpu]->mode))
1384                 etm4_disable_hw(etmdrvdata[cpu]);
1385         spin_unlock(&etmdrvdata[cpu]->spinlock);
1386         return 0;
1387 }
1388
1389 static void etm4_init_trace_id(struct etmv4_drvdata *drvdata)
1390 {
1391         drvdata->trcid = coresight_get_trace_id(drvdata->cpu);
1392 }
1393
1394 static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
1395 {
1396         int i, ret = 0;
1397         struct etmv4_save_state *state;
1398         struct coresight_device *csdev = drvdata->csdev;
1399         struct csdev_access *csa;
1400         struct device *etm_dev;
1401
1402         if (WARN_ON(!csdev))
1403                 return -ENODEV;
1404
1405         etm_dev = &csdev->dev;
1406         csa = &csdev->access;
1407
1408         /*
1409          * As recommended by 3.4.1 ("The procedure when powering down the PE")
1410          * of ARM IHI 0064D
1411          */
1412         dsb(sy);
1413         isb();
1414
1415         etm4_cs_unlock(drvdata, csa);
1416         /* Lock the OS lock to disable trace and external debugger access */
1417         etm4_os_lock(drvdata);
1418
1419         /* wait for TRCSTATR.PMSTABLE to go up */
1420         if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1)) {
1421                 dev_err(etm_dev,
1422                         "timeout while waiting for PM Stable Status\n");
1423                 etm4_os_unlock(drvdata);
1424                 ret = -EBUSY;
1425                 goto out;
1426         }
1427
1428         state = drvdata->save_state;
1429
1430         state->trcprgctlr = etm4x_read32(csa, TRCPRGCTLR);
1431         if (drvdata->nr_pe)
1432                 state->trcprocselr = etm4x_read32(csa, TRCPROCSELR);
1433         state->trcconfigr = etm4x_read32(csa, TRCCONFIGR);
1434         state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR);
1435         state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R);
1436         state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R);
1437         state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
1438         state->trctsctlr = etm4x_read32(csa, TRCTSCTLR);
1439         state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR);
1440         state->trcccctlr = etm4x_read32(csa, TRCCCCTLR);
1441         state->trcbbctlr = etm4x_read32(csa, TRCBBCTLR);
1442         state->trctraceidr = etm4x_read32(csa, TRCTRACEIDR);
1443         state->trcqctlr = etm4x_read32(csa, TRCQCTLR);
1444
1445         state->trcvictlr = etm4x_read32(csa, TRCVICTLR);
1446         state->trcviiectlr = etm4x_read32(csa, TRCVIIECTLR);
1447         state->trcvissctlr = etm4x_read32(csa, TRCVISSCTLR);
1448         if (drvdata->nr_pe_cmp)
1449                 state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR);
1450         state->trcvdctlr = etm4x_read32(csa, TRCVDCTLR);
1451         state->trcvdsacctlr = etm4x_read32(csa, TRCVDSACCTLR);
1452         state->trcvdarcctlr = etm4x_read32(csa, TRCVDARCCTLR);
1453
1454         for (i = 0; i < drvdata->nrseqstate - 1; i++)
1455                 state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
1456
1457         state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR);
1458         state->trcseqstr = etm4x_read32(csa, TRCSEQSTR);
1459         state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR);
1460
1461         for (i = 0; i < drvdata->nr_cntr; i++) {
1462                 state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i));
1463                 state->trccntctlr[i] = etm4x_read32(csa, TRCCNTCTLRn(i));
1464                 state->trccntvr[i] = etm4x_read32(csa, TRCCNTVRn(i));
1465         }
1466
1467         for (i = 0; i < drvdata->nr_resource * 2; i++)
1468                 state->trcrsctlr[i] = etm4x_read32(csa, TRCRSCTLRn(i));
1469
1470         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1471                 state->trcssccr[i] = etm4x_read32(csa, TRCSSCCRn(i));
1472                 state->trcsscsr[i] = etm4x_read32(csa, TRCSSCSRn(i));
1473                 if (etm4x_sspcicrn_present(drvdata, i))
1474                         state->trcsspcicr[i] = etm4x_read32(csa, TRCSSPCICRn(i));
1475         }
1476
1477         for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1478                 state->trcacvr[i] = etm4x_read64(csa, TRCACVRn(i));
1479                 state->trcacatr[i] = etm4x_read64(csa, TRCACATRn(i));
1480         }
1481
1482         /*
1483          * Data trace stream is architecturally prohibited for A profile cores
1484          * so we don't save (or later restore) trcdvcvr and trcdvcmr - As per
1485          * section 1.3.4 ("Possible functional configurations of an ETMv4 trace
1486          * unit") of ARM IHI 0064D.
1487          */
1488
1489         for (i = 0; i < drvdata->numcidc; i++)
1490                 state->trccidcvr[i] = etm4x_read64(csa, TRCCIDCVRn(i));
1491
1492         for (i = 0; i < drvdata->numvmidc; i++)
1493                 state->trcvmidcvr[i] = etm4x_read64(csa, TRCVMIDCVRn(i));
1494
1495         state->trccidcctlr0 = etm4x_read32(csa, TRCCIDCCTLR0);
1496         if (drvdata->numcidc > 4)
1497                 state->trccidcctlr1 = etm4x_read32(csa, TRCCIDCCTLR1);
1498
1499         state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR0);
1500         if (drvdata->numvmidc > 4)
1501                 state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR1);
1502
1503         state->trcclaimset = etm4x_read32(csa, TRCCLAIMCLR);
1504
1505         if (!drvdata->skip_power_up)
1506                 state->trcpdcr = etm4x_read32(csa, TRCPDCR);
1507
1508         /* wait for TRCSTATR.IDLE to go up */
1509         if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) {
1510                 dev_err(etm_dev,
1511                         "timeout while waiting for Idle Trace Status\n");
1512                 etm4_os_unlock(drvdata);
1513                 ret = -EBUSY;
1514                 goto out;
1515         }
1516
1517         drvdata->state_needs_restore = true;
1518
1519         /*
1520          * Power can be removed from the trace unit now. We do this to
1521          * potentially save power on systems that respect the TRCPDCR_PU
1522          * despite requesting software to save/restore state.
1523          */
1524         if (!drvdata->skip_power_up)
1525                 etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU),
1526                                       TRCPDCR);
1527 out:
1528         etm4_cs_lock(drvdata, csa);
1529         return ret;
1530 }
1531
1532 static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
1533 {
1534         int i;
1535         struct etmv4_save_state *state = drvdata->save_state;
1536         struct csdev_access tmp_csa = CSDEV_ACCESS_IOMEM(drvdata->base);
1537         struct csdev_access *csa = &tmp_csa;
1538
1539         etm4_cs_unlock(drvdata, csa);
1540         etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
1541
1542         etm4x_relaxed_write32(csa, state->trcprgctlr, TRCPRGCTLR);
1543         if (drvdata->nr_pe)
1544                 etm4x_relaxed_write32(csa, state->trcprocselr, TRCPROCSELR);
1545         etm4x_relaxed_write32(csa, state->trcconfigr, TRCCONFIGR);
1546         etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR);
1547         etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R);
1548         etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R);
1549         etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
1550         etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR);
1551         etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR);
1552         etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR);
1553         etm4x_relaxed_write32(csa, state->trcbbctlr, TRCBBCTLR);
1554         etm4x_relaxed_write32(csa, state->trctraceidr, TRCTRACEIDR);
1555         etm4x_relaxed_write32(csa, state->trcqctlr, TRCQCTLR);
1556
1557         etm4x_relaxed_write32(csa, state->trcvictlr, TRCVICTLR);
1558         etm4x_relaxed_write32(csa, state->trcviiectlr, TRCVIIECTLR);
1559         etm4x_relaxed_write32(csa, state->trcvissctlr, TRCVISSCTLR);
1560         if (drvdata->nr_pe_cmp)
1561                 etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR);
1562         etm4x_relaxed_write32(csa, state->trcvdctlr, TRCVDCTLR);
1563         etm4x_relaxed_write32(csa, state->trcvdsacctlr, TRCVDSACCTLR);
1564         etm4x_relaxed_write32(csa, state->trcvdarcctlr, TRCVDARCCTLR);
1565
1566         for (i = 0; i < drvdata->nrseqstate - 1; i++)
1567                 etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
1568
1569         etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR);
1570         etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR);
1571         etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR);
1572
1573         for (i = 0; i < drvdata->nr_cntr; i++) {
1574                 etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i));
1575                 etm4x_relaxed_write32(csa, state->trccntctlr[i], TRCCNTCTLRn(i));
1576                 etm4x_relaxed_write32(csa, state->trccntvr[i], TRCCNTVRn(i));
1577         }
1578
1579         for (i = 0; i < drvdata->nr_resource * 2; i++)
1580                 etm4x_relaxed_write32(csa, state->trcrsctlr[i], TRCRSCTLRn(i));
1581
1582         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1583                 etm4x_relaxed_write32(csa, state->trcssccr[i], TRCSSCCRn(i));
1584                 etm4x_relaxed_write32(csa, state->trcsscsr[i], TRCSSCSRn(i));
1585                 if (etm4x_sspcicrn_present(drvdata, i))
1586                         etm4x_relaxed_write32(csa, state->trcsspcicr[i], TRCSSPCICRn(i));
1587         }
1588
1589         for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1590                 etm4x_relaxed_write64(csa, state->trcacvr[i], TRCACVRn(i));
1591                 etm4x_relaxed_write64(csa, state->trcacatr[i], TRCACATRn(i));
1592         }
1593
1594         for (i = 0; i < drvdata->numcidc; i++)
1595                 etm4x_relaxed_write64(csa, state->trccidcvr[i], TRCCIDCVRn(i));
1596
1597         for (i = 0; i < drvdata->numvmidc; i++)
1598                 etm4x_relaxed_write64(csa, state->trcvmidcvr[i], TRCVMIDCVRn(i));
1599
1600         etm4x_relaxed_write32(csa, state->trccidcctlr0, TRCCIDCCTLR0);
1601         if (drvdata->numcidc > 4)
1602                 etm4x_relaxed_write32(csa, state->trccidcctlr1, TRCCIDCCTLR1);
1603
1604         etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR0);
1605         if (drvdata->numvmidc > 4)
1606                 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR1);
1607
1608         etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
1609
1610         if (!drvdata->skip_power_up)
1611                 etm4x_relaxed_write32(csa, state->trcpdcr, TRCPDCR);
1612
1613         drvdata->state_needs_restore = false;
1614
1615         /*
1616          * As recommended by section 4.3.7 ("Synchronization when using the
1617          * memory-mapped interface") of ARM IHI 0064D
1618          */
1619         dsb(sy);
1620         isb();
1621
1622         /* Unlock the OS lock to re-enable trace and external debug access */
1623         etm4_os_unlock(drvdata);
1624         etm4_cs_lock(drvdata, csa);
1625 }
1626
1627 static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd,
1628                               void *v)
1629 {
1630         struct etmv4_drvdata *drvdata;
1631         unsigned int cpu = smp_processor_id();
1632
1633         if (!etmdrvdata[cpu])
1634                 return NOTIFY_OK;
1635
1636         drvdata = etmdrvdata[cpu];
1637
1638         if (!drvdata->save_state)
1639                 return NOTIFY_OK;
1640
1641         if (WARN_ON_ONCE(drvdata->cpu != cpu))
1642                 return NOTIFY_BAD;
1643
1644         switch (cmd) {
1645         case CPU_PM_ENTER:
1646                 /* save the state if self-hosted coresight is in use */
1647                 if (local_read(&drvdata->mode))
1648                         if (etm4_cpu_save(drvdata))
1649                                 return NOTIFY_BAD;
1650                 break;
1651         case CPU_PM_EXIT:
1652         case CPU_PM_ENTER_FAILED:
1653                 if (drvdata->state_needs_restore)
1654                         etm4_cpu_restore(drvdata);
1655                 break;
1656         default:
1657                 return NOTIFY_DONE;
1658         }
1659
1660         return NOTIFY_OK;
1661 }
1662
1663 static struct notifier_block etm4_cpu_pm_nb = {
1664         .notifier_call = etm4_cpu_pm_notify,
1665 };
1666
1667 /* Setup PM. Deals with error conditions and counts */
1668 static int __init etm4_pm_setup(void)
1669 {
1670         int ret;
1671
1672         ret = cpu_pm_register_notifier(&etm4_cpu_pm_nb);
1673         if (ret)
1674                 return ret;
1675
1676         ret = cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING,
1677                                         "arm/coresight4:starting",
1678                                         etm4_starting_cpu, etm4_dying_cpu);
1679
1680         if (ret)
1681                 goto unregister_notifier;
1682
1683         ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN,
1684                                         "arm/coresight4:online",
1685                                         etm4_online_cpu, NULL);
1686
1687         /* HP dyn state ID returned in ret on success */
1688         if (ret > 0) {
1689                 hp_online = ret;
1690                 return 0;
1691         }
1692
1693         /* failed dyn state - remove others */
1694         cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
1695
1696 unregister_notifier:
1697         cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
1698         return ret;
1699 }
1700
1701 static void etm4_pm_clear(void)
1702 {
1703         cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
1704         cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
1705         if (hp_online) {
1706                 cpuhp_remove_state_nocalls(hp_online);
1707                 hp_online = 0;
1708         }
1709 }
1710
1711 static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
1712 {
1713         int ret;
1714         void __iomem *base;
1715         struct device *dev = &adev->dev;
1716         struct coresight_platform_data *pdata = NULL;
1717         struct etmv4_drvdata *drvdata;
1718         struct resource *res = &adev->res;
1719         struct coresight_desc desc = { 0 };
1720         struct etm4_init_arg init_arg = { 0 };
1721
1722         drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
1723         if (!drvdata)
1724                 return -ENOMEM;
1725
1726         dev_set_drvdata(dev, drvdata);
1727
1728         if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE)
1729                 pm_save_enable = coresight_loses_context_with_cpu(dev) ?
1730                                PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER;
1731
1732         if (pm_save_enable != PARAM_PM_SAVE_NEVER) {
1733                 drvdata->save_state = devm_kmalloc(dev,
1734                                 sizeof(struct etmv4_save_state), GFP_KERNEL);
1735                 if (!drvdata->save_state)
1736                         return -ENOMEM;
1737         }
1738
1739         if (fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up"))
1740                 drvdata->skip_power_up = true;
1741
1742         /* Validity for the resource is already checked by the AMBA core */
1743         base = devm_ioremap_resource(dev, res);
1744         if (IS_ERR(base))
1745                 return PTR_ERR(base);
1746
1747         drvdata->base = base;
1748
1749         spin_lock_init(&drvdata->spinlock);
1750
1751         drvdata->cpu = coresight_get_cpu(dev);
1752         if (drvdata->cpu < 0)
1753                 return drvdata->cpu;
1754
1755         desc.name = devm_kasprintf(dev, GFP_KERNEL, "etm%d", drvdata->cpu);
1756         if (!desc.name)
1757                 return -ENOMEM;
1758
1759         init_arg.drvdata = drvdata;
1760         init_arg.csa = &desc.access;
1761
1762         if (smp_call_function_single(drvdata->cpu,
1763                                 etm4_init_arch_data,  &init_arg, 1))
1764                 dev_err(dev, "ETM arch init failed\n");
1765
1766         if (!drvdata->arch)
1767                 return -EINVAL;
1768
1769         etm4_init_trace_id(drvdata);
1770         etm4_set_default(&drvdata->config);
1771
1772         pdata = coresight_get_platform_data(dev);
1773         if (IS_ERR(pdata))
1774                 return PTR_ERR(pdata);
1775
1776         adev->dev.platform_data = pdata;
1777
1778         desc.type = CORESIGHT_DEV_TYPE_SOURCE;
1779         desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
1780         desc.ops = &etm4_cs_ops;
1781         desc.pdata = pdata;
1782         desc.dev = dev;
1783         desc.groups = coresight_etmv4_groups;
1784         drvdata->csdev = coresight_register(&desc);
1785         if (IS_ERR(drvdata->csdev))
1786                 return PTR_ERR(drvdata->csdev);
1787
1788         ret = etm_perf_symlink(drvdata->csdev, true);
1789         if (ret) {
1790                 coresight_unregister(drvdata->csdev);
1791                 return ret;
1792         }
1793
1794         etmdrvdata[drvdata->cpu] = drvdata;
1795
1796         pm_runtime_put(&adev->dev);
1797         dev_info(&drvdata->csdev->dev, "CPU%d: ETM v%d.%d initialized\n",
1798                  drvdata->cpu, ETM_ARCH_MAJOR_VERSION(drvdata->arch),
1799                  ETM_ARCH_MINOR_VERSION(drvdata->arch));
1800
1801         if (boot_enable) {
1802                 coresight_enable(drvdata->csdev);
1803                 drvdata->boot_enable = true;
1804         }
1805
1806         etm4_check_arch_features(drvdata, id->id);
1807
1808         return 0;
1809 }
1810
1811 static struct amba_cs_uci_id uci_id_etm4[] = {
1812         {
1813                 /*  ETMv4 UCI data */
1814                 .devarch        = ETM_DEVARCH_ETMv4x_ARCH,
1815                 .devarch_mask   = ETM_DEVARCH_ID_MASK,
1816                 .devtype        = 0x00000013,
1817         }
1818 };
1819
1820 static void clear_etmdrvdata(void *info)
1821 {
1822         int cpu = *(int *)info;
1823
1824         etmdrvdata[cpu] = NULL;
1825 }
1826
1827 static int etm4_remove(struct amba_device *adev)
1828 {
1829         struct etmv4_drvdata *drvdata = dev_get_drvdata(&adev->dev);
1830
1831         etm_perf_symlink(drvdata->csdev, false);
1832
1833         /*
1834          * Taking hotplug lock here to avoid racing between etm4_remove and
1835          * CPU hotplug call backs.
1836          */
1837         cpus_read_lock();
1838         /*
1839          * The readers for etmdrvdata[] are CPU hotplug call backs
1840          * and PM notification call backs. Change etmdrvdata[i] on
1841          * CPU i ensures these call backs has consistent view
1842          * inside one call back function.
1843          */
1844         if (smp_call_function_single(drvdata->cpu, clear_etmdrvdata, &drvdata->cpu, 1))
1845                 etmdrvdata[drvdata->cpu] = NULL;
1846
1847         cpus_read_unlock();
1848
1849         coresight_unregister(drvdata->csdev);
1850
1851         return 0;
1852 }
1853
1854 static const struct amba_id etm4_ids[] = {
1855         CS_AMBA_ID(0x000bb95d),                 /* Cortex-A53 */
1856         CS_AMBA_ID(0x000bb95e),                 /* Cortex-A57 */
1857         CS_AMBA_ID(0x000bb95a),                 /* Cortex-A72 */
1858         CS_AMBA_ID(0x000bb959),                 /* Cortex-A73 */
1859         CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */
1860         CS_AMBA_UCI_ID(0x000bbd05, uci_id_etm4),/* Cortex-A55 */
1861         CS_AMBA_UCI_ID(0x000bbd0a, uci_id_etm4),/* Cortex-A75 */
1862         CS_AMBA_UCI_ID(0x000bbd0c, uci_id_etm4),/* Neoverse N1 */
1863         CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */
1864         CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */
1865         CS_AMBA_UCI_ID(0x000bb802, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A55 */
1866         CS_AMBA_UCI_ID(0x000bb803, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A75 */
1867         CS_AMBA_UCI_ID(0x000bb805, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A55 */
1868         CS_AMBA_UCI_ID(0x000bb804, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A76 */
1869         CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */
1870         CS_AMBA_UCI_ID(0x000b6d01, uci_id_etm4),/* HiSilicon-Hip08 */
1871         CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */
1872         {},
1873 };
1874
1875 MODULE_DEVICE_TABLE(amba, etm4_ids);
1876
1877 static struct amba_driver etm4x_driver = {
1878         .drv = {
1879                 .name   = "coresight-etm4x",
1880                 .owner  = THIS_MODULE,
1881                 .suppress_bind_attrs = true,
1882         },
1883         .probe          = etm4_probe,
1884         .remove         = etm4_remove,
1885         .id_table       = etm4_ids,
1886 };
1887
1888 static int __init etm4x_init(void)
1889 {
1890         int ret;
1891
1892         ret = etm4_pm_setup();
1893
1894         /* etm4_pm_setup() does its own cleanup - exit on error */
1895         if (ret)
1896                 return ret;
1897
1898         ret = amba_driver_register(&etm4x_driver);
1899         if (ret) {
1900                 pr_err("Error registering etm4x driver\n");
1901                 etm4_pm_clear();
1902         }
1903
1904         return ret;
1905 }
1906
1907 static void __exit etm4x_exit(void)
1908 {
1909         amba_driver_unregister(&etm4x_driver);
1910         etm4_pm_clear();
1911 }
1912
1913 module_init(etm4x_init);
1914 module_exit(etm4x_exit);
1915
1916 MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
1917 MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier@linaro.org>");
1918 MODULE_DESCRIPTION("Arm CoreSight Program Flow Trace v4.x driver");
1919 MODULE_LICENSE("GPL v2");