drivers/hwtracing/coresight/coresight-etm4x-core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/bitops.h>
   7 #include <linux/kernel.h>
   8 #include <linux/moduleparam.h>
   9 #include <linux/init.h>
  10 #include <linux/types.h>
  11 #include <linux/device.h>
  12 #include <linux/io.h>
  13 #include <linux/err.h>
  14 #include <linux/fs.h>
  15 #include <linux/slab.h>
  16 #include <linux/delay.h>
  17 #include <linux/smp.h>
  18 #include <linux/sysfs.h>
  19 #include <linux/stat.h>
  20 #include <linux/clk.h>
  21 #include <linux/cpu.h>
  22 #include <linux/cpu_pm.h>
  23 #include <linux/coresight.h>
  24 #include <linux/coresight-pmu.h>
  25 #include <linux/pm_wakeup.h>
  26 #include <linux/amba/bus.h>
  27 #include <linux/seq_file.h>
  28 #include <linux/uaccess.h>
  29 #include <linux/perf_event.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/property.h>
  32
  33 #include <asm/sections.h>
  34 #include <asm/sysreg.h>
  35 #include <asm/local.h>
  36 #include <asm/virt.h>
  37
  38 #include "coresight-etm4x.h"
  39 #include "coresight-etm-perf.h"
  40
  41 static int boot_enable;
  42 module_param(boot_enable, int, 0444);
  43 MODULE_PARM_DESC(boot_enable, "Enable tracing on boot");
  44
  45 #define PARAM_PM_SAVE_FIRMWARE    0 /* save self-hosted state as per firmware */
  46 #define PARAM_PM_SAVE_NEVER       1 /* never save any state */
  47 #define PARAM_PM_SAVE_SELF_HOSTED 2 /* save self-hosted state only */
  48
  49 static int pm_save_enable = PARAM_PM_SAVE_FIRMWARE;
  50 module_param(pm_save_enable, int, 0444);
  51 MODULE_PARM_DESC(pm_save_enable,
  52         "Save/restore state on power down: 1 = never, 2 = self-hosted");
  53
  54 static struct etmv4_drvdata *etmdrvdata[NR_CPUS];
  55 static void etm4_set_default_config(struct etmv4_config *config);
  56 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
  57                                   struct perf_event *event);
  58 static u64 etm4_get_access_type(struct etmv4_config *config);
  59
  60 static enum cpuhp_state hp_online;
  61
  62 static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
  63 {
  64         /* Writing 0 to TRCOSLAR unlocks the trace registers */
  65         writel_relaxed(0x0, drvdata->base + TRCOSLAR);
  66         drvdata->os_unlock = true;
  67         isb();
  68 }
  69
  70 static void etm4_os_lock(struct etmv4_drvdata *drvdata)
  71 {
  72         /* Writing 0x1 to TRCOSLAR locks the trace registers */
  73         writel_relaxed(0x1, drvdata->base + TRCOSLAR);
  74         drvdata->os_unlock = false;
  75         isb();
  76 }
  77
  78 static bool etm4_arch_supported(u8 arch)
  79 {
  80         /* Mask out the minor version number */
  81         switch (arch & 0xf0) {
  82         case ETM_ARCH_V4:
  83                 break;
  84         default:
  85                 return false;
  86         }
  87         return true;
  88 }
  89
  90 static int etm4_cpu_id(struct coresight_device *csdev)
  91 {
  92         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  93
  94         return drvdata->cpu;
  95 }
  96
  97 static int etm4_trace_id(struct coresight_device *csdev)
  98 {
  99         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 100
 101         return drvdata->trcid;
 102 }
 103
 104 struct etm4_enable_arg {
 105         struct etmv4_drvdata *drvdata;
 106         int rc;
 107 };
 108
 109 #ifdef CONFIG_ETM4X_IMPDEF_FEATURE
 110
 111 #define HISI_HIP08_AMBA_ID              0x000b6d01
 112 #define ETM4_AMBA_MASK                  0xfffff
 113 #define HISI_HIP08_CORE_COMMIT_MASK     0x3000
 114 #define HISI_HIP08_CORE_COMMIT_SHIFT    12
 115 #define HISI_HIP08_CORE_COMMIT_FULL     0b00
 116 #define HISI_HIP08_CORE_COMMIT_LVL_1    0b01
 117 #define HISI_HIP08_CORE_COMMIT_REG      sys_reg(3, 1, 15, 2, 5)
 118
 119 struct etm4_arch_features {
 120         void (*arch_callback)(bool enable);
 121 };
 122
 123 static bool etm4_hisi_match_pid(unsigned int id)
 124 {
 125         return (id & ETM4_AMBA_MASK) == HISI_HIP08_AMBA_ID;
 126 }
 127
 128 static void etm4_hisi_config_core_commit(bool enable)
 129 {
 130         u8 commit = enable ? HISI_HIP08_CORE_COMMIT_LVL_1 :
 131                     HISI_HIP08_CORE_COMMIT_FULL;
 132         u64 val;
 133
 134         /*
 135          * bit 12 and 13 of HISI_HIP08_CORE_COMMIT_REG are used together
 136          * to set core-commit, 2'b00 means cpu is at full speed, 2'b01,
 137          * 2'b10, 2'b11 mean reduce pipeline speed, and 2'b01 means level-1
 138          * speed(minimun value). So bit 12 and 13 should be cleared together.
 139          */
 140         val = read_sysreg_s(HISI_HIP08_CORE_COMMIT_REG);
 141         val &= ~HISI_HIP08_CORE_COMMIT_MASK;
 142         val |= commit << HISI_HIP08_CORE_COMMIT_SHIFT;
 143         write_sysreg_s(val, HISI_HIP08_CORE_COMMIT_REG);
 144 }
 145
 146 static struct etm4_arch_features etm4_features[] = {
 147         [ETM4_IMPDEF_HISI_CORE_COMMIT] = {
 148                 .arch_callback = etm4_hisi_config_core_commit,
 149         },
 150         {},
 151 };
 152
 153 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
 154 {
 155         struct etm4_arch_features *ftr;
 156         int bit;
 157
 158         for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
 159                 ftr = &etm4_features[bit];
 160
 161                 if (ftr->arch_callback)
 162                         ftr->arch_callback(true);
 163         }
 164 }
 165
 166 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
 167 {
 168         struct etm4_arch_features *ftr;
 169         int bit;
 170
 171         for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
 172                 ftr = &etm4_features[bit];
 173
 174                 if (ftr->arch_callback)
 175                         ftr->arch_callback(false);
 176         }
 177 }
 178
 179 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,
 180                                       unsigned int id)
 181 {
 182         if (etm4_hisi_match_pid(id))
 183                 set_bit(ETM4_IMPDEF_HISI_CORE_COMMIT, drvdata->arch_features);
 184 }
 185 #else
 186 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
 187 {
 188 }
 189
 190 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
 191 {
 192 }
 193
 194 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,
 195                                      unsigned int id)
 196 {
 197 }
 198 #endif /* CONFIG_ETM4X_IMPDEF_FEATURE */
 199
 200 static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
 201 {
 202         int i, rc;
 203         struct etmv4_config *config = &drvdata->config;
 204         struct device *etm_dev = &drvdata->csdev->dev;
 205
 206         CS_UNLOCK(drvdata->base);
 207         etm4_enable_arch_specific(drvdata);
 208
 209         etm4_os_unlock(drvdata);
 210
 211         rc = coresight_claim_device_unlocked(drvdata->base);
 212         if (rc)
 213                 goto done;
 214
 215         /* Disable the trace unit before programming trace registers */
 216         writel_relaxed(0, drvdata->base + TRCPRGCTLR);
 217
 218         /* wait for TRCSTATR.IDLE to go up */
 219         if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
 220                 dev_err(etm_dev,
 221                         "timeout while waiting for Idle Trace Status\n");
 222         if (drvdata->nr_pe)
 223                 writel_relaxed(config->pe_sel, drvdata->base + TRCPROCSELR);
 224         writel_relaxed(config->cfg, drvdata->base + TRCCONFIGR);
 225         /* nothing specific implemented */
 226         writel_relaxed(0x0, drvdata->base + TRCAUXCTLR);
 227         writel_relaxed(config->eventctrl0, drvdata->base + TRCEVENTCTL0R);
 228         writel_relaxed(config->eventctrl1, drvdata->base + TRCEVENTCTL1R);
 229         writel_relaxed(config->stall_ctrl, drvdata->base + TRCSTALLCTLR);
 230         writel_relaxed(config->ts_ctrl, drvdata->base + TRCTSCTLR);
 231         writel_relaxed(config->syncfreq, drvdata->base + TRCSYNCPR);
 232         writel_relaxed(config->ccctlr, drvdata->base + TRCCCCTLR);
 233         writel_relaxed(config->bb_ctrl, drvdata->base + TRCBBCTLR);
 234         writel_relaxed(drvdata->trcid, drvdata->base + TRCTRACEIDR);
 235         writel_relaxed(config->vinst_ctrl, drvdata->base + TRCVICTLR);
 236         writel_relaxed(config->viiectlr, drvdata->base + TRCVIIECTLR);
 237         writel_relaxed(config->vissctlr,
 238                        drvdata->base + TRCVISSCTLR);
 239         if (drvdata->nr_pe_cmp)
 240                 writel_relaxed(config->vipcssctlr,
 241                                drvdata->base + TRCVIPCSSCTLR);
 242         for (i = 0; i < drvdata->nrseqstate - 1; i++)
 243                 writel_relaxed(config->seq_ctrl[i],
 244                                drvdata->base + TRCSEQEVRn(i));
 245         writel_relaxed(config->seq_rst, drvdata->base + TRCSEQRSTEVR);
 246         writel_relaxed(config->seq_state, drvdata->base + TRCSEQSTR);
 247         writel_relaxed(config->ext_inp, drvdata->base + TRCEXTINSELR);
 248         for (i = 0; i < drvdata->nr_cntr; i++) {
 249                 writel_relaxed(config->cntrldvr[i],
 250                                drvdata->base + TRCCNTRLDVRn(i));
 251                 writel_relaxed(config->cntr_ctrl[i],
 252                                drvdata->base + TRCCNTCTLRn(i));
 253                 writel_relaxed(config->cntr_val[i],
 254                                drvdata->base + TRCCNTVRn(i));
 255         }
 256
 257         /*
 258          * Resource selector pair 0 is always implemented and reserved.  As
 259          * such start at 2.
 260          */
 261         for (i = 2; i < drvdata->nr_resource * 2; i++)
 262                 writel_relaxed(config->res_ctrl[i],
 263                                drvdata->base + TRCRSCTLRn(i));
 264
 265         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
 266                 /* always clear status bit on restart if using single-shot */
 267                 if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
 268                         config->ss_status[i] &= ~BIT(31);
 269                 writel_relaxed(config->ss_ctrl[i],
 270                                drvdata->base + TRCSSCCRn(i));
 271                 writel_relaxed(config->ss_status[i],
 272                                drvdata->base + TRCSSCSRn(i));
 273                 writel_relaxed(config->ss_pe_cmp[i],
 274                                drvdata->base + TRCSSPCICRn(i));
 275         }
 276         for (i = 0; i < drvdata->nr_addr_cmp; i++) {
 277                 writeq_relaxed(config->addr_val[i],
 278                                drvdata->base + TRCACVRn(i));
 279                 writeq_relaxed(config->addr_acc[i],
 280                                drvdata->base + TRCACATRn(i));
 281         }
 282         for (i = 0; i < drvdata->numcidc; i++)
 283                 writeq_relaxed(config->ctxid_pid[i],
 284                                drvdata->base + TRCCIDCVRn(i));
 285         writel_relaxed(config->ctxid_mask0, drvdata->base + TRCCIDCCTLR0);
 286         if (drvdata->numcidc > 4)
 287                 writel_relaxed(config->ctxid_mask1, drvdata->base + TRCCIDCCTLR1);
 288
 289         for (i = 0; i < drvdata->numvmidc; i++)
 290                 writeq_relaxed(config->vmid_val[i],
 291                                drvdata->base + TRCVMIDCVRn(i));
 292         writel_relaxed(config->vmid_mask0, drvdata->base + TRCVMIDCCTLR0);
 293         if (drvdata->numvmidc > 4)
 294                 writel_relaxed(config->vmid_mask1, drvdata->base + TRCVMIDCCTLR1);
 295
 296         if (!drvdata->skip_power_up) {
 297                 /*
 298                  * Request to keep the trace unit powered and also
 299                  * emulation of powerdown
 300                  */
 301                 writel_relaxed(readl_relaxed(drvdata->base + TRCPDCR) |
 302                                TRCPDCR_PU, drvdata->base + TRCPDCR);
 303         }
 304
 305         /* Enable the trace unit */
 306         writel_relaxed(1, drvdata->base + TRCPRGCTLR);
 307
 308         /* wait for TRCSTATR.IDLE to go back down to '0' */
 309         if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
 310                 dev_err(etm_dev,
 311                         "timeout while waiting for Idle Trace Status\n");
 312
 313         /*
 314          * As recommended by section 4.3.7 ("Synchronization when using the
 315          * memory-mapped interface") of ARM IHI 0064D
 316          */
 317         dsb(sy);
 318         isb();
 319
 320 done:
 321         CS_LOCK(drvdata->base);
 322
 323         dev_dbg(etm_dev, "cpu: %d enable smp call done: %d\n",
 324                 drvdata->cpu, rc);
 325         return rc;
 326 }
 327
 328 static void etm4_enable_hw_smp_call(void *info)
 329 {
 330         struct etm4_enable_arg *arg = info;
 331
 332         if (WARN_ON(!arg))
 333                 return;
 334         arg->rc = etm4_enable_hw(arg->drvdata);
 335 }
 336
 337 /*
 338  * The goal of function etm4_config_timestamp_event() is to configure a
 339  * counter that will tell the tracer to emit a timestamp packet when it
 340  * reaches zero.  This is done in order to get a more fine grained idea
 341  * of when instructions are executed so that they can be correlated
 342  * with execution on other CPUs.
 343  *
 344  * To do this the counter itself is configured to self reload and
 345  * TRCRSCTLR1 (always true) used to get the counter to decrement.  From
 346  * there a resource selector is configured with the counter and the
 347  * timestamp control register to use the resource selector to trigger the
 348  * event that will insert a timestamp packet in the stream.
 349  */
 350 static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata)
 351 {
 352         int ctridx, ret = -EINVAL;
 353         int counter, rselector;
 354         u32 val = 0;
 355         struct etmv4_config *config = &drvdata->config;
 356
 357         /* No point in trying if we don't have at least one counter */
 358         if (!drvdata->nr_cntr)
 359                 goto out;
 360
 361         /* Find a counter that hasn't been initialised */
 362         for (ctridx = 0; ctridx < drvdata->nr_cntr; ctridx++)
 363                 if (config->cntr_val[ctridx] == 0)
 364                         break;
 365
 366         /* All the counters have been configured already, bail out */
 367         if (ctridx == drvdata->nr_cntr) {
 368                 pr_debug("%s: no available counter found\n", __func__);
 369                 ret = -ENOSPC;
 370                 goto out;
 371         }
 372
 373         /*
 374          * Searching for an available resource selector to use, starting at
 375          * '2' since every implementation has at least 2 resource selector.
 376          * ETMIDR4 gives the number of resource selector _pairs_,
 377          * hence multiply by 2.
 378          */
 379         for (rselector = 2; rselector < drvdata->nr_resource * 2; rselector++)
 380                 if (!config->res_ctrl[rselector])
 381                         break;
 382
 383         if (rselector == drvdata->nr_resource * 2) {
 384                 pr_debug("%s: no available resource selector found\n",
 385                          __func__);
 386                 ret = -ENOSPC;
 387                 goto out;
 388         }
 389
 390         /* Remember what counter we used */
 391         counter = 1 << ctridx;
 392
 393         /*
 394          * Initialise original and reload counter value to the smallest
 395          * possible value in order to get as much precision as we can.
 396          */
 397         config->cntr_val[ctridx] = 1;
 398         config->cntrldvr[ctridx] = 1;
 399
 400         /* Set the trace counter control register */
 401         val =  0x1 << 16        |  /* Bit 16, reload counter automatically */
 402                0x0 << 7         |  /* Select single resource selector */
 403                0x1;                /* Resource selector 1, i.e always true */
 404
 405         config->cntr_ctrl[ctridx] = val;
 406
 407         val = 0x2 << 16         | /* Group 0b0010 - Counter and sequencers */
 408               counter << 0;       /* Counter to use */
 409
 410         config->res_ctrl[rselector] = val;
 411
 412         val = 0x0 << 7          | /* Select single resource selector */
 413               rselector;          /* Resource selector */
 414
 415         config->ts_ctrl = val;
 416
 417         ret = 0;
 418 out:
 419         return ret;
 420 }
 421
 422 static int etm4_parse_event_config(struct etmv4_drvdata *drvdata,
 423                                    struct perf_event *event)
 424 {
 425         int ret = 0;
 426         struct etmv4_config *config = &drvdata->config;
 427         struct perf_event_attr *attr = &event->attr;
 428
 429         if (!attr) {
 430                 ret = -EINVAL;
 431                 goto out;
 432         }
 433
 434         /* Clear configuration from previous run */
 435         memset(config, 0, sizeof(struct etmv4_config));
 436
 437         if (attr->exclude_kernel)
 438                 config->mode = ETM_MODE_EXCL_KERN;
 439
 440         if (attr->exclude_user)
 441                 config->mode = ETM_MODE_EXCL_USER;
 442
 443         /* Always start from the default config */
 444         etm4_set_default_config(config);
 445
 446         /* Configure filters specified on the perf cmd line, if any. */
 447         ret = etm4_set_event_filters(drvdata, event);
 448         if (ret)
 449                 goto out;
 450
 451         /* Go from generic option to ETMv4 specifics */
 452         if (attr->config & BIT(ETM_OPT_CYCACC)) {
 453                 config->cfg |= BIT(4);
 454                 /* TRM: Must program this for cycacc to work */
 455                 config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT;
 456         }
 457         if (attr->config & BIT(ETM_OPT_TS)) {
 458                 /*
 459                  * Configure timestamps to be emitted at regular intervals in
 460                  * order to correlate instructions executed on different CPUs
 461                  * (CPU-wide trace scenarios).
 462                  */
 463                 ret = etm4_config_timestamp_event(drvdata);
 464
 465                 /*
 466                  * No need to go further if timestamp intervals can't
 467                  * be configured.
 468                  */
 469                 if (ret)
 470                         goto out;
 471
 472                 /* bit[11], Global timestamp tracing bit */
 473                 config->cfg |= BIT(11);
 474         }
 475
 476         if (attr->config & BIT(ETM_OPT_CTXTID))
 477                 /* bit[6], Context ID tracing bit */
 478                 config->cfg |= BIT(ETM4_CFG_BIT_CTXTID);
 479
 480         /* return stack - enable if selected and supported */
 481         if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack)
 482                 /* bit[12], Return stack enable bit */
 483                 config->cfg |= BIT(12);
 484
 485 out:
 486         return ret;
 487 }
 488
 489 static int etm4_enable_perf(struct coresight_device *csdev,
 490                             struct perf_event *event)
 491 {
 492         int ret = 0;
 493         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 494
 495         if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) {
 496                 ret = -EINVAL;
 497                 goto out;
 498         }
 499
 500         /* Configure the tracer based on the session's specifics */
 501         ret = etm4_parse_event_config(drvdata, event);
 502         if (ret)
 503                 goto out;
 504         /* And enable it */
 505         ret = etm4_enable_hw(drvdata);
 506
 507 out:
 508         return ret;
 509 }
 510
 511 static int etm4_enable_sysfs(struct coresight_device *csdev)
 512 {
 513         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 514         struct etm4_enable_arg arg = { };
 515         int ret;
 516
 517         spin_lock(&drvdata->spinlock);
 518
 519         /*
 520          * Executing etm4_enable_hw on the cpu whose ETM is being enabled
 521          * ensures that register writes occur when cpu is powered.
 522          */
 523         arg.drvdata = drvdata;
 524         ret = smp_call_function_single(drvdata->cpu,
 525                                        etm4_enable_hw_smp_call, &arg, 1);
 526         if (!ret)
 527                 ret = arg.rc;
 528         if (!ret)
 529                 drvdata->sticky_enable = true;
 530         spin_unlock(&drvdata->spinlock);
 531
 532         if (!ret)
 533                 dev_dbg(&csdev->dev, "ETM tracing enabled\n");
 534         return ret;
 535 }
 536
 537 static int etm4_enable(struct coresight_device *csdev,
 538                        struct perf_event *event, u32 mode)
 539 {
 540         int ret;
 541         u32 val;
 542         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 543
 544         val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
 545
 546         /* Someone is already using the tracer */
 547         if (val)
 548                 return -EBUSY;
 549
 550         switch (mode) {
 551         case CS_MODE_SYSFS:
 552                 ret = etm4_enable_sysfs(csdev);
 553                 break;
 554         case CS_MODE_PERF:
 555                 ret = etm4_enable_perf(csdev, event);
 556                 break;
 557         default:
 558                 ret = -EINVAL;
 559         }
 560
 561         /* The tracer didn't start */
 562         if (ret)
 563                 local_set(&drvdata->mode, CS_MODE_DISABLED);
 564
 565         return ret;
 566 }
 567
 568 static void etm4_disable_hw(void *info)
 569 {
 570         u32 control;
 571         struct etmv4_drvdata *drvdata = info;
 572         struct etmv4_config *config = &drvdata->config;
 573         struct device *etm_dev = &drvdata->csdev->dev;
 574         int i;
 575
 576         CS_UNLOCK(drvdata->base);
 577         etm4_disable_arch_specific(drvdata);
 578
 579         if (!drvdata->skip_power_up) {
 580                 /* power can be removed from the trace unit now */
 581                 control = readl_relaxed(drvdata->base + TRCPDCR);
 582                 control &= ~TRCPDCR_PU;
 583                 writel_relaxed(control, drvdata->base + TRCPDCR);
 584         }
 585
 586         control = readl_relaxed(drvdata->base + TRCPRGCTLR);
 587
 588         /* EN, bit[0] Trace unit enable bit */
 589         control &= ~0x1;
 590
 591         /*
 592          * Make sure everything completes before disabling, as recommended
 593          * by section 7.3.77 ("TRCVICTLR, ViewInst Main Control Register,
 594          * SSTATUS") of ARM IHI 0064D
 595          */
 596         dsb(sy);
 597         isb();
 598         writel_relaxed(control, drvdata->base + TRCPRGCTLR);
 599
 600         /* wait for TRCSTATR.PMSTABLE to go to '1' */
 601         if (coresight_timeout(drvdata->base, TRCSTATR,
 602                               TRCSTATR_PMSTABLE_BIT, 1))
 603                 dev_err(etm_dev,
 604                         "timeout while waiting for PM stable Trace Status\n");
 605
 606         /* read the status of the single shot comparators */
 607         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
 608                 config->ss_status[i] =
 609                         readl_relaxed(drvdata->base + TRCSSCSRn(i));
 610         }
 611
 612         /* read back the current counter values */
 613         for (i = 0; i < drvdata->nr_cntr; i++) {
 614                 config->cntr_val[i] =
 615                         readl_relaxed(drvdata->base + TRCCNTVRn(i));
 616         }
 617
 618         coresight_disclaim_device_unlocked(drvdata->base);
 619
 620         CS_LOCK(drvdata->base);
 621
 622         dev_dbg(&drvdata->csdev->dev,
 623                 "cpu: %d disable smp call done\n", drvdata->cpu);
 624 }
 625
 626 static int etm4_disable_perf(struct coresight_device *csdev,
 627                              struct perf_event *event)
 628 {
 629         u32 control;
 630         struct etm_filters *filters = event->hw.addr_filters;
 631         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 632
 633         if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
 634                 return -EINVAL;
 635
 636         etm4_disable_hw(drvdata);
 637
 638         /*
 639          * Check if the start/stop logic was active when the unit was stopped.
 640          * That way we can re-enable the start/stop logic when the process is
 641          * scheduled again.  Configuration of the start/stop logic happens in
 642          * function etm4_set_event_filters().
 643          */
 644         control = readl_relaxed(drvdata->base + TRCVICTLR);
 645         /* TRCVICTLR::SSSTATUS, bit[9] */
 646         filters->ssstatus = (control & BIT(9));
 647
 648         return 0;
 649 }
 650
 651 static void etm4_disable_sysfs(struct coresight_device *csdev)
 652 {
 653         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 654
 655         /*
 656          * Taking hotplug lock here protects from clocks getting disabled
 657          * with tracing being left on (crash scenario) if user disable occurs
 658          * after cpu online mask indicates the cpu is offline but before the
 659          * DYING hotplug callback is serviced by the ETM driver.
 660          */
 661         cpus_read_lock();
 662         spin_lock(&drvdata->spinlock);
 663
 664         /*
 665          * Executing etm4_disable_hw on the cpu whose ETM is being disabled
 666          * ensures that register writes occur when cpu is powered.
 667          */
 668         smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1);
 669
 670         spin_unlock(&drvdata->spinlock);
 671         cpus_read_unlock();
 672
 673         dev_dbg(&csdev->dev, "ETM tracing disabled\n");
 674 }
 675
 676 static void etm4_disable(struct coresight_device *csdev,
 677                          struct perf_event *event)
 678 {
 679         u32 mode;
 680         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 681
 682         /*
 683          * For as long as the tracer isn't disabled another entity can't
 684          * change its status.  As such we can read the status here without
 685          * fearing it will change under us.
 686          */
 687         mode = local_read(&drvdata->mode);
 688
 689         switch (mode) {
 690         case CS_MODE_DISABLED:
 691                 break;
 692         case CS_MODE_SYSFS:
 693                 etm4_disable_sysfs(csdev);
 694                 break;
 695         case CS_MODE_PERF:
 696                 etm4_disable_perf(csdev, event);
 697                 break;
 698         }
 699
 700         if (mode)
 701                 local_set(&drvdata->mode, CS_MODE_DISABLED);
 702 }
 703
 704 static const struct coresight_ops_source etm4_source_ops = {
 705         .cpu_id         = etm4_cpu_id,
 706         .trace_id       = etm4_trace_id,
 707         .enable         = etm4_enable,
 708         .disable        = etm4_disable,
 709 };
 710
 711 static const struct coresight_ops etm4_cs_ops = {
 712         .source_ops     = &etm4_source_ops,
 713 };
 714
 715 static void etm4_init_arch_data(void *info)
 716 {
 717         u32 etmidr0;
 718         u32 etmidr1;
 719         u32 etmidr2;
 720         u32 etmidr3;
 721         u32 etmidr4;
 722         u32 etmidr5;
 723         struct etmv4_drvdata *drvdata = info;
 724         int i;
 725
 726         /* Make sure all registers are accessible */
 727         etm4_os_unlock(drvdata);
 728
 729         CS_UNLOCK(drvdata->base);
 730
 731         /* find all capabilities of the tracing unit */
 732         etmidr0 = readl_relaxed(drvdata->base + TRCIDR0);
 733
 734         /* INSTP0, bits[2:1] P0 tracing support field */
 735         if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2))
 736                 drvdata->instrp0 = true;
 737         else
 738                 drvdata->instrp0 = false;
 739
 740         /* TRCBB, bit[5] Branch broadcast tracing support bit */
 741         if (BMVAL(etmidr0, 5, 5))
 742                 drvdata->trcbb = true;
 743         else
 744                 drvdata->trcbb = false;
 745
 746         /* TRCCOND, bit[6] Conditional instruction tracing support bit */
 747         if (BMVAL(etmidr0, 6, 6))
 748                 drvdata->trccond = true;
 749         else
 750                 drvdata->trccond = false;
 751
 752         /* TRCCCI, bit[7] Cycle counting instruction bit */
 753         if (BMVAL(etmidr0, 7, 7))
 754                 drvdata->trccci = true;
 755         else
 756                 drvdata->trccci = false;
 757
 758         /* RETSTACK, bit[9] Return stack bit */
 759         if (BMVAL(etmidr0, 9, 9))
 760                 drvdata->retstack = true;
 761         else
 762                 drvdata->retstack = false;
 763
 764         /* NUMEVENT, bits[11:10] Number of events field */
 765         drvdata->nr_event = BMVAL(etmidr0, 10, 11);
 766         /* QSUPP, bits[16:15] Q element support field */
 767         drvdata->q_support = BMVAL(etmidr0, 15, 16);
 768         /* TSSIZE, bits[28:24] Global timestamp size field */
 769         drvdata->ts_size = BMVAL(etmidr0, 24, 28);
 770
 771         /* base architecture of trace unit */
 772         etmidr1 = readl_relaxed(drvdata->base + TRCIDR1);
 773         /*
 774          * TRCARCHMIN, bits[7:4] architecture the minor version number
 775          * TRCARCHMAJ, bits[11:8] architecture major versin number
 776          */
 777         drvdata->arch = BMVAL(etmidr1, 4, 11);
 778         drvdata->config.arch = drvdata->arch;
 779
 780         /* maximum size of resources */
 781         etmidr2 = readl_relaxed(drvdata->base + TRCIDR2);
 782         /* CIDSIZE, bits[9:5] Indicates the Context ID size */
 783         drvdata->ctxid_size = BMVAL(etmidr2, 5, 9);
 784         /* VMIDSIZE, bits[14:10] Indicates the VMID size */
 785         drvdata->vmid_size = BMVAL(etmidr2, 10, 14);
 786         /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
 787         drvdata->ccsize = BMVAL(etmidr2, 25, 28);
 788
 789         etmidr3 = readl_relaxed(drvdata->base + TRCIDR3);
 790         /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
 791         drvdata->ccitmin = BMVAL(etmidr3, 0, 11);
 792         /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
 793         drvdata->s_ex_level = BMVAL(etmidr3, 16, 19);
 794         /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
 795         drvdata->ns_ex_level = BMVAL(etmidr3, 20, 23);
 796
 797         /*
 798          * TRCERR, bit[24] whether a trace unit can trace a
 799          * system error exception.
 800          */
 801         if (BMVAL(etmidr3, 24, 24))
 802                 drvdata->trc_error = true;
 803         else
 804                 drvdata->trc_error = false;
 805
 806         /* SYNCPR, bit[25] implementation has a fixed synchronization period? */
 807         if (BMVAL(etmidr3, 25, 25))
 808                 drvdata->syncpr = true;
 809         else
 810                 drvdata->syncpr = false;
 811
 812         /* STALLCTL, bit[26] is stall control implemented? */
 813         if (BMVAL(etmidr3, 26, 26))
 814                 drvdata->stallctl = true;
 815         else
 816                 drvdata->stallctl = false;
 817
 818         /* SYSSTALL, bit[27] implementation can support stall control? */
 819         if (BMVAL(etmidr3, 27, 27))
 820                 drvdata->sysstall = true;
 821         else
 822                 drvdata->sysstall = false;
 823
 824         /*
 825          * NUMPROC - the number of PEs available for tracing, 5bits
 826          *         = TRCIDR3.bits[13:12]bits[30:28]
 827          *  bits[4:3] = TRCIDR3.bits[13:12] (since etm-v4.2, otherwise RES0)
 828          *  bits[3:0] = TRCIDR3.bits[30:28]
 829          */
 830         drvdata->nr_pe = (BMVAL(etmidr3, 12, 13) << 3) | BMVAL(etmidr3, 28, 30);
 831
 832         /* NOOVERFLOW, bit[31] is trace overflow prevention supported */
 833         if (BMVAL(etmidr3, 31, 31))
 834                 drvdata->nooverflow = true;
 835         else
 836                 drvdata->nooverflow = false;
 837
 838         /* number of resources trace unit supports */
 839         etmidr4 = readl_relaxed(drvdata->base + TRCIDR4);
 840         /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
 841         drvdata->nr_addr_cmp = BMVAL(etmidr4, 0, 3);
 842         /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
 843         drvdata->nr_pe_cmp = BMVAL(etmidr4, 12, 15);
 844         /*
 845          * NUMRSPAIR, bits[19:16]
 846          * The number of resource pairs conveyed by the HW starts at 0, i.e a
 847          * value of 0x0 indicate 1 resource pair, 0x1 indicate two and so on.
 848          * As such add 1 to the value of NUMRSPAIR for a better representation.
 849          *
 850          * For ETM v4.3 and later, 0x0 means 0, and no pairs are available -
 851          * the default TRUE and FALSE resource selectors are omitted.
 852          * Otherwise for values 0x1 and above the number is N + 1 as per v4.2.
 853          */
 854         drvdata->nr_resource = BMVAL(etmidr4, 16, 19);
 855         if ((drvdata->arch < ETM4X_ARCH_4V3) || (drvdata->nr_resource > 0))
 856                 drvdata->nr_resource += 1;
 857         /*
 858          * NUMSSCC, bits[23:20] the number of single-shot
 859          * comparator control for tracing. Read any status regs as these
 860          * also contain RO capability data.
 861          */
 862         drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23);
 863         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
 864                 drvdata->config.ss_status[i] =
 865                         readl_relaxed(drvdata->base + TRCSSCSRn(i));
 866         }
 867         /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
 868         drvdata->numcidc = BMVAL(etmidr4, 24, 27);
 869         /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
 870         drvdata->numvmidc = BMVAL(etmidr4, 28, 31);
 871
 872         etmidr5 = readl_relaxed(drvdata->base + TRCIDR5);
 873         /* NUMEXTIN, bits[8:0] number of external inputs implemented */
 874         drvdata->nr_ext_inp = BMVAL(etmidr5, 0, 8);
 875         /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
 876         drvdata->trcid_size = BMVAL(etmidr5, 16, 21);
 877         /* ATBTRIG, bit[22] implementation can support ATB triggers? */
 878         if (BMVAL(etmidr5, 22, 22))
 879                 drvdata->atbtrig = true;
 880         else
 881                 drvdata->atbtrig = false;
 882         /*
 883          * LPOVERRIDE, bit[23] implementation supports
 884          * low-power state override
 885          */
 886         if (BMVAL(etmidr5, 23, 23) && (!drvdata->skip_power_up))
 887                 drvdata->lpoverride = true;
 888         else
 889                 drvdata->lpoverride = false;
 890         /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
 891         drvdata->nrseqstate = BMVAL(etmidr5, 25, 27);
 892         /* NUMCNTR, bits[30:28] number of counters available for tracing */
 893         drvdata->nr_cntr = BMVAL(etmidr5, 28, 30);
 894         CS_LOCK(drvdata->base);
 895 }
 896
 897 /* Set ELx trace filter access in the TRCVICTLR register */
 898 static void etm4_set_victlr_access(struct etmv4_config *config)
 899 {
 900         u64 access_type;
 901
 902         config->vinst_ctrl &= ~(ETM_EXLEVEL_S_VICTLR_MASK | ETM_EXLEVEL_NS_VICTLR_MASK);
 903
 904         /*
 905          * TRCVICTLR::EXLEVEL_NS:EXLEVELS: Set kernel / user filtering
 906          * bits in vinst_ctrl, same bit pattern as TRCACATRn values returned by
 907          * etm4_get_access_type() but with a relative shift in this register.
 908          */
 909         access_type = etm4_get_access_type(config) << ETM_EXLEVEL_LSHIFT_TRCVICTLR;
 910         config->vinst_ctrl |= (u32)access_type;
 911 }
 912
 913 static void etm4_set_default_config(struct etmv4_config *config)
 914 {
 915         /* disable all events tracing */
 916         config->eventctrl0 = 0x0;
 917         config->eventctrl1 = 0x0;
 918
 919         /* disable stalling */
 920         config->stall_ctrl = 0x0;
 921
 922         /* enable trace synchronization every 4096 bytes, if available */
 923         config->syncfreq = 0xC;
 924
 925         /* disable timestamp event */
 926         config->ts_ctrl = 0x0;
 927
 928         /* TRCVICTLR::EVENT = 0x01, select the always on logic */
 929         config->vinst_ctrl = BIT(0);
 930
 931         /* TRCVICTLR::EXLEVEL_NS:EXLEVELS: Set kernel / user filtering */
 932         etm4_set_victlr_access(config);
 933 }
 934
 935 static u64 etm4_get_ns_access_type(struct etmv4_config *config)
 936 {
 937         u64 access_type = 0;
 938
 939         /*
 940          * EXLEVEL_NS, bits[15:12]
 941          * The Exception levels are:
 942          *   Bit[12] Exception level 0 - Application
 943          *   Bit[13] Exception level 1 - OS
 944          *   Bit[14] Exception level 2 - Hypervisor
 945          *   Bit[15] Never implemented
 946          */
 947         if (!is_kernel_in_hyp_mode()) {
 948                 /* Stay away from hypervisor mode for non-VHE */
 949                 access_type =  ETM_EXLEVEL_NS_HYP;
 950                 if (config->mode & ETM_MODE_EXCL_KERN)
 951                         access_type |= ETM_EXLEVEL_NS_OS;
 952         } else if (config->mode & ETM_MODE_EXCL_KERN) {
 953                 access_type = ETM_EXLEVEL_NS_HYP;
 954         }
 955
 956         if (config->mode & ETM_MODE_EXCL_USER)
 957                 access_type |= ETM_EXLEVEL_NS_APP;
 958
 959         return access_type;
 960 }
 961
 962 static u64 etm4_get_access_type(struct etmv4_config *config)
 963 {
 964         u64 access_type = etm4_get_ns_access_type(config);
 965         u64 s_hyp = (config->arch & 0x0f) >= 0x4 ? ETM_EXLEVEL_S_HYP : 0;
 966
 967         /*
 968          * EXLEVEL_S, bits[11:8], don't trace anything happening
 969          * in secure state.
 970          */
 971         access_type |= (ETM_EXLEVEL_S_APP       |
 972                         ETM_EXLEVEL_S_OS        |
 973                         s_hyp                   |
 974                         ETM_EXLEVEL_S_MON);
 975
 976         return access_type;
 977 }
 978
 979 static void etm4_set_comparator_filter(struct etmv4_config *config,
 980                                        u64 start, u64 stop, int comparator)
 981 {
 982         u64 access_type = etm4_get_access_type(config);
 983
 984         /* First half of default address comparator */
 985         config->addr_val[comparator] = start;
 986         config->addr_acc[comparator] = access_type;
 987         config->addr_type[comparator] = ETM_ADDR_TYPE_RANGE;
 988
 989         /* Second half of default address comparator */
 990         config->addr_val[comparator + 1] = stop;
 991         config->addr_acc[comparator + 1] = access_type;
 992         config->addr_type[comparator + 1] = ETM_ADDR_TYPE_RANGE;
 993
 994         /*
 995          * Configure the ViewInst function to include this address range
 996          * comparator.
 997          *
 998          * @comparator is divided by two since it is the index in the
 999          * etmv4_config::addr_val array but register TRCVIIECTLR deals with
1000          * address range comparator _pairs_.
1001          *
1002          * Therefore:
1003          *      index 0 -> compatator pair 0
1004          *      index 2 -> comparator pair 1
1005          *      index 4 -> comparator pair 2
1006          *      ...
1007          *      index 14 -> comparator pair 7
1008          */
1009         config->viiectlr |= BIT(comparator / 2);
1010 }
1011
1012 static void etm4_set_start_stop_filter(struct etmv4_config *config,
1013                                        u64 address, int comparator,
1014                                        enum etm_addr_type type)
1015 {
1016         int shift;
1017         u64 access_type = etm4_get_access_type(config);
1018
1019         /* Configure the comparator */
1020         config->addr_val[comparator] = address;
1021         config->addr_acc[comparator] = access_type;
1022         config->addr_type[comparator] = type;
1023
1024         /*
1025          * Configure ViewInst Start-Stop control register.
1026          * Addresses configured to start tracing go from bit 0 to n-1,
1027          * while those configured to stop tracing from 16 to 16 + n-1.
1028          */
1029         shift = (type == ETM_ADDR_TYPE_START ? 0 : 16);
1030         config->vissctlr |= BIT(shift + comparator);
1031 }
1032
1033 static void etm4_set_default_filter(struct etmv4_config *config)
1034 {
1035         /* Trace everything 'default' filter achieved by no filtering */
1036         config->viiectlr = 0x0;
1037
1038         /*
1039          * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1040          * in the started state
1041          */
1042         config->vinst_ctrl |= BIT(9);
1043         config->mode |= ETM_MODE_VIEWINST_STARTSTOP;
1044
1045         /* No start-stop filtering for ViewInst */
1046         config->vissctlr = 0x0;
1047 }
1048
1049 static void etm4_set_default(struct etmv4_config *config)
1050 {
1051         if (WARN_ON_ONCE(!config))
1052                 return;
1053
1054         /*
1055          * Make default initialisation trace everything
1056          *
1057          * This is done by a minimum default config sufficient to enable
1058          * full instruction trace - with a default filter for trace all
1059          * achieved by having no filtering.
1060          */
1061         etm4_set_default_config(config);
1062         etm4_set_default_filter(config);
1063 }
1064
1065 static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type)
1066 {
1067         int nr_comparator, index = 0;
1068         struct etmv4_config *config = &drvdata->config;
1069
1070         /*
1071          * nr_addr_cmp holds the number of comparator _pair_, so time 2
1072          * for the total number of comparators.
1073          */
1074         nr_comparator = drvdata->nr_addr_cmp * 2;
1075
1076         /* Go through the tally of comparators looking for a free one. */
1077         while (index < nr_comparator) {
1078                 switch (type) {
1079                 case ETM_ADDR_TYPE_RANGE:
1080                         if (config->addr_type[index] == ETM_ADDR_TYPE_NONE &&
1081                             config->addr_type[index + 1] == ETM_ADDR_TYPE_NONE)
1082                                 return index;
1083
1084                         /* Address range comparators go in pairs */
1085                         index += 2;
1086                         break;
1087                 case ETM_ADDR_TYPE_START:
1088                 case ETM_ADDR_TYPE_STOP:
1089                         if (config->addr_type[index] == ETM_ADDR_TYPE_NONE)
1090                                 return index;
1091
1092                         /* Start/stop address can have odd indexes */
1093                         index += 1;
1094                         break;
1095                 default:
1096                         return -EINVAL;
1097                 }
1098         }
1099
1100         /* If we are here all the comparators have been used. */
1101         return -ENOSPC;
1102 }
1103
1104 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
1105                                   struct perf_event *event)
1106 {
1107         int i, comparator, ret = 0;
1108         u64 address;
1109         struct etmv4_config *config = &drvdata->config;
1110         struct etm_filters *filters = event->hw.addr_filters;
1111
1112         if (!filters)
1113                 goto default_filter;
1114
1115         /* Sync events with what Perf got */
1116         perf_event_addr_filters_sync(event);
1117
1118         /*
1119          * If there are no filters to deal with simply go ahead with
1120          * the default filter, i.e the entire address range.
1121          */
1122         if (!filters->nr_filters)
1123                 goto default_filter;
1124
1125         for (i = 0; i < filters->nr_filters; i++) {
1126                 struct etm_filter *filter = &filters->etm_filter[i];
1127                 enum etm_addr_type type = filter->type;
1128
1129                 /* See if a comparator is free. */
1130                 comparator = etm4_get_next_comparator(drvdata, type);
1131                 if (comparator < 0) {
1132                         ret = comparator;
1133                         goto out;
1134                 }
1135
1136                 switch (type) {
1137                 case ETM_ADDR_TYPE_RANGE:
1138                         etm4_set_comparator_filter(config,
1139                                                    filter->start_addr,
1140                                                    filter->stop_addr,
1141                                                    comparator);
1142                         /*
1143                          * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1144                          * in the started state
1145                          */
1146                         config->vinst_ctrl |= BIT(9);
1147
1148                         /* No start-stop filtering for ViewInst */
1149                         config->vissctlr = 0x0;
1150                         break;
1151                 case ETM_ADDR_TYPE_START:
1152                 case ETM_ADDR_TYPE_STOP:
1153                         /* Get the right start or stop address */
1154                         address = (type == ETM_ADDR_TYPE_START ?
1155                                    filter->start_addr :
1156                                    filter->stop_addr);
1157
1158                         /* Configure comparator */
1159                         etm4_set_start_stop_filter(config, address,
1160                                                    comparator, type);
1161
1162                         /*
1163                          * If filters::ssstatus == 1, trace acquisition was
1164                          * started but the process was yanked away before the
1165                          * the stop address was hit.  As such the start/stop
1166                          * logic needs to be re-started so that tracing can
1167                          * resume where it left.
1168                          *
1169                          * The start/stop logic status when a process is
1170                          * scheduled out is checked in function
1171                          * etm4_disable_perf().
1172                          */
1173                         if (filters->ssstatus)
1174                                 config->vinst_ctrl |= BIT(9);
1175
1176                         /* No include/exclude filtering for ViewInst */
1177                         config->viiectlr = 0x0;
1178                         break;
1179                 default:
1180                         ret = -EINVAL;
1181                         goto out;
1182                 }
1183         }
1184
1185         goto out;
1186
1187
1188 default_filter:
1189         etm4_set_default_filter(config);
1190
1191 out:
1192         return ret;
1193 }
1194
1195 void etm4_config_trace_mode(struct etmv4_config *config)
1196 {
1197         u32 mode;
1198
1199         mode = config->mode;
1200         mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
1201
1202         /* excluding kernel AND user space doesn't make sense */
1203         WARN_ON_ONCE(mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER));
1204
1205         /* nothing to do if neither flags are set */
1206         if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
1207                 return;
1208
1209         etm4_set_victlr_access(config);
1210 }
1211
1212 static int etm4_online_cpu(unsigned int cpu)
1213 {
1214         if (!etmdrvdata[cpu])
1215                 return 0;
1216
1217         if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable)
1218                 coresight_enable(etmdrvdata[cpu]->csdev);
1219         return 0;
1220 }
1221
1222 static int etm4_starting_cpu(unsigned int cpu)
1223 {
1224         if (!etmdrvdata[cpu])
1225                 return 0;
1226
1227         spin_lock(&etmdrvdata[cpu]->spinlock);
1228         if (!etmdrvdata[cpu]->os_unlock)
1229                 etm4_os_unlock(etmdrvdata[cpu]);
1230
1231         if (local_read(&etmdrvdata[cpu]->mode))
1232                 etm4_enable_hw(etmdrvdata[cpu]);
1233         spin_unlock(&etmdrvdata[cpu]->spinlock);
1234         return 0;
1235 }
1236
1237 static int etm4_dying_cpu(unsigned int cpu)
1238 {
1239         if (!etmdrvdata[cpu])
1240                 return 0;
1241
1242         spin_lock(&etmdrvdata[cpu]->spinlock);
1243         if (local_read(&etmdrvdata[cpu]->mode))
1244                 etm4_disable_hw(etmdrvdata[cpu]);
1245         spin_unlock(&etmdrvdata[cpu]->spinlock);
1246         return 0;
1247 }
1248
1249 static void etm4_init_trace_id(struct etmv4_drvdata *drvdata)
1250 {
1251         drvdata->trcid = coresight_get_trace_id(drvdata->cpu);
1252 }
1253
1254 static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
1255 {
1256         int i, ret = 0;
1257         struct etmv4_save_state *state;
1258         struct device *etm_dev = &drvdata->csdev->dev;
1259
1260         /*
1261          * As recommended by 3.4.1 ("The procedure when powering down the PE")
1262          * of ARM IHI 0064D
1263          */
1264         dsb(sy);
1265         isb();
1266
1267         CS_UNLOCK(drvdata->base);
1268
1269         /* Lock the OS lock to disable trace and external debugger access */
1270         etm4_os_lock(drvdata);
1271
1272         /* wait for TRCSTATR.PMSTABLE to go up */
1273         if (coresight_timeout(drvdata->base, TRCSTATR,
1274                               TRCSTATR_PMSTABLE_BIT, 1)) {
1275                 dev_err(etm_dev,
1276                         "timeout while waiting for PM Stable Status\n");
1277                 etm4_os_unlock(drvdata);
1278                 ret = -EBUSY;
1279                 goto out;
1280         }
1281
1282         state = drvdata->save_state;
1283
1284         state->trcprgctlr = readl(drvdata->base + TRCPRGCTLR);
1285         if (drvdata->nr_pe)
1286                 state->trcprocselr = readl(drvdata->base + TRCPROCSELR);
1287         state->trcconfigr = readl(drvdata->base + TRCCONFIGR);
1288         state->trcauxctlr = readl(drvdata->base + TRCAUXCTLR);
1289         state->trceventctl0r = readl(drvdata->base + TRCEVENTCTL0R);
1290         state->trceventctl1r = readl(drvdata->base + TRCEVENTCTL1R);
1291         state->trcstallctlr = readl(drvdata->base + TRCSTALLCTLR);
1292         state->trctsctlr = readl(drvdata->base + TRCTSCTLR);
1293         state->trcsyncpr = readl(drvdata->base + TRCSYNCPR);
1294         state->trcccctlr = readl(drvdata->base + TRCCCCTLR);
1295         state->trcbbctlr = readl(drvdata->base + TRCBBCTLR);
1296         state->trctraceidr = readl(drvdata->base + TRCTRACEIDR);
1297         state->trcqctlr = readl(drvdata->base + TRCQCTLR);
1298
1299         state->trcvictlr = readl(drvdata->base + TRCVICTLR);
1300         state->trcviiectlr = readl(drvdata->base + TRCVIIECTLR);
1301         state->trcvissctlr = readl(drvdata->base + TRCVISSCTLR);
1302         if (drvdata->nr_pe_cmp)
1303                 state->trcvipcssctlr = readl(drvdata->base + TRCVIPCSSCTLR);
1304         state->trcvdctlr = readl(drvdata->base + TRCVDCTLR);
1305         state->trcvdsacctlr = readl(drvdata->base + TRCVDSACCTLR);
1306         state->trcvdarcctlr = readl(drvdata->base + TRCVDARCCTLR);
1307
1308         for (i = 0; i < drvdata->nrseqstate - 1; i++)
1309                 state->trcseqevr[i] = readl(drvdata->base + TRCSEQEVRn(i));
1310
1311         state->trcseqrstevr = readl(drvdata->base + TRCSEQRSTEVR);
1312         state->trcseqstr = readl(drvdata->base + TRCSEQSTR);
1313         state->trcextinselr = readl(drvdata->base + TRCEXTINSELR);
1314
1315         for (i = 0; i < drvdata->nr_cntr; i++) {
1316                 state->trccntrldvr[i] = readl(drvdata->base + TRCCNTRLDVRn(i));
1317                 state->trccntctlr[i] = readl(drvdata->base + TRCCNTCTLRn(i));
1318                 state->trccntvr[i] = readl(drvdata->base + TRCCNTVRn(i));
1319         }
1320
1321         for (i = 0; i < drvdata->nr_resource * 2; i++)
1322                 state->trcrsctlr[i] = readl(drvdata->base + TRCRSCTLRn(i));
1323
1324         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1325                 state->trcssccr[i] = readl(drvdata->base + TRCSSCCRn(i));
1326                 state->trcsscsr[i] = readl(drvdata->base + TRCSSCSRn(i));
1327                 state->trcsspcicr[i] = readl(drvdata->base + TRCSSPCICRn(i));
1328         }
1329
1330         for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1331                 state->trcacvr[i] = readq(drvdata->base + TRCACVRn(i));
1332                 state->trcacatr[i] = readq(drvdata->base + TRCACATRn(i));
1333         }
1334
1335         /*
1336          * Data trace stream is architecturally prohibited for A profile cores
1337          * so we don't save (or later restore) trcdvcvr and trcdvcmr - As per
1338          * section 1.3.4 ("Possible functional configurations of an ETMv4 trace
1339          * unit") of ARM IHI 0064D.
1340          */
1341
1342         for (i = 0; i < drvdata->numcidc; i++)
1343                 state->trccidcvr[i] = readq(drvdata->base + TRCCIDCVRn(i));
1344
1345         for (i = 0; i < drvdata->numvmidc; i++)
1346                 state->trcvmidcvr[i] = readq(drvdata->base + TRCVMIDCVRn(i));
1347
1348         state->trccidcctlr0 = readl(drvdata->base + TRCCIDCCTLR0);
1349         if (drvdata->numcidc > 4)
1350                 state->trccidcctlr1 = readl(drvdata->base + TRCCIDCCTLR1);
1351
1352         state->trcvmidcctlr0 = readl(drvdata->base + TRCVMIDCCTLR0);
1353         if (drvdata->numvmidc > 4)
1354                 state->trcvmidcctlr1 = readl(drvdata->base + TRCVMIDCCTLR1);
1355
1356         state->trcclaimset = readl(drvdata->base + TRCCLAIMCLR);
1357
1358         state->trcpdcr = readl(drvdata->base + TRCPDCR);
1359
1360         /* wait for TRCSTATR.IDLE to go up */
1361         if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) {
1362                 dev_err(etm_dev,
1363                         "timeout while waiting for Idle Trace Status\n");
1364                 etm4_os_unlock(drvdata);
1365                 ret = -EBUSY;
1366                 goto out;
1367         }
1368
1369         drvdata->state_needs_restore = true;
1370
1371         /*
1372          * Power can be removed from the trace unit now. We do this to
1373          * potentially save power on systems that respect the TRCPDCR_PU
1374          * despite requesting software to save/restore state.
1375          */
1376         writel_relaxed((state->trcpdcr & ~TRCPDCR_PU),
1377                         drvdata->base + TRCPDCR);
1378
1379 out:
1380         CS_LOCK(drvdata->base);
1381         return ret;
1382 }
1383
1384 static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
1385 {
1386         int i;
1387         struct etmv4_save_state *state = drvdata->save_state;
1388
1389         CS_UNLOCK(drvdata->base);
1390
1391         writel_relaxed(state->trcclaimset, drvdata->base + TRCCLAIMSET);
1392
1393         writel_relaxed(state->trcprgctlr, drvdata->base + TRCPRGCTLR);
1394         if (drvdata->nr_pe)
1395                 writel_relaxed(state->trcprocselr, drvdata->base + TRCPROCSELR);
1396         writel_relaxed(state->trcconfigr, drvdata->base + TRCCONFIGR);
1397         writel_relaxed(state->trcauxctlr, drvdata->base + TRCAUXCTLR);
1398         writel_relaxed(state->trceventctl0r, drvdata->base + TRCEVENTCTL0R);
1399         writel_relaxed(state->trceventctl1r, drvdata->base + TRCEVENTCTL1R);
1400         writel_relaxed(state->trcstallctlr, drvdata->base + TRCSTALLCTLR);
1401         writel_relaxed(state->trctsctlr, drvdata->base + TRCTSCTLR);
1402         writel_relaxed(state->trcsyncpr, drvdata->base + TRCSYNCPR);
1403         writel_relaxed(state->trcccctlr, drvdata->base + TRCCCCTLR);
1404         writel_relaxed(state->trcbbctlr, drvdata->base + TRCBBCTLR);
1405         writel_relaxed(state->trctraceidr, drvdata->base + TRCTRACEIDR);
1406         writel_relaxed(state->trcqctlr, drvdata->base + TRCQCTLR);
1407
1408         writel_relaxed(state->trcvictlr, drvdata->base + TRCVICTLR);
1409         writel_relaxed(state->trcviiectlr, drvdata->base + TRCVIIECTLR);
1410         writel_relaxed(state->trcvissctlr, drvdata->base + TRCVISSCTLR);
1411         if (drvdata->nr_pe_cmp)
1412                 writel_relaxed(state->trcvipcssctlr, drvdata->base + TRCVIPCSSCTLR);
1413         writel_relaxed(state->trcvdctlr, drvdata->base + TRCVDCTLR);
1414         writel_relaxed(state->trcvdsacctlr, drvdata->base + TRCVDSACCTLR);
1415         writel_relaxed(state->trcvdarcctlr, drvdata->base + TRCVDARCCTLR);
1416
1417         for (i = 0; i < drvdata->nrseqstate - 1; i++)
1418                 writel_relaxed(state->trcseqevr[i],
1419                                drvdata->base + TRCSEQEVRn(i));
1420
1421         writel_relaxed(state->trcseqrstevr, drvdata->base + TRCSEQRSTEVR);
1422         writel_relaxed(state->trcseqstr, drvdata->base + TRCSEQSTR);
1423         writel_relaxed(state->trcextinselr, drvdata->base + TRCEXTINSELR);
1424
1425         for (i = 0; i < drvdata->nr_cntr; i++) {
1426                 writel_relaxed(state->trccntrldvr[i],
1427                                drvdata->base + TRCCNTRLDVRn(i));
1428                 writel_relaxed(state->trccntctlr[i],
1429                                drvdata->base + TRCCNTCTLRn(i));
1430                 writel_relaxed(state->trccntvr[i],
1431                                drvdata->base + TRCCNTVRn(i));
1432         }
1433
1434         for (i = 0; i < drvdata->nr_resource * 2; i++)
1435                 writel_relaxed(state->trcrsctlr[i],
1436                                drvdata->base + TRCRSCTLRn(i));
1437
1438         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1439                 writel_relaxed(state->trcssccr[i],
1440                                drvdata->base + TRCSSCCRn(i));
1441                 writel_relaxed(state->trcsscsr[i],
1442                                drvdata->base + TRCSSCSRn(i));
1443                 writel_relaxed(state->trcsspcicr[i],
1444                                drvdata->base + TRCSSPCICRn(i));
1445         }
1446
1447         for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1448                 writeq_relaxed(state->trcacvr[i],
1449                                drvdata->base + TRCACVRn(i));
1450                 writeq_relaxed(state->trcacatr[i],
1451                                drvdata->base + TRCACATRn(i));
1452         }
1453
1454         for (i = 0; i < drvdata->numcidc; i++)
1455                 writeq_relaxed(state->trccidcvr[i],
1456                                drvdata->base + TRCCIDCVRn(i));
1457
1458         for (i = 0; i < drvdata->numvmidc; i++)
1459                 writeq_relaxed(state->trcvmidcvr[i],
1460                                drvdata->base + TRCVMIDCVRn(i));
1461
1462         writel_relaxed(state->trccidcctlr0, drvdata->base + TRCCIDCCTLR0);
1463         if (drvdata->numcidc > 4)
1464                 writel_relaxed(state->trccidcctlr1, drvdata->base + TRCCIDCCTLR1);
1465
1466         writel_relaxed(state->trcvmidcctlr0, drvdata->base + TRCVMIDCCTLR0);
1467         if (drvdata->numvmidc > 4)
1468                 writel_relaxed(state->trcvmidcctlr1, drvdata->base + TRCVMIDCCTLR1);
1469
1470         writel_relaxed(state->trcclaimset, drvdata->base + TRCCLAIMSET);
1471
1472         writel_relaxed(state->trcpdcr, drvdata->base + TRCPDCR);
1473
1474         drvdata->state_needs_restore = false;
1475
1476         /*
1477          * As recommended by section 4.3.7 ("Synchronization when using the
1478          * memory-mapped interface") of ARM IHI 0064D
1479          */
1480         dsb(sy);
1481         isb();
1482
1483         /* Unlock the OS lock to re-enable trace and external debug access */
1484         etm4_os_unlock(drvdata);
1485         CS_LOCK(drvdata->base);
1486 }
1487
1488 static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd,
1489                               void *v)
1490 {
1491         struct etmv4_drvdata *drvdata;
1492         unsigned int cpu = smp_processor_id();
1493
1494         if (!etmdrvdata[cpu])
1495                 return NOTIFY_OK;
1496
1497         drvdata = etmdrvdata[cpu];
1498
1499         if (!drvdata->save_state)
1500                 return NOTIFY_OK;
1501
1502         if (WARN_ON_ONCE(drvdata->cpu != cpu))
1503                 return NOTIFY_BAD;
1504
1505         switch (cmd) {
1506         case CPU_PM_ENTER:
1507                 /* save the state if self-hosted coresight is in use */
1508                 if (local_read(&drvdata->mode))
1509                         if (etm4_cpu_save(drvdata))
1510                                 return NOTIFY_BAD;
1511                 break;
1512         case CPU_PM_EXIT:
1513         case CPU_PM_ENTER_FAILED:
1514                 if (drvdata->state_needs_restore)
1515                         etm4_cpu_restore(drvdata);
1516                 break;
1517         default:
1518                 return NOTIFY_DONE;
1519         }
1520
1521         return NOTIFY_OK;
1522 }
1523
1524 static struct notifier_block etm4_cpu_pm_nb = {
1525         .notifier_call = etm4_cpu_pm_notify,
1526 };
1527
1528 /* Setup PM. Deals with error conditions and counts */
1529 static int __init etm4_pm_setup(void)
1530 {
1531         int ret;
1532
1533         ret = cpu_pm_register_notifier(&etm4_cpu_pm_nb);
1534         if (ret)
1535                 return ret;
1536
1537         ret = cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING,
1538                                         "arm/coresight4:starting",
1539                                         etm4_starting_cpu, etm4_dying_cpu);
1540
1541         if (ret)
1542                 goto unregister_notifier;
1543
1544         ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN,
1545                                         "arm/coresight4:online",
1546                                         etm4_online_cpu, NULL);
1547
1548         /* HP dyn state ID returned in ret on success */
1549         if (ret > 0) {
1550                 hp_online = ret;
1551                 return 0;
1552         }
1553
1554         /* failed dyn state - remove others */
1555         cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
1556
1557 unregister_notifier:
1558         cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
1559         return ret;
1560 }
1561
1562 static void etm4_pm_clear(void)
1563 {
1564         cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
1565         cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
1566         if (hp_online) {
1567                 cpuhp_remove_state_nocalls(hp_online);
1568                 hp_online = 0;
1569         }
1570 }
1571
1572 static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
1573 {
1574         int ret;
1575         void __iomem *base;
1576         struct device *dev = &adev->dev;
1577         struct coresight_platform_data *pdata = NULL;
1578         struct etmv4_drvdata *drvdata;
1579         struct resource *res = &adev->res;
1580         struct coresight_desc desc = { 0 };
1581
1582         drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
1583         if (!drvdata)
1584                 return -ENOMEM;
1585
1586         dev_set_drvdata(dev, drvdata);
1587
1588         if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE)
1589                 pm_save_enable = coresight_loses_context_with_cpu(dev) ?
1590                                PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER;
1591
1592         if (pm_save_enable != PARAM_PM_SAVE_NEVER) {
1593                 drvdata->save_state = devm_kmalloc(dev,
1594                                 sizeof(struct etmv4_save_state), GFP_KERNEL);
1595                 if (!drvdata->save_state)
1596                         return -ENOMEM;
1597         }
1598
1599         if (fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up"))
1600                 drvdata->skip_power_up = true;
1601
1602         /* Validity for the resource is already checked by the AMBA core */
1603         base = devm_ioremap_resource(dev, res);
1604         if (IS_ERR(base))
1605                 return PTR_ERR(base);
1606
1607         drvdata->base = base;
1608
1609         spin_lock_init(&drvdata->spinlock);
1610
1611         drvdata->cpu = coresight_get_cpu(dev);
1612         if (drvdata->cpu < 0)
1613                 return drvdata->cpu;
1614
1615         desc.name = devm_kasprintf(dev, GFP_KERNEL, "etm%d", drvdata->cpu);
1616         if (!desc.name)
1617                 return -ENOMEM;
1618
1619         if (smp_call_function_single(drvdata->cpu,
1620                                 etm4_init_arch_data,  drvdata, 1))
1621                 dev_err(dev, "ETM arch init failed\n");
1622
1623         if (etm4_arch_supported(drvdata->arch) == false)
1624                 return -EINVAL;
1625
1626         etm4_init_trace_id(drvdata);
1627         etm4_set_default(&drvdata->config);
1628
1629         pdata = coresight_get_platform_data(dev);
1630         if (IS_ERR(pdata))
1631                 return PTR_ERR(pdata);
1632
1633         adev->dev.platform_data = pdata;
1634
1635         desc.type = CORESIGHT_DEV_TYPE_SOURCE;
1636         desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
1637         desc.ops = &etm4_cs_ops;
1638         desc.pdata = pdata;
1639         desc.dev = dev;
1640         desc.groups = coresight_etmv4_groups;
1641         drvdata->csdev = coresight_register(&desc);
1642         if (IS_ERR(drvdata->csdev))
1643                 return PTR_ERR(drvdata->csdev);
1644
1645         ret = etm_perf_symlink(drvdata->csdev, true);
1646         if (ret) {
1647                 coresight_unregister(drvdata->csdev);
1648                 return ret;
1649         }
1650
1651         etmdrvdata[drvdata->cpu] = drvdata;
1652
1653         pm_runtime_put(&adev->dev);
1654         dev_info(&drvdata->csdev->dev, "CPU%d: ETM v%d.%d initialized\n",
1655                  drvdata->cpu, drvdata->arch >> 4, drvdata->arch & 0xf);
1656
1657         if (boot_enable) {
1658                 coresight_enable(drvdata->csdev);
1659                 drvdata->boot_enable = true;
1660         }
1661
1662         etm4_check_arch_features(drvdata, id->id);
1663
1664         return 0;
1665 }
1666
1667 static struct amba_cs_uci_id uci_id_etm4[] = {
1668         {
1669                 /*  ETMv4 UCI data */
1670                 .devarch        = 0x47704a13,
1671                 .devarch_mask   = 0xfff0ffff,
1672                 .devtype        = 0x00000013,
1673         }
1674 };
1675
1676 static void clear_etmdrvdata(void *info)
1677 {
1678         int cpu = *(int *)info;
1679
1680         etmdrvdata[cpu] = NULL;
1681 }
1682
1683 static int etm4_remove(struct amba_device *adev)
1684 {
1685         struct etmv4_drvdata *drvdata = dev_get_drvdata(&adev->dev);
1686
1687         etm_perf_symlink(drvdata->csdev, false);
1688
1689         /*
1690          * Taking hotplug lock here to avoid racing between etm4_remove and
1691          * CPU hotplug call backs.
1692          */
1693         cpus_read_lock();
1694         /*
1695          * The readers for etmdrvdata[] are CPU hotplug call backs
1696          * and PM notification call backs. Change etmdrvdata[i] on
1697          * CPU i ensures these call backs has consistent view
1698          * inside one call back function.
1699          */
1700         if (smp_call_function_single(drvdata->cpu, clear_etmdrvdata, &drvdata->cpu, 1))
1701                 etmdrvdata[drvdata->cpu] = NULL;
1702
1703         cpus_read_unlock();
1704
1705         coresight_unregister(drvdata->csdev);
1706
1707         return 0;
1708 }
1709
1710 static const struct amba_id etm4_ids[] = {
1711         CS_AMBA_ID(0x000bb95d),                 /* Cortex-A53 */
1712         CS_AMBA_ID(0x000bb95e),                 /* Cortex-A57 */
1713         CS_AMBA_ID(0x000bb95a),                 /* Cortex-A72 */
1714         CS_AMBA_ID(0x000bb959),                 /* Cortex-A73 */
1715         CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */
1716         CS_AMBA_UCI_ID(0x000bbd0c, uci_id_etm4),/* Neoverse N1 */
1717         CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */
1718         CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */
1719         CS_AMBA_UCI_ID(0x000bb802, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A55 */
1720         CS_AMBA_UCI_ID(0x000bb803, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A75 */
1721         CS_AMBA_UCI_ID(0x000bb805, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A55 */
1722         CS_AMBA_UCI_ID(0x000bb804, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A76 */
1723         CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */
1724         CS_AMBA_UCI_ID(0x000b6d01, uci_id_etm4),/* HiSilicon-Hip08 */
1725         CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */
1726         {},
1727 };
1728
1729 MODULE_DEVICE_TABLE(amba, etm4_ids);
1730
1731 static struct amba_driver etm4x_driver = {
1732         .drv = {
1733                 .name   = "coresight-etm4x",
1734                 .owner  = THIS_MODULE,
1735                 .suppress_bind_attrs = true,
1736         },
1737         .probe          = etm4_probe,
1738         .remove         = etm4_remove,
1739         .id_table       = etm4_ids,
1740 };
1741
1742 static int __init etm4x_init(void)
1743 {
1744         int ret;
1745
1746         ret = etm4_pm_setup();
1747
1748         /* etm4_pm_setup() does its own cleanup - exit on error */
1749         if (ret)
1750                 return ret;
1751
1752         ret = amba_driver_register(&etm4x_driver);
1753         if (ret) {
1754                 pr_err("Error registering etm4x driver\n");
1755                 etm4_pm_clear();
1756         }
1757
1758         return ret;
1759 }
1760
1761 static void __exit etm4x_exit(void)
1762 {
1763         amba_driver_unregister(&etm4x_driver);
1764         etm4_pm_clear();
1765 }
1766
1767 module_init(etm4x_init);
1768 module_exit(etm4x_exit);
1769
1770 MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
1771 MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier@linaro.org>");
1772 MODULE_DESCRIPTION("Arm CoreSight Program Flow Trace v4.x driver");
1773 MODULE_LICENSE("GPL v2");